Nitride Semiconductor Device

Abstract

To provide a nitride semiconductor device that can suppress the deterioration of electrical characteristics caused by dangling bond.SOLUTION: A nitride semiconductor device includes a gallium nitride based semiconductor layer, and an insulating film provided on a first surface of the gallium nitride based semiconductor layer and containing oxygen and other elements other than oxygen. The interface between the gallium nitride based semiconductor layer and the insulating film contains a terminal element that terminates the dangling bond of gallium. The terminal element has a valence electron state in which a closed shell structure lacks one electron, and an atom or molecule that binds more strongly to gallium than hydrogen. At the interface where the gallium nitride based semiconductor layer and the insulating film are in contact with each other, the amount of bonding between gallium and oxygen is larger than the amount of bonding between gallium and other elements.SELECTED DRAWING: Figure 3

Description

[Technical field]

[0001] The present invention relates to a nitride semiconductor device. [Background technology]

[0002] A nitride semiconductor device having a MOS (Metal Oxide Semiconductor) structure is known (see, for example, Patent Document 1). It is also known that dangling bonds near the surface of a nitride semiconductor layer are terminated with hydrogen to suppress inter-electrode leakage caused near the surface (see, for example, Patent Document 2). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2019-96744 A [Patent Document 2] JP 2008-205029 A Summary of the Invention [Problem to be solved by the invention]

[0004] When a silicon oxide film (SiO2 film) is formed as a gate insulating film on a gallium nitride layer (GaN layer), the SiO2 film is formed by chemical vapor deposition (CVD) rather than thermal oxidation. Insulating films formed by CVD have low density, and the formed SiO2 film must be annealed at high temperatures to increase the dielectric strength. At this time, if the gallium (Ga) atoms near the interface between the GaN layer and the SiO2 film are terminated with hydrogen (H) atoms, the H atoms may be detached from the Ga atoms due to heat, resulting in dangling bonds in the Ga atoms. When dangling bonds of Ga atoms occur near the interface between the GaN layer and the SiO2 film, spatially localized interface states are formed in the band gap and become a carrier trap source, which may reduce carrier mobility and degrade the electrical characteristics of the device. The present invention has been made in view of the above circumstances, and has an object to provide a nitride semiconductor device capable of suppressing degradation of electrical characteristics caused by dangling bonds. [Means for solving the problem]

[0005] In order to solve the above problems, a nitride semiconductor device according to one aspect of the present invention includes a gallium nitride semiconductor layer and an insulating film provided on a first surface of the gallium nitride semiconductor layer and containing oxygen and other elements other than oxygen. The interface where the gallium nitride semiconductor layer and the insulating film contact each other contains a terminating element that terminates dangling bonds of gallium. The terminating element is an atom or molecule that has a valence state with one electron missing in a closed shell structure and that bonds more strongly with gallium than with hydrogen. At the interface where the gallium nitride semiconductor layer and the insulating film contact each other, the amount of bonding between gallium and oxygen is greater than the amount of bonding between gallium and other elements. The gallium nitride based semiconductor layer has an electrically conductive region within a range of 20 nm from the first surface in contact with the insulating film to a second surface located on the opposite side of the first surface, and the p-type dopant contained in the electrically conductive region is more than the n-type dopant contained in the electrically conductive region. Effect of the Invention

[0006] According to the present invention, it is possible to provide a nitride semiconductor device capable of suppressing degradation of electrical characteristics caused by dangling bonds. [Brief description of the drawings]

[0007] [Figure 1] FIG. 1 is a cross-sectional view showing an example of the configuration of a MOS transistor according to an embodiment of the present invention. [Diagram 2] FIG. 2 is a model diagram showing the atomic bonding state in a region including the interface where the well region and the gate insulating film are in contact with each other. [Diagram 3] FIG. 3 is an enlarged model diagram showing the bonding state of atoms near the interface. [Figure 4] FIG. 4 is a diagram showing the band gap at the interface. [Diagram 5] FIG. 5 is a flow chart showing a method for manufacturing a MOS transistor according to an embodiment of the present invention, illustrating a step of terminating dangling bonds of Ga atoms with F atoms and steps before and after the step. [Figure 6A] FIG. 6A is a diagram showing a schematic diagram of a cleaning step (Step ST1) of the GaN layer. [Figure 6B] FIG. 6B is a diagram illustrating the process of terminating the dangling bonds (step ST2). [Figure 6C] FIG. 6C is a diagram illustrating the gate insulating film forming step (step ST3) and the heat treatment step (step ST4). [Figure 7] FIG. 7 is a flow chart showing a method (variation 1) for manufacturing a MOS transistor according to an embodiment of the present invention, illustrating a step of terminating dangling bonds of Ga atoms with OH groups and steps before and after the step. [Figure 8] FIG. 8 is a flow chart showing a method (variation 2) for manufacturing a MOS transistor according to an embodiment of the present invention, illustrating a step of terminating dangling bonds of Ga atoms with Cl atoms and steps before and after the step. [Figure 9] FIG. 9 is a flow chart showing a method for manufacturing a MOS transistor according to an embodiment of the present invention (Modification 3), illustrating a step of terminating dangling bonds of Ga atoms with CN groups and steps before and after the step. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0008] The present inventors have found that when the dangling bonds at the GaN / SiO2 interface are terminated with an atom (F, Cl) or molecule (OH, CN) lacking one electron in the closed shell, they have a stronger bond with the Ga atom than when they are terminated with an H atom. In addition, the inventors have found that, regarding the interface bond of GaN / SiO2, when it is Ga-O, a level (hereinafter referred to as an intra-gap level) is not formed in the gap, and when it is Ga-Si, an intra-gap level is formed near the top of the valence band. Regarding the interface bond, the inventors have found that by making the Ga-O bond the main bond, it is possible to suppress the formation of an intra-gap level and to achieve good conduction. The present invention has been made based on such findings.

[0009] An embodiment of the present invention will be described below. In the following description of the drawings, the same or similar parts are given the same or similar reference numerals. However, it should be noted that the drawings are schematic, and the relationship between thickness and planar dimensions, the thickness ratio of each device and each member, etc., differ from the actual ones. Therefore, the specific thickness and dimensions should be determined by taking into consideration the following description. In addition, it goes without saying that the drawings include parts whose dimensional relationships and ratios differ from each other.

[0010] In the following description, directions may be described using the terms X-axis, Y-axis, and Z-axis. For example, the X-axis or Y-axis direction is a direction parallel to the surface 12a of the GaN layer 12. The X-axis, Y-axis, or both the X-axis and Y-axis directions may be called horizontal directions. The Z-axis direction is a normal direction to the surface 12a. The Z-axis direction is also the thickness direction of the GaN layer 12. The X-axis, Y-axis, and Z-axis directions are mutually orthogonal.

[0011] In the following description, the direction of the Z-axis arrow may be referred to as "up" and the opposite direction of the Z-axis arrow may be referred to as "down". "Up" and "down" do not necessarily mean the vertical direction with respect to the ground. In other words, the directions of "up" and "down" are not limited to the direction of gravity. "Up" and "down" are merely convenient expressions for specifying the relative positional relationship in regions, layers, films, substrates, etc., and do not limit the technical idea of ​​the present invention. For example, if the paper is rotated 180 degrees, "up" will of course become "down" and "down" will become "up".

[0012] In the following description, n and p mean that electrons and holes are the majority carriers, respectively. Also, + and - attached to p and n mean that the semiconductor region has a relatively high or low impurity concentration, respectively, compared to a semiconductor region without + or -. However, even if the same p and p are attached to semiconductor regions, it does not mean that the impurity concentrations of the respective semiconductor regions are strictly the same.

[0013] <Structure> FIG. 1 is a cross-sectional view showing a configuration example of a MOS (Metal Oxide Semiconductor) transistor 100 according to an embodiment of the present invention. The nitride semiconductor device according to the embodiment of the present invention is, for example, a power semiconductor device, and includes a gallium nitride based semiconductor substrate 1 shown in FIG. 1 and an n-type MOS transistor 100 provided on the gallium nitride based semiconductor substrate 1. FIG. 1 shows a unit structure of the MOS transistor 100. The unit structures extend in the Y-axis direction and are repeatedly provided in the X-axis direction. A region in which a plurality of unit structures are provided is called an active region. Although not shown, an edge termination structure having a function of preventing electric field concentration in the active region is provided around the active region. The edge termination structure may include one or more of a guard ring structure, a field plate structure, and a JTE (Junction Termination ExtenSiOn) structure.

[0014] As shown in FIG. 1, the MOS transistor 100 has a gate insulating film 5 (an example of an "insulating film" in the present invention) provided on a gallium nitride based semiconductor substrate 1, a gate electrode 6 provided on the gate insulating film 5, and a source electrode 7 and a drain electrode 8 provided on the gallium nitride based semiconductor substrate 1. Gallium nitride semiconductor substrate 1 has, for example, a GaN substrate 11 and a GaN layer 12 (an example of a "gallium nitride semiconductor layer" of the present invention) provided on GaN substrate 11. As shown in Fig. 1, front surface 12a (an example of a "first surface" of the present invention) of GaN layer 12 is also front surface 1a of gallium nitride semiconductor substrate 1. A back surface 12b (an example of a "second surface" of the present invention) located opposite front surface 12a of GaN layer 12 is in contact with GaN substrate 11. Back surface 11b of GaN substrate 11 is also back surface 1b of gallium nitride semiconductor substrate 1.

[0015] The GaN substrate 11 is a GaN single crystal substrate. The conductivity type of the GaN substrate 11 is, for example, n+ type. The n-type dopant contained in the GaN substrate 11 is one or more elements selected from the group consisting of Si (silicon), O (oxygen) and Ge (germanium), and one example is O. The impurity concentration of O in the GaN substrate 11 is 2×10 18 / cm3 That's all. The GaN substrate 11 has a dislocation density of 1E+7 / cm 2 The GaN substrate 11 may be a low dislocation freestanding substrate having a dislocation density of less than 100 nm. When the GaN substrate 11 is a low dislocation freestanding substrate, the dislocation density of the GaN layer 12 formed on the GaN substrate 11 is also low. Furthermore, by using a low dislocation freestanding substrate for the GaN substrate 11, it is possible to reduce leakage current in the power device even when a large-area power device is formed on the GaN substrate 11. This enables the manufacturing equipment to manufacture power devices with a high yield rate. Furthermore, it is possible to prevent ion-implanted impurities from diffusing deeply along the dislocations during heat treatment. Note that E+ is an exponential notation. For example, 1E+7 is 1×10 7 means.

[0016] The GaN layer 12 is provided on the GaN substrate 11. The GaN layer 12 is an n-type GaN single crystal layer, and is a layer formed by epitaxial growth on the GaN substrate 11. The n-type dopant (n-type impurity) contained in the GaN layer 12 is one or more elements selected from the group consisting of Si (silicon), O (oxygen), and Ge (germanium), and one example is O. A p-type well region 13, an n+ type source region 14, and a p+ type contact region 16 are provided on the surface 12a side of the GaN layer 12. A region of the GaN layer 12 where the well region 13, the source region 14, and the contact region 16 are not provided may be called a drift region. The drift region functions as a current path between the GaN substrate 11 and the well region 13.

[0017] The well region 13 is formed by ion-implanting a p-type dopant (p-type impurity) from the surface 12a side of the GaN layer 12 and activating the p-type dopant by heat treatment. The p-type dopant is, for example, magnesium (Mg). The well region 13 faces the surface 12a of the GaN layer 12. The well region 13 has a first side surface adjacent to the source region 14 in the horizontal direction and a second side surface in contact with the drift region directly below the gate insulating film 5. In the well region 13, a channel of the MOS transistor 100 is formed between the first side surface and the second side surface, at the contact interface with the gate insulating film 5 and in the vicinity thereof. Hereinafter, the region in the well region 13 where the channel is formed is referred to as a channel region CR (an example of the "electrically conductive region" in this disclosure).

[0018] For example, the channel region CR is located within a range of 20 nm from the front surface 12a in contact with the gate insulating film 5 toward the back surface 12b. The concentration of a p-type dopant (e.g., Mg) in the channel region CR is higher than the concentration of an n-type dopant contained in the channel region CR, and is, for example, 1E+16 / cm 3 That's all. The source region 14 is formed by ion-implanting an n-type dopant from the surface 12a side of the GaN layer 12 and activating the n-type dopant by heat treatment. The n-type dopant is, for example, one or more elements selected from the group consisting of Si, O, and Ge. The source region 14 faces the surface 12a of the GaN layer 12 and is located inside the well region 13. The sides and bottom of the source region 14 are in contact with the well region 13. The source region 14 and the well region 13 are in contact with each other in the X-axis direction, the Y-axis direction, and the Z-axis direction.

[0019] The p+ type contact region 16 is formed by ion-implanting a p-type dopant from the surface 12a side of the GaN layer 12 and activating the p-type dopant by heat treatment. The p-type dopant is, for example, Mg. The contact region 16 faces the surface 12a of the GaN layer 12 and is located inside the well region 13. At least a bottom portion of the contact region 16 contacts the well region 13. In the Z-axis direction, the contact region 16 and the well region 13 contact each other.

[0020] The gate insulating film 5 is provided on the well region 13. The gate insulating film 5 is, for example, a silicon oxide film (SiO2 film) having an amorphous structure, and has a thickness of 50 nm or more and 100 nm or less. The gate electrode 6 is provided on the gate insulating film 5. The gate electrode 6 is a planar type electrode provided on the flat gate insulating film 5. The gate electrode 6 is formed of, for example, polysilicon doped with impurities. The source electrode 7 is provided continuously from above the n+ type source region 14 to above the p+ type contact region 16, and is electrically connected to the source region 14 and the contact region 16. Although not shown, the source electrode 7 may be provided so as to cover the gate electrode 6 via an interlayer insulating film. The source electrode 7 is made of, for example, Al or an Al-Si alloy.

[0021] Drain electrode 8 is provided on the back surface 11b side of GaN substrate 11 and is electrically connected to GaN substrate 11. Drain electrode 8 is made of, for example, Al or an Al-Si alloy. The crystal plane of the surface 12a of the GaN layer 12 is a (0001) plane, a (1-100) plane, a (11-20) plane, or a (1-102) plane, or a plane equivalent to any one of these planes. As an example, planes equivalent to the (1-100) plane include a (10-10) plane, a (01-10) plane, a (0-110) plane, a (-1100) plane, and a (-1010) plane. As a result, the surface 12a of the GaN layer 12 is a plane in which more gallium (Ga) atoms appear in the outermost layer than nitrogen (N) atoms. For example, when the surface 12a of the GaN layer 12 is a (0001) plane, i.e., a C-plane, the atoms appearing in the outermost layer are almost 100% Ga atoms.

[0022] Fig. 2 is a model diagram showing the atomic bonding state in a portion 20 including an interface 21 where well region 13 and gate insulating film 5 are in contact. Fig. 3 is a model diagram showing an enlarged view of the atomic bonding state in the vicinity of interface 21. In Figs. 2 and 3, the surface of GaN layer 12 (see Fig. 1) is a (0001) plane, and Ga atoms are lined up in the outermost layer of well region 13 formed in GaN layer 12. Many of the Ga atoms are bonded to O atoms that constitute the SiO2 film that constitutes gate insulating film 5.

[0023] In the MOS transistor 100, the number of bonds between Ga atoms and O atoms is greater than the number of bonds between Ga atoms and Si atoms at the interface 21. This is because the gate insulating film 5 is made of an amorphous SiO2 film, and the atomic ratio in one molecule is such that there are more O atoms than Si atoms. At the interface 21, some of the Ga atoms are bonded to, for example, fluorine (F) atoms (an example of a "terminating element" of the present invention). The dangling bonds of the Ga atoms are terminated with F atoms. For example, if a range within 10 nm from the interface 21 toward the well region 13 is defined as a first range, and a range within 10 nm from the interface 21 toward the gate insulating film 5 is defined as a second range, then at least one of the first range and the second range has F atoms at a density of 1E+11 / cm 2 The dangling bonds of the Ga atoms are terminated by the F atoms present in this region.

[0024] Fig. 4 is a diagram showing the band gap at the interface 21. The vertical axis of Fig. 4 indicates energy (eV), and the horizontal axis of Fig. 4 indicates the symmetric point in wave number space. As shown in Figs. 2 and 3, at the interface 21 where the well region 13 and the gate insulating film 5 are in contact with each other, the dangling bonds of Ga atoms are terminated with F atoms. This makes it possible to suppress the formation of an intra-gap level due to dangling bonds between the valence band and the conduction band (i.e., within the gap) as shown in Fig. 4.

[0025] As shown in Table 1 below, the bond between Ga and F has a larger bond energy and is stronger than the bond between Ga and H. Table 1 shows the difference in bond energy from the bond energy at the Ga-O bond interface, and the larger the negative value, the larger the bond energy. Since the bond between Ga and F is stronger and more stable than the bond between Ga and H, F atoms are less likely to be detached from Ga atoms even when heat treatment is performed after the gate insulating film 5 is formed. This makes it possible to suppress the formation of intra-gap levels due to dangling bonds at the interface 21 even after heat treatment.

[0026] [Table 1]

[0027] As described above, the amount of bonds between Ga atoms and O atoms is greater than the amount of bonds between Ga atoms and Si atoms at the interface 21. Although not shown, an intra-gap level is formed near the valence band at the Ga-Si bonded interface. If an intra-gap level exists near the valence band, carriers may be trapped in the intra-gap level, resulting in a decrease in carriers and a decrease in carrier mobility. In contrast, an intra-gap level is not formed at the Ga-O bonded interface. In the MOS transistor 100, a channel region exists near the interface 21, but the formation of an intra-gap level near the interface 21 is suppressed, so that a decrease in the mobility of carriers (e.g., electrons) in the channel region can be suppressed.

[0028] In the embodiment of the present invention, the amount of bonds between Ga atoms and O atoms at the interface 21 is preferably 10 times or more larger than the amount of bonds between Ga atoms and other elements (elements other than O atoms constituting the gate insulating film 5; for example, Si atoms). This can further suppress the formation of intra-gap levels near the interface 21.

[0029] <Manufacturing method> Next, a method for manufacturing the MOS transistor 100 will be described. FIG. 5 is a flow chart showing a process for terminating dangling bonds of Ga atoms with fluorine (F) atoms and the processes before and after the process, in a method for manufacturing the MOS transistor 100 according to an embodiment of the present invention. FIG. 6A is a diagram showing a schematic diagram of a cleaning process (step ST1) of the GaN layer 12. FIG. 6B is a diagram showing a schematic diagram of a termination process (step ST2) of the dangling bonds. FIG. 6C is a diagram showing a schematic diagram of a process for forming a gate insulating film 5 (step ST3) and a heat treatment process (step ST4). The MOS transistor 100 is manufactured by various devices such as a cleaning device, a plasma treatment device, a film forming device, a heat treatment device, an exposure device, and an etching device. Hereinafter, these devices are collectively referred to as manufacturing devices.

[0030] In a cleaning process (step ST1) shown in FIG. 5, for example, a p-type well region 13 (see FIG. 1) is formed in GaN layer 12. The manufacturing equipment cleans surface 12a of GaN layer 12. The cleaning method may be wet cleaning or dry cleaning. In wet cleaning, organic matter and the like are removed from surface 12a of GaN layer 12 by immersing gallium nitride semiconductor substrate 1 having GaN layer 12 in a chemical solution or spraying the chemical solution onto surface 12a of GaN layer 12. In dry cleaning, organic matter and the like are removed by exposing surface 12a of GaN layer 12 to a plasma atmosphere in a chamber.

[0031] Dry cleaning will be described in more detail. In the manufacturing device, gallium nitride semiconductor substrate 1 having GaN layer 12 is carried into a chamber of a plasma generating device, and oxygen gas (O2 gas) is introduced into the chamber to generate oxygen plasma. This makes it possible to remove organic matter attached to surface 12a of GaN layer 12, and O atoms and OH groups naturally attached to Ga atoms exposed on surface 12a. The manufacturing apparatus may also generate nitrogen plasma by introducing nitrogen gas (N2 gas) into the chamber. The nitrogen plasma may be used to remove organic matter attached to the surface 12a and O atoms naturally attached to Ga atoms.

[0032] In the embodiment of the present invention, in step ST1, only one of O2 plasma and N2 plasma may be performed, or both may be performed consecutively in the chamber without being exposed to the atmosphere. Next, the manufacturing equipment irradiates the surface 12a of the GaN layer 12 with carbon tetrafluoride (CF4) plasma to terminate the dangling bonds of Ga atoms exposed on the surface 12a of the GaN layer 12 with F atoms (step ST2). The termination step using CF4 plasma in step ST2 may be performed in the chamber in which the cleaning step in step ST1 was performed, or in a different chamber, but it is preferable not to expose the surface 12a of the GaN layer 12 to the atmosphere between steps. This makes it possible to prevent organic matter and the like from re-adhering to the surface 12a of the GaN layer 12.

[0033] Next, the manufacturing equipment forms an SiO2 film on the surface 12a of the GaN layer 12 (step ST3). The SiO2 film is the gate insulating film 5 (see FIG. 1). The SiO2 film is formed by, for example, a CVD method using monosilane (SiH4) gas and oxygen (O2) gas. The SiO2 film forming process may be performed in the chamber in which the termination process of step ST2 was performed, or in a different chamber, but it is preferable not to expose the surface 12a of the GaN layer 12 to the atmosphere between processes. This makes it possible to prevent organic matter and the like from re-adhering to the surface 12a of the GaN layer 12.

[0034] In step ST3, various vapor phase growth methods such as plasma CVD and low pressure CVD can be used as the CVD method. The source gas is not limited to monosilane (SiH4) gas and oxygen (O2) gas, and may be, for example, TEOS (tetraethyl orthosilicate). The SiO2 film may be formed by ALD (Atomic Layer Deposition) instead of the CVD method.

[0035] Next, the manufacturing equipment applies heat treatment to the SiO2 film formed in step ST3 (step ST4). SiO2 films formed by vapor phase growth tend to be less dense and have a lower dielectric strength than SiO2 films formed by thermal oxidation. For this reason, in step ST4, heat treatment is performed to increase the density of the SiO2 film and improve the dielectric strength. For example, the heat treatment temperature is 800°C. The heat treatment is performed in an inert gas atmosphere such as argon (Ar) and in a state isolated from the atmosphere.

[0036] In step ST2, the dangling bonds of the Ga atoms are terminated with F atoms. As shown in Table 1, the bond between Ga and F has a larger bond energy and is stronger than the bond between Ga and H. Therefore, even if heat treatment is performed in step ST4, most of the bonds between Ga and F are maintained as they are without the F atoms being separated from the Ga atoms. The heat treatment process in step ST4 may be performed in the chamber in which the film formation process in step ST3 was performed, or in a different chamber, but it is preferable not to expose the surface of the SiO2 film to the atmosphere between the processes, which can prevent organic matter from adhering to the surface of the SiO2 film.

[0037] Next, the manufacturing equipment forms a gate electrode film on the heat-treated SiO2 film (step ST5). The gate electrode film is, for example, polysilicon doped with impurities, and is formed by a CVD method. The gate electrode film formation process may be performed in the chamber in which the heat treatment process of step ST4 was performed, or in a different chamber, but it is preferable not to expose the surface of the SiO2 film to the atmosphere between processes. This makes it possible to prevent organic matter, etc. from adhering to the surface of the SiO2 film. Thereafter, the manufacturing equipment patterns the gate electrode film to form a gate electrode 6 (see FIG. 1). Next, the manufacturing equipment uses the gate electrode 6 and a resist pattern (not shown) as a mask to ion-implant an n-type dopant or a p-type dopant into the surface 12a side of the GaN layer 12 to form an n+ type source region 14 and a p+ type contact region 16. Through the above steps, the MOS transistor 100 shown in FIG. 1 is completed.

[0038] The advantages of terminating the dangling bonds of Ga atoms with F atoms include that no intra-gap level is formed at the Ga-F bond interface, and that F atoms have the strongest bond with Ga atoms among all single atoms. Another advantage of the above is that the process is simple, since the dangling bonds of Ga atoms can be terminated simply by exposing the surface of the GaN layer 12 to CF4 plasma. The advantage of using a SiO2 film for the gate insulating film 5 is that the SiO2 film has a large band gap and a large band offset with respect to GaN, so that good insulating properties can be ensured regardless of whether the film is n-type or p-type.

[0039] <Effects of the embodiment> As described above, the nitride semiconductor device according to the embodiment of the present invention includes the GaN layer 12 and the gate insulating film 5 provided on the surface 12a of the GaN layer 12 and containing O atoms and other elements (e.g., Si atoms) other than O atoms. The interface 21 where the GaN layer 12 and the gate insulating film 5 are in contact with each other contains F atoms that terminate dangling bonds of Ga atoms. The F atoms have a valence state in which one electron is deficient in a closed shell structure, and bond more strongly to Ga atoms than to H atoms. At the interface 21 between the GaN layer 12 and the gate insulating film 5, the bond amount between the Ga atoms and O atoms is greater than the bond amount between the Ga atoms and other elements (e.g., Si).

[0040] In this configuration, since the dangling bonds of the Ga atoms are strongly bonded to the F atoms, even if heat treatment (annealing) is applied after the termination of the Ga atoms, it is possible to suppress the detachment of the termination element from the Ga atoms, and the termination of the Ga atoms can be maintained in a good condition. This makes it possible to suppress the trapping of carriers in the dangling bonds, so that, for example, the decrease in carrier mobility can be suppressed, enabling good conduction. This makes it possible to suppress the decrease in electrical characteristics caused by the dangling bonds.

[0041] Moreover, the bond at the interface between the GaN layer 12 and the gate insulating film 5 is mainly a bond between Ga atoms and oxygen (O) atoms (Ga-O bond). This makes it possible to reduce the interface state at the upper end of the valence band at the interface, and to suppress the formation of intra-gap states. This makes it possible to suppress carriers from being trapped in the intra-gap states, and thus to further suppress the deterioration of electrical characteristics.

[0042] <Modification> In the above embodiment, it has been described that the dangling bonds of Ga atoms are terminated with F atoms. However, in the embodiment of the present invention, the terminating element that terminates the dangling bonds of Ga atoms is not limited to F atoms. The terminating element that terminates the dangling bonds of Ga atoms may include, for example, one or more of F atoms, chlorine (Cl) atoms, hydroxyl groups (OH groups), and cyano groups (CN groups).

[0043] (Variation 1) Fig. 7 is a flowchart showing a manufacturing method (variation 1) of a MOS transistor 100 according to an embodiment of the present invention, including a step of terminating dangling bonds of Ga atoms with OH groups and steps before and after the step. The difference between the flowchart shown in Fig. 7 and the flowchart shown in Fig. 5 is that step ST2 is replaced with step ST2A. The steps in Fig. 7 other than step ST2A are the same as those shown in Fig. 7.

[0044] 7, the manufacturing equipment immerses the gallium nitride semiconductor substrate 1 having the GaN layer 12 in an aqueous solution of hydrofluoric acid (HF) to terminate the dangling bonds of Ga atoms exposed on the surface 12a of the GaN layer 12 with OH groups. As shown in Table 1, the Ga-OH bond has a larger bond energy and is stronger than the Ga-H bond. Therefore, even if the heat treatment is performed in step ST4, most of the Ga-OH bonds are maintained as they are without the OH groups being separated from the Ga atoms.

[0045] Advantages of terminating the dangling bonds of Ga atoms with OH groups include that no intra-gap levels are formed at the Ga-OH bond interface, and that the bond between Ga-OH is stronger than the bond between Ga-H (see Table 1). Another advantage of the above is that the process is simple, since the dangling bonds of Ga atoms can be terminated simply by immersing the gallium nitride semiconductor substrate 1 in an aqueous HF solution.

[0046] (Variation 2) Fig. 8 is a flowchart showing a method (variation 2) for manufacturing a MOS transistor 100 according to an embodiment of the present invention, including a step of terminating dangling bonds of Ga atoms with Cl atoms and steps before and after the step. The difference between the flow chart shown in Fig. 8 and the flow chart shown in Fig. 5 is that step ST2 is replaced with step ST2B. The steps in Fig. 8 other than step ST2B are the same as those shown in Fig. 8.

[0047] 8, the manufacturing equipment irradiates surface 12a of GaN layer 12 with chlorine (Cl2+) plasma to terminate dangling bonds of Ga atoms exposed on surface 12a of GaN layer 12 with Cl atoms. As shown in Table 1, the Ga-Cl bond has a larger bond energy and is stronger than the Ga-H bond. Therefore, even if heat treatment is performed in step ST4, most of the Ga-Cl bonds are maintained as they are without the Cl atoms being separated from the Ga atoms.

[0048] The advantages of terminating the dangling bonds of Ga atoms with Cl atoms include that no intra-gap level is formed at the Ga-Cl bond interface, and that the bond between Ga and Cl is stronger than the bond between Ga and H (see Table 1). Another advantage of the above is that the process is simple, since the dangling bonds of Ga atoms can be terminated simply by exposing the surface of the GaN layer 12 to Cl2+ plasma. (Variation 3) Fig. 9 is a flowchart showing a manufacturing method (variation 3) of a MOS transistor 100 according to an embodiment of the present invention, including a step of terminating dangling bonds of Ga atoms with CN groups and steps before and after the step. The difference between the flowchart shown in Fig. 9 and the flowchart shown in Fig. 5 is that step ST2 is replaced with step ST2C. The steps in Fig. 9 other than step ST2C are the same as those shown in Fig. 9.

[0049] 9, the manufacturing equipment immerses the gallium nitride semiconductor substrate 1 having the GaN layer 12 in a crown ether cyanide solution to terminate the dangling bonds of Ga atoms exposed on the surface 12a of the GaN layer 12 with CN groups. As shown in Table 1, the bond between Ga-CN has a larger bond energy and is stronger than the bond between Ga-H. Therefore, even if the heat treatment is performed in step ST4, most of the bonds between Ga-CN are maintained as they are without the CN groups being separated from the Ga atoms.

[0050] Advantages of terminating the dangling bonds of Ga atoms with CN groups include that no intra-gap levels are formed at the Ga-CN bond interface, and that the bond between Ga-CN is stronger than the bond between Ga-H (see Table 1). Another advantage of the above is that the process is simple, since the dangling bonds of Ga atoms can be terminated simply by immersing the gallium nitride semiconductor substrate 1 in a crown ether cyanide solution.

[0051] <Other embodiments> As described above, the present invention has been described by the embodiments and modifications, but the descriptions and drawings forming a part of this disclosure should not be understood as limiting the present invention. Various alternative embodiments and modifications will become apparent to those skilled in the art from this disclosure. For example, the p-type dopant used in the MOS transistor 100 is not limited to magnesium (Mg). The p-type dopant may be beryllium (Be), zinc (Zn), or cadmium (Cd). For example, the channel region CR may contain one or more of Mg, Be, Zn, and Cd as the p-type dopant at a concentration of 1E+16 / cm3 It may be contained in a concentration of 10 or more.

[0052] Moreover, the gate insulating film 5 is not limited to a SiO2 film. The gate insulating film 5 may be, for example, an aluminum oxide (Al2O3) film. The gate insulating film 5 may be an oxide or oxynitride containing one or more of boron (B), aluminum (Al), silicon (Si), gallium (Ga), scandium (Sc), titanium (Ti), yttrium (Y), zirconium (Zr), hafnium (Hf), tantalum (Ta), and tungsten (W).

[0053] 1, an n-type JFET region may be provided in the drift region immediately below the gate insulating film 5. The JFET region is a region having a higher concentration of n-type dopants and a lower electrical resistance than the other drift regions. The on-resistance of the MOS transistor 100 may be reduced by providing the JFET region. In the above embodiment, the GaN layer 12 is exemplified as the "gallium nitride semiconductor layer" of the present invention, but the "gallium nitride semiconductor layer" is not limited to the GaN layer. For example, the "gallium nitride semiconductor layer" may be a bulk GaN substrate. The "gallium nitride semiconductor layer" may contain GaN as a main component, and may further contain one or more elements selected from the group consisting of aluminum (Al) and indium (In).

[0054] Thus, the present invention naturally includes various embodiments not described here. At least one of various omissions, substitutions, and modifications of components can be made without departing from the spirit of the above-mentioned embodiments and modifications. Furthermore, the effects described in this specification are merely examples and are not limited to the present invention, and other effects may also be present. The technical scope of the present invention is defined only by the invention-specific matters related to the scope of the claims that are appropriate from the above description. [Explanation of symbols]

[0055] 1. Gallium nitride semiconductor substrate 1a, 12a surface 1b, 11b, 12b back side 5 Gate insulating film 6 Gate electrode 7. Source Electrode 8 Drain electrode 11 GaN substrate 12 GaN layers 13 Well Area 14 Source Area 16 Contact Area 20 parts 21 Interface 100 MOS Transistors

Claims

1. A gallium nitride based semiconductor layer; an insulating film provided on a first surface of the gallium nitride based semiconductor layer and containing oxygen and an element other than oxygen; an interface between the gallium nitride based semiconductor layer and the insulating film contains a terminating element that terminates a dangling bond of gallium, The terminal element is an atom or molecule that has a valence electron state in which one electron is deficient in a closed shell structure and that bonds more strongly with gallium than with hydrogen, At the interface, the amount of bonding between gallium and oxygen is greater than the amount of bonding between gallium and the other element, The gallium nitride based semiconductor layer is an electrically conductive region is provided within a range of 20 nm from the first surface in contact with the insulating film to a second surface located on the opposite side of the first surface; A nitride semiconductor device, wherein the electrically conductive region contains more p-type dopants than n-type dopants.

2. The electrically conductive region contains, as the p-type dopant, Magnesium, beryllium, zinc, cadmium, or any one of these at least 1E+16 / cm ３ The nitride semiconductor device according to claim 1 , wherein the nitride semiconductor device contains at least one of these elements at a concentration of at least one of the elements.

3. The nitride semiconductor device according to claim 1 , wherein the terminating element includes at least one of fluorine, chlorine, a hydroxyl group, and a cyano group.

4. 4. The nitride semiconductor device according to claim 1, wherein the first crystal plane is a (0001) plane, a (1-100) plane, a (11-20) plane or a (1-102) plane.

5. The nitride semiconductor device according to claim 1 , wherein an amount of bond between gallium and oxygen at said interface is at least 10 times greater than an amount of bond between gallium and said other element.

6. If a range within 10 nm from the interface toward the gallium nitride based semiconductor layer side is defined as a first range, and a range within 10 nm from the interface toward the insulating film side is defined as a second range, At least one of the first range and the second range is a range in which the terminal element is 1E+11 / cm ２ The nitride semiconductor device according to claim 1 , further comprising a region in which one or more of the above-mentioned oxides are present.

7. 7. The nitride semiconductor device according to claim 1, wherein the insulating film is an oxide or an oxynitride containing one or more of boron, aluminum, silicon, gallium, scandium, titanium, yttrium, zirconium, hafnium, tantalum, and tungsten.

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