Semiconductor Device

Abstract

To alleviate electric field concentration near a bottom of a guard ring.SOLUTION: A semiconductor device comprises a semiconductor substrate including a drift region of a first conductivity type, an active region provided in the semiconductor substrate, and an edge termination structure part provided in the semiconductor substrate and provided between the active region and an end part of the semiconductor substrate on an upper surface of the semiconductor substrate. The edge termination structure part comprises a plurality of guard rings of a second conductivity type in contact with the upper surface of the semiconductor substrate, and a high concentration region of the first conductivity type provided from a position shallower than a lower end of the guard ring to a position deeper than the lower end of the guard ring between two adjacent guard rings and having a higher doping concentration than the drift region. When viewed from a lower surface side of the semiconductor substrate, each guard ring includes a region not covered by the high concentration region.SELECTED DRAWING: Figure 5

Description

[Technical field]

[0001] The present invention relates to a semiconductor device. [Background technology]

[0002] 2. Description of the Related Art Conventionally, there has been known a structure in which a P-type guard ring is provided on the outer periphery of an N-type semiconductor substrate on which semiconductor elements such as IGBTs (insulated gate bipolar transistors) are formed (see, for example, Patent Document 1). Patent Document 1: Japanese Patent Application Laid-Open No. 8-167715 Summary of the Invention [Problem to be solved by the invention]

[0003] The electric field may become stronger near the bottom of the guard ring. [Means for solving the problem]

[0004] In order to solve the above problem, one aspect of the present invention provides a semiconductor device including a semiconductor substrate having a drift region of a first conductivity type. The semiconductor device may include an active region provided in the semiconductor substrate. The semiconductor device may include an edge termination structure provided in the semiconductor substrate and disposed on an upper surface of the semiconductor substrate between the active region and an edge of the semiconductor substrate. The edge termination structure may include a plurality of guard rings of a second conductivity type in contact with the upper surface of the semiconductor substrate. The edge termination structure may include a high concentration region of the first conductivity type having a doping concentration higher than the drift region, disposed between two adjacent guard rings from a position shallower than the lower ends of the guard rings to a position deeper than the lower ends of the guard rings. Each guard ring may have a region not covered by the high concentration region when viewed from the lower surface side of the semiconductor substrate.

[0005] At least a portion of the lower surface of each guard ring may be in contact with the drift region.

[0006] The high concentration region may be in contact with a top surface of the semiconductor substrate.

[0007] The heavily doped region may have an upper portion in contact with the upper surface of the semiconductor substrate, and a lower portion separated from the upper portion and extending from a position shallower than a lower end of the guard ring to a position deeper than a lower end of the guard ring.

[0008] The upper portion may include a first dopant of a first conductivity type, and the lower portion may include a second dopant of the first conductivity type, the second dopant being a different element than the first dopant.

[0009] The second dopant may be hydrogen.

[0010] The active region may have a base region of a second conductivity type, and a well region of the second conductivity type having a doping concentration higher than that of the base region and extending from the upper surface of the semiconductor substrate to a position deeper than that of the base region, and the doping concentration of the lower portion may be lower than that of the well region.

[0011] The lower end of the lower portion may be located at a position shallower than the lower end of the well region. The upper end of the high concentration region may be located below the upper ends of the adjacent guard rings. The guard rings may be in contact with the upper surface of the semiconductor substrate. The upper end of the high concentration region may be located below the upper surface of the semiconductor substrate. The semiconductor device may include an interlayer insulating film covering the high concentration region.

[0012] The above summary of the invention does not list all of the necessary features of the present invention. Also, subcombinations of these features may also be inventions. [Brief description of the drawings]

[0013] [Figure 1] FIG. 1 is a top view illustrating an example of a semiconductor device 100 according to an embodiment of the present invention. [Diagram 2] FIG. 2 is an enlarged view of an area A in FIG. [Diagram 3]FIG. 3 is a diagram showing an example of a bb cross section in FIG. 2. [Figure 4] FIG. 2 is a diagram showing an example of a cc cross section in FIG. [Diagram 5] 5 is an enlarged view of the semiconductor substrate 10 in the vicinity of the well region 11 and the guard ring 92 in FIG. [Figure 6] FIG. 13 is a diagram showing another example of the high-concentration region 202. [Figure 7A] 2A to 2C are diagrams illustrating a part of the manufacturing process of the semiconductor device 100. [Figure 7B] 10A to 10C are diagrams illustrating another example of a part of the manufacturing process of the semiconductor device 100. [Figure 8A] 1 is a cross-sectional view of the vicinity of the emitter electrode 52 and the peripheral gate wiring 130. FIG. [Figure 8B] 13 is a diagram showing another example of a cross section in the vicinity of the emitter electrode 52 and the peripheral gate wiring 130. FIG. [Figure 9] 10A to 10C are diagrams illustrating another example of a part of the manufacturing process of the semiconductor device 100. [Figure 10] 13 is a diagram showing another example of a cross section in the vicinity of the emitter electrode 52 and the peripheral gate wiring 130. FIG. [Figure 11] 13A and 13B are diagrams illustrating other exemplary structures of the edge termination structure 90. [Figure 12] 13 is a diagram showing another example of the arrangement of the field plate 94. FIG. [Figure 13] 1. FIG. 4 is a diagram showing another example of the cc cross section in FIG. [Figure 14] 13 is a diagram showing another example of the structure between the outermost guard ring 92 and the channel stopper 174. FIG. [Figure 15] FIG. 2 is a diagram showing another configuration example of the semiconductor device 100. [Figure 16] 13A and 13B are diagrams illustrating other structural examples of the interlayer insulating film 38. [Figure 17] 13A and 13B are diagrams illustrating other structural examples of the interlayer insulating film 38. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0014] The present invention will be described below through embodiments of the invention, but the following embodiments do not limit the scope of the invention according to the claims. Furthermore, not all of the combinations of features described in the embodiments are necessarily essential to the solution of the invention.

[0015] In this specification, one side in a direction parallel to the depth direction of a semiconductor substrate is referred to as "upper" and the other side as "lower." Of the two main surfaces of a substrate, layer, or other member, one surface is referred to as the upper surface and the other surface is referred to as the lower surface. The directions of "upper" and "lower" are not limited to the direction of gravity or the directions when the semiconductor device is mounted.

[0016] In this specification, technical matters may be explained using orthogonal coordinate axes of X-axis, Y-axis, and Z-axis. The orthogonal coordinate axes merely identify the relative positions of components, and do not limit a specific direction. For example, the Z-axis does not limit the height direction relative to the ground. Note that the +Z-axis direction and the -Z-axis direction are opposite directions. When the Z-axis direction is described without indicating positive or negative, it means a direction parallel to the +Z-axis and -Z-axis.

[0017] In this specification, the orthogonal axes parallel to the upper and lower surfaces of the semiconductor substrate are the X-axis and the Y-axis. The axis perpendicular to the upper and lower surfaces of the semiconductor substrate is the Z-axis. In this specification, the direction of the Z-axis may be referred to as the depth direction. In this specification, the direction parallel to the upper and lower surfaces of the semiconductor substrate, including the X-axis and the Y-axis, may be referred to as the horizontal direction.

[0018] In this specification, when the term "same" or "equal" is used, it may include cases where there is an error due to manufacturing variations, etc. The error is, for example, within 10%.

[0019] In this specification, the conductivity type of a doped region doped with impurities is described as P type or N type. In this specification, the impurity may particularly mean either an N type donor or a P type acceptor, and may be described as a dopant. In this specification, doping means introducing a donor or an acceptor into a semiconductor substrate to make it a semiconductor exhibiting an N type conductivity type or a semiconductor exhibiting a P type conductivity type.

[0020] In this specification, the doping concentration means the concentration of donors or acceptors in a thermal equilibrium state. In this specification, the net doping concentration means the net concentration obtained by adding up the donor concentration as the concentration of positive ions and the acceptor concentration as the concentration of negative ions, including the polarity of the charge. As an example, the donor concentration is N D , acceptor concentration N A Then, the net doping concentration at any position is N D -N A It becomes.

[0021] A donor has the function of supplying electrons to a semiconductor. An acceptor has the function of receiving electrons from a semiconductor. Donors and acceptors are not limited to impurities themselves. For example, the VOH defect, which is a combination of vacancy (V), oxygen (O), and hydrogen (H) present in a semiconductor, functions as a donor that supplies electrons.

[0022] In this specification, when it is described as P+ type or N+ type, it means that the doping concentration is higher than that of P type or N type, and when it is described as P- type or N- type, it means that the doping concentration is lower than that of P type or N type. Also, when it is described as P++ type or N++ type, it means that the doping concentration is higher than that of P+ type or N+ type.

[0023] In this specification, the chemical concentration refers to the concentration of an impurity measured regardless of the state of electrical activation. The chemical concentration can be measured, for example, by secondary ion mass spectrometry (SIMS). The above-mentioned net doping concentration can be measured by voltage-capacitance measurement (CV). The carrier concentration measured by spreading resistance measurement (SR) may be the net doping concentration. The carrier concentration measured by CV or SR may be a value in a thermal equilibrium state. In the N-type region, the donor concentration is sufficiently larger than the acceptor concentration, so the carrier concentration in the region may be the donor concentration. Similarly, in the P-type region, the carrier concentration in the region may be the acceptor concentration.

[0024] In addition, when the concentration distribution of the donor, acceptor or net doping has a peak, the peak value may be taken as the concentration of the donor, acceptor or net doping in the region. In cases where the concentration of the donor, acceptor or net doping is almost uniform, the average value of the concentration of the donor, acceptor or net doping in the region may be taken as the concentration of the donor, acceptor or net doping.

[0025] The carrier concentration measured by the SR method may be lower than the concentration of the donor or acceptor. In the range where the current flows when measuring the spreading resistance, the carrier mobility of the semiconductor substrate may be lower than the value in the crystalline state. The reduction in carrier mobility occurs when the carriers are scattered due to a disorder in the crystal structure caused by lattice defects, etc.

[0026] The donor or acceptor concentration calculated from the carrier concentration measured by the CV method or the SR method may be lower than the chemical concentration of the element indicating the donor or acceptor. As an example, the donor concentration of phosphorus or arsenic, which acts as a donor in a silicon semiconductor, or the acceptor concentration of boron, which acts as an acceptor, is about 99% of the chemical concentration. On the other hand, the donor concentration of hydrogen, which acts as a donor in a silicon semiconductor, is about 0.1% to 10% of the chemical concentration of hydrogen.

[0027] Fig. 1 is a top view showing an example of a semiconductor device 100 according to an embodiment of the present invention. Fig. 1 shows the positions of each component projected onto the top surface of a semiconductor substrate 10. Fig. 1 shows only some of the components of the semiconductor device 100, and some components are omitted.

[0028] The semiconductor device 100 includes a semiconductor substrate 10. The semiconductor substrate 10 has edges 102 in a top view. When simply referred to as a top view in this specification, it means that the semiconductor substrate 10 is viewed from the top surface side. The semiconductor substrate 10 of this example has two pairs of edges 102 that face each other in a top view. In FIG. 1, the X-axis and the Y-axis are parallel to either of the edges 102. The Z-axis is perpendicular to the top surface of the semiconductor substrate 10.

[0029] An active portion 160 is provided on the semiconductor substrate 10. The active portion 160 is a region through which a main current flows in the depth direction between the upper and lower surfaces of the semiconductor substrate 10 when the semiconductor device 100 is in operation. An emitter electrode is provided above the active portion 160, but is omitted in FIG.

[0030] The active section 160 is provided with at least one of a transistor section 70 including a transistor element such as an IGBT, and a diode section 80 including a diode element such as a free wheel diode (FWD). In the example of Fig. 1, the transistor section 70 and the diode section 80 are alternately arranged along a predetermined arrangement direction (the X-axis direction in this example) on the upper surface of the semiconductor substrate 10. In another example, the active section 160 may be provided with only one of the transistor section 70 and the diode section 80.

[0031] In FIG. 1, the region in which the transistor section 70 is arranged is marked with the symbol "I", and the region in which the diode section 80 is arranged is marked with the symbol "F". In this specification, the direction perpendicular to the arrangement direction in a top view may be referred to as the extension direction (Y-axis direction in FIG. 1). The transistor section 70 and the diode section 80 may each have a longitudinal direction in the extension direction. That is, the length of the transistor section 70 in the Y-axis direction is greater than its width in the X-axis direction. Similarly, the length of the diode section 80 in the Y-axis direction is greater than its width in the X-axis direction. The extension direction of the transistor section 70 and the diode section 80 may be the same as the longitudinal direction of each trench section described later.

[0032] The diode section 80 has an N+ type cathode region in a region in contact with the lower surface of the semiconductor substrate 10. In this specification, the region in which the cathode region is provided is referred to as the diode section 80. In other words, the diode section 80 is a region that overlaps with the cathode region in a top view. A P+ type collector region may be provided in a region of the lower surface of the semiconductor substrate 10 other than the cathode region. In this specification, an extension region 81 in which the diode section 80 is extended in the Y-axis direction to a gate wiring to be described later may also be included in the diode section 80. A collector region is provided on the lower surface of the extension region 81.

[0033] The transistor section 70 has a P+ type collector region in a region in contact with the lower surface of the semiconductor substrate 10. In addition, the transistor section 70 has a gate structure, which has an N type emitter region, a P type base region, a gate conductive portion, and a gate insulating film, periodically arranged on the upper surface side of the semiconductor substrate 10.

[0034] The semiconductor device 100 may have one or more pads above the semiconductor substrate 10. The semiconductor device 100 of this example has a gate pad 112. The semiconductor device 100 may also have pads such as an anode pad, a cathode pad, and a current detection pad. Each pad is disposed near an end edge 102. The vicinity of the end edge 102 refers to the region between the end edge 102 and the emitter electrode in a top view. When the semiconductor device 100 is mounted, each pad may be connected to an external circuit via wiring such as a wire.

[0035] A gate potential is applied to the gate pad 112. The gate pad 112 is electrically connected to a conductive portion of the gate trench portion of the active portion 160. The semiconductor device 100 includes a gate wiring that connects the gate pad 112 and the gate trench portion. In FIG. 1, the gate wiring is hatched with oblique lines.

[0036] The gate wiring in this example has a peripheral gate wiring 130 and an active side gate wiring 131. The peripheral gate wiring 130 is disposed between the active portion 160 and the edge 102 of the semiconductor substrate 10 in a top view. The peripheral gate wiring 130 in this example surrounds the active portion 160 in a top view. The area surrounded by the peripheral gate wiring 130 in a top view may be the active portion 160. The peripheral gate wiring 130 is connected to the gate pad 112. The peripheral gate wiring 130 is disposed above the semiconductor substrate 10. The peripheral gate wiring 130 may be a metal wiring containing aluminum or the like.

[0037] The active side gate wiring 131 is provided in the active section 160. By providing the active side gate wiring 131 in the active section 160, the variation in wiring length from the gate pad 112 for each region of the semiconductor substrate 10 can be reduced.

[0038] The active side gate wiring 131 is connected to a gate trench portion of the active section 160. The active side gate wiring 131 is disposed above the semiconductor substrate 10. The active side gate wiring 131 may be a wiring formed of a semiconductor such as polysilicon doped with impurities.

[0039] The active side gate wiring 131 may be connected to the peripheral gate wiring 130. In this example, the active side gate wiring 131 is provided extending in the X axis direction from one peripheral gate wiring 130 to the other peripheral gate wiring 130 at approximately the center in the Y axis direction so as to cross the active section 160. When the active section 160 is divided by the active side gate wiring 131, the transistor section 70 and the diode section 80 may be arranged alternately in the X axis direction in each divided region.

[0040] Furthermore, the semiconductor device 100 may include a temperature sensor (not shown) that is a PN junction diode formed of polysilicon or the like, and a current detector (not shown) that simulates the operation of a transistor section provided in the active section 160.

[0041] The semiconductor device 100 of this example includes an edge termination structure 90 between the active section 160 and the edge 102. The edge termination structure 90 of this example is disposed between the peripheral gate wiring 130 and the edge 102. The edge termination structure 90 relieves electric field concentration on the upper surface side of the semiconductor substrate 10. The edge termination structure 90 has a plurality of guard rings 92. The guard rings 92 are P-type regions in contact with the upper surface of the semiconductor substrate 10. The guard rings 92 may surround the active section 160 in a top view. The multiple guard rings 92 are disposed at predetermined intervals between the peripheral gate wiring 130 and the edge 102. The guard ring 92 disposed on the outer side may surround the guard ring 92 disposed one step inward. The outer side refers to the side closer to the edge 102, and the inner side refers to the side closer to the peripheral gate wiring 130. By providing multiple guard rings 92, the depletion layer on the upper surface side of active portion 160 can be extended outward, improving the breakdown voltage of semiconductor device 100. Edge termination structure 90 may further include at least one of a field plate and a resurf provided in an annular shape surrounding active portion 160.

[0042] 2 is an enlarged view of region A in FIG. 1. Region A is a region including a transistor section 70, a diode section 80, and an active side gate wiring 131. The semiconductor device 100 of this example includes a gate trench section 40, a dummy trench section 30, a well region 11, an emitter region 12, a base region 14, and a contact region 15 provided inside the upper surface side of a semiconductor substrate 10. The gate trench section 40 and the dummy trench section 30 are each an example of a trench section. The semiconductor device 100 of this example also includes an emitter electrode 52 and an active side gate wiring 131 provided above the upper surface of the semiconductor substrate 10. The emitter electrode 52 and the active side gate wiring 131 are provided separately from each other.

[0043] An interlayer insulating film is provided between the emitter electrode 52 and the active side gate wiring 131 and the upper surface of the semiconductor substrate 10, but is omitted in Fig. 1. In the interlayer insulating film of this example, contact holes 54 are provided so as to penetrate the interlayer insulating film. In Fig. 2, each contact hole 54 is hatched with oblique lines.

[0044] The emitter electrode 52 is provided above the gate trench portion 40, the dummy trench portion 30, the well region 11, the emitter region 12, the base region 14, and the contact region 15. The emitter electrode 52 contacts the emitter region 12, the contact region 15, and the base region 14 on the upper surface of the semiconductor substrate 10 through a contact hole 54. The emitter electrode 52 is also connected to a dummy conductive portion in the dummy trench portion 30 through a contact hole provided in the interlayer insulating film. The emitter electrode 52 may be connected to the dummy conductive portion of the dummy trench portion 30 at the tip of the dummy trench portion 30 in the Y-axis direction.

[0045] The active side gate wiring 131 is connected to the gate trench portion 40 through a contact hole provided in the interlayer insulating film. The active side gate wiring 131 may be connected to the gate conductive portion of the gate trench portion 40 at the tip portion 41 of the gate trench portion 40 in the Y-axis direction. The active side gate wiring 131 is not connected to the dummy conductive portion in the dummy trench portion 30.

[0046] The emitter electrode 52 is made of a material containing metal. FIG. 2 shows the range in which the emitter electrode 52 is provided. For example, at least a portion of the emitter electrode 52 is made of aluminum or an aluminum-silicon alloy, such as a metal alloy such as AlSi or AlSiCu. The emitter electrode 52 may have a barrier metal made of titanium, a titanium compound, or the like, below the region made of aluminum or the like. Furthermore, the emitter electrode 52 may have a plug formed by embedding tungsten or the like in the contact hole so as to contact the barrier metal and aluminum or the like.

[0047] The well region 11 is provided so as to overlap with the active side gate wiring 131. The well region 11 is also provided so as to extend by a predetermined width to an area where it does not overlap with the active side gate wiring 131. The well region 11 in this example is provided away from the end of the contact hole 54 in the Y-axis direction toward the active side gate wiring 131. The well region 11 is a region of a second conductivity type having a higher doping concentration than the base region 14. In this example, the base region 14 is P- type, and the well region 11 is P+ type.

[0048] Each of the transistor section 70 and the diode section 80 has a plurality of trench sections arranged in the arrangement direction. In the transistor section 70 of this example, one or more gate trench sections 40 and one or more dummy trench sections 30 are alternately provided along the arrangement direction. In the diode section 80 of this example, a plurality of dummy trench sections 30 are provided along the arrangement direction. In the diode section 80 of this example, no gate trench section 40 is provided.

[0049] The gate trench portion 40 in this example may have two straight line portions 39 (portions of the trench that are straight along the extension direction) that extend along an extension direction perpendicular to the arrangement direction, and a tip portion 41 that connects the two straight line portions 39. The extension direction in FIG. 2 is the Y-axis direction.

[0050] At least a part of the tip portion 41 is preferably curved in a top view. By connecting the ends of the two straight portions 39 in the Y-axis direction with each other by the tip portion 41, electric field concentration at the ends of the straight portions 39 can be alleviated.

[0051] In the transistor section 70, the dummy trench section 30 is provided between the respective straight line portions 39 of the gate trench section 40. One dummy trench section 30 may be provided between the respective straight line portions 39, or a plurality of dummy trench sections 30 may be provided. The dummy trench section 30 may have a straight line shape extending in the extension direction, and may have a straight line portion 29 and a tip section 31, similar to the gate trench section 40. The semiconductor device 100 shown in FIG. 2 includes both a straight line dummy trench section 30 without a tip section 31 and a dummy trench section 30 with a tip section 31.

[0052] The diffusion depth of the well region 11 may be deeper than the depth of the gate trench portion 40 and the dummy trench portion 30. The ends in the Y-axis direction of the gate trench portion 40 and the dummy trench portion 30 are provided in the well region 11 when viewed from above. That is, at the ends in the Y-axis direction of each trench portion, the bottoms in the depth direction of each trench portion are covered by the well region 11. This makes it possible to alleviate electric field concentration at the bottoms of each trench portion.

[0053] A mesa portion is provided between each trench portion in the arrangement direction. The mesa portion refers to a region sandwiched between the trench portions inside the semiconductor substrate 10. As an example, the upper end of the mesa portion is the upper surface of the semiconductor substrate 10. The depth position of the lower end of the mesa portion is the same as the depth position of the lower end of the trench portion. The mesa portion in this example is provided on the upper surface of the semiconductor substrate 10, extending in the extension direction (Y-axis direction) along the trench. In this example, the transistor portion 70 is provided with a mesa portion 60, and the diode portion 80 is provided with a mesa portion 61. In this specification, when the term "mesa portion" is simply used, it refers to each of the mesa portion 60 and the mesa portion 61.

[0054] A base region 14 is provided in each mesa portion. Of the base regions 14 exposed on the upper surface of the semiconductor substrate 10 in the mesa portion, the region closest to the active side gate wiring 131 is defined as the base region 14-e. In FIG. 2, the base region 14-e is shown at one end in the extension direction of each mesa portion, but the base region 14-e is also provided at the other end of each mesa portion. In each mesa portion, at least one of the emitter region 12 of the first conductivity type and the contact region 15 of the second conductivity type may be provided in a region sandwiched between the base regions 14-e in a top view. In this example, the emitter region 12 is N+ type, and the contact region 15 is P+ type. The emitter region 12 and the contact region 15 may be provided between the base region 14 and the upper surface of the semiconductor substrate 10 in the depth direction.

[0055] The mesa portion 60 of the transistor portion 70 has an emitter region 12 exposed on the upper surface of the semiconductor substrate 10. The emitter region 12 is provided in contact with the gate trench portion 40. The mesa portion 60 in contact with the gate trench portion 40 may be provided with a contact region 15 exposed on the upper surface of the semiconductor substrate 10.

[0056] Each of the contact region 15 and the emitter region 12 in the mesa portion 60 is provided from one trench portion to the other trench portion in the X-axis direction. As an example, the contact region 15 and the emitter region 12 in the mesa portion 60 are alternately arranged along the extension direction of the trench portion (the Y-axis direction).

[0057] In another example, the contact region 15 and the emitter region 12 of the mesa portion 60 may be provided in a stripe shape along the extension direction (Y-axis direction) of the trench portion. For example, the emitter region 12 is provided in a region in contact with the trench portion, and the contact region 15 is provided in a region sandwiched between the emitter regions 12.

[0058] No emitter region 12 is provided in the mesa portion 61 of the diode portion 80. A base region 14 and a contact region 15 may be provided on the upper surface of the mesa portion 61. In a region sandwiched between the base regions 14-e on the upper surface of the mesa portion 61, a contact region 15 may be provided in contact with each of the base regions 14-e. In a region sandwiched between the contact regions 15 on the upper surface of the mesa portion 61, a base region 14 may be provided. The base region 14 may be disposed in the entire region sandwiched between the contact regions 15.

[0059] A contact hole 54 is provided above each mesa portion. The contact hole 54 is disposed in a region sandwiched between the base regions 14-e. In this example, the contact holes 54 are provided above the contact region 15, the base region 14, and the emitter region 12. The contact holes 54 are not provided in regions corresponding to the base region 14-e and the well region 11. The contact hole 54 may be disposed in the center of the arrangement direction of the mesa portions 60 (X-axis direction).

[0060] In the diode section 80, an N+ type cathode region 82 is provided in a region adjacent to the lower surface of the semiconductor substrate 10. In the lower surface of the semiconductor substrate 10, a P+ type collector region 22 may be provided in a region where the cathode region 82 is not provided. In FIG. 2, the boundary between the cathode region 82 and the collector region 22 is indicated by a dotted line.

[0061] The cathode region 82 is disposed away from the well region 11 in the Y-axis direction. This ensures a distance between the cathode region 82 and a P-type region (well region 11) that has a relatively high doping concentration and is formed to a deep position, thereby improving the breakdown voltage. In this example, the end of the cathode region 82 in the Y-axis direction is disposed farther from the well region 11 than the end of the contact hole 54 in the Y-axis direction. In another example, the end of the cathode region 82 in the Y-axis direction may be disposed between the well region 11 and the contact hole 54.

[0062] 3 is a diagram showing an example of the bb cross section in FIG. 2. The bb cross section is an XZ plane passing through the emitter region 12 and the cathode region 82. In this cross section, the semiconductor device 100 of this example has a semiconductor substrate 10, an interlayer insulating film 38, an emitter electrode 52, and a collector electrode 24. The interlayer insulating film 38 is provided on the upper surface of the semiconductor substrate 10. The interlayer insulating film 38 is a film including at least one layer of an insulating film such as silicate glass doped with impurities such as boron or phosphorus, a thermal oxide film, and other insulating films. The interlayer insulating film 38 is provided with the contact hole 54 described in FIG. 2.

[0063] The emitter electrode 52 is provided above the interlayer insulating film 38. The emitter electrode 52 passes through a contact hole 54 in the interlayer insulating film 38 and is in contact with the upper surface 21 of the semiconductor substrate 10. The collector electrode 24 is provided on the lower surface 23 of the semiconductor substrate 10. The emitter electrode 52 and the collector electrode 24 are made of a metal material such as aluminum. In this specification, the direction connecting the emitter electrode 52 and the collector electrode 24 (the Z-axis direction) is referred to as the depth direction.

[0064] The semiconductor substrate 10 has an N-type drift region 18. The drift region 18 is provided in each of the transistor section 70 and the diode section 80.

[0065] In the mesa portion 60 of the transistor section 70, an N+ type emitter region 12 and a P- type base region 14 are provided in this order from the upper surface 21 side of the semiconductor substrate 10. A drift region 18 is provided below the base region 14. An N+ type accumulation region 16 may be provided in the mesa portion 60. The accumulation region 16 is disposed between the base region 14 and the drift region 18.

[0066] The emitter region 12 is exposed on the upper surface 21 of the semiconductor substrate 10, and is provided in contact with the gate trench portion 40. The emitter region 12 may be in contact with the trench portions on both sides of the mesa portion 60. The emitter region 12 has a higher doping concentration than the drift region 18.

[0067] The base region 14 is provided below the emitter region 12. In this example, the base region 14 is provided in contact with the emitter region 12. The base region 14 may be in contact with the trench portions on both sides of the mesa portion 60.

[0068] The accumulation region 16 is provided below the base region 14. The accumulation region 16 is an N+ type region having a higher doping concentration than the drift region 18. By providing the high-concentration accumulation region 16 between the drift region 18 and the base region 14, the carrier injection enhancement effect (IE effect) can be enhanced and the on-voltage can be reduced. The accumulation region 16 may be provided so as to cover the entire lower surface of the base region 14 in each mesa portion 60.

[0069] A P-type base region 14 is provided in the mesa portion 61 of the diode portion 80 in contact with the upper surface 21 of the semiconductor substrate 10. A drift region 18 is provided below the base region 14. In the mesa portion 61, an accumulation region 16 may be provided below the base region 14.

[0070] In each of the transistor section 70 and the diode section 80, an N+ type buffer region 20 may be provided under the drift region 18. The doping concentration of the buffer region 20 is higher than that of the drift region 18. The buffer region 20 has one or more donor concentration peaks having a higher donor concentration than the drift region 18. The multiple donor concentration peaks are disposed at different positions in the depth direction of the semiconductor substrate 10. The donor concentration peak of the buffer region 20 may be, for example, a concentration peak of hydrogen (protons) or phosphorus. The buffer region 20 may function as a field stop layer that prevents a depletion layer extending from the lower end of the base region 14 from reaching the P+ type collector region 22 and the N+ type cathode region 82.

[0071] In the transistor portion 70, a P+ type collector region 22 is provided below the buffer region 20. The acceptor concentration of the collector region 22 is higher than the acceptor concentration of the base region 14. The collector region 22 may contain the same acceptor as the base region 14, or may contain a different acceptor. The acceptor of the collector region 22 is, for example, boron.

[0072] In the diode section 80, an N+ type cathode region 82 is provided below the buffer region 20. The donor concentration of the cathode region 82 is higher than the donor concentration of the drift region 18. The donor of the cathode region 82 is, for example, hydrogen or phosphorus. The elements serving as the donor and acceptor of each region are not limited to the above-mentioned examples. The collector region 22 and the cathode region 82 are exposed to the lower surface 23 of the semiconductor substrate 10 and are connected to the collector electrode 24. The collector electrode 24 may be in contact with the entire lower surface 23 of the semiconductor substrate 10. The emitter electrode 52 and the collector electrode 24 are formed of a metal material such as aluminum.

[0073] On the upper surface 21 side of the semiconductor substrate 10, one or more gate trench portions 40 and one or more dummy trench portions 30 are provided. Each trench portion penetrates the base region 14 from the upper surface 21 of the semiconductor substrate 10 and reaches the drift region 18. In a region where at least one of the emitter region 12, the contact region 15, and the accumulation region 16 is provided, each trench portion also penetrates these doping regions and reaches the drift region 18. The trench portion penetrating the doping region is not limited to a case where the trench portion is formed in the order of forming the doping region and then the trench portion. A case where the trench portion is formed and then the doping region is formed between the trench portions is also included in the case where the trench portion penetrates the doping region.

[0074] As described above, the transistor portion 70 is provided with the gate trench portion 40 and the dummy trench portion 30. The diode portion 80 is provided with the dummy trench portion 30, but is not provided with the gate trench portion 40. In this example, the boundary between the diode portion 80 and the transistor portion 70 in the X-axis direction is the boundary between the cathode region 82 and the collector region 22.

[0075] The gate trench portion 40 has a gate trench provided on the upper surface 21 of the semiconductor substrate 10, a gate insulating film 42, and a gate conductive portion 44. The gate insulating film 42 is provided to cover the inner wall of the gate trench. The gate insulating film 42 may be formed by oxidizing or nitriding the semiconductor on the inner wall of the gate trench. The gate conductive portion 44 is provided inside the gate insulating film 42 within the gate trench. In other words, the gate insulating film 42 insulates the gate conductive portion 44 from the semiconductor substrate 10. The gate conductive portion 44 is formed of a conductive material such as polysilicon.

[0076] The gate conductive portion 44 may be provided longer in the depth direction than the base region 14. The gate trench portion 40 in this cross section is covered with an interlayer insulating film 38 on the upper surface 21 of the semiconductor substrate 10. The gate conductive portion 44 is electrically connected to the gate wiring. When a predetermined gate voltage is applied to the gate conductive portion 44, a channel is formed by an electron inversion layer in the surface layer of the interface of the base region 14 that contacts the gate trench portion 40.

[0077] The dummy trench portion 30 may have the same structure as the gate trench portion 40 in the cross section. The dummy trench portion 30 has a dummy trench, a dummy insulating film 32, and a dummy conductive portion 34 provided on the upper surface 21 of the semiconductor substrate 10. The dummy conductive portion 34 is electrically connected to the emitter electrode 52. The dummy insulating film 32 is provided to cover the inner wall of the dummy trench. The dummy conductive portion 34 is provided inside the dummy trench and is provided on the inner side of the dummy insulating film 32. The dummy insulating film 32 insulates the dummy conductive portion 34 from the semiconductor substrate 10. The dummy conductive portion 34 may be formed of the same material as the gate conductive portion 44. For example, the dummy conductive portion 34 is formed of a conductive material such as polysilicon. The dummy conductive portion 34 may have the same length as the gate conductive portion 44 in the depth direction.

[0078] The gate trench portion 40 and the dummy trench portion 30 in this example are covered with an interlayer insulating film 38 on the upper surface 21 of the semiconductor substrate 10. The bottoms of the dummy trench portion 30 and the gate trench portion 40 may be curved (curved in cross section) convex downward.

[0079] Figure 4 is a diagram showing an example of a cc cross section in Figure 1. The cc cross section is an XZ plane passing through the edge termination structure portion 90, the transistor portion 70, and the diode portion 80. The structures of the transistor portion 70 and the diode portion 80 are the same as those of the transistor portion 70 and the diode portion 80 described in Figures 2 and 3. In Figure 4, the structures of the gate trench portion 40 and the dummy trench portion 30 are shown in a simplified manner.

[0080] In the semiconductor substrate 10, a well region 11 is provided between the edge termination structure portion 90 and the transistor portion 70. The well region 11 is a P+ type region in contact with the upper surface 21 of the semiconductor substrate 10. The well region 11 may be provided to a position deeper than the lower ends of the gate trench portion 40 and the dummy trench portion 30. A portion of the gate trench portion 40 and the dummy trench portion 30 may be disposed inside the well region 11.

[0081] An interlayer insulating film 38 covering the well region 11 may be provided on the upper surface 21 of the semiconductor substrate 10. Electrodes and wiring such as an emitter electrode 52 and a peripheral gate wiring 130 are provided above the interlayer insulating film 38. The emitter electrode 52 is provided extending from above the active portion 160 to above the well region 11. The emitter electrode 52 may be connected to the well region 11 via a contact hole provided in the interlayer insulating film 38.

[0082] The peripheral gate wiring 130 is disposed between the emitter electrode 52 and the edge termination structure 90. The emitter electrode 52 and the peripheral gate wiring 130 are disposed separately from each other, but the gap between the emitter electrode 52 and the peripheral gate wiring 130 is omitted in Figure 4. The peripheral gate wiring 130 is electrically insulated from the well region 11 by the interlayer insulating film 38.

[0083] Edge termination structure 90 includes a plurality of guard rings 92, a plurality of high concentration regions 202, a plurality of field plates 94, and a channel stopper 174. In edge termination structure 90, a collector region 22 may be provided in a region in contact with lower surface 23. Each guard ring 92 may be provided to surround active portion 160 on upper surface 21. The plurality of guard rings 92 may have the function of spreading a depletion layer generated in active portion 160 to the outside of semiconductor substrate 10. This can prevent electric field concentration inside semiconductor substrate 10, and can improve the breakdown voltage of semiconductor device 100.

[0084] The guard ring 92 in this example is a P+ type semiconductor region formed by ion implantation near the upper surface 21. The depth of the bottom of the guard ring 92 may be deeper than the depth of the bottom of the gate trench portion 40 and the dummy trench portion 30. The depth of the bottom of the guard ring 92 may be the same as or different from the depth of the bottom of the well region 11.

[0085] The upper surface of the guard ring 92 is covered with the interlayer insulating film 38. The field plate 94 is made of a metal such as aluminum or a conductive material such as polysilicon. The field plate 94 may be made of a metal alloy such as an aluminum-silicon alloy, for example, AlSi or AlSiCu. The field plate 94 may be made of the same material as the peripheral gate wiring 130 or the emitter electrode 52. The field plate 94 is provided on the interlayer insulating film 38. The field plate 94 in this example is connected to the guard ring 92 through a through hole provided in the interlayer insulating film 38.

[0086] The channel stopper 174 is provided exposed on the upper surface 21 and the side wall near the edge 102 of the semiconductor substrate 10. The channel stopper 174 is an N-type region having a higher doping concentration than the drift region 18. The channel stopper 174 has a function of terminating the depletion layer generated in the active portion 160 near the edge 102 of the semiconductor substrate 10. In FIG. 4, the interlayer insulating films 38 of the transistor portion 70, the diode portion 80, and the edge termination structure portion 90 are depicted with the same thickness, but they may have different thicknesses or compositions due to different processes for forming them. At least a portion of the field plate 94, the peripheral gate wiring 130, and the emitter electrode 52 are covered with a protective film such as a polyimide or nitride film, but the protective film may be omitted in the drawings of this specification.

[0087] The high concentration region 202 is an N-type region having a doping concentration higher than that of the drift region 18. The high concentration region 202 is provided between two adjacent guard rings 92, from a position shallower than the lower ends of the guard rings 92 to a position deeper than the lower ends of the guard rings 92. The high concentration region 202 may also be provided between the well region 11 and the guard ring 92. The high concentration region 202 may be provided to a position deeper than the lower ends of the well region 11.

[0088] The high concentration region 203 is disposed between the guard ring 92 closest to the channel stopper 174 and the channel stopper 174. The high concentration region 203 may have the same structure and doping concentration distribution as the high concentration region 202. In another example, the high concentration region 203 may be provided at a different depth from the high concentration region 202. The high concentration region 203 may be provided to a position shallower than the lower end of the high concentration region 202, or may be provided to a deeper position. The high concentration region 203 in this example is provided from the upper surface 21 of the semiconductor substrate 10 to a position deeper than the lower end of the guard ring 92.

[0089] Furthermore, the doping concentration of the high concentration region 203 may be higher or lower than that of the high concentration region 202. This makes it possible to reduce electric field concentration between the guard ring 92 disposed on the outermost side and the channel stopper 174.

[0090] Fig. 5 is an enlarged view of semiconductor substrate 10 in the vicinity of well region 11 and guard ring 92 in Fig. 4. In this example, the position in the Z-axis direction of the lower end of guard ring 92 is designated as Z1.

[0091] The high concentration region 202 has a region located closer to the upper surface 21 than position Z1, and a region located closer to the lower surface 23 than position Z1. The high concentration region 202 in this example is provided continuously from position Z0, where the high concentration region 202 contacts the upper surface 21 of the semiconductor substrate 10, to depth position Z2. Position Z2 is farther from the upper surface 21 than position Z1.

[0092] In this example, high concentration region 202 covers a part of guard ring 92 when viewed from the lower surface 23 side of semiconductor substrate 10. That is, in the Z-axis direction, a part of high concentration region 202 overlaps a part of guard ring 92. A region of high concentration region 202 located between depth positions Z1 and Z2 may cover a part of guard ring 92. This can alleviate electric field concentration near the lower end of guard ring 92 and suppress the spread of a depletion layer.

[0093] 5 shows a schematic diagram of equipotential lines 262. As shown in FIG. 5, an electric field may concentrate near a lower region 260 of guard ring 92. The lower region 260 may be a region where the curvature of the boundary between guard ring 92 and the N-type region is maximum. The lower region 260 may be a region where the change in the slope of the boundary between guard ring 92 and the N-type region (i.e., the second-order differential value) is maximum. The lower region 260 is disposed near the lower end of guard ring 92. The lower end of guard ring 92 refers to the portion of guard ring 92 that is disposed at the deepest position.

[0094] Note that guard ring 92 may have lower region 260 and lower region 261. When the cross-sectional shape of guard ring 92 is line-symmetrical with respect to a center line parallel to the Z-axis, guard ring 92 has lower region 260 and lower region 261 at line-symmetrical positions. Of the two lower regions 260, the one closer to well region 11 is referred to as lower region 261, and the one farther from well region 11 is referred to as lower region 260. As shown in FIG. 5, an electric field is likely to concentrate near lower region 260.

[0095] By providing the high concentration region 202, a high concentration N-type region can be arranged in the vicinity of the lower region 260 and the lower region 261. This can alleviate electric field concentration in the vicinity of the lower region 260 and the lower region 261 and suppress the spread of a depletion layer. It is preferable that the high concentration region 202 covers the lower region 260. In other words, it is preferable that the high concentration region 202 is in contact with the lower region 260. The high concentration region 202 may further cover the lower region 261. The cross-sectional shape of the high concentration region 202 may be symmetrical with respect to a center line parallel to the Z axis.

[0096] In addition, since the electric field is concentrated in the area between the guard rings 92 and in the area near the lower end of the guard rings 92, if the donor concentration in the area varies, the breakdown voltage will vary. If the high concentration region 202 is not provided, the drift region 18 is formed in the area. The donor concentration in the drift region 18 is the concentration of the donor contained in the semiconductor substrate 10 from the time of manufacture, so it is relatively easy to vary. In contrast, in this example, the high concentration region 202 is provided in the area. The high concentration region 202 is formed by ion implantation or the like. The concentration of the ion implantation is relatively easy to control, so the variation in the donor concentration in the high concentration region 202 is relatively small. Therefore, by providing the high concentration region 202, the variation in the breakdown voltage of the semiconductor device 100 can be reduced.

[0097] The high concentration region 202 is provided in at least one of the regions sandwiched between the guard rings 92. The high concentration region 202 may be provided in all of the regions sandwiched between the guard rings 92.

[0098] Each guard ring 92 has a region 204 that is not covered by the high concentration region 202 when viewed from the lower surface 23 side of the semiconductor substrate 10. The region 204 may be a region including the lower end of the guard ring 92 at the center in the X-axis direction. The region 204 may be in contact with the drift region 18. When the high concentration guard ring 92 is entirely covered with the high concentration region 202, the electric field strength increases even at the bottom surface of the guard ring 92. Therefore, the electric field strength easily reaches the critical electric field strength at a relatively low voltage, causing avalanche breakdown and reducing the breakdown voltage of the semiconductor device 100. By providing the region 204, the bottom surface of the guard ring 92 is in contact with the low concentration drift region 18, so that the increase in the electric field strength is suppressed.

[0099] The maximum donor concentration in the high concentration region 202 is defined as Dmax. The donor concentration in the drift region 18 is defined as Db. The donor concentration in the drift region 18 below the guard ring 92 and at the center in the depth direction of the semiconductor substrate 10 may be defined as the donor concentration Db. The donor concentration Dmax may be 10 times or more higher than the donor concentration Db. In this case, the position where the donor concentration is twice as high as Db may be defined as the boundary between the high concentration region 202 and the drift region 18. Alternatively, the position where the donor concentration in the drift region 18 starts to increase higher than Db may be defined as the boundary between the high concentration region 202 and the drift region 18.

[0100] A width W2 of region 204 in the X-axis direction is smaller than a width W1 of guard ring 92 on upper surface 21 of semiconductor substrate 10. Width W2 may be 10% or more of width W1, 30% or more, 50% or more, or 70% or more.

[0101] FIG. 6 is a diagram showing another example of the high concentration region 202. The structure other than the high concentration region 202 is the same as the example shown in FIG. 5. The high concentration region 202 of this example has an upper portion 206 and a lower portion 208. The upper portion 206 and the lower portion 208 are provided separately from each other. In this example, a drift region 18 is provided between the upper portion 206 and the lower portion 208. When an N-type dopant is injected from the upper surface 21 to the lower portion 208, a donor may be formed in the region through which the N-type dopant has passed. In this case, the donor concentration gradually decreases from the lower portion 208 to the upper surface 21. Between the lower portion 208 and the upper portion 206, the donor concentration may gradually decrease from the lower portion 208 to the upper portion 206. For example, when hydrogen is used as an N-type dopant, vacancy defects (V) formed in the region through which hydrogen has passed combine with oxygen (O) contained in the semiconductor substrate 10 and hydrogen (H) diffused from the lower portion 208 to form VOH defects. The VOH defects function as donors.

[0102] The upper portion 206 is provided between the two guard rings 92 and in contact with the upper surface 21 of the semiconductor substrate 10. The upper portion 206 may be disposed away from the guard rings 92. This makes it possible to suppress the donors doped at a high concentration in the upper portion 206 from diffusing into the guard rings 92. In another example, the upper portion 206 may be in contact with the guard ring 92.

[0103] The lower portion 208 is provided from a position shallower than the lower end of the guard ring 92 to a position Z2 deeper than the lower end of the guard ring 92. The lower portion 208 in this example is provided in contact with the side 93-2 of the guard ring 92 that is farther from the well region 11 than the two side surfaces 93-1 and 93-2. The side surface 93-1 of the guard ring 92 in FIG. 6 is the surface closer to the well region 11 than the center of the guard ring 92 in the X-axis direction. The side surface 93-2 of the guard ring 92 is the surface on the opposite side to the side surface 93-1. The lower portion 208 may not be in contact with the side surface 93-1, or may be in contact with it. By providing the lower portion 208 in contact with the side surface 93-2, it is possible to protect a region where an electric field is likely to concentrate. The lower portion 208 is preferably in contact with the lower region 260. Moreover, the width W2 of the region 204 in this example is larger than half the width W1 of the guard ring 92.

[0104] The position in the Z-axis direction of the upper end of the lower portion 208 is designated as Z3. The distance Z1-Z3 between the positions Z1 and Z3 in the Z-axis direction may be the same as the distance Z2-Z1 between the positions Z1 and Z2 in the Z-axis direction. The distance Z2-Z1 may be greater than the distance Z1-Z3. This makes it easier to protect an area where an electric field is likely to concentrate. The distance Z2-Z1 may be less than the distance Z1-Z3.

[0105] 1 to 6 may be formed by injecting a dopant from the upper surface 21 of the semiconductor substrate 10. The guard ring 92 can be formed by selectively injecting a P-type dopant such as boron from the upper surface 21 of the semiconductor substrate 10 and performing a heat treatment.

[0106] The high concentration regions 202 (upper portion 206 and lower portion 208 in this example) can be formed by selectively implanting an N-type dopant, such as hydrogen or phosphorus, from the upper surface 21 of the semiconductor substrate 10 and performing a heat treatment. The N-type dopant may be implanted at a plurality of depth positions by changing the acceleration energy.

[0107] By using hydrogen as an N-type dopant, the high concentration region 202 can be easily formed at a deep position. However, if a long-term heat treatment is performed at a high temperature after hydrogen is injected, the hydrogen donor will disappear. For this reason, it is preferable to perform the hydrogen injection and heat treatment steps at the end of the manufacturing process of the semiconductor device 100. For example, the disappearance of the hydrogen donor can be suppressed by injecting hydrogen after forming a protective film above the field plate 94, etc. Hydrogen can be injected from the upper surface 21 or the lower surface 23 of the semiconductor substrate 10.

[0108] 1 to 6, at least a portion of the high concentration region 202 may be provided in a region not covered by the field plate 94. In other words, at least a portion of the high concentration region 202 does not overlap with the field plate 94 in the Z-axis direction. At least a portion of the high concentration region 202 may be formed by implanting an N-type dopant using the field plate 94 as a mask.

[0109] Also, multiple types of N-type dopants may be used to form the high concentration region 202. For example, a first dopant such as phosphorus may be implanted to form the upper portion 206, and a second dopant such as hydrogen may be implanted to form the lower portion 208. In this case, the upper portion 206 includes a higher concentration of the first dopant (phosphorus) than the second dopant (hydrogen), and the lower portion 208 includes a higher concentration of the second dopant (hydrogen) than the first dopant (phosphorus).

[0110] In addition, the dose of the N-type dopant to be implanted into the high concentration region 202 may be adjusted according to the resistivity or donor concentration of the semiconductor substrate 10 before the implantation of the N-type dopant. This allows the resistivity or donor concentration of the semiconductor substrate 10 after the high concentration region 202 is formed to be adjusted with greater precision.

[0111] 7A and 7B are diagrams illustrating a part of the manufacturing process of semiconductor device 100. 7A and 7B show the process of forming lower portion 208 of high concentration region 202. In this example, N-type dopants are implanted into lower portion 208 using electrodes such as field plate 94, peripheral gate wiring 130, and emitter electrode 52 as masks. In edge termination structure 90, N-type dopants are implanted through gaps 95 between adjacent field plates 94.

[0112] In this example, an N-type dopant is implanted after the interlayer insulating film 38, the field plate 94, and other electrodes are formed. The N-type dopant is, for example, hydrogen. Alternatively, an N-type dopant may be implanted into the lower portion 208 after the well region 11, the upper portion 206, and the guard ring 92 are formed. After the lower portion 208 is formed by implanting the N-type dopant, a protective film such as a polyimide or nitride film may be formed above the field plate 94, the peripheral gate wiring 130, and the emitter electrode 52, and other electrodes.

[0113] According to this example, since field plate 94 is used as a mask, it is possible to simplify the manufacturing process of semiconductor device 100. In this example, at least a part of the region of lower portion 208 overlaps with gap 95 in the Z-axis direction. In lower portion 208, a region where the donor concentration is maximum may overlap with gap 95 in the Z-axis direction.

[0114] Field plate 94 may overlap a portion of lower portion 208 in the Z-axis direction. N-type dopants implanted into lower portion 208 diffuse in the X-axis direction to form a portion of lower portion 208 at a position overlapping field plate 94. Field plate 94 may overlap a portion or the entire region of upper portion 206.

[0115] The central position of field plate 94 in the X-axis direction is designated as X1, and the central position of guard ring 92 in the X-axis direction is designated as X2. Central position X1 of field plate 94 may be located closer to well region 11 than central position X2 of guard ring 92. This makes it easier to form the lower portion in lower region 260 without forming lower portion 208 in lower region 261 shown in FIG.

[0116] In this example, the position of the lower end of the well region 11 in the Z-axis direction is Z4. In FIG. 7A, the position Z1 of the lower end of the guard ring 92 coincides with the position Z4 of the lower end of the well region 11. That is, the lower portion 208 is disposed in a region deeper than the well region 11. On the other hand, in FIG. 7B, the position Z4 of the lower end of the well region 11 is disposed in a position deeper than the position Z1 of the lower end of the guard ring 92. Also, in FIG. 7B, the position Z2 of the lower end of the lower portion 208 is disposed closer to the upper surface 21 than the position Z4 of the lower end of the well region 11. That is, the lower portion 208 is disposed in a region shallower than the well region 11. Also, in both FIG. 7A and FIG. 7B, the doping concentration of the lower portion 208 is lower than the doping concentration of the well region 11.

[0117] 8A and 8B are cross-sectional views in the vicinity of the emitter electrode 52 and the peripheral gate wiring 130. FIG. 8A corresponds to the example of FIG. 7A, and FIG. 8B corresponds to the example of FIG. 7B. That is, the depth position Z4 of the well region 11 in FIG. 8A is the same as that in the example shown in FIG. 7A, and the depth position Z4 of the well region 11 in FIG. 8B is the same as that in the example shown in FIG. 7B. In FIGS. 8A and 8B, the structure of the trench and the like is simplified, and the contact hole in the interlayer insulating film 38 is omitted. A gap 95 is provided between the emitter electrode 52 and the peripheral gate wiring 130.

[0118] If an N-type dopant is injected using the electrodes, such as the field plate 94, the peripheral gate wiring 130, and the emitter electrode 52, as a mask, the N-type dopant will also be injected from the gap 95 between the peripheral gate wiring 130 and the emitter electrode 52. In Figures 8A and 8B, the region into which the N-type dopant is injected is designated as region 209. Region 209 is located at the same depth as lower portion 208 shown in Figures 7A and 7B, etc.

[0119] Well region 11 is formed below gap 95. For this reason, in the case where the bottom ends of well region 11 and guard ring 92 are aligned as in Fig. 7A, if lower portion 208 is disposed at a position deeper than well region 11, lower portion 208 is formed to protrude from the bottom end of well region 11 as in Fig. 8A.

[0120] On the other hand, as shown in FIG. 7B, when the position Z4 of the lower end of the well region 11 is deeper than the position Z1 of the lower end of the guard ring 92, the lower portion 208 is disposed in a region shallower than the well region 11, so that the lower portion 208 does not protrude from the lower end of the well region 11 as shown in FIG. 8B. In this case, the position Z4 of the lower end of the well region 11 is farther from the upper surface 21 of the semiconductor substrate 10 than the position Z2 of the lower end of the guard ring 92. That is, the well region 11 is provided deeper than the guard ring 92. This allows the lower portion 208 to be formed deeper than the guard ring 92 while being shallower than the well region 11. In the examples of FIG. 7A and FIG. 8A, a mask for decelerating or shielding ions may be provided at a position covering the gap 95 above the well region 11. This also allows the lower portion 208 to not protrude from the lower end of the well region 11.

[0121] In addition, if the doping concentration of the lower portion 208 is higher than that of the well region 11, the conductivity type of the region 209 in Figures 8A and 8B will be inverted from P type to N type. This may result in a PN junction being formed at an unintended position, causing the characteristics of the semiconductor device 100 to fluctuate.

[0122] In contrast, the doping concentration of the lower portion 208 is made lower than the doping concentration of the well region 11, thereby preventing the conductivity type of the region 209 from becoming N-type. The doping concentration of the well region 11 may be higher than, the same as, or lower than the doping concentration of the guard ring 92. The doping concentration of the guard ring 92 is 1.0×10 17 atoms / cm 3 It may be the following:

[0123] 7A to 8B, an example has been described in which ion implantation is performed using field plate 94 as a mask in lower portion 208. In another example, after a protective film such as polyimide is formed above field plate 94 etc., ion implantation may be performed using the protective film as a mask.

[0124] 9 and 10 are diagrams showing an example of ion implantation using protective film 140 as a mask. Fig. 9 is a diagram showing another example of a cross section in the vicinity of edge termination structure 90. Fig. 10 is a diagram showing another example of a cross section in the vicinity of emitter electrode 52 and peripheral gate wiring 130.

[0125] As shown in FIG. 9, the protective film 140 has an opening 98 above the lower portion 208. The opening 98 passes through the gap 95 of the field plate 94. Neither the protective film 140 nor the field plate 94 is provided at the position where the opening 98 and the gap 95 overlap. In this example, an N-type dopant is implanted into the region of the lower portion 208 through the opening 98 and the gap 95. At this time, as shown in FIG. 10, by not providing an opening in the protective film 140 above the well region 11, it is possible to prevent ions from being implanted into the well region 11. Note that a recess may be used instead of the opening 98. The recess may be formed by etching the protective film 140 or may be formed during deposition of the protective film 140. When the protective film 140 is a nitride film or the like, a recess reflecting the presence or absence of the gap 95 of the field plate 94 may be formed during deposition.

[0126] Furthermore, instead of protective film 140, a mask pattern may be formed using photoresist or the like to implant N-type dopants. Alternatively, when ion implantation is performed on lower portion 208 using the gap in field plate 94 above guard ring 92 as a mask, the gap 95 in field plate 94 above well region 11 may be covered with resist. In this case, ion implantation into semiconductor substrate 10 can be prevented by being shielded by resist, or ion implantation can be prevented by being slowed down by resist, making region 209 shallower and preventing it from protruding below well region 11.

[0127] Figure 11 is a diagram showing another example structure of edge termination structure 90. Edge termination structure 90 of this example differs from edge termination structure 90 described with reference to Figures 1 to 10 in that edge termination structure 90 has a recessed portion 97 in upper surface 21 of semiconductor substrate 10. The structure other than recessed portion 97 may be the same as edge termination structure 90 described with reference to Figures 1 to 10.

[0128] The recess 97 is a recess provided in the Z-axis direction in the upper surface 21 of the semiconductor substrate 10. The recess 97 can be formed by etching the upper surface 21 of the semiconductor substrate 10. The recess 97 in this example is formed in a region in which the guard ring 92 is provided. That is, the guard ring 92 is exposed at the bottom surface of the recess 97. The high concentration region 202 is not exposed at the bottom surface of the recess 97 in this example. In another example, the high concentration region 202 may also be exposed at the bottom surface of the recess 97.

[0129] 11, an interlayer insulating film 38 may be provided inside the recess 97. A field plate 94 may be provided inside the recess 97. As indicated by the dashed line in FIG. 11, the field plate 94 may be in contact with the guard ring 92 at the bottom surface of the recess 97. The field plate 94 does not have to be in contact with the guard ring 92.

[0130] After forming the recessed portion 97, a P-type dopant may be implanted to form the guard ring 92. This makes it easier to form the guard ring 92 to a deep position. In another example, the recessed portion 97 may be formed after the guard ring 92 is formed.

[0131] The recessed portion 97 may be formed in the region where the high concentration region 202 is provided, instead of in the guard ring 92. In this case, it becomes easier to form the high concentration region 202 to a deep position.

[0132] 12 is a diagram showing another example of the arrangement of the field plate 94. The arrangement of the field plate 94 in this example may be applied to each of the examples described in FIGS.

[0133] In this example, the field plate 94 is disposed above the high concentration region 202. The field plate 94 may be disposed so as to cover the entire high concentration region 202. In other words, the width W3 of the field plate 94 in the X-axis direction is greater than the width W4 of the high concentration region 202 in the X-axis direction. The field plate 94 may be disposed across two guard rings 92 adjacent to each other in the X-axis direction. In this example, the field plate 94 is not connected to the guard rings 92.

[0134] 13 is a diagram showing another example of the cc cross section in FIG. 1. The semiconductor device 100 of this example differs from the configuration of the semiconductor device 100 described in relation to FIG. 4 etc. in that it does not include the high concentration region 203. The other structures are the same as those of the semiconductor device 100 of any of the aspects described in this specification etc. In other words, the semiconductor device 100 does not need to include the high concentration region 203.

[0135] 14 is a diagram showing another example of the structure between the outermost guard ring 92 and the channel stopper 174. The semiconductor device 100 of this example includes an upper portion 207 and a lower portion 211 instead of the high concentration region 203 shown in FIG. The upper portion 207 and the lower portion 211 are N-type regions having a higher doping concentration than the drift region 18. In other words, the upper portion 207 and the lower portion 211 are examples of high concentration regions.

[0136] The upper portion 207 may have the same structure and doping concentration distribution as the upper portion 206 described in FIG. 6 and the like. The lower portion 211 may have the same structure and doping concentration distribution as the lower portion 208 described in FIG. 6 and the like. In another example, the upper portion 207 may be provided to a position shallower than the lower end of the upper portion 206, or may be provided to a deeper position. The lower portion 211 may be provided to a position shallower than the lower end of the lower portion 208, or may be provided to a deeper position. The upper portion 207 may have a higher or lower doping concentration than the upper portion 206. The lower portion 211 may have a higher or lower doping concentration than the lower portion 208.

[0137] 15 is a diagram showing another example of the configuration of the semiconductor device 100. In this example, the upper end 221 of the high concentration region 202 is disposed lower than the upper end 241 of the adjacent guard ring 92 (i.e., closer to the lower surface 23 of the semiconductor substrate 10). The other structures are the same as those of the semiconductor device 100 according to any of the aspects described in this specification.

[0138] In this example, guard ring 92 is in contact with upper surface 21 of semiconductor substrate 10. In other words, upper end 241 of guard ring 92 is located at the same depth as upper surface 21 of semiconductor substrate 10. In addition, upper end 221 of high concentration region 202 is located below upper surface 21 of semiconductor substrate 10.

[0139] The high concentration region 202 may be covered with an interlayer insulating film 38. At least a portion of the interlayer insulating film 38 in this example is disposed below the upper surface 21 of the semiconductor substrate 10. The interlayer insulating film 38 may be disposed in a recess formed in the upper surface 21 of the semiconductor substrate 10. The entire interlayer insulating film 38 in this example is disposed below the upper surface 21. The upper end of the interlayer insulating film 38 may be disposed at the same depth as the upper surface 21 of the semiconductor substrate 10.

[0140] Furthermore, interlayer insulating film 38 may be formed by locally oxidizing a partial region of upper surface 21 of semiconductor substrate 10. Even in this case, the lower end of interlayer insulating film 38 may be located lower than upper surface 21. In this example, upper end 221 of high concentration region 202 has been described, but the upper ends of high concentration region 203, upper portion 206, and upper portion 207 may also be located in similar positions.

[0141] FIG. 16 is a diagram showing another example of the structure of the interlayer insulating film 38. The structure other than the interlayer insulating film 38 is the same as that of the semiconductor device 100 according to any aspect described in this specification. The sidewall of the interlayer insulating film 38 in this example is formed in a tapered shape. The cross-sectional area of ​​the interlayer insulating film 38 in the XY plane increases toward the upper side. The interlayer insulating film 38 in this example can be formed by locally oxidizing the upper surface 21 of the semiconductor substrate 10 to form a LOCOS film, and then planarizing the LOCOS film to the same height as the upper surface 21 of the semiconductor substrate 10. Alternatively, the interlayer insulating film 38 in this example can be formed by etching the upper surface 21 of the semiconductor substrate 10 into a recess, and then locally oxidizing the recessed portion to form a LOCOS film. Alternatively, the interlayer insulating film 38 in this example can be formed by etching the upper surface 21 of the semiconductor substrate 10 into a recess, and then thermally oxidizing the semiconductor substrate 10, and removing the thermal oxide film so that the entire surface is planarized, thereby exposing Si.

[0142] FIG. 17 is a diagram showing another example of the structure of the interlayer insulating film 38. The structure other than the interlayer insulating film 38 is the same as that of the semiconductor device 100 of any of the aspects described in this specification. The lower part of the interlayer insulating film 38 of this example is disposed below the upper surface 21, and the upper part is disposed above the upper surface 21. In addition, at least a part of the lower part of the interlayer insulating film 38 of this example is formed in a tapered shape. The lower part of the interlayer insulating film 38 has a larger cross-sectional area in the XY plane toward the upper side. At least a part of the upper part of the interlayer insulating film 38 is also formed in a tapered shape. The upper part of the interlayer insulating film 38 has a larger cross-sectional area in the XY plane toward the lower side. The interlayer insulating film 38 of this example is a LOCOS film formed by locally oxidizing the upper surface 21 of the semiconductor substrate 10. Alternatively, the interlayer insulating film 38 of this example can be formed by etching the upper surface 21 of the semiconductor substrate 10 into a recess, thermally oxidizing the semiconductor substrate 10, and selectively removing the thermal oxide film to expose Si.

[0143] The composition and shape of the interlayer insulating film 38 and the like may be manufactured in various different modes depending on the manufacturing process or manufacturing method, not limited to the above-mentioned process. As an example, the interlayer insulating film 38 of the active section 160 and the interlayer insulating film 38 of the edge termination structure section 90 may be made of different materials or have different thicknesses. In the examples of Figures 15 to 17, the interlayer insulating film 38 is formed closer to the lower surface 23 than the upper surface 21. This is called a recess, but the interlayer insulating film 38 of the active section 160 may be formed in the +Z direction from the upper surface 21 without being recessed.

[0144] Although the present invention has been described above using the embodiments, the technical scope of the present invention is not limited to the scope described in the above embodiments. It is clear to those skilled in the art that various modifications and improvements can be made to the above embodiments. It is clear from the description of the claims that such modifications and improvements can also be included in the technical scope of the present invention. [Explanation of symbols]

[0145] 10 semiconductor substrate, 11 well region, 12 emitter region, 14 base region, 15 contact region, 16 accumulation region, 18 drift region, 20 buffer region, 21 upper surface, 22 collector region, 23 lower surface, 24 collector electrode, 29 straight portion, 30 dummy trench portion, 31 tip portion, 32 dummy insulating film, 34 dummy conductive portion, 38 interlayer insulating film, 39 straight portion, 40 gate trench portion, 41 tip portion, 42 gate insulating film, 44 gate conductive portion, 52 emitter electrode, 54 contact hole, 60, 61 mesa portion, 70 transistor portion, 80 Diode portion, 81, extension region, 82, cathode region, 90, edge termination structure portion, 92, guard ring, 93, side surface, 94, field plate, 95, gap, 97, recessed portion, 98, opening, 100, semiconductor device, 102, edge, 112, gate pad, 130, peripheral gate wiring, 131 Active side gate wiring, 140, protective film, 160, active portion, 174, channel stopper, 202, 203, high concentration region, 204, region, 206, 207, upper portion, 208, 211, lower portion, 209, region, 221, 241, upper end, 260, lower region, 261, lower region, 262, equipotential line

Claims

1. a semiconductor substrate having a drift region of a first conductivity type; an active region provided in the semiconductor substrate; an edge termination structure provided on the semiconductor substrate and disposed on a top surface of the semiconductor substrate between the active region and an edge of the semiconductor substrate; Equipped with The edge termination structure comprises: a plurality of guard rings of a second conductivity type in contact with the top surface of the semiconductor substrate; a high-concentration region of a first conductivity type having a doping concentration higher than that of the drift region, the high-concentration region being provided between two adjacent guard rings from a position shallower than the lower ends of the guard rings to a position deeper than the lower ends of the guard rings; having each of the guard rings has a region that is not covered by the high concentration region when viewed from the bottom surface side of the semiconductor substrate; The high concentration region is Among the side surfaces of the guard ring adjacent to the active region on the edge side of the semiconductor substrate, From a half depth position from the top surface of the semiconductor substrate to the bottom surface of the guard ring, Covering at least a portion of the side surface of the guard ring down to the bottom surface Semiconductor device.

2. A semiconductor substrate having a drift region of a first conductivity type; an active region provided in the semiconductor substrate; an edge termination structure provided on the semiconductor substrate and disposed on a top surface of the semiconductor substrate between the active region and an edge of the semiconductor substrate; Equipped with The edge termination structure comprises: a plurality of guard rings of a second conductivity type in contact with the top surface of the semiconductor substrate; a high-concentration region of a first conductivity type having a doping concentration higher than that of the drift region, the high-concentration region being provided between two adjacent guard rings from a position shallower than the lower ends of the guard rings to a position deeper than the lower ends of the guard rings; having each of the guard rings has a region that is not covered by the high concentration region when viewed from the bottom surface side of the semiconductor substrate; The high concentration region is provided away from an upper surface of the semiconductor substrate and has a lower portion that extends from a position shallower than a lower end of the guard ring to a position deeper than a lower end of the guard ring. Semiconductor device.

3. the high concentration region has an upper portion in contact with the top surface of the semiconductor substrate; The upper and lower portions are separate. The semiconductor device according to claim 2 .

4. the upper portion includes a first dopant of a first conductivity type; The lower portion includes a second dopant of a first conductivity type, the second dopant being a different element than the first dopant. The semiconductor device according to claim 3 .

5. The second dopant is hydrogen. The semiconductor device according to claim 4.

6. The active region comprises: a base region of a second conductivity type; a well region of a second conductivity type having a doping concentration higher than that of the base region and provided from the top surface of the semiconductor substrate to a position deeper than that of the base region; having The doping concentration of the lower portion is less than the doping concentration of the well region. The semiconductor device according to claim 3 .

7. The lower end of the lower portion is located at a position shallower than the lower end of the well region. The semiconductor device according to claim 6.

8. A semiconductor substrate having a drift region of a first conductivity type; an active region provided in the semiconductor substrate and having the drift region; an edge termination structure provided on the semiconductor substrate and disposed on a top surface of the semiconductor substrate between the active region and an edge of the semiconductor substrate; Equipped with The edge termination structure comprises: a plurality of guard rings of a second conductivity type in contact with the top surface of the semiconductor substrate; a high-concentration region of a first conductivity type having a doping concentration higher than that of the drift region, the high-concentration region being provided between two adjacent guard rings from a position shallower than the lower ends of the guard rings to a position deeper than the lower ends of the guard rings; having each of the guard rings has a region that is not covered by the high concentration region when viewed from the bottom surface side of the semiconductor substrate; the drift region is provided from a center in a depth direction of the semiconductor substrate to an upper surface side, has a uniform doping concentration in the depth direction, and at least a portion of the edge termination structure is in contact with the upper surface of the semiconductor substrate; At least a portion of the lower surface of each of the guard rings is in contact with the drift region. Semiconductor device.

9. A semiconductor substrate having a drift region of a first conductivity type; an active region provided in the semiconductor substrate; an edge termination structure provided on the semiconductor substrate and disposed on a top surface of the semiconductor substrate between the active region and an edge of the semiconductor substrate; Equipped with The edge termination structure comprises: a plurality of guard rings of a second conductivity type in contact with the top surface of the semiconductor substrate; a high-concentration region of a first conductivity type having a doping concentration higher than that of the drift region, the high-concentration region being provided between two adjacent guard rings from a position shallower than the lower ends of the guard rings to a position deeper than the lower ends of the guard rings; having each of the guard rings has a region that is not covered by the high concentration region when viewed from the bottom surface side of the semiconductor substrate; The guard ring is a first side proximate the active region; a second side remote from the active region; and having The high concentration region is provided in contact with the second side surface from a position shallower than a lower end of the guard ring to a position deeper than a lower end of the guard ring. Semiconductor device.

10. A semiconductor substrate having a drift region of a first conductivity type; an active region provided in the semiconductor substrate; an edge termination structure provided on the semiconductor substrate and disposed on a top surface of the semiconductor substrate between the active region and an edge of the semiconductor substrate; Equipped with The edge termination structure comprises: a plurality of guard rings of a second conductivity type in contact with the top surface of the semiconductor substrate; a high-concentration region of a first conductivity type having a doping concentration higher than that of the drift region, the high-concentration region being provided between two adjacent guard rings from a position shallower than the lower ends of the guard rings to a position deeper than the lower ends of the guard rings; having each of the guard rings has a region that is not covered by the high concentration region when viewed from the bottom surface side of the semiconductor substrate; The high concentration region is provided continuously from a position where one of the two adjacent guard rings contacts the other of the two guard rings. Semiconductor device.

11. A semiconductor substrate having a drift region of a first conductivity type; an active region provided in the semiconductor substrate; an edge termination structure provided on the semiconductor substrate and disposed on a top surface of the semiconductor substrate between the active region and an edge of the semiconductor substrate; Equipped with The edge termination structure comprises: a plurality of guard rings of a second conductivity type in contact with the top surface of the semiconductor substrate; a high-concentration region of a first conductivity type having a doping concentration higher than that of the drift region, the high-concentration region being provided between two adjacent guard rings from a position shallower than the lower ends of the guard rings to a position deeper than the lower ends of the guard rings; a first conductivity type channel stopper provided on an upper surface and a side wall of the semiconductor substrate in the vicinity of an edge of the semiconductor substrate and having a doping concentration higher than that of the drift region; having each of the guard rings has a region that is not covered by the high concentration region when viewed from the bottom surface side of the semiconductor substrate; The high concentration region is provided between the outermost guard ring and the channel stopper, away from the upper surface of the semiconductor substrate, and has a lower portion that extends from a position shallower than the lower end of the guard ring to a position deeper than the lower end of the guard ring. Semiconductor device.

12. The high concentration region has an upper portion in contact with the top surface of the semiconductor substrate between the outermost guard ring and the channel stopper, The upper and lower portions are separate. The semiconductor device according to claim 11.

13. A semiconductor substrate having a drift region of a first conductivity type; an active region provided in the semiconductor substrate; an edge termination structure provided on the semiconductor substrate and disposed on a top surface of the semiconductor substrate between the active region and an edge of the semiconductor substrate; Equipped with The edge termination structure comprises: a plurality of guard rings of a second conductivity type in contact with the top surface of the semiconductor substrate; a high-concentration region of a first conductivity type having a doping concentration higher than that of the drift region, the high-concentration region being provided between two adjacent guard rings from a position shallower than the lower ends of the guard rings to a position deeper than the lower ends of the guard rings; having each of the guard rings has a region that is not covered by the high concentration region when viewed from the bottom surface side of the semiconductor substrate; The upper end of the high concentration region is disposed below the upper ends of the adjacent guard rings. Semiconductor device.

14. the guard ring is in contact with an upper surface of the semiconductor substrate; The upper end of the high concentration region is located below the upper surface of the semiconductor substrate. The semiconductor device according to claim 13.

15. The high concentration region is further covered with an interlayer insulating film. The semiconductor device according to claim 14.

16. At least a portion of the lower surface of each of the guard rings is in contact with the drift region. The semiconductor device according to claim 1 ,

17. The high concentration region is in contact with the top surface of the semiconductor substrate. The semiconductor device according to claim 1 or 8 to 10.

18. The entire side surface of the guard ring on the end side of the semiconductor substrate is in contact with a first conductivity type region. The semiconductor device according to claim 1 .

19. The guard ring further has a bottom surface, The high concentration region is in contact with a portion of the bottom surface. The semiconductor device according to claim 9.

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