Semiconductor device and clock

Abstract

To provide a semiconductor device and a watch that can achieve an improvement in operation stability and prevention of an increase in power consumption, and can prevent an increase in manufacturing cost.SOLUTION: A semiconductor device comprises: a first circuit that is driven at a first period and outputs a first clock signal at the first period; a divider circuit that has a floating body type, partial-depletion type transistor formed in a semiconductor layer on an insulating layer, and receives input of the first clock signal and a second clock signal at a second period shorter than the first period; and a second circuit that receives input of a signal output from the divider circuit in response to the input of the first clock signal.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] The present invention relates to a semiconductor device and a timepiece using the semiconductor device. [Background technology]

[0002] Conventionally, as described in Patent Document 1, MOSFETs (metal-oxide-semiconductor field-effect transistors) having an SOI (silicon on insulator) structure have been known as circuit elements used from the viewpoint of reducing the power consumption of electronic circuits. SOI-structure MOSFETs can reduce the operating voltage by reducing the junction capacitance and the threshold voltage, and the use of these circuit elements can reduce the power consumption of electronic circuits. Among SOI-structure MOSFETs, FB (Floating Body) MOSFETs, which do not electrically connect the body region to other regions and float the potential, can set the threshold voltage low without increasing the leakage current in the OFF state, and are suitable for reducing power consumption.

[0003] Immediately after starting operation, the absolute value of the threshold voltage of an SOI FB MOSFET is low, allowing a larger drain current Id to flow. As operation continues, the absolute value of the threshold voltage increases, and the drain current Id gradually decreases, until a constant current flows. Regarding this phenomenon, it takes a certain amount of time for the FB MOSFET to reach a stable state. Therefore, when an FB MOSFET that has been OFF for a long time is turned ON for a short time, or when an FB MOSFET that has been ON for a long time is turned OFF for a short time, the drain current Id may flow more than the design value, or too much leakage current may flow, causing the FB MOSFET to malfunction.

[0004] As a countermeasure to this problem, Patent Document 1 changes the threshold voltage of each FB type MOSFET according to the input frequency, thereby improving the operational stability and suppressing an increase in power consumption. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] JP 2010-273044 A Summary of the Invention [Problem to be solved by the invention]

[0006] However, in order to change the threshold voltage of each FB MOSFET in accordance with the input frequency, an additional glass mask or manufacturing process is required, increasing the manufacturing cost of a semiconductor device having FB MOSFETs. [Means for solving the problem]

[0007] The semiconductor device disclosed herein is characterized by comprising: a first circuit that is driven at a first period and outputs a first clock signal at the first period; a frequency divider circuit having a floating body type partially depleted transistor formed in a semiconductor layer on an insulating layer, and receiving as input a second clock signal having a second period shorter than the first period and the first clock signal; and a second circuit that receives as input a signal output from the frequency divider circuit in response to the input of the first clock signal.

[0008] The timepiece of the present disclosure is characterized by including the semiconductor device described above. [Brief description of the drawings]

[0009] [Figure 1] FIG. 1 is a front view showing a timepiece according to an embodiment. [Diagram 2] FIG. 2 is a block diagram showing the configuration of a watch. [Diagram 3] FIG. 2 is a circuit diagram showing a flip-flop circuit constituting a frequency divider circuit. [Figure 4] FIG. 2 is a circuit diagram showing a clocked inverter of a flip-flop circuit. [Diagram 5] FIG. 2 is a circuit diagram showing an inverter of a flip-flop circuit. [Figure 6] 4 is a diagram showing a first clock signal and a second clock signal input to a frequency divider circuit; FIG. [Figure 7] 4 is a diagram showing a first clock signal and a second clock signal input to a frequency divider circuit; FIG. [Figure 8] FIG. 13 is a diagram showing the results of actual measurements when a MOSFET is turned on and off. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] [Embodiment] A timepiece 1 according to an embodiment of the present disclosure will now be described with reference to the drawings. 1 is a front view showing the timepiece 1. In this embodiment, the timepiece 1 is configured as an electronically controlled mechanical timepiece. As shown in Fig. 1, the timepiece 1 is a wristwatch worn on the wrist of a user, and has a cylindrical exterior case 2, with a dial 3 disposed on the inner circumference of the exterior case 2. Of the two openings in the exterior case 2, the opening on the front side is closed by a cover crystal, and the opening on the back side is closed by a back cover.

[0011] The timepiece 1 is equipped with a movement (not shown) housed in an exterior case 2, and an hour hand 4A, minute hand 4B, and second hand 4C that display time information. A small calendar window 3A is provided on the dial 3, and a date wheel 6 can be seen through the small calendar window 3A. The dial 3 also has hour marks 3B for indicating the time, and a fan-shaped sub-dial 3C that indicates the duration with a power reserve hand 5.

[0012] A crown 7 is provided on the side of the exterior case 2. The crown 7 can be moved from a 0 position where it is pushed toward the center of the timepiece 1 to a 1 position or a 2 position by being pulled out. When the crown 7 is pulled to the first position and rotated, the date wheel 6 moves and the date can be adjusted. When the crown 7 is pulled to the second position, the second hand 4C stops, and when the crown 7 is rotated in the second position, the hour hand 4A and minute hand 4B move and the time can be adjusted. The method of adjusting the date wheel 6, hour hand 4A, and minute hand 4B using the crown 7 is the same as that of conventional watches, so a description is omitted here.

[0013] Furthermore, when the crown 7 is rotated at the 0 position, the mainspring 40, which will be described later, can be wound up. The power reserve hand 5 moves in conjunction with the winding of the mainspring 40. The timepiece 1 of this embodiment can ensure a running time of about 40 hours when the mainspring 40 is fully wound.

[0014] [Outline of the clock] FIG. 2 is a block diagram showing a schematic configuration of the timepiece 1. As shown in Fig. 2, the timepiece 1 comprises an IC 10 which is a semiconductor device, a mainspring 40, a speed-increasing gear train 50, a time display unit 60, a generator 70 which also serves as a speed regulator, a quartz crystal oscillator 80, a rectifier circuit 90, and a power supply circuit 95. The time display unit 60 comprises an hour hand 4A, a minute hand 4B, a second hand 4C, and a date wheel 6. Note that in this embodiment, the timepiece 1 is configured to be able to maintain the time precision known as an annual difference clock.

[0015] The crystal oscillator 80 is driven by an oscillation circuit 11, which will be described later, to generate an oscillation signal. The speed-increasing gear train 50 transmits the driving force of the mainspring 40 to the hour hand 4A, minute hand 4B, second hand 4C, power reserve hand 5, date wheel 6, and the rotor of the generator 70 described below.

[0016] Although not shown, the generator 70 is configured to include a rotor, a stator, and a coil. The electrical energy generated by the generator 70 is charged to a power supply circuit 95 via a rectifier circuit 90, and the power supply circuit 95 drives the IC 10. The generator 70 also includes a brake circuit that shorts the coil to generate a braking force to control the rotation of the rotor, thereby functioning as a speed governor. The rectifier circuit 90 is made up of a step-up rectifier, a full-wave rectifier, a half-wave rectifier, a transistor rectifier, or the like, and steps up and rectifies the AC output from the generator 70 to supply the power to the power supply circuit 95 for charging.

[0017] [I C] The IC 10 includes an oscillator circuit 11, a frequency divider circuit 12, a rotation detection circuit 13, a braking control circuit 14, and a temperature compensation function unit 20. Note that IC is an abbreviation for Integrated Circuit.

[0018] The oscillator circuit 11 is a crystal oscillator circuit that outputs an oscillation signal of a predetermined frequency generated by the oscillation of a crystal oscillator 80 to the frequency divider circuit 12. In this embodiment, the oscillator circuit 11 generates an oscillation signal of 32768 Hz. The frequency divider circuit 12 divides the output of the oscillator circuit 11 to generate a frequency-divided signal of a predetermined frequency, and outputs it to the braking control circuit 14, and to a temperature compensation function control circuit 21 and a frequency divider circuit 34, which will be described later. The frequency divider circuit 12 of this embodiment is capable of outputting at least a frequency-divided signal with a 160-second period and a frequency-divided signal with a 20-second period.

[0019] The rotation detection circuit 13 is composed of a waveform shaping circuit and a mono-multivibrator, not shown, connected to the generator 70 , and outputs a rotation detection signal of the rotor of the generator 70 to the braking control circuit 14 . The braking control circuit 14 compares the rotation detection signal output from the rotation detection circuit 13 with the reference signal output from the frequency division circuit 12, and outputs a braking control signal to the brake circuit of the generator 70 to regulate the speed of the generator 70. In this embodiment, the reference signal is a signal that is set to the reference rotation speed of the rotor during normal hand movement. Therefore, the brake control circuit 14 adjusts the braking force by the brake circuit and controls the rotation of the rotor by outputting a brake control signal according to the difference between the rotation detection signal corresponding to the rotor rotation speed and the reference signal.

[0020] [Temperature compensation function section] The temperature compensation function unit 20 compensates for the temperature characteristics of the crystal oscillator 80 and the like to suppress fluctuations in the oscillation frequency, and includes a temperature compensation function control circuit 21 and a temperature compensation circuit 30.

[0021] The temperature compensation function control circuit 21 receives a signal from the frequency divider circuit 12 and operates the temperature compensation circuit 30 at a preset first cycle. In this embodiment, a signal with a 160-second cycle is input from the frequency divider circuit 12 to the temperature compensation function control circuit 21, and the temperature compensation function control circuit 21 controls the temperature compensation circuit 30 to operate for 1 second at the 160-second cycle and stop for 159 seconds. Therefore, the temperature compensation circuit 30 is driven by the temperature compensation function control circuit 21 at a 160-second cycle, which is the first cycle.

[0022] The temperature compensation circuit 30 includes a temperature sensor 31, a temperature correction table storage unit 32, an individual difference correction data storage unit 33, a frequency divider circuit 34, an arithmetic circuit 35, a logical speed-adjustment circuit 36, and a frequency adjustment control circuit 37. The temperature compensation circuit 30 performs a temperature compensation function operation that suppresses fluctuations in the oscillation frequency due to the temperature of the crystal resonator 80 by compensating for fluctuations due to temperature, etc. in the reference signal output from the frequency divider circuit 12 at a constant period. Note that in this embodiment, the operation of adjusting the rate according to the temperature measured by the temperature sensor 31 is referred to as the temperature compensation function operation.

[0023] The temperature sensor 31 inputs an output corresponding to the measured temperature, that is, an output corresponding to the temperature of the environment in which the watch 1 is used, to the frequency divider circuit 34. The temperature sensor 31 can be one using a diode or one using a CR oscillation circuit, and detects the current temperature with an output signal that changes using the temperature characteristics of the diode or CR oscillation circuit. In this embodiment, a CR oscillation circuit that can immediately perform digital signal processing by shaping the output signal is used as the temperature sensor 31. That is, the frequency of the signal output from the CR oscillation circuit, which is the temperature sensor 31, changes depending on the environmental temperature, and the arithmetic circuit 35 detects the temperature based on that frequency. Also, if the CR oscillation circuit is configured to be driven with a constant current, the drive current of the temperature sensor 31 is determined by the constant current value, so the current value can be controlled by design, making it easier to reduce current consumption. A constant current drive type CR oscillation circuit can be driven at a low voltage and consumes low current, so it is suitable as a temperature sensor 31 when a temperature compensation function is added to the watch 1. This temperature sensor 31 is the first circuit of the present disclosure that is driven in the first cycle, and is also an example of a temperature-sensitive oscillator circuit. The temperature sensor 31, which is the first circuit, is driven for one second in the first cycle, that is, in a 160-second cycle, and outputs a signal with a frequency corresponding to the environmental temperature, that is, the measured temperature, as a first clock signal.

[0024] The temperature correction table storage unit 32 stores a temperature correction table that sets how much rate should be compensated at a certain temperature for an ideal crystal unit 80 and an ideal temperature sensor 31. In other words, the temperature correction table storage unit 32 stores a temperature correction table that is common to the crystal unit 80 and the temperature sensor 31. Furthermore, individual differences occur in the crystal unit 80 and the temperature sensor 31 due to manufacturing. Examples of individual differences include the quadratic coefficient of the temperature characteristic of the crystal unit 80, the peak temperature of the crystal unit 80, the peak rate of the crystal unit 80, the output frequency of the temperature sensor 31, and the load capacitance of the oscillation circuit 11. Therefore, individual difference correction data that sets how much individual difference should be corrected based on the characteristics of the crystal unit 80 and the characteristics of the temperature sensor 31 measured in advance during the manufacturing and inspection processes is written in the individual difference correction data storage unit 33. Note that in this embodiment, the operation of compensating for the individual differences of the crystal unit 80 and the temperature sensor 31 described above in the temperature compensation function operation is referred to as individual difference temperature compensation operation. A masked ROM is used for the temperature correction table storage unit 32. The reason for using a masked ROM is that it is the simplest of semiconductor memories, and therefore allows for a high degree of integration and a small area. The individual difference correction data storage unit 33 is composed of a non-volatile memory, and in particular uses FAMOS, because FAMOS has a low current value after writing and allows data to be written at a relatively low voltage among non-volatile memories.

[0025] The frequency divider circuit 34 functions as a counter circuit that counts the first clock signal output from the temperature sensor 31, and counts the number of signals output from the temperature sensor 31 during the one second that the temperature compensation circuit 30 is operating, thereby outputting the frequency of the output signal of the temperature sensor 31, i.e., a signal corresponding to the temperature measurement value by the temperature sensor 31, to the arithmetic circuit 35. The arithmetic circuit 35 calculates the rate correction amount using the temperature measured by the temperature sensor 31, the temperature correction table stored in the temperature correction table storage unit 32, and the individual difference correction data stored in the individual difference correction data storage unit 33. The arithmetic circuit 35 then outputs the calculation result to the logical speed adjustment circuit 36 ​​and the frequency adjustment control circuit 37. That is, in the temperature compensation function operation of this embodiment, in addition to the temperature measurement operation by the temperature sensor 31 and the operation of reading the temperature correction table from the temperature correction table storage unit 32, an operation of reading the individual difference correction data from the individual difference correction data storage unit 33 is performed, thereby executing the individual difference temperature compensation operation.

[0026] The logical slowdown circuit 36 ​​is a circuit that digitally lengthens or shortens the period of the reference signal by inputting a set or reset signal to each frequency division stage of the frequency division circuit 12 at a predetermined timing. The frequency adjustment control circuit 37 is a circuit that adjusts the oscillation frequency of the oscillation circuit 11 by adjusting the additional capacitance of the oscillation circuit 11. When the additional capacitance of the oscillation circuit 11 is increased, the oscillation frequency decreases, so that the time can be delayed. Conversely, when the additional capacitance is decreased, the oscillation frequency increases, so that the time can be advanced. In this manner, in this embodiment, the logical slowdown / fastening circuit 36 ​​and the frequency adjustment control circuit 37 are combined to adjust the rate.

[0027] [Frequency divider circuit] The frequency divider circuit 34 has a structure in which n flip-flop circuits 100 are connected in series in n stages. The flip-flop circuits 100 are, for example, quasi-static T flip-flop circuits. In the following description, the flip-flop circuits 100 are referred to as FF circuits 100. In the frequency divider circuit 34, the input terminal of the first-stage FF circuit 100 is connected to the temperature sensor 31, and the output terminal of the first-stage FF circuit 100 is connected to the input terminal of the second-stage FF circuit 100. Similarly, when n is 3 or more, the output terminal of the (n-1)th stage FF circuit 100 is connected to the input terminal of the nth FF circuit 100, and the output terminal of the (n-1)th stage FF circuit 100 is connected to the output terminal of the nth FF circuit 100.

[0028] When the first clock signal output from the temperature sensor 31 is input to the frequency divider circuit 34, the output of each FF circuit 100 in the frequency divider circuit 34 changes sequentially, and the number of signals input to the frequency divider circuit 34 can be counted depending on whether the output of each FF circuit 100 is at a high level or a low level. That is, the frequency divider circuit 34 functions as a binary counter.

[0029] 3, the FF circuit 100 constituting the frequency divider circuit 34 has clocked inverters 110, 130, 140, and 150, and inverters 120 and 160. The inverters 120 and 160 are respectively formed by combining AND circuits 120A and 160A with NOR circuits 120B and 160B. Each of the clocked inverters 110, 130, 140, and 150 is provided with either an input terminal C or an input terminal XC. Here, the signal input to the input terminal C, i.e., the input signal C, is the output signal of the temperature sensor 31. Also, the signal input to the input terminal XC, i.e., the input signal XC, is a signal obtained by inverting the input signal C. Further, a set terminal S and a reset terminal XR are connected to the inverters 120 and 160, respectively.

[0030] Explaining the connection relationship between the clocked inverters 110, 130, 140, 150 and the inverters 120 and 160, the output terminal of the clocked inverter 110 is connected to the input terminal of the inverter 120, specifically, the input terminal of the AND circuit 120A, and the output terminal of the clocked inverter 130. An output terminal of the inverter 120 , specifically an output terminal of a NOR circuit 120 B, and an input terminal of the clocked inverter 130 are connected to an input terminal of a clocked inverter 140 . The output terminal of clocked inverter 140 is connected to the input terminal of clocked inverter 110, the output terminal of clocked inverter 150, and the input terminal of inverter 160, specifically, the input terminal of AND circuit 160A, and the output terminal Q. The input terminal of the clocked inverter 150 and the output terminal of the inverter 160, specifically the output terminal of the NOR circuit 160B, are connected to an output terminal XQ.

[0031] As a result, an output signal Q is output from output terminal Q, and an output signal XQ is output from output terminal XQ in synchronization with input signal C. The output signal Q has twice the period of the input signal C, i.e., its frequency is half, and the output signal XQ is a signal obtained by inverting the H and L of the output signal Q. A reset terminal XR is connected to the input terminals of the AND circuits 120A and 160A of the inverters 120 and 160, and a set terminal S is connected to the input terminals of the NOR circuits 120B and 160B. The clocked inverters 110, 130, 140, 150 and the inverters 120, 160 are each constituted by a floating body type partially depleted transistor formed in a semiconductor layer on an insulating layer, i.e., an FB-PD-SOI-MOSFET. Here, FB (Floating Body) means a floating body type in which the body region is not electrically connected to other regions and the potential is floating, and PD (Partially Depleted) means a partially depleted type in which a neutral region with majority carriers exists in the body region. SOI (Silicon on Insulator) means a structure in which a silicon thin film is stacked on an insulating film, and MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) means a metal-oxide semiconductor field effect transistor.

[0032] 4 is a circuit diagram showing an example of the configuration of the clocked inverter 110. The clocked inverter 110 has N-channel FB-PD-SOI-MOSFETs 111 and 112 and P-channel FB-PD-SOI-MOSFETs 113 and 114. Among these, MOSFETs 111 and 113 constitute the inverter main body, with the source of MOSFET 111 connected to, for example, ground potential VSS and the drain of MOSFET 113 connected to, for example, power supply potential VDD. In addition, the gates of MOSFETs 111 and 113 are each connected to input terminal A of the clocked inverter 110. The MOSFET 112 is connected between the MOSFET 111 and the output terminal B, and the MOSFET 114 is connected between the MOSFET 113 and the output terminal B. The gate of the MOSFET 112 is connected to the input terminal XC, and the gate of the MOSFET 114 is connected to the input terminal C.

[0033] In this clocked inverter 110, when input signal C is L, i.e., when input signal XC is H, both MOSFETs 112 and 114 are on, so that clocked inverter 110 functions as an inverter, as its name suggests, that is, an element that outputs an L signal from output terminal B if the signal input to input terminal A is H, and outputs an H signal from output terminal B if the signal input to input terminal A is L. On the other hand, when the input signal C is H, i.e., when the input signal XC is L, both MOSFETs 112 and 114 are turned off, so that the drain of MOSFET 111 is electrically isolated from the output terminal B, and the source of MOSFET 113 is electrically isolated from the output terminal B. Therefore, the potential of the output terminal B is maintained as it is. The other clocked inverters 130, 140, and 150 shown in FIG.

[0034] FIG. 5 is a circuit diagram showing an example of the configuration of an inverter 120 configured with a composite gate of an AND circuit 120A and a NOR circuit 120B. The inverter 120 has N-channel type FB-PD-SOI-MOSFETs 121-123 and P-channel type FB-PD-SOI-MOSFETs 124-126. The MOSFETs 121 and 125 constitute the inverter body, and the source of the MOSFET 121 is connected to, for example, a ground potential VSS, and the drain of the MOSFET 125 is connected to, for example, a power supply potential VDD. The gates of the MOSFETs 121 and 125 are connected to the input terminal A of the inverter 120. The MOSFET 122 is connected between the MOSFET 121 and the output terminal B, and the MOSFET 124 is connected between the MOSFET 125 and the output terminal B. The gate of the MOSFET 122 is connected to a reset terminal XR, and the gate of the MOSFET 124 is connected to a set terminal S. The MOSFET 123 is connected between the ground potential VSS and the output terminal B. The MOSFET 126 is connected between the power supply potential VDD and the MOSFET 124, and is connected in parallel with the MOSFET 125. The gate of the MOSFET 123 is connected to a set terminal S, and the gate of the MOSFET 126 is connected to a reset terminal XR.

[0035] As shown in FIG. 5, in this inverter 120, when the signal input to the set terminal S is L and the signal input to the reset terminal XR is H, the MOSFETs 122 and 124 are turned on and the MOSFETs 123 and 126 are turned off, so that the inverter 120 functions as an inverter, as its name suggests. On the other hand, when the signal input to the set terminal S is H and the signal input to the reset terminal XR is L, the MOSFETs 122 and 124 are turned off and the MOSFETs 123 and 126 are turned on, so that the potential of the output terminal B becomes the ground potential VSS regardless of whether the signal input to the input terminal A is H or L. This makes it possible to initially set the potential of the output terminal B. The other inverter 160 shown in FIG.

[0036] [Temperature compensation processing] Next, the temperature compensation process of this embodiment will be described. In order to reduce power consumption, IC10, which has a temperature compensation function, controls the timing of operation of temperature sensor 31 and achieves low power consumption by operating temperature sensor 31 for only a short period, i.e., one second, during a certain long period, i.e., the first period. 6, the first clock signal output from the temperature sensor 31 is output for one second in a first cycle, that is, a cycle of 160 seconds. Therefore, the frequency divider circuit 34 counts the first clock signal output from the temperature sensor 31 during the one second that the temperature compensation circuit 30 operates. In this way, if you try to switch an FB type MOSFET that has been kept in the OFF state for a long period of time, such as 100 seconds or more, or that has been kept in the ON state for a long period of time, the history effect will make the operation unstable, causing the circuit to not work and resulting in a malfunction.

[0037] Therefore, in this embodiment, a second clock signal having a second period of 20 seconds is output from the frequency divider circuit 12 to the frequency divider circuit 34, and as shown in the lower part of FIG. 6, the frequency divider circuit 34 including one or more FF circuits 100 using FB type MOSFETs is operated by the first clock signal having a period of 160 seconds and the second clock signal having a period of 20 seconds. That is, as shown in FIG. 7, the signal output from the temperature sensor 31 is the first clock signal, the signal output from the frequency divider circuit 12 is the second clock signal, these clocks are synthesized by an OR circuit 341, and this synthesized signal is input to the frequency divider circuit 34. The temperature sensor 31 outputs a first clock signal having a frequency corresponding to the measured temperature. The first clock signal is, for example, a signal of 8 kHz. The second clock signal is a 32768 Hz clock signal output from the oscillation circuit 11, or a divided signal obtained by dividing the signal by the frequency divider circuit 12. The examples shown in Figs. 6 and 7 are examples in which the output timing of a first clock signal with a 160-second cycle and a second clock signal with a 20-second cycle differ by 10 seconds. The second clock signal is output for 1 second at 20-second intervals starting 10 seconds after the first clock signal. For this reason, the frequency divider circuit 34 is driven for 1 second every 20 seconds. Furthermore, since the first clock signal is output between the second clock signals output at 20-second intervals, the second clock signal is input to the frequency divider circuit 34 150 seconds after the previous output of the first clock signal, the first clock signal is input 160 seconds later, and the second clock signal is input 170 seconds later. Based on the cycle of the first clock signal, 170 seconds later is the same as 10 seconds later, so the input of the clock signal shown in Fig. 6 is repeated and continues. In Fig. 6, the second clock signal is surrounded by a dotted line to distinguish it from the first clock signal.

[0038] When the frequency divider circuit 34 receives the composite signal of the first and second clock signals, it counts the composite signal. Meanwhile, the arithmetic circuit 35, to which the frequency divider circuit 34 outputs, is operated by the temperature compensation function control circuit 21 at the same timing as the output of the first clock signal, that is, for one second at 160-second intervals. Therefore, when the second clock signal is input to the frequency divider circuit 34, the output of the frequency divider circuit 34 is not processed by the arithmetic circuit 35. Therefore, the arithmetic circuit 35 obtains the count value obtained by counting the output signal of the temperature sensor 31, which is the first clock signal, by the frequency divider circuit 34, that is, a frequency signal corresponding to the temperature, and executes the temperature compensation function operation corresponding to the measured temperature.

[0039] [Effects of this embodiment] Since the frequency divider circuit 34 including the FB type MOSFET is driven at a fixed timing, specifically, in a 20-second cycle by the second clock signal, it is not necessary to drive the temperature sensor 31 in a 20-second cycle, compared to a case in which the temperature sensor 31 is driven in a 20-second cycle and the frequency divider circuit 34 is driven in a 20-second cycle by the first clock signal output from the temperature sensor 31, and therefore power consumption can be reduced. In addition, since the frequency divider circuit 34 is driven by the second clock signal at 20-second intervals, it is possible to prevent the frequency divider circuit 34 from malfunctioning due to the history effect of the FB MOSFET becoming unstable, as in the case where the frequency divider circuit 34 is not driven for a long period of time, for example, 100 seconds or more. That is, if the frequency divider circuit 34 is driven at long intervals of time, for example, 100 seconds or more, as shown in the left diagram of FIG. 8, the absolute value of the threshold voltage is low immediately after the frequency divider circuit 34 starts to be driven, so that a larger drain current Id flows, and there is a high possibility of malfunction. On the other hand, in this embodiment, since the frequency divider circuit 34 is driven at least at 20-second intervals, it is possible to prevent the absolute value of the threshold voltage from becoming low immediately after the frequency divider circuit 34 starts to be driven, as shown in the right diagram of FIG. 8, and the drain current Id can be maintained at a constant level, thereby preventing malfunction of the frequency divider circuit 34. Therefore, according to this embodiment, the frequency divider circuit 34 can be operated stably without significantly increasing power consumption.

[0040] Since the frequency divider circuit 34 is driven not only by the first clock signal output from the temperature sensor 31 but also by the second clock signal output from the frequency divider circuit 12, the circuit added to the IC 10 may be a small-scale circuit such as an OR circuit 341, and the chip size of the IC 10 can be prevented from increasing. Furthermore, compared to the conventional technology in which the threshold voltage of the FB type MOSFET constituting the FF circuit 100 of the frequency divider circuit 34 is changed according to the operating frequency, this can be achieved by adding a small-scale circuit, so that the addition of glass masks and manufacturing processes can be minimized, and increases in manufacturing costs can be suppressed.

[0041] In this embodiment, the frequency divider circuit 34 is driven at 20-second intervals by the second clock signal with a 20-second period output from the frequency divider circuit 12, and the frequency divider circuit 12 needs to generate and output a 20-second period signal. Here, since the frequency divider circuit 12 already generates a 20-second period signal to generate a 160-second period signal to be output to the temperature compensation function control circuit 21, there is no need to add a circuit to generate a 20-second period signal, and in this respect, an increase in manufacturing costs can also be suppressed.

[0042] It is the frequency divider circuit 34 configured with the FF circuit 100 including the FB type MOSFET that operates at 20 second intervals, and other circuits of the temperature compensation circuit 30 are not operated, so that an increase in power consumption can be suppressed. In addition, the second clock signal uses a signal obtained by dividing the signal from the oscillation circuit 11 by the frequency divider circuit 12, and outputting the second clock signal does not result in a large increase in power consumption. Furthermore, the second clock signal for stabilizing the operation of the FB type MOSFET uses signals from the oscillator circuit 11 and the frequency divider circuit 12, which are always driven, so there is no increase in current. In contrast, when the first clock signal output from the temperature sensor 31 is used, a current increase is expected because a signal that is originally operated only for 1 second every 160 seconds is used. The increase is due to the circuit of the temperature sensor 31, which has been operated in a 160-second cycle, being operated in a 20-second cycle, which is 1 / 8 of the cycle, so that the current consumption increases by 8 times. That is, in this embodiment, the second clock signal is generated and output using the oscillator circuit 11 and the frequency divider circuit 12, which are always driven, to drive the frequency divider circuit 34 at 20-second intervals, so that the current consumption can be reduced compared to when the temperature sensor 31, which is not always driven, is driven at 20-second intervals to drive the frequency divider circuit 34 at 20-second intervals.

[0043] The temperature sensor 31 consumes a larger current than the oscillation circuit 11 and the frequency divider circuit 12, so that the operation of the temperature sensor 31 can be minimized, and the current consumption can be reduced. The reason why the temperature sensor 31 consumes a larger current than the oscillation circuit 11 and the frequency divider circuit 12 is to ensure temperature compensation accuracy. The compensation accuracy of the clock 1 with a temperature compensation function requires compensation in units of 0.1°C. In other words, a frequency change of 1 Hz is required at least for a temperature change of 0.1°C, and therefore a large amount of current needs to flow, and the temperature sensor 31 consumes a larger current than the oscillation circuit 11 and the frequency divider circuit 12. Therefore, it is inappropriate to use the output signal of the temperature sensor 31 as the second clock signal for stably operating the frequency divider circuit 34, and the current consumption can be reduced by using the second clock signal output from the frequency divider circuit 12 as in this embodiment. As described above, according to this embodiment, it is possible to minimize an increase in current consumption without increasing the size of the circuit of the IC 10, and to achieve stable operation without increasing the number of manufacturing steps for the IC 10.

[0044] [Other embodiments] It should be noted that the present disclosure is not limited to the above-described embodiments, and modifications and improvements within the scope of the present disclosure that can achieve the object of the present disclosure are included in the present invention. For example, in the above embodiment, the temperature sensor 31 is the first circuit and the arithmetic circuit 35 is the second circuit, but the first circuit and the second circuit may have other configurations. That is, the first circuit may output a signal to a frequency divider circuit using an FB type MOSFET having an SOI structure, and the second circuit may receive a signal from the frequency divider circuit. For example, in a watch, there is a signal that adjusts the pulse width that drives a stepping motor, and this operates in a relatively long period such as a period of 320 seconds. Since there is a high possibility of malfunction occurring with such a long period, it is possible to prevent malfunction by using a circuit configuration that operates the circuit periodically as described above.

[0045] In the above embodiment, the first period is 160 seconds and the second period is 20 seconds, but the periods are not limited to these. The first period may be 100 seconds or more, and the second period may be less than 100 seconds. In particular, it is preferable that the second period is a short period of 50 seconds or less. Furthermore, it is preferable that the first period is a multiple of the second period, because if the first period is a multiple of the second period, the second clock signal of the second period can be generated in the process of generating the first clock signal of the first period by the frequency divider circuit 12, and there is no need to provide a special circuit for generating the second clock signal.

[0046] [Summary of this disclosure] The semiconductor device disclosed herein is characterized by comprising: a first circuit that is driven at a first period and outputs a first clock signal at the first period; a frequency divider circuit having a floating body type partially depleted transistor formed in a semiconductor layer on an insulating layer, and receiving as input a second clock signal having a second period shorter than the first period and the first clock signal; and a second circuit that receives as input a signal output from the frequency divider circuit in response to the input of the first clock signal. According to the semiconductor device of the present disclosure, the frequency divider circuit having the floating body type partially depleted transistor formed in the semiconductor layer on the insulating layer is driven by the second clock signal at a second period shorter than the first period, so that the frequency divider circuit can be prevented from malfunctioning. Therefore, according to the semiconductor device of the present disclosure, the frequency divider circuit can be operated more stably than when the frequency divider circuit is operated only by the first clock signal having the first period longer than the second period.

[0047] In the semiconductor device of the present disclosure, it is preferable that the first circuit is a temperature-sensitive oscillator circuit, the second circuit is an arithmetic circuit, the first clock signal is output from the temperature-sensitive oscillator circuit at a frequency corresponding to a measured temperature, and the second clock signal is a clock signal output from a crystal oscillator circuit or a divided signal obtained by dividing the clock signal. According to the semiconductor device of the present disclosure, the second clock signal uses a clock signal output from a constantly operating crystal oscillator circuit or a divided signal from a frequency divider circuit, so there is no need to provide an additional circuit for generating the second clock signal, and this can prevent the IC chip size from increasing and the power consumption from increasing. In addition, since the first circuit is a temperature-sensitive oscillator circuit, if the first circuit is driven at the first period, the first clock signal can be output from the first circuit at the first period. Furthermore, since the first circuit is driven at the first period, which is longer than the second period, and there is no need to drive at the second period, this can prevent the power consumption from increasing.

[0048] In the semiconductor device of the present disclosure, the frequency divider circuit is preferably a count circuit configured by connecting a plurality of flip-flop circuits in series and counting the first clock signal. According to the semiconductor device of the present disclosure, each flip-flop circuit of the frequency divider circuit can be operated stably, and therefore the number of inputs of the first clock signal output from the first circuit can be counted accurately.

[0049] The timepiece of the present disclosure is characterized by including the semiconductor device described above. According to the timepiece of the present disclosure, since it includes the semiconductor device, it is possible to operate the frequency divider circuit stably without significantly increasing power consumption. [Explanation of symbols]

[0050] 1...clock, 10...IC, 11...oscillating circuit, 12...frequency dividing circuit, 13...rotation detection circuit, 14...brake control circuit, 20...temperature compensation function unit, 21...temperature compensation function control circuit, 30...temperature compensation circuit, 31...temperature sensor, 32...temperature correction table memory unit, 33...individual difference correction data memory unit, 34...frequency dividing circuit, 35...arithmetic circuit, 36...logical speed reducing / speed reducing circuit, 37...frequency adjustment control circuit, 40...mainspring, 50...speed increasing gear train, 60...time display unit, 70...generator, 80...quartz oscillator, 90...rectifier circuit, 95...power supply circuit, 100...flip-flop circuit, 110, 130, 140, 150...clocked inverter, 120, 160...inverter, 111, 112, 113, 114, 121, 122, 123, 124, 125, 126...MOSFET, 120A, 160A...AND circuit, 120B, 160B...NOR circuit.

Claims

1. a temperature-sensitive oscillator circuit that is driven at a first period and outputs a first clock signal having a frequency corresponding to a measured temperature; a frequency divider circuit having a floating body type partially depleted transistor formed in a semiconductor layer on an insulating layer; an OR circuit which receives the first clock signal and a second clock signal, which is a clock signal output from a crystal oscillation circuit or a divided signal obtained by dividing the clock signal and drives the frequency divider circuit with a second period shorter than the first period, and outputs a composite signal of the first clock signal and the second clock signal to the frequency divider circuit; an arithmetic circuit that is driven at the first cycle and receives a signal output from the frequency divider circuit in response to an input of the first clock signal; The first clock signal is output at a timing different from the output timing of the second clock signal. A semiconductor device comprising:

2. 2. The semiconductor device according to claim 1, The frequency divider circuit is a count circuit configured by connecting a plurality of flip-flop circuits in series and counting the first clock signal. A semiconductor device comprising:

3. A timepiece comprising the semiconductor device according to claim 1 or 2.

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