Semiconductor device and method for manufacturing the same

Abstract

To provide a normally-off semiconductor device that can be manufactured by a simpler process than conventional ones.SOLUTION: A semiconductor device 1 has a stacked structure 18 having M (M is an integer of 1 or more) stacked units 180 between a barrier layer 16 and a gate electrode 19G. In the stacked structure 18, a composition formula of the composition layer of the i-th composition layer from the bottom (i is an integer between 1 and P) in the stacked unit 180 in which P composition layers from the first composition layer 181 to the Pth composition layer (P is an integer between 2 and more) are stacked in this order from bottom to top is expressed as InαiGa1-αiN (where 0≤α i≤1). A composition formula of the composition layer of the j-th (j is an integer between 1 and P) (however, i≠j) from the bottom in the stacked unit 180 is expressed as InαjGa1-αjN (however, 0≤α(j)≤1). For all combinations of i and j, αi≠αj is satisfied.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] One embodiment of the present invention relates to a normally-off semiconductor device. [Background technology]

[0002] Conventionally, various techniques have been proposed for realizing normally-off semiconductor devices. For example, a technique has been proposed for providing a structure for imparting normally-off characteristics to a semiconductor device. As an example of such a structure, a p-type semiconductor layer (for convenience, referred to as a "p-cap structure") is known as a cap layer provided directly under a gate electrode (see Patent Document 1). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2015-26629 A [Patent Document 2] JP 2017-126736 A Summary of the Invention [Problem to be solved by the invention]

[0004] However, as described below, in the conventional technology, the process of forming a structure (e.g., a p-cap structure) for imparting normally-off characteristics to a semiconductor device is complicated. An object of one aspect of the present invention is to realize a normally-off semiconductor device that can be manufactured by a process simpler than the conventional process. [Means for solving the problem]

[0005] In order to solve the above problems, a semiconductor device according to one aspect of the present invention is a semiconductor device including a barrier layer and a gate electrode, in which a direction from the barrier layer toward the gate electrode is referred to as an upward direction, and a direction opposite to the upward direction is referred to as a downward direction, and a structure in which P composition layers from a first composition layer to a Pth composition layer (P is an integer of 2 or more) are stacked in this order from the downward direction to the upward direction is referred to as a stacking unit, and the composition formula of the ith composition layer, which is the ith composition layer from the bottom in the stacking unit (i is an integer of 1 or more and P or less), is In α(i) Ga 1-α(i) N (where 0≦α(i)≦1), and the composition formula of the jth composition layer, which is the jth composition layer from the bottom in the stack unit (j is an integer of 1 or more and P or less) (where i ≠ j), is In α(j) Ga 1-α(j) N (where 0≦α(j)≦1), where α(i) ≠ α(j) for all combinations of i and j, and the semiconductor device comprises a stacked structure having M stacked units (M is an integer equal to or greater than 1) between the barrier layer and the gate electrode.

[0006] In order to solve the above-mentioned problems, a method for manufacturing a semiconductor device according to one aspect of the present invention is a method for manufacturing a semiconductor device including a barrier layer and a gate electrode, in which a direction from the barrier layer toward the gate electrode is referred to as an upward direction, and a direction opposite to the upward direction is referred to as a downward direction, and a structure in which P composition layers from a first composition layer to a Pth composition layer (P is an integer of 2 or more) are stacked in this order from the downward direction to the upward direction is referred to as a stacking unit, and the composition formula of the ith composition layer, which is the ith composition layer from the bottom in the stacking unit (i is an integer of 1 or more and P or less), is represented by the formula: In α(i) Ga 1-α(i) N (where 0≦α(i)≦1), and the composition formula of the jth composition layer, which is the jth composition layer from the bottom in the stack unit (j is an integer of 1 or more and P or less) (where i ≠ j), is In α(j) Ga 1-α(j)N (where 0≦α(j)≦1), where α(i) ≠ α(j) for all combinations of i and j, and the manufacturing method includes the steps of forming the barrier layer, forming a stacked structure having M stacked units (M is an integer equal to or greater than 1) on an upper surface of the barrier layer, and forming the gate electrode on an upper surface of the stacked structure. Effect of the Invention

[0007] According to one aspect of the present invention, it is possible to realize a normally-off type semiconductor device that can be manufactured by a process simpler than conventional processes. [Brief description of the drawings]

[0008] [Figure 1] 1 is a diagram showing a configuration of a semiconductor device according to a first embodiment. [Diagram 2] FIG. 1 is a diagram showing a configuration of a semiconductor device in a comparative example. [Diagram 3] 1 is a graph showing a depth profile of carrier concentration in a semiconductor device in a comparative example. [Figure 4] 1 is a graph showing a depth profile of carrier concentration in a semiconductor device according to an example. [Diagram 5] FIG. 13 is a diagram illustrating a difference in threshold voltage (Vth) between an example and a comparative example. [Figure 6] 1 is a graph showing the relationship of drain current density (Jd), gate current density (Jg), and mutual conductance (gm) to gate voltage (Vg) in an embodiment. [Figure 7] 1 is a graph showing Vd-Jd characteristics at each Vg in an embodiment. [Figure 8] 1 is a graph showing the relationship between Lgd (gate-drain distance) and Vw (off-state breakdown voltage) in an example. [Figure 9] 2 is a flow chart illustrating a method for manufacturing the semiconductor device of FIG. 1. [Figure 10] FIG. 13 is a diagram showing a configuration of a semiconductor device according to a second embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] [Embodiment 1] The semiconductor device 1 of the first embodiment will be described below. For convenience of explanation, the members having the same functions as those described in the first embodiment will be denoted by the same reference numerals in the following embodiments, and the explanations thereof will not be repeated. In addition, the explanations of matters similar to those of the known technology will be omitted as appropriate.

[0010] The configurations shown in each figure are merely examples for the convenience of explanation. Therefore, unless otherwise specified, the positional relationship of each member is not limited to the example of each figure. In addition, please note that each drawing is intended to roughly explain the shape, structure, and positional relationship of each member, and is not necessarily drawn to scale. Furthermore, unless otherwise specified, each material, each numerical value, and each composition formula described below in the specification are also merely examples. In this specification, the description "A to B" regarding two numbers A and B means "A or more and B or less" unless otherwise specified.

[0011] (Overview of Semiconductor Device 1) 1 is a diagram showing a configuration of a semiconductor device 1. The semiconductor device 1 in the first embodiment is a normally-off GaN-HEMT (High Electron Mobility Transistor). Each layer of the semiconductor device 1 may be formed by a known growth process.

[0012] FIG. 1 shows the growth direction of each layer in the growth process. Hereinafter, the growth direction is also referred to as the "upward direction". The growth direction is also the thickness direction of each layer of the semiconductor device 1. The upward direction can also be expressed as the direction from the barrier layer 16 to the gate electrode 19G described below. In this specification, the direction opposite to the upward direction is referred to as the "downward direction". The downward direction can also be expressed as the "depth direction of the semiconductor device 1".

[0013] Each layer of the semiconductor device 1 is deposited on a substrate 11. The substrate 11 is a support member that supports each layer of the semiconductor device 1. In the example of FIG. 1, the substrate 11 is a Si substrate (more specifically, a p-Si substrate). The semiconductor device 1 includes, from the upper side as viewed from the substrate 11, an initial layer 12, an intermediate layer 13, a strained superlattice layer 14, an undoped GaN layer 15, and a barrier layer 16, in this order. The semiconductor device 1 further includes an insulating film 17, a stacked structure 18, a source electrode 19S, a drain electrode 19D, and a gate electrode 19G.

[0014] In the example of FIG. 1, the initial layer 12 is an AlN layer having a thickness of 80 nm. The intermediate layer 13 is an AlGaN layer having a thickness of 30 nm. The strained superlattice layer 14 is an AlGaN / AlN strained superlattice layer having a thickness of 2.8 μm. The strained superlattice layer 14 is composed of 135 pairs of "15 nm thick AlGaN layers and 6 nm thick AlN layers."

[0015] Unlike the barrier layer 16 described below, the undoped GaN layer 15 is a semiconductor layer that is not doped with impurities (Al in the example of FIG. 1). The undoped GaN layer 15 has a thickness of 1 μm. The undoped GaN layer 15 may be formed by, for example, MOCVD (Metal-Organic Chemical Vapor Deposition).

[0016] The barrier layer 16 is an AlGaN layer having a thickness of 20 nm. The composition formula of the barrier layer 16 in the first embodiment is Al 0.2 Ga 0.8N. Unlike the undoped GaN layer 15 described above, the barrier layer 16 is a semiconductor layer doped with an impurity (Al in the example of FIG. 1). Therefore, the interface between the barrier layer 16 and the undoped GaN layer 15 is a semiconductor heterojunction interface (hereinafter, simply referred to as a "heterointerface"). Hereinafter, the interface is also referred to as an "AlGaN / GaN heterointerface." Thus, in the first embodiment, the undoped GaN layer 15 forms a heterojunction with the barrier layer 16. In the first embodiment, the composition of the barrier layer 16 is not particularly limited as long as the interface between the undoped GaN layer 15 and the barrier layer 16 is set to be a heterointerface.

[0017] A source electrode 19S, a drain electrode 19D, and a laminated structure 18, which will be described in detail below, are formed on the upper surface of the barrier layer 16. The gate electrode 19G is formed on the upper surface of the laminated structure 18. In other words, in the semiconductor device 1, the laminated structure 18 is formed so that the laminated structure 18 is interposed between the gate electrode 19G and the barrier layer 16. A manufacturing method for the semiconductor device 1 (in particular, a method for forming the laminated structure 18) will be described later.

[0018] The insulating film 17 is provided so as to cover the surface of the barrier layer 16 except for the portions where the source electrode 19S, the drain electrode 19D, and the laminated structure 18 are formed. In the example of FIG. 1, the insulating film 17 is a 100 nm-thick SiO 2 The insulating film 17 is also called a "passivation film."

[0019] In the example of the first embodiment, the source electrode 19S and the drain electrode 19D are ohmic electrodes (electrodes having ohmic characteristics). In contrast, the gate electrode 19G is a Schottky electrode (electrode having Schottky characteristics). However, as described later, the gate electrode 19G may be an ohmic electrode.

[0020] (Laminated structure 18) FIG. 1 further shows an enlarged view 100 of the laminated structure 18. Hereinafter, the laminated structure 18 will be described with reference to the enlarged view 100. The laminated structure 18 is an example of a laminated structure according to one embodiment of the present invention. The laminated structure means a structure in which M laminated units (M is an integer of 1 or more) are laminated. FIG. 1 shows an example of a laminated structure (laminate structure 18) in which M=2.

[0021] The laminate unit means a structure in which P composition layers from a first composition layer to a Pth composition layer (P is an integer of 2 or more) are laminated in this order from bottom to top (see also embodiment 3 described later). The laminate unit 180 in Fig. 1 is an example of a laminate unit according to one aspect of the present invention. In the laminate unit 180 in Fig. 1, the case where P=2 is illustrated.

[0022] In the following description, the first composition layer in the example of Fig. 1 will be referred to as "first composition layer 181" and the second composition layer as "second composition layer 182". The laminate unit 180 in the example of Fig. 1 has a structure in which the first composition layer 181 and the second composition layer 182 are laminated in this order from bottom to top. Note that the laminate unit 180 in the case of P=2 may be referred to as a "lamination pair".

[0023] When distinguishing between the two stacked units 180 in FIG. (i) The lower stacked unit 180 is referred to as the "first stacked unit 180a"; (ii) The upper stack unit 180 is referred to as the "second stack unit 180b."

[0024] In addition, when the two first composition layers 181 are to be distinguished from each other, (i) The first composition layer 181 of the first laminate unit 180a is referred to as the "first composition layer 181a in the first laminate unit," (ii) The first composition layer 181 of the second stack unit 180b is referred to as the "first composition layer 181b in the second stack unit."

[0025] Similarly, when distinguishing between two second composition layers 182, (i) The second composition layer 182 of the first stacking unit 180a is referred to as "the second composition layer 182a within the first stacking unit". (ii) The second composition layer 182 of the second stacking unit 180b is referred to as "the second composition layer 182b within the second stacking unit".

[0026] The composition formula of the first composition layer 181 is represented as In x Ga 1-x N. x is a number satisfying 0 < x ≤ 1. x represents the In content rate in the first composition layer 181. In the example of FIG. 1, the thickness of the first composition layer 181 is 8 nm. In FIG. 1, the case of x = 0.05 is illustrated. Therefore, the first composition layer 181 in the example of FIG. 1 is an In 0.05 Ga 0.95 N layer.

[0027] The composition formula of the second composition layer 182 is represented as In y Ga 1-y N (where y is a number satisfying 0 ≤ y < 1). y is a number satisfying 0 ≤ y < 1. y represents the In content rate in the second composition layer 182. In the example of FIG. 1, the thickness of the second composition layer 182 is 20 nm. The second composition layer 182 is formed to have an In content rate different from that of the first composition layer 181. That is, in the semiconductor device 1, the stacking unit 180 is formed so that the condition x ≠ y is satisfied. Since x ≠ y, the interface between the first composition layer 181 and the second composition layer 182 is a heterointerface.

[0028] As described later, it is preferable that the In content rate in the second composition layer 182 is lower than the In content rate in the first composition layer 181. That is, in the semiconductor device 1, it is preferable that the stacking unit 180 is formed so that the condition x > y is satisfied. In FIG. 1, the case of y = 0 (that is, the case where the second composition layer 182 does not contain In) is illustrated. Therefore, the second composition layer 182 in the example of FIG. 1 is a GaN layer.

[0029] As described above, the multilayer structure 18 is formed by stacking P InGaN composition layers (in the example of FIG. 1, two InGaN composition layers, the first composition layer 181 and the second composition layer 182) each having a different In content. For this reason, the multilayer structure 18 may be referred to as an InGaN multilayer structure. In the example of FIG. 1, the thickness of one multilayer unit 180 is 28 nm. Therefore, the thickness of the multilayer structure 18 is 56 nm.

[0030] According to the positional relationship of each component in FIG. 1, (i) the first composition layer 181 (in the example of FIG. 1, the first composition layer 181a in the first stack unit) is in contact with the barrier layer 16, and (ii) the second composition layer 182 as the P composition layer (in the example of FIG. 1, the second composition layer 182b in the second stack unit) is in contact with the gate electrode 19G.

[0031] (Comparative Example) Prior to describing the effects of the semiconductor device 1, a semiconductor device 1r will be described as a comparative example. FIG. 2 is a diagram showing the configuration of the semiconductor device 1r. For simplification, the insulating film 17, the source electrode 19S, the drain electrode 19D, and the gate electrode 19G are omitted from FIG. 2. The semiconductor device 1r is an example of a conventional GaN-HEMT. However, as described below, the semiconductor device 1r is a normally-on type device. As shown in FIG. 2, unlike the semiconductor device 1, the semiconductor device 1r does not have the stacked structure 18. For this reason, the semiconductor device 1r can also be expressed as a device in which the stacked structure 18 has been removed from the semiconductor device 1.

[0032] Fig. 3 is a graph showing the depth direction (downward) profile of the carrier concentration of the semiconductor device 1r. In the graph of Fig. 3, the vertical axis (N) represents the impurity concentration (dopant concentration), and the vertical axis (D) represents the depth. N can also be read as the carrier concentration.

[0033] The profile in FIG. 3 was obtained by the inventor of the present application (hereinafter simply referred to as the "inventor") by performing CV measurement (capacitance-voltage measurement) on the semiconductor device 1r. Therefore, N=Nd-Na. Nd represents the donor concentration, and Na represents the acceptor concentration. Nd can also be interpreted as the electron concentration, and Na as the hole concentration, respectively. In the comparative example, the origin (D=0) in the depth direction is the top surface of the barrier layer 16.

[0034] 2, in the semiconductor device 1r, a two-dimensional electron gas (also referred to as "2DEG") region is formed near the upper surface of the undoped GaN layer 15. The 2DEG region 260 in FIG. 2 is an example of the 2DEG region. Thus, in the semiconductor device 1r, the 2DEG region 260 is formed near the interface (AlGaN / GaN heterointerface) between the GaN layer 15 and the barrier layer 16.

[0035] Therefore, in the semiconductor device 1r, a high concentration of electrons exists near the AlGaN / GaN heterointerface. In the comparative example, it was confirmed that Nd is more dominant than Na over the entire depth direction shown in FIG. 3 (see the black circle plot in FIG. 3). In the comparative example, near the AlGaN / GaN heterointerface, the concentration of electrons was about 10 20 cm -3 There is a high concentration of electrons.

[0036] The normally-on characteristic of the semiconductor device 1r is due to the presence of a high concentration of electrons near the AlGaN / GaN heterointerface (in other words, the presence of the 2DEG region 260). For this reason, in the past, in order to impart normally-off characteristics to a semiconductor device, a process for compensating for the high electron concentration near the AlGaN / GaN heterointerface (e.g., a process for providing a p-cap structure) was required.

[0037] (Example) The inventors performed various characteristic measurements on the semiconductor device 1 for comparison with the comparative example. The main measurement results will be described below.

[0038] (Carrier concentration depth profile) Fig. 4 is a graph showing the depth profile of the carrier concentration of the semiconductor device 1. Fig. 4 is a diagram paired with Fig. 3. The profile in Fig. 4 was obtained by the inventor by performing CV measurement on the semiconductor device 1r. In the embodiment, the origin of the depth direction (D=0) is the upper surface of the stacked structure 18. In the example of Fig. 1, the origin of the depth direction is the upper surface of the second composition layer 182b in the second stacked unit.

[0039] 4, in the semiconductor device 1, it was confirmed that Na is more dominant than Nd in the stacked structure 18 (at D=0 to 0.056 μm) (see the plot of white circles in FIG. 4). That is, in the stacked structure 18, holes (maximum concentration: about 5×10 16 cm -3 ) was confirmed to have occurred.

[0040] 4, in the semiconductor device 1, similarly to the semiconductor device 1r, Nd is more prevalent than Na near the AlGaN / GaN heterointerface. However, unlike the semiconductor device 1r, the electron concentration near the AlGaN / GaN heterointerface in the semiconductor device 1 is about 5×10 16 cm -3 As described above, it was confirmed that the electron concentration in the vicinity of the AlGaN / GaN hetero-interface in the semiconductor device 1 is sufficiently smaller than that in the semiconductor device 1r.

[0041] As described above, the inventors have experimentally demonstrated that "in the semiconductor device 1, the high electron concentration in the vicinity of the AlGaN / GaN hetero-interface is compensated for by the holes generated in the stacked structure 18." In other words, the inventors have demonstrated that "in the semiconductor device 1, the 2DEG region in the vicinity of the AlGaN / GaN hetero-interface can be eliminated by providing the stacked structure 18."

[0042] (Threshold voltage) Next, the inventors measured the threshold voltage (Vth) of the semiconductor device 1r. Specifically, the inventors derived Vth based on the measured values ​​of the gate voltage (Vg) and drain current density (Jd) of the semiconductor device 1r. The inventors then measured Vth for the semiconductor device 1 using the same method as above.

[0043] In each measurement example described below, the source electrode of the semiconductor device 1 is grounded (the same applies to the semiconductor device 1r). In other words, the source voltage (Vs) is set to 0 V. For this reason, the gate voltage in this specification can be read as the "gate-source voltage." Similarly, the drain voltage (Vd) in this specification can be read as the "drain-source voltage."

[0044] 5 is a diagram illustrating the difference in Vth between the semiconductor device 1 and the semiconductor device 1r. In the graph of FIG. 5, the horizontal axis represents Vg, and the vertical axis represents Jd 1 / 2 As known to those skilled in the art, in the unsaturated region of a MOS (Metal-Oxide-Semiconductor) transistor, Jd 1 / 2 is proportional to (Vg-Vth). Therefore, the inventors have 1 / 2 Tangent to the rising part of the Vg axis (Jd 1 / 2 The value of Vg at the intersection with the horizontal line at =0 was derived as Vth.

[0045] As a result, it was confirmed that in the semiconductor device 1r, Vth = -2.0 V. The semiconductor device 1r satisfies the condition of Vth < 0 V, and is therefore a normally-on type device.

[0046] In contrast, it was confirmed that Vth = 0.53 V in the semiconductor device 1. That is, it was confirmed that the Vth of the semiconductor device 1 was shifted in the positive direction by 2.53 V with respect to the Vth of the semiconductor device 1r. As described above, it was confirmed that the semiconductor device 1 satisfies the condition of Vth > 0 V and is therefore a normally-off type device.

[0047] (Drain current density, gate current density, and transconductance) The inventors measured the relationships of the drain current density (Jd), the gate current density (Jg), and the mutual conductance (gm) with respect to the gate voltage (Vg) for the semiconductor device 1.

[0048] 6 is a graph showing the relationship of Jd, Jg, and gm to Vg in the semiconductor device 1. The sizes of the semiconductor device 1 on which the measurements in FIG. 6 were taken are as follows: ·Lsg (source-gate distance) = 4μm ·Lg(gate length)=1.5μm ·Lgd (gate-drain distance) = 4μm Wg (gate width) = 15 μm These dimensions are the same as those for the measurements in FIG.

[0049] gm is expressed by the following formula:

number

[0050] As shown in FIG. 6, in the semiconductor device 1, it was confirmed that a large Jd can be obtained when it is turned on (when Vg≧Vth). In addition, in the semiconductor device 1, it was confirmed that Jg is small both when it is turned off (when Vg<Vth) and when it is turned on. In particular, in the semiconductor device 1, it was confirmed that Jg is sufficiently smaller than Jd when it is turned on. As described above, in the semiconductor device 1, it was confirmed that a large drain current and a small gate leakage current are realized when it is turned on.

[0051] Furthermore, as shown in FIG. 6, in the semiconductor device 1, it was confirmed that gm tends to increase as Vg increases. Furthermore, in the semiconductor device 1, it was confirmed that gm has two peaks. The first peak of gm (pk1 in FIG. 6) exists at a position where Vg≒2V. The second peak of gm (pk2 in FIG. 6) exists at a position where Vg≒9V.

[0052] As shown in FIG. 6, the peak value of gm at pk1 (conveniently referred to as the "first peak value") is about 10 mS / mm. The peak value of gm at pk2 (conveniently referred to as the "second peak value") is about 40 mS / mm. Thus, the second peak value is about four times the first peak value. As described above, it was confirmed that the second peak value is sufficiently larger than the first peak value.

[0053] In a conventional normally-off type semiconductor device, it is common for gm to have a single peak. And it is common for the peak value at the single peak to be about the first peak value. In contrast, in the semiconductor device 1, gm further has pk2 in addition to pk1. Therefore, in the semiconductor device 1, a sufficiently high gm is realized as compared with a conventional normally-off type semiconductor device. As described above, in the semiconductor device 1, it was confirmed that higher performance is realized as compared with a conventional normally-off type semiconductor device.

[0054] At present, the mechanism by which pk2 occurs in the semiconductor device 1 has not been specifically elucidated. However, the inventors speculate that "the presence of the stacked structure 18 increases the amount of holes injected near the AlGaN / GaN heterointerface, and electrons are injected from the source electrode 19S to satisfy the electrical neutrality condition, causing pk2 to occur."

[0055] (Drain voltage - drain current density characteristics) Next, the inventors measured the drain voltage-drain current density characteristics (Vd-Jd characteristics) of the semiconductor device 1. Specifically, the inventors increased the Vg value by 1 V in a range from 1 V to 10 V (i.e., set ΔVg=+1 V) and measured the Vd-Jd characteristics for each Vg.

[0056] Figure 7 is a graph showing the measurement results of the Vd-Jd characteristics at each Vg. As shown in Figure 7, it was confirmed that Jd tends to increase with increasing Vg. It was also confirmed that at each Vg, Jd shifts from the non-saturation region to the saturation region with increasing Vd.

[0057] The maximum value of Jd in the example of Fig. 7 is about 175 mA / mm (see the case where Vg = 10 V). It was also confirmed from the measurement result of Fig. 7 that the semiconductor device 1 achieves a large drain current when it is on.

[0058] (Off voltage) Next, the inventors measured the off-state breakdown voltage (Vw) of the semiconductor device 1. Specifically, the inventors fabricated semiconductor devices 1 having various Lgd (gate-drain distances). Then, the inventors measured Vw for each of the semiconductor devices 1 under the condition of Vg=-1.5V (the semiconductor device 1 in its off-state). Note that Vw is the value of Vd at which breakdown of the semiconductor device 1 occurs under a constant value of Vg (in this example, Vg=-1.5V) at which the semiconductor device 1 is in its off-state.

[0059] FIG. 8 is a graph showing the measurement results regarding the relationship between Lgd and Vw. The sizes of each semiconductor device 1 for which the measurement in FIG. 8 was made are as follows: ·Lsg = 4 μm ·Lg = 1.5 μm ·Wg = 200 μm as follows.

[0060] In the example of FIG. 8, for each of two semiconductor devices 1 having the same specifications, the measured values of Vw are plotted for one Lgd. Then, based on these measured values, the inventor derived an approximate formula (interpolation formula) for the Lgd-Vw characteristics. In FIG. 8, the curve showing the approximate formula is drawn by a dotted line.

[0061] As shown by the curve in FIG. 8, it was confirmed that Vw tends to increase as Lgd increases. In the example of FIG. 8, among the plurality of fabricated semiconductor devices 1, it was confirmed that when Lgd is the largest (when Lgd = 40 μm), Vw is about 1000 V. Thus, it was confirmed that high breakdown voltage characteristics are realized in the semiconductor device 1.

[0062] (Method for manufacturing semiconductor device 1) FIG. 9 is a flowchart exemplifying the method for manufacturing the semiconductor device 1. The manufacturing method includes the processes S1 to S7 in FIG. 9. Since the processes up to the formation of the undoped GaN layer 15 are the same as the known techniques, the description thereof is omitted. Hereinafter, the case of manufacturing the semiconductor device 1 in FIG. 1 (the semiconductor device 1 with x = 0.05 and y = 0) will be described.

[0063] <S1: Formation of barrier layer> A barrier layer 16 is formed on the upper surface of the undoped GaN layer 15. Specifically, an AlGaN layer with a thickness of 20 nm is formed as the barrier layer 16 on the upper surface of the undoped GaN layer 15.

[0064] <S2: Formation of InGaN multilayer film> An InGaN multilayer film is formed on the upper surface of the barrier layer 16. The InGaN multilayer film refers to a multilayer film in which P composition layers from the first composition layer to the Pth composition layer are stacked in this order from bottom to top. The InGaN multilayer film in the first embodiment is a first composition layer 181 (In x Ga 1-x N layer) and the second composition layer 182 (In y Ga 1-y N layers) are laminated in this order from bottom to top. As described above, in the example of FIG. 1, the first composition layer 181 is an In 0.05 Ga 0.95 The second composition layer 181 is an N layer, and the second composition layer 182 is a GaN layer.

[0065] First, an 8 nm thick In layer is formed on the upper surface of the barrier layer 16. 0.05 Ga 0.95 N layer (first In 0.05 Ga 0.95 Next, the first In 0.05 Ga 0.95 A GaN layer (first GaN layer) having a thickness of 20 nm is formed on the upper surface of the N layer. 0.05 Ga 0.95 The N layer and the first GaN layer correspond to the first stack unit 180a described above. 0.05 Ga 0.95 The N layer corresponds to the first composition layer 181a in the first stack unit, and the first GaN layer corresponds to the second composition layer 182a in the first stack unit.

[0066] Then, an 8-nm-thick In layer was deposited on the top surface of the first GaN layer. 0.05 Ga 0.95 N layer (second In 0.05 Ga 0.95 Next, a second In 0.05 Ga 0.95 A 20 nm thick GaN layer (second GaN layer) is formed on the top surface of the N layer. 0.05 Ga 0.95 The N layer and the second GaN layer correspond to the second stack unit 180b described above. 0.05 Ga 0.95The N layer corresponds to the first composition layer 181b in the second stacking unit, and the second GaN layer corresponds to the second composition layer 182b in the second stacking unit, respectively.

[0067] <S3: Element isolation> By using the reactive ion etching (RIE) method and using a photoresist as a mask, etching for separating each of the plurality of semiconductor devices 1 (etching for element isolation) is performed. The etching conditions in S3 are as follows: · Etching gas: BCl 3 · Pressure: 3 Pa · Power: 10 W · Depth: 220 nm as follows.

[0068] <S4: Etching of InGaN multilayer film other than directly under gate region> Using a photoresist as a mask, the InGaN multilayer film is etched at locations other than directly under the gate region on the upper surface of the barrier layer 16. The etching conditions in S4 are as follows: · Etching gas: BCl 3 · Pressure: 3 Pa · Power: 5 W · Etching rate: 2.4 nm / min · Depth: 56 nm as follows. As a result of the etching in S4, the stacked structure 18 of FIG. 1 is formed in the gate region. From this, S2 and S4 may be collectively referred to as "processing for forming the stacked structure 18".

[0069] <S5: Formation of source electrode and drain electrode> Using the electron beam evaporation method, a Ti / Al / Ni / Au metal laminated film (film thickness: 15 nm / 80 nm / 12 nm / 40 nm) is evaporated onto the source region and the drain region on the upper surface of the barrier layer 16, respectively. Then, by processing the Ti / Al / Ni / Au metal laminated film by the lift-off method, the patterns of the source electrode 19S and the drain electrode 19D are formed.

[0070] Subsequently, by heating (heat treatment) with a lamp heating device, the source electrode 19S and the drain electrode 19D as ohmic electrodes are formed. The heating conditions in S5 are · Temperature: 850 °C · Heating time: 30 seconds · Atmosphere: N 2 as follows.

[0071] <S6: Formation of Gate Electrode> Using the electron beam evaporation method, a Ni / Au metal laminated film (film thickness: 30 nm / 150 nm) is evaporated onto the gate region. Specifically, the Ni / Au metal laminated film is evaporated onto the upper surface of the laminated structure 18 (more specifically, the upper surface of the second composition layer 182b in the second laminated unit). Then, by the lift-off method, the gate electrode 19G as a Schottky electrode is formed.

[0072] <S7: Formation of Insulating Film> Using the electron beam evaporation method, a SiO film with a thickness of 100 nm is evaporated to form the insulating film 17. 2 膜を蒸着することにより、絶縁膜17を形成する。

[0073] (Effect) In the conventional technology, in order to realize a semiconductor device with normally-off characteristics, it was necessary to form a structure (e.g., a p-cap structure) for imparting normally-off characteristics to the semiconductor device. However, in order to form a p-cap layer, it is necessary to achieve p-type conversion of a p-type semiconductor layer doped with Mg (hereinafter referred to as a "Mg-doped p-type semiconductor layer"). Specifically, activation annealing is required to activate Mg in the Mg-doped p-type semiconductor layer. Note that typical examples of Mg-doped p-type semiconductor layers include a "Mg-doped p-(Al)GaN layer" or a "Mg-doped p-(In)GaN layer."

[0074] However, the activation annealing is a heat treatment at high temperature for a long time (for example, at a temperature of 800 to 1000°C and for 30 minutes). In such a high-temperature environment, phenomena that lead to deterioration of the characteristics of the semiconductor device 1, such as desorption of nitrogen from the GaN layer, may occur. For this reason, the activation annealing requires advanced temperature and time control. Therefore, it can be said that the activation annealing for activating Mg is a complicated process.

[0075] As described above, the conventional technology has a problem that a structure (e.g., p-cap structure) for imparting normally-off characteristics to a semiconductor device cannot be formed by a simple process. In response to this problem, the inventor experimentally discovered a new finding that "by providing a stacked structure (e.g., stacked structure 18) instead of a p-cap structure, it is possible to impart normally-off characteristics to a semiconductor device" (see the above-mentioned measurement results).

[0076] As described above, the process of forming the stacked structure does not require activation annealing (or high-temperature, long-time heat treatment equivalent to activation annealing). Therefore, the stacked structure can be formed by a simple process. Thus, according to one aspect of the present invention, a stacked structure (a structure newly discovered by the inventors), which is a structure for imparting normally-off characteristics to a semiconductor device, can be formed by a process simpler than conventional processes. Thus, according to one aspect of the present invention, a normally-off type semiconductor device (e.g., semiconductor device 1) that can be manufactured by a process simpler than conventional processes can be realized.

[0077] Meanwhile, a recess gate structure is known as another example of a structure for imparting normally-off characteristics (see Patent Document 2). In the process of forming the recess gate structure, the barrier layer directly below the gate region is thinned by dry etching. However, there is a concern that the dry etching may cause damage to each layer of the semiconductor device. In addition, in order to prevent damage to each layer of the semiconductor device, it is necessary to precisely control the depth of the dry etching. For this reason, the process of forming the recess gate structure can also be said to be a complicated process.

[0078] In contrast, in one embodiment of the present invention, a normally-off type semiconductor device can be realized without forming a recess gate structure in the first place. From this point of view, it can be understood that in one embodiment of the present invention, a normally-off type semiconductor device can be manufactured by a process that is simpler than the conventional process.

[0079] 〔supplement〕 (1) The mechanism by which holes are generated in the laminate structure 18 (more specifically, the mechanism by which holes are generated in the laminate unit 180) has not yet been specifically elucidated. However, the inventors speculate that "holes are generated in the laminate unit 180 due to a polarization effect that occurs between the first composition layer 181 and the second composition layer 182 in the laminate unit 180."

[0080] The polarization effect is considered to occur at the interface (heterointerface) between the first composition layer 181 and the second composition layer 182. In other words, it is considered that the polarization effect can be generated by making the In content rates of the first composition layer 181 and the second composition layer 182 different. From the above, it is considered that holes can be generated in the stacked unit 180 by forming the stacked unit 180 so that the condition x≠y is satisfied.

[0081] (2) In Embodiment 1, the case where x>y was exemplified. Also, in Embodiment 1, the case where y = 0 was exemplified. However, as understood from the description in (1) above, in the semiconductor device according to one aspect of the present invention, x<y may be satisfied. Also, as understood from the same description, in the semiconductor device according to one aspect of the present invention, y≠0 may be satisfied.

[0082] However, the higher the In content rate in the InGaN composition layer, the greater the segregation of In or the surface unevenness in the InGaN composition layer. For this reason, the higher the In content rate in the InGaN composition layer, the greater the leakage current.

[0083] In addition, as described above, since the second composition layer 182 is the upper composition layer in the stacked unit 180, it is in contact with the gate electrode 19G. Considering these points, it is preferable that y (the In content rate of the second composition layer 182) is as small as possible. This is because when y is small, the leakage current in the gate electrode 19G can be reduced.

[0084] From the above, in the semiconductor device according to one aspect of the present invention, it is preferable that the stacked unit 180 is formed so that the condition x>y is satisfied. From the viewpoint of reducing the leakage current, it is particularly preferable that y = 0. Taking these matters into consideration, the inventor set y = 0 in Embodiment 1.

[0085] (3) In the first embodiment, the gate electrode 19G is a Schottky electrode. However, the gate electrode 19G may be an ohmic electrode. For example, in the above-mentioned S6, after deposition of a Ni / Au metal laminate film, a heat treatment is performed in an oxygen atmosphere at 600° C. for 30 minutes to form the gate electrode 19G as an ohmic electrode. The inventors have confirmed that even when the gate electrode 19G is formed as an ohmic electrode in this way, the same effects as those of the semiconductor device 1 of the first embodiment can be obtained.

[0086] (4) In the first embodiment, the first composition layer 181 has a thickness of 8 nm, and the second composition layer 182 has a thickness of 20 nm. However, it is needless to say that the thicknesses of the first composition layer 181 and the second composition layer 182 are not limited to the above example. For example, the first composition layer 181 may have a thickness of 3 to 10 nm. Furthermore, the second composition layer 182 may have a thickness of 10 to 30 nm.

[0087] [Embodiment 2] In the first embodiment, the case where M=2 is exemplified. However, as will be understood from the explanation of the first embodiment, in the semiconductor device according to one aspect of the present invention (more specifically, in the stacked structure according to one aspect of the present invention), M=1 may be used. Therefore, in the second embodiment, the case where M=1 is exemplified. Note that in the second embodiment, the case where P=2 is also exemplified.

[0088] Fig. 10 is a diagram showing the configuration of a semiconductor device 2 of embodiment 2. The semiconductor device 2 includes a multilayer structure 18V instead of the multilayer structure 18 of embodiment 1. Fig. 10 further shows an enlarged view 200 of the multilayer structure 18V.

[0089] As shown in the enlarged view 200, the multilayer structure 18V has one multilayer unit 180. The one multilayer unit 180 in FIG. 10 corresponds to the first multilayer unit 180a in the first embodiment. Therefore, the multilayer structure 18V can also be expressed as a multilayer structure in which the second multilayer unit 180b has been removed from the multilayer structure 18. In the semiconductor device 2, unlike the semiconductor device 1, the second composition layer 182a in the first multilayer unit as the P composition layer is in contact with the gate electrode 19G.

[0090] The inventors have confirmed that the semiconductor device 2 also provides the same effects as the semiconductor device 1 of the embodiment 1. That is, the inventors have confirmed that the stacked structure 18V also provides the same effects as the stacked structure 18.

[0091] However, the inventors confirmed that the semiconductor device 1 has a higher hole concentration in the stacked structure than the semiconductor device 2. That is, it was confirmed that a higher hole concentration can be achieved when M=2 compared to when M=1. This suggests that "the hole concentration can be improved by generating a polarization effect in more stacked units 180." From the above, it is considered preferable that M is 2 or more.

[0092] [Embodiment 3] In the above-mentioned embodiments 1 and 2, the case where P=2 has been exemplified. However, as described in embodiment 1, in a semiconductor device according to an aspect of the present invention (more specifically, in a stacked unit according to an aspect of the present invention), P may be 3 or more. A general case will be described below.

[0093] In the following description, the i-th composition layer from the bottom in the stack unit according to one embodiment of the present invention is referred to as the "i-th composition layer." i is an integer that is 1 or more and P or less. The composition formula of the i-th composition layer is In α(i) Ga 1-α(i)N, where α(i) represents the In content in the i-th composition layer. Note that 0≦α(i)≦1. The first composition layer 181 in the first and second embodiments is an example of the above-mentioned first composition layer (where i=1). Therefore, x in the first and second embodiments is an example of α(1). As described above, the first and second embodiments illustrate the case where α(1)=0.05.

[0094] Similarly, the jth composition layer from the bottom in the stack unit according to one embodiment of the present invention is referred to as the "jth composition layer." j is an integer of 1 or more and P or less, where i ≠ j. The composition formula of the jth composition layer is In α(j) Ga 1-α(j) N, where α(j) represents the In content in the j-th composition layer. Note that 0≦α(j)≦1. The second composition layer 182 in the first and second embodiments is an example of the second composition layer (where j=2). Therefore, y in the first and second embodiments is an example of α(2). As described above, the first and second embodiments illustrate the case where α(2)=α(P)=0.

[0095] As will be understood from the descriptions in the first embodiment, in the laminate unit according to one aspect of the present invention, it is sufficient that each composition layer is formed so that the condition α(i) ≠ α(j) is satisfied for all combinations of i and j. That is, in the laminate unit according to one aspect of the present invention, it is sufficient that each of the P composition layers (the first composition layer to the Pth composition layer) has a different In content.

[0096] By forming each composition layer as described above, the interface between any two adjacent composition layers in the stack unit becomes a heterointerface, which is believed to be effective in generating holes in the stack unit.

[0097] In addition, as will be understood from the respective descriptions in embodiment 1, in a laminate unit according to one aspect of the present invention, it is preferable that α(i)>α(i+1) holds for all i between 1 and P−1.

[0098] That is, in the laminate unit according to one aspect of the present invention, α(1)>α(2)>α(3)>…>α(P-1)>α(P) In other words, the multilayer unit according to one aspect of the present invention is preferably formed such that α(i) decreases from the bottom to the top (as i increases).

[0099] When α(1) to α(P) are set as described above, the Pth composition layer, which is the uppermost composition layer in the stack unit (i.e., the composition layer in contact with the gate electrode 19G), has the smallest In content among the P composition layers belonging to the stack unit. This makes it possible to reduce the leakage current in the gate electrode 19G. Note that, as described above, from the viewpoint of reducing the leakage current, it is particularly preferable that α(P)=0.

[0100] [Additional Notes] One aspect of the present invention is not limited to the above-described embodiments, and various modifications are possible within the scope of the claims. Embodiments obtained by appropriately combining the technical means disclosed in different embodiments are also included in the technical scope of one aspect of the present invention. [Explanation of symbols]

[0101] 1, 2 Semiconductor devices 15 Undoped GaN layer 16 Barrier Layer 18, 18V laminated structure 19G Gate electrode 180 Stacking Unit 180a First stacking unit (stacking unit) 180b Second stacking unit (stacking unit) 181 1st composition layer 181a: First composition layer in first laminate unit (first composition layer) 181b: First composition layer in second stack unit (first composition layer) 182 Second composition layer 182a: Second composition layer in first laminate unit (second composition layer, Pth composition layer) 182b: second composition layer in second stack unit (second composition layer, Pth composition layer)

Claims

1. A semiconductor device comprising a barrier layer and a gate electrode, A direction from the barrier layer toward the gate electrode is referred to as an upward direction, and a direction opposite to the upward direction is referred to as a downward direction. A structure in which P composition layers, from a first composition layer to a Pth composition layer (P is an integer of 2 or more), are stacked in this order from the bottom to the top, is referred to as a stacking unit, The composition formula of the ith composition layer, which is the ith composition layer from the bottom in the stacked unit (i is an integer of 1 or more and P or less), is In α（ｉ） G １－α（ｉ） N, where 0≦α(i)≦1, The jth composition layer, which is the jth composition layer from the bottom in the stack unit (j is an integer of 1 or more and P or less) (wherein i≠j), has a composition formula of In α（ｊ） G １－α（ｊ） N, where 0≦α(j)≦1, For all combinations of i and j, α(i) ≠ α(j), The semiconductor device includes a stacked structure having M stacked units (M is an integer of 2 or more) between the barrier layer and the gate electrode.

2. 2. The semiconductor device of claim 1, wherein α(i)>α(i+1) for all i greater than or equal to 1 and less than or equal to P-1.

3. 3. The semiconductor device of claim 1, wherein α(P)=0.

4. The semiconductor device of claim 1 , further comprising an undoped GaN layer in a heterojunction with the barrier layer.

5. 1. A method for manufacturing a semiconductor device having a barrier layer and a gate electrode, comprising: A direction from the barrier layer toward the gate electrode is referred to as an upward direction, and a direction opposite to the upward direction is referred to as a downward direction. A structure in which P composition layers, from a first composition layer to a Pth composition layer (P is an integer of 2 or more), are stacked in this order from the bottom to the top, is referred to as a stacking unit, The composition formula of the ith composition layer, which is the ith composition layer from the bottom in the stacked unit (i is an integer of 1 or more and P or less), is In α（ｉ） G １－α（ｉ） N, where 0≦α(i)≦1, The jth composition layer, which is the jth composition layer from the bottom in the stack unit (j is an integer of 1 or more and P or less) (wherein i≠j), has a composition formula of In α（ｊ） G １－α（ｊ） N, where 0≦α(j)≦1, For all combinations of i and j, α(i) ≠ α(j), The above manufacturing method includes: forming the barrier layer; forming a laminate structure having M (M is an integer of 2 or more) laminate units on an upper surface of the barrier layer; forming the gate electrode on the upper surface of the stacked structure.

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