Offset Vertical Interconnects and Compression Posts for Three-Dimensional Integrated Electrical Devices.

Abstract

An electrical device including a substrate (130), a dielectric layer (120) supported by the substrate, the dielectric layer having at least one vertical post (122) disposed within a via hole (123) in the dielectric layer, and at least one conductive vertical interconnect (126) laterally offset from the post. The post is configured to provide a non-tensioned state to a region of the electrical device underlying the post. The coefficient of thermal expansion (CTE) of the post may be configured to provide the non-tensioned state in combination with the CTE of the dielectric layer, such as a dielectric layer having a CTE equal to or greater than the coefficient of thermal expansion (CTE) of the post. The dielectric layer may have a CTE less than the CTE of the conductive vertical interconnect and may be arranged to provide a buffer against the tensile forces provided by the vertical interconnect.

Description

[Technical field]

[0001] Related Applications This application claims priority to U.S. Application No. 17 / 686,692, filed March 4, 2022, which claims the benefit of U.S. Provisional Application No. 63 / 159,749, filed March 11, 2021, both of which are incorporated by reference in their entireties.

[0002] Technical Field The present disclosure relates generally to electrical devices having electrical interconnect structures, and more particularly to electrical devices having vertical interconnects offset from compression posts, especially for three-dimensional integrated electrical devices such as planar infrared (IR) detectors operating at low temperatures. [Background technology]

[0003] Electrical devices, such as semiconductor integrated circuits (ICs) or other semiconductor devices, are typically fabricated in and / or on a substrate, such as a silicon wafer, resulting in an IC area, the size and density of which generally increases as the complexity of the IC increases. One recent trend in IC manufacturing is to increase the number and / or different types of ICs by vertically stacking ICs together and vertically interconnecting them. Typically, each vertically stacked IC may be a different size, may be made from a different sized wafer, may have a different function, may be made of different materials, etc.

[0004] Conventional methods for achieving the vertical stacking and integration approach of ICs include through direct or hybrid bonding processes. In general, after vertically stacking a desired number of individual ICs, the stacked electrical device assembly is subjected to a temperature treatment to induce diffusion between the structure(s) of the opposing ICs, resulting in a three-dimensional integrated electrical device structure with electrical connections throughout the stacked ICs. Summary of the Invention

[0005] Some vertically integrated electrical devices of the above types are intended to operate in temperature regimes far removed from standard ambient temperature (i.e., 25°C according to IUPAC standards). For example, some infrared detector types may operate at temperatures of approximately -200°C. This has been found to disrupt electrical communication between interconnect structures in the electrical device due to mismatches in the coefficient of thermal expansion (CTE) between different structures in the device. Furthermore, some electrical devices may incorporate brittle materials in their architecture, e.g., materials with low fracture toughness, such that tensile forces applied to the brittle materials can cause damage and / or prevent the proper operation of the materials.

[0006] Embodiments of the present disclosure provide vertical interconnect designs that reduce or eliminate damage and / or electrical interruptions caused by tensile strain due to thermal expansion and contraction during fabrication or operation of electrical devices, particularly three-dimensional integrated devices formed by wafer bonding techniques.

[0007] According to one aspect, an electrical device provides a design in which a conductive vertical interconnect structure is laterally offset from a via post, thereby placing the region under the post in a non-tensioned state, such as a neutral or compressed state, rather than in tension.

[0008] The posts can be configured to cooperate with a buffer layer that forms a via hole and at least partially surrounds the posts such that the posts do not exert tensile forces on the underlying regions below the posts upon expansion or contraction during manufacturing or operation.

[0009] To enable such a design, the buffer layer can have a coefficient of thermal expansion (CTE) that is equal to or greater than that of the posts over the entire temperature range that the device will experience from fabrication through operation.

[0010] The buffer layer may also provide a buffer against tensile forces imparted by the laterally offset vertical interconnects.

[0011] The region underlying the post may include an electrical contact pad, and a conductive connecting layer may extend laterally between the vertical interconnect and the contact pad underlying the post to enable electrical connection between the contact pad and the laterally offset vertical interconnect.

[0012] In certain applications, the three-dimensional integrated electrical device can include a photodetector bonded to a readout integrated circuit (ROIC). The photodetector can be, for example, a mercury cadmium telluride (Hg 1-x CD x In some IR sensors, KTe (also called "MCT") is used as the photoconductive material. MCT is an example of a brittle material that is susceptible to damage (e.g., defects, crack propagation, and / or interfacial failure) and / or electrical interruption (e.g., piezoelectric response) when subjected to a relatively small amount of tensile strain. For example, the K IC The fracture toughness was measured by microindentation testing to be approximately 0.20 MPa m 1 / 2 It could be.

[0013] Bonding electrical connections between wafers, including MCT wafers containing ROICs, typically requires robust conductive interconnect structures passing through dielectric insulating layers, which can result in individual electrical devices with total thickness of approximately 4 μm. However, conventional methods used to form interconnects for such 3D integrated detectors have been found to become unstable or fail when cooled below ambient room temperature, especially when cooled to the very low operating temperature of the devices, 76 K (−197° C.). This is believed to be due to a CTE mismatch in conventional designs, where conventional metal interconnect posts contract more than the surrounding dielectric layers, placing high tensile stresses on the contact pads and MCT layers.

[0014] According to one aspect of the present disclosure, it is desirable to construct electrical interconnects to minimize tensile strain on the brittle MCT material over a temperature range that includes the temperatures encountered during fabrication and operation, e.g., from about 70 K to 433 K, to enable good electrical construction during fabrication and operation.

[0015] More specifically, according to one aspect, described herein is an interconnect and corresponding post structure that overcomes at least the aforementioned problems associated with conventional designs by providing an electrical device that ensures good electrical contact between an ROIC and an MCT-based detector through dielectric and bond oxide layers without inducing tensile strain between the fragile MCT semiconductor contacts and their contact metal interfaces. Such designs can be extended to other II-VI materials, as they are also very fragile.

[0016] According to one aspect, an electrical device comprises a substrate, a dielectric layer supported by the substrate, the dielectric layer having at least one via hole and a vertical post in the at least one via hole, and at least one conductive vertical interconnect laterally offset from the post, the post being configured to impart a non-tensioned state to a region of the electrical device underlying the post.

[0017] According to an embodiment of any paragraph or paragraphs of this Summary, the dielectric layer has a coefficient of thermal expansion different from a coefficient of thermal expansion of the posts, and the dielectric layer is configured to at least partially surround and interact with the posts to impart a non-tensioned state to the regions underlying the posts.

[0018] According to an embodiment of any paragraph or paragraphs of this Summary, the dielectric layer has a coefficient of thermal expansion that is equal to or greater than the coefficient of thermal expansion of the posts.

[0019] According to an embodiment of any paragraph or paragraphs of this Summary, the dielectric layer has a coefficient of thermal expansion that is less than or equal to the coefficient of thermal expansion of the vertical interconnect.

[0020] According to an embodiment of any paragraph or paragraphs of this summary, the vertical interconnect overlies the dielectric layer and is vertically offset from the post.

[0021] According to an embodiment of any paragraph or paragraphs of this summary, the method further includes a bonding layer, the vertical interconnect being disposed in a via hole of the bonding layer, the bonding layer overlying at least a portion of the dielectric layer, and the bonding layer being disposed in the via hole of the dielectric layer to form a post.

[0022] According to an embodiment of any paragraph or paragraphs of this summary, the dielectric layer includes a first dielectric layer portion and a second dielectric layer portion at least partially overlying the first dielectric layer portion, a bonding layer at least partially overlying the second dielectric layer portion, the first dielectric layer portion being deposited to provide a neutral stress, the second dielectric layer portion being deposited to provide a tensile stress, and the bonding layer being deposited to provide a compressive stress.

[0023] According to an embodiment of any paragraph or paragraphs of this Summary, the first dielectric layer portion is AlN, the second dielectric layer portion is AlN, and the bonding layer is SiO x It is.

[0024] According to an embodiment of any paragraph or paragraphs of this Summary, a region of the electrical device underlying the post comprises a brittle material forming at least a portion of the substrate, the brittle material having a strength of at least 1 MPa m 1 / 2 Less than K IC Has fracture toughness.

[0025] According to an embodiment of any paragraph or paragraphs of this Summary, the brittle material includes mercury cadmium telluride.

[0026] According to an embodiment of any paragraph or paragraphs of this Summary, further comprising an electrical contact pad between the post and the brittle material.

[0027] According to an embodiment of any paragraph or paragraphs of this summary, further including an electrical contact pad underlying the post and an electrical connection extending from the electrical contact pad to the vertical interconnect to provide electrical communication therebetween.

[0028] According to an embodiment of any paragraph or paragraphs of this Summary, the electrical connection includes a conductive layer overlying a portion of the dielectric layer and extending up a sidewall of a via hole in the dielectric layer.

[0029] According to an embodiment of any paragraph(s) of this Summary, when the electrical device is in an operating state, the post provides a neutral or compressive state to the area underlying the post.

[0030] According to one aspect, a three-dimensional integrated electrical device comprises a first electrical device bonded and electrically integrated with a second electrical device, the three-dimensional integrated electrical device comprising: a bonding layer; a first dielectric layer and a second dielectric layer on either side of respective portions of the bonding layer; a first via hole and a second via hole in respective portions of the first dielectric layer and the second dielectric layer, the first via hole and the second via hole being disposed opposite each other, and the bonding layer being disposed within the first via hole and the second via hole to form a first post portion and a second post portion, respectively, of the three-dimensional integrated electrical device; a conductive vertical interconnect extending through the bonding layer, the vertical interconnect being laterally offset from the first post portion and the second post portion; a contact pad underlying at least a portion of the first post portion; and a conductor layer overlying at least a portion of the first dielectric layer and electrically connecting the contact pad to a first end of the vertical interconnect.

[0031] According to an embodiment of any paragraph or paragraphs of this summary, the first and second dielectric layers have a thermal expansion coefficient equal to or greater than a thermal expansion coefficient of the first and second post portions, respectively; the vertical interconnect has a thermal expansion coefficient greater than the first and second dielectric layers and greater than the bonding layer; at least the first post portion is configured to impart a non-tensioned state to an area underlying the contact pad; and at least the first dielectric layer underlies a first end of the vertical interconnect to provide a buffer against tensile stress imparted under the first end of the vertical interconnect.

[0032] According to an embodiment of any paragraph or paragraphs of this summary, the dielectric layer includes a first dielectric layer portion and a second dielectric layer portion at least partially overlying the first dielectric layer portion, and a bonding layer at least partially overlying the second dielectric layer portion, the first dielectric layer portion being deposited to provide a neutral stress, the second dielectric layer portion being deposited to provide a tensile stress, and the bonding layer being deposited to provide a compressive stress.

[0033] According to an embodiment of any paragraph or paragraphs of this Summary, the first dielectric layer portion is AlN, the second dielectric layer portion is AlN, and the bonding layer is SiO x and the post is SiO x wherein the vertical interconnect is copper and the region of the electrical device underlying the first post portion comprises mercury cadmium telluride.

[0034] According to an embodiment of any paragraph or paragraphs of this summary, the first electrical device is a photodetector and the second electrical device is a readout integrated circuit.

[0035] According to one aspect, a method for manufacturing an electrical device includes providing a substrate, forming a dielectric layer overlying at least a portion of the substrate, forming a via hole in the dielectric layer, forming a post in the via hole, and forming a conductive vertical interconnect laterally offset from the post, the post configured to impart a non-tensioned state to a region of the electrical device underlying the post.

[0036] The following description and accompanying drawings set forth certain exemplary embodiments of the invention. These embodiments are indicative, however, of but a few of the various ways in which the principles of the invention may be employed. Other objects, advantages and novel features in accordance with aspects of the invention will become apparent from the following detailed description when considered in conjunction with the drawings.

[0037] The accompanying drawings, which are not necessarily to scale, depict various aspects in accordance with the present disclosure. [Brief description of the drawings]

[0038] [Figure 1] FIG. 1 is a schematic diagram of a first conventional electrical device and a second conventional electrical device prepared for three-dimensional integration. [Diagram 2] 2 is a schematic diagram of an initial contact state between the first and second conventional electrical devices of FIG. 1 at standard ambient temperature; [Diagram 3] FIG. 2 is a schematic diagram of high temperature bonding and three-dimensional integration of the first conventional electrical device of FIG. 1 with the second conventional electrical device. [Figure 4] FIG. 4 is a schematic diagram of the conventional three-dimensional integrated device of FIG. 3 when cooled below standard ambient temperature after high temperature bonding. [Figure 5A] 1A-1D are schematic cross-sectional views illustrating exemplary process steps for forming an exemplary electrical device according to one embodiment. [Figure 5B] 1A-1D are schematic cross-sectional views illustrating exemplary process steps for forming an exemplary electrical device according to one embodiment. [Figure 5C]1A-1D are schematic cross-sectional views illustrating exemplary process steps for forming an exemplary electrical device according to one embodiment. [Figure 5D] 1A-1D are schematic cross-sectional views illustrating exemplary process steps for forming an exemplary electrical device according to one embodiment. [Figure 5E] 1A-1D are schematic cross-sectional views illustrating exemplary process steps for forming an exemplary electrical device according to one embodiment. [Figure 5F] 1A-1D are schematic cross-sectional views illustrating exemplary process steps for forming an exemplary electrical device according to one embodiment. [Figure 5G] 1A-1D are schematic cross-sectional views illustrating exemplary process steps for forming an exemplary electrical device according to one embodiment. [Figure 5H] 1A-1D are schematic cross-sectional views illustrating exemplary process steps for forming an exemplary electrical device according to one embodiment. [Figure 5I] 1A-1D are schematic cross-sectional views illustrating exemplary process steps for forming an exemplary electrical device according to one embodiment. [Figure 5J] 1A-1D are schematic cross-sectional views illustrating exemplary process steps for forming an exemplary electrical device according to one embodiment. [Figure 5K] 1A-1D are schematic cross-sectional views illustrating exemplary process steps for forming an exemplary electrical device according to one embodiment. [Figure 5L] 1A-1D are schematic cross-sectional views illustrating exemplary process steps for forming an exemplary electrical device according to one embodiment. [Figure 5M] 1A-1D are schematic cross-sectional views illustrating exemplary process steps for forming an exemplary electrical device according to one embodiment. [Figure 5N] 1A-1D are schematic cross-sectional views illustrating exemplary process steps for forming an exemplary electrical device according to one embodiment. [Figure 5O] 1A-1D are schematic cross-sectional views illustrating exemplary process steps for forming an exemplary electrical device according to one embodiment. [Figure 5P] 1A-1D are schematic cross-sectional views illustrating exemplary process steps for forming an exemplary electrical device according to one embodiment. [Figure 5Q] 1A-1D are schematic cross-sectional views illustrating exemplary process steps for forming an exemplary electrical device according to one embodiment. [Figure 5R] 1A-1D are schematic cross-sectional views illustrating exemplary process steps for forming an exemplary electrical device according to one embodiment. [Figure 6] 8 is a schematic cross-sectional view showing the electrical device of FIG. 5R aligned with another electrical device in preparation for three-dimensional integration to yield the three-dimensional integrated device shown in FIG. 7. [Figure 7] 1 is a schematic cross-sectional view of an exemplary three-dimensional integrated device according to an embodiment of the present disclosure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0039] The principles and aspects of the present disclosure have particular application to electrical devices such as integrated circuit (IC) devices, more specifically vertically integrated semiconductor integrated circuit (IC) devices including application specific integrated circuits (ASICs), focal plane arrays and intelligent image sensors, memory chips, monolithic microwave integrated circuits (MMICs), infrared electrical devices (e.g., infrared detectors), antenna circuits, striplines, power distribution networks, and the like, and will be described primarily in this context below. However, it will be understood that the principles and aspects of the present disclosure are generally applicable to other electrical devices or circuits in which it is desirable to provide an aluminum nitride tensile layer to balance forces and thereby control the amount of bending deformation in such devices. Non-limiting examples of such electrical devices may include non-semiconductor devices such as passive radio frequency (RF) circuits (e.g., filters or antenna arrays), or other semiconductor devices such as diodes, photovoltaic cells, transistors, sensors, and the like. The exemplary method of forming the exemplary electrical device may also be applicable to vertically integrating both active and passive electrical devices.

[0040] 1-4, there is shown a schematic diagram of a conventional three-dimensional integrated device 10 including a readout integrated circuit (ROIC) 12 and a photodetector 14. As shown, the ROIC 12 includes a metal vertical interconnect 16 in a via hole that extends through a bonding layer 18 supported by a substrate 20. Also shown, the conventional photodetector 14 includes a corresponding metal vertical interconnect 22 that extends in a via hole that extends through a bonding layer 24 supported by a substrate 26. The substrate 26 of the photodetector 14 is made of mercury cadmium telluride (HgTe) as the photoconductive material for the sensor. 1-x CD x Te) (also referred to as "MCT"), in order to provide an electrical connection between the MCT material and the metal interconnect 22. Metal contact pads 27 overlie the MCT layer (also referenced in this figure by reference numeral 26) to provide an electrical connection between the MCT material and the metal interconnect 22.

[0041] As shown in Figure 1, each of the interconnects 16 of the ROIC 12 and the interconnects 22 of the photodetector 14 may have a concave profile 28, 30, respectively, due to chemical mechanical polishing (CMP) during processing of each device 12, 14. Figure 2 shows the photodetector 14 and the ROIC 12 in contact with each other and bonded at the interfaces of the respective bonding layers 18, 24. As shown, due to the concave profiles 28, 30, a gap 32 exists between the interfaces of the respective interconnects 16, 22.

[0042] 3 illustrates an electrical device assembly in a high temperature annealed state. As shown, during the high temperature anneal, the metal interconnects 16, 22 expand more than the surrounding bonding layers 18, 24, closing the gap 32 therebetween and forming a compressive contact where the interconnects 16, 22 undergo diffusion across their interfaces and fuse into a single, integrated conductive post 34 that extends through the integrated bonding layers 36.

[0043] FIG. 4 illustrates the effect of cooling to below standard ambient temperature after the high temperature anneal shown in FIG. 3. As shown in FIG. 4, the integrated metal interconnect structure 34 contracts more than its surrounding integrated bonding layer 36, resulting in tensile stress (indicated by arrow T). This tensile stress increases significantly when the temperature is cooled to the very low operating temperature of the device, which may be about 76 K (-197°C). It has been found that the CTE mismatch between the metal interconnect structure(s) 34 and the surrounding insulating bonding layer(s) 36 can degrade or cause failure of the three-dimensional integrated device 10 when cooled to ambient room temperature, and more specifically, when cooled to the operating temperature of the device (e.g., 76 K). More specifically, the effect of this tensile stress is to cause distortion at the semiconductor interface. The performance of the electrical device 10 can be adversely affected by tensile strain, especially when applied to a brittle material such as MCT. For example, tensile strain applied to MCT material can affect performance by inducing a piezoelectric response. Alternatively or additionally, tensile strains can cause damage to the MCT material in the form of defects, crack propagation, and / or interfacial failure with the metal contact pads 27. The effects of these tensile strains can become more pronounced as the difference in CTE between the interconnect material and the surrounding insulator (e.g., bonding layer) increases.

[0044] As a comparative example of a conventional design, an interconnect structure 34 made of copper melts at 150° C. to form a single integrated vertical interconnect structure (also 34). If the bond between the bonding layers 36 does not separate, this is the starting volume and length to consider. When the part cools down from 150° C., the bonding layer 36 shrinks less than the Cu interconnect structure 34, so the interconnect is under high tensile stress. When the tensile stress on the Cu interconnect 34 reaches its yield strength, plastic deformation begins. The tensile stress required to initiate plastic deformation of Cu is about 300 MPa at ambient room temperature (25° C.) and about 322 MPa at 76 K. The value of the relative shrinkage of the Cu interconnect 34 as a function of temperature can be calculated based on its CTE and length. For example, Cu at 60 K shrinks by about −316 Å / μm. A 4 μm thick Cu interconnect 34 will shrink by approximately −2100 Å / μm over the temperature range from 423 K to 76 K, which may be approximately 4.5% more than the surrounding bonding layer 36 over the same temperature range. If the Cu interconnect 34 were allowed to peel away from the sidewall of the bonding layer 36 and stretch plastically, the residual tensile stress (yield strength) at 76 K would be approximately 330 MPa. This level of tensile stress imparted to the MCT region beneath the interconnect would exceed the fracture toughness of the MCT (approximately 0.20 MPa m 1 / 2 K IC ) will exceed that.

[0045] An exemplary electrical device that improves upon one or more deficiencies of conventional design(s) is described herein. Specifically, one embodiment provides an electrical device comprising a substrate, a dielectric layer supported by the substrate, the dielectric layer having at least one vertical post (made of a low CTE dielectric) disposed within a via hole in the dielectric layer, and at least one conductive vertical interconnect laterally offset from the post, where the dielectric post is configured to provide a non-tension state to a region of the electrical device underlying the post. According to one embodiment, the dielectric layer provides a CTE equal to or greater than the CTE of the dielectric post, thereby providing a non-tension state (e.g., a neutral or compressive force) to the region underlying the post. The dielectric layer may have a CTE less than the CTE of the conductive vertical interconnect structure and may be arranged to provide a buffer against the tensile force provided by the vertical interconnect structure. One embodiment also provides a method(s) of manufacturing such device(s) according to the above.

[0046] Referring first to FIG. 7, an exemplary three-dimensional integrated electrical device 110 is shown in accordance with one embodiment of the present disclosure. The exemplary state shown in FIG. 7 may be a low temperature operating state of the device, such as about 76 K. As shown, the exemplary three-dimensional integrated device 110 includes an exemplary first electrical device 112 bonded and electrically integrated with an exemplary second electrical device 212. The boundary between the first and second electrical devices is shown by a dashed line 116. However, it is understood that after bonding and three-dimensional integration (described below), the two electrical devices 112, 212 form a single three-dimensional integrated electrical device 110.

[0047] The first electrical device 112 includes a substrate 118, an electrically insulating dielectric layer 120 supported by the substrate 118, at least one vertical post 122 disposed in a via hole 123 in the dielectric layer 120, a bonding layer 124, and at least one conductive interconnect 126 laterally offset from the post 122 and extending through the bonding layer 124. In an exemplary embodiment, the first electrical device 112 is a semiconductor device in the form of a photodetector (also referred to as 112). In the illustrated embodiment, the photodetector 112 is an IR detector. The first electrical device 112 can correspond to one pixel of a photodetector array. The second electrical device 212 in the illustrated embodiment is a readout integrated circuit (ROIC), which can include some of the same or similar structures as the photodetector 112, as described in more detail below.

[0048] In the illustrated embodiment, the substrate 118 supporting the dielectric layer 120, the posts 122, the interconnects 126, and the bonding layer 124 may include a photoconductor material layer 128 that at least partially overlies and is supported by a lower substrate layer 130. In an exemplary embodiment, the photoconductor material 128 is mercury cadmium telluride (Hg 1-x CD x Te) (also referred to as "MCT"), which forms a photoconductive layer (also 128) overlying a lower substrate layer 130. The lower substrate layer 130 may be any suitable substrate configured to support other layers, such as, for example, a silicon substrate. In the photodetector 112, incident IR photons may pass through the lower substrate layer 130 and interact with the MCT photoconductive layer 128 to generate a photocurrent. To provide the photoelectric effect, the photoconductive layer 128 may include an implant 132 that is oppositely doped to the photoconductive material 128. For example, the MCT photoconductive material 128 may be an n-type semiconductor and the implant 132 may be a p-type implant, such as arsenic.

[0049] The layers below the dielectric layer 120 are generally referred to herein collectively as simply the substrate 118, but may include additional layers depending on the type of electrical device and the method of manufacture. For example, one or more buffer layers may be provided between the MCT photoconductive layer 128 and the lower substrate layer 130, which may include cadmium and tellurium, and may improve the epitaxial growth of the overlying MCT photoconductive layer 128. Additionally, one or more passivation layers 134 may be formed on the photoconductive layer 128, which may include cadmium and tellurium, and may improve the interfacial bond between the MCT photoconductive layer 128 and the adjacent dielectric layer 120.

[0050] Between the MCT photoconductive layer 128 and the post 122 is an electrical contact pad 136 for transferring electricity generated in the MCT photoconductive layer 128 to the interconnect 126. Typically, the electrical contact pad 136 is disposed over the implant 132 in the MCT photoconductive layer 128 for transferring electrons generated at the pn junction by the photoelectric effect. The contact pad 136 may be formed of any suitable conductive material, including a conductive metal. In an exemplary embodiment, the contact pad 136 may include a metal layer (e.g., gold) and a barrier layer (e.g., TiN) overlying the metal layer to increase rigidity and / or prevent interdiffusion.

[0051] Because the vertical interconnect 126 is laterally offset from the post 122 and the contact pad 136 (for reasons explained in more detail below), an electrical connection 138 is provided to electrically couple the contact pad 136 to the vertical interconnect 126. In the illustrated embodiment, for example, the electrical connection 138 is formed as a conductive layer having a horizontal portion 138a that overlies a portion of the dielectric layer 120 and a vertical portion 138b that extends up a sidewall of the via hole 123 in the dielectric layer 120. The electrical connection 138 may be made of any suitable conductive material that may be formed on an electrical device in any suitable manner. For example, the electrical connection 138 may include the same material(s) as the contact pad 136 and may be formed simultaneously with the contact pad 136.

[0052] The vertical interconnect 126 is made of a conductive material that conducts electricity to an opposing interconnect 226 of the second electronic device 212 (e.g., the ROIC in the illustrated embodiment). In the illustrated embodiment, the interconnect 126 is made of copper (Cu), although other suitable materials such as nickel or indium may be used. In an exemplary embodiment, the interconnect 126 may be preferably made of a material that does not require high processing temperatures that would destroy the integrity of the material in the device, such as, for example, temperature sensitive MCT. As shown, the interconnect 126 is formed in a via hole 127 in the bonding layer 124, which may be accomplished in any suitable manner. For example, an interconnect made of copper may have a thickness of approximately 16.65×10 -6 / K CTE.

[0053] In an exemplary embodiment, the bonding layer 124 is a conformal dielectric film having a flat surface. The bonding layer 124 provides a bond with an opposing bonding layer 224 of the second electrical device 212. This bond includes ambient room temperature bonding via van der Waals forces between the bonding layers 124, 224, which may be further enhanced by covalent fusion bonding at elevated temperatures. The bonding layer 124 is preferably made of an oxide, more specifically, silicon oxide (SiO x), or a non-metallic material such as silicon dioxide (e.g., fused silica or SiO2). The bonding layer 124 may be formed by any suitable technique, such as a deposition process including physical vapor deposition, reactive physical vapor deposition, chemical vapor deposition, plasma enhanced chemical vapor deposition, sputtering, or a spin-on glass process. By way of example and not limitation, SiO x The bonding layer 124 made of -6 / K CTE.

[0054] The vertical interconnect 126 (e.g., copper) and its surrounding bonding layer 124 (e.g., SiO x Due to the CTE mismatch between the MCT material and the photoconductive layer 128, tensile stresses are generated at both ends of the vertical interconnect structure 124 during cooling during fabrication (e.g., from about 150° C. to about 25° C.) or during operation (e.g., from about 25° C. to about −200° C.). These tensile stresses can exceed 300 MPa, which can adversely affect the brittle materials of the electrical device 112. For example, the MCT material of the photoconductive layer 128 is a brittle material, with a CTE of about 0.20 MPa m 1 / 2 K IC MCT has a low fracture toughness of 0.1 mm. However, some brittle materials, such as MCT, may have a higher compressive strength than tensile strength. Thus, to mitigate adverse effects on brittle materials during fabrication or operation at high or low temperatures, an exemplary first electrical device 112 including a brittle material (e.g., MCT) has a dielectric post 122 disposed above the contact pad 136 in a configuration that laterally offsets the vertical interconnect 126 from the interfacial contact pad 136 and imparts a non-tensioned state (e.g., neutral or compressive) to the underlying region of the MCT material 128 below the contact pad 136.

[0055] In an exemplary embodiment, to provide a non-tensioned state in the regions of the photoconductive layer 128 underlying the posts 122, the CTE of the dielectric layer 120 surrounding and constraining the posts 122 is configured to be approximately equal to or greater than the CTE of the posts 122. This is effectively the opposite of what occurs with the interaction of the interconnects 126 and bonding layer 124 during cooling and contraction, thus providing a neutral or compressive stress instead of a tensile stress.

[0056] The dielectric layer 120 may be formed in any suitable manner and using any suitable material or combination of materials that provides the desired interaction with the posts 122 to achieve the desired non-tensioned state. Additionally, the dielectric layer 120 may be provided as a buffer layer underlying the vertical interconnects 126, thereby absorbing tensile forces imparted by the vertical interconnects 126 to reduce or eliminate transmission of these forces to the underlying MCT photoconductive layer 128. It will be appreciated that the CTE and thickness of the dielectric layer 120 relative to the posts 122 and / or interconnects 126 may generally be selected to achieve the desired forces exerted on the photoconductive layer 128 or brittle materials (e.g., MCT) in the substrate 118.

[0057] In the exemplary embodiment, the insulating layer 120 is a multi-layer structure including an upper dielectric layer portion 140 and a lower dielectric layer portion 142. As shown, the via hole 123 for the post 122 extends through both layers 140, 142 such that a respective portion of the post 122 is surrounded by each of the upper and lower dielectric layer portions 140, 142. In this manner, the combined CTE of the respective dielectric layer portions 140, 142 constitutes an overall CTE of the dielectric layer 120 that is tailored relative to the CTE of the post 122 to provide the non-tensile stress state described above. As a non-limiting example, both dielectric layer portions 140 and 142 in the illustrated embodiment have a CTE of approximately 5×10 -6The dielectric layers 120 are made of aluminum nitride (AlN) with a CTE of 100 / K, but they are deposited in different ways to provide additional functionality (discussed in more detail below). Alternatively or additionally, a layer of aluminum oxide (Al2O3) can be used above or below the AlN layer(s) or by itself as the dielectric layer 120. The aluminum oxide layer has a CTE of about 8×10 -6 It may have a CTE of 0.15 / K.

[0058] In an exemplary embodiment, the different layer portions 140, 142 of the dielectric layer 120 may be adapted to provide an enhanced buffering effect against the tensile stress imparted by the interconnect 126. For example, depending on the deposition parameters, the lower dielectric layer 142 (e.g., AlN) may be deposited to have an inherent neutral stress, and the upper dielectric layer 140 (e.g., also AlN) may be deposited to have an inherent low tensile stress. Thus, the combination of these layers may facilitate improved buffering against the high tensile stress (e.g., 300 MPa or more) generated by the interconnect structure 126, thereby reducing or eliminating the tensile stress imparted to the underlying region (e.g., the photoconductive layer 128).

[0059] The posts 122 can be made in any suitable configuration with any suitable material or combination of materials to provide the desired interaction with the surroundings (e.g., the dielectric layer 120) to achieve a non-tensioned state of the area underneath the posts 122 (e.g., the photoconductive layer 128 via the contact pads 136). As previously mentioned, the non-tensioned state can be a neutral state or a compressive stress state. In an exemplary embodiment, the posts 122 are formed with an inherent compressive stress in the material to facilitate a compressive force underneath. For example, the posts 122 are made of compressible SiO x As shown in the illustrated embodiment, the bonding layer 124 overlying the dielectric layer 120 can also extend into the via hole 123 to form the post 122. Because compressible SiO x The layer is suitable as a bonding material and the CTE of the AlN dielectric layer (approximately 5×10 -6 / K) has a lower CTE (approximately 1.5×10 -6 / K). As a result, when the exemplary three-dimensional integrated device 110 is used at low temperatures (e.g., 60K to 90K), for example, the AlN dielectric layer 120 and the SiO x The difference in CTE between the posts 122 causes the MCT photoconductive layer 128 to be in a slightly compressive stress state rather than a tensile stress state. x The inherent compressive stress of the material can be modified based on deposition parameters to further promote a compressive state in the underlying MCT photoconductive layer 128. Additionally, as can be seen from the illustrated embodiment, using the same material for the bonding layer 124 and the posts 122 facilitates manufacturing since the bonding layer 124 and the posts 122 can be formed in the same deposition step.

[0060] 7, the second electrical device 212 is a ROIC in the illustrated embodiment and may have some of the same or similar features as the first electrical device 112, including a substrate 218, a dielectric layer 220 and a bonding layer 224 supported by the substrate 218, and at least one conductive interconnect 222 extending through the dielectric layer 220 and the bonding layer 224 into a via hole. The substrate 218 may include the ROIC circuitry and contact pads 236 or trace layers for receiving electrons from the photodetector 112 through the bonded interconnect structure. The bonding layer 224 may be a SiO 2 layer for bonding to the first electrical device 112. x etc. Interconnect 226 may be the same as interconnect 126 for compatibility in forming a single integrated vertical interconnect structure 150.

[0061] As shown in the illustrated embodiment, the second electrical device 212 also includes its interconnect 226 that is offset from the post 222. The post 222 in the illustrated embodiment is made of an adhesive layer material (e.g., SiO x), and dielectric layer 220 is formed of AlN or other suitable material that provides a CTE equal to or greater than the CTE of post 222. Thus, post 222 also induces a compressive force on its substrate 218. Because post 222 faces post 122, this can contribute to the compressive force imparted to substrate 118 of first electrical device 112. It will be appreciated that the above can be accomplished with post 122 alone, and not with post 222, if the CTE is designed to do so.

[0062] The three-dimensional integration of the first electrical device 112 and the second electrical device 212 can be accomplished in any suitable manner, such as by conventional three-dimensional integration techniques. For example, after preparation of each electrical device 112, 212, the bonding layers 124, 224 can be aligned and connected to each other at room temperature (approximately 25° C.), thereby forming initial van der Waals bonds. A high temperature anneal at approximately 150° C. can be performed to promote covalent fusion of the bonding layers 124, 224. During the high temperature anneal, the respective interconnects 126, 226 connect and fuse to each other to form a single, integrated interconnect structure 150. Thus, in this hybrid bonding process, the individually stacked electrical devices 112, 212 are bonded to each other and electrically integrated to form the exemplary three-dimensional integrated device 110.

[0063] 5A-5R, an exemplary method for fabricating an exemplary electrical device 112 to achieve the exemplary state of the three-dimensional integrated device 110 shown in FIG. 7 is illustrated.

[0064] Figure 5A shows an initial state in which a substrate 118 is provided, including a lower substrate layer 130 (e.g., silicon), a photoconductive layer 128 (e.g., MCT), and a passivation layer 134 (e.g., CdTe) (note that the thicknesses are not to scale). As shown, the MCT layer is epitaxially grown and the CdTe layer is deposited in-situ. Figure 5B shows the process of performing a hole-fill anneal (dashed lines) and etching fiducial markers 160 on the passivation layer 134.

[0065] Figure 5C shows the deposition of a bottom dielectric layer 142 (e.g., AlN) on the passivation layer 134. A photoresist layer 162 is then deposited on the dielectric layer 142. Figure 5D shows a PE window 164 developed in the photoresist layer 162. A reference PE window 166 is also developed in the photoresist layer 162.

[0066] Figure 5E shows dry etching the lower dielectric layer 142 (e.g., AlN) to extend the via hole 123 down to the lower dielectric layer 142. Figure 5F shows dry etching the passivation layer 134 (e.g., CdTe) to further extend the via hole 123. As shown, fiducial marker 166 also follows.

[0067] Figure 5G illustrates implanting an implant 132 (eg, arsenic) into the photoconductor layer 128. Figure 5H illustrates stripping the photoresist layer 162.

[0068] Figure 5I shows the process of activating the implant 132 (e.g., arsenic). Figure 5J shows the deposition of electrical contact pads 136 and an electrical connection layer 138 (redistribution layer). The redistribution layer is then patterned.

[0069] Figure 5K shows the deposition of a patterned PVD oxide (e.g., SiOx) that fills the via holes 123 and forms part of the posts 122. This layer also fills the areas between the patterned redistribution layer 138 and forms part of the posts 122. Figure 5L shows the chemical mechanical polishing and removal of the top of the patterned PVD oxide layer.

[0070] FIG 5M shows deposition of a PVD bond oxide (bonding layer 124) (e.g., SiOx). FIG 5N shows deposition of a photoresist layer 168. FIG 5O shows developing an offset via pattern by forming a window 170 in the photoresist layer. FIG 5P shows dry etching the bonding layer 124 to form a via hole 127.

[0071] Figure 5Q shows the removal of photoresist layer 168 and electroplating of interconnects 126 (e.g., indium or copper). Figure 5R shows chemical-mechanical polishing to remove the top layer and expose the bonding layer 124. Figure 5R shows the electrical device 112 ready for three-dimensional integration.

[0072] FIG. 6 illustrates the alignment of a first electrical device 112 (eg, a photodetector) and a second electrical device 212 (eg, a ROIC) for three-dimensional integration, as described above.

[0073] Although exemplary configurations of the exemplary electrical device 112 and / or three-dimensional integrated electrical device 110 are described above, alternative configurations may be used in accordance with the principles and aspects described herein. For example, while reference has been made primarily to MCT as the brittle material, it will be understood that other brittle materials may be used in other regions of the electrical device, in which case it may be desirable to tailor the structure of the device as described herein to provide the desired forces. Generally, brittle materials include K IC Fracture toughness of 1MPa m 1 / 2 This refers to materials that are less than

[0074] In general, an exemplary electrical device has been described herein that includes a substrate, a dielectric layer supported by the substrate, the dielectric layer having at least one vertical post disposed in a via hole in the dielectric layer, and at least one conductive vertical interconnect laterally offset from the post. The post is configured to provide a non-tensioned state to a region of the electrical device underlying the post. The coefficient of thermal expansion (CTE) of the post may be configured to provide a non-tensioned state in combination with the CTE of the dielectric layer, such as a dielectric layer having a CTE equal to or greater than the coefficient of thermal expansion (CTE) of the post. The dielectric layer may have a CTE less than the CTE of the conductive vertical interconnect and may be positioned to provide a buffer against the tensile forces provided by the vertical interconnect.

[0075] According to a general aspect of the present disclosure, an electrical device is provided that includes laterally offset vias with stress buffers and dielectric compression posts.

[0076] According to one embodiment, an exemplary electrical device comprises at least two parts that, in combination, provide a neutral state or compression to the MCT contact during cooling. The first part is an offset conductive via located laterally away from the MCT contact pad and connected thereto by a film line (a patterned lateral conductor). The second part is a dielectric compression post fabricated from a low CTE dielectric and located directly above the MCT contact pad. During cooling, the compression post is less likely to shrink than the surrounding bonding layer so as to maintain axial compression on the MCT contact pad, while tensile strain from the shrinking conductive via is isolated by the distance and buffered by the dielectric layer.

[0077] According to one embodiment, the SiO on the MCT contact pads x The filling post is surrounded by AlN / SiO x It has a lower CTE than the stack and maintains pressure (compression) on the MCT contact pads as the bond structure cools to an operating temperature, such as 76K.

[0078] According to one embodiment, the offset conductive interconnects are anchored to an AlN buffer layer that buffers the underlying MCT substrate from tensile strain.

[0079] It is understood that all range and ratio limits disclosed in the specification and claims can be combined in any manner. As used herein, the term "about" refers to any value within a range defined by up to ±10% variation of the stated value, for example, ±10%, ±9%, ±8%, ±7%, ±6%, ±5%, ±4%, ±3%, ±2%, ±1%, ±0.01%, ±0.0% variation of the stated value, and any intervening values ​​between such stated values.

[0080] As used herein, the term "essentially" when used in connection with a composition or material, such as "consisting essentially of," is understood to mean that the composition or material may contain trace amounts of components and / or impurities that do not affect the basic function of the composition or material.

[0081] It should be understood that references to "a," "an," and / or "the" may include one or more, and references to singular items may also include the plural items, unless otherwise specified. The term "and / or" should be understood to mean "either or both" of the elements so conjoined, i.e., elements that are conjunctive in some cases and disjunctive in other cases. Other elements other than the elements specifically identified by the "and / or" clause may optionally be present, whether associated with the elements specifically identified, unless expressly indicated to the contrary. Thus, as a non-limiting example, when used in conjunction with open-ended language such as "comprising," a reference to "A and / or B" may refer in one embodiment to A (optionally including elements other than B) without B, in another embodiment to B (optionally including elements other than A) without A, in yet another embodiment to both A and B (optionally including other elements), and so forth.

[0082] The word "or" should be understood to have the same meaning as "and / or" as defined above. For example, when separating items in a list, "or" or "and / or" should be interpreted as inclusive, i.e., including at least one, but also including two or more, of a number or list of elements, possibly including additional non-list items. Only terms clearly indicating the contrary, such as "only one of" or "exactly one of," can refer to the inclusion of exactly one element of a number or list of elements. In general, the term "or" as used herein shall only be interpreted as indicating exclusive alternatives (i.e., "one or the other but not both") when preceded by an exclusive term, such as "either," "one of," "only one of," or "exactly one of."

[0083] Transitional words such as "comprising," "including," "carrying," "having," "containing," "involving," "holding," "made of / made with," and the like, unless otherwise expressly stated, are understood to be open-ended, i.e., meaning including but not limited to.

[0084] Although the present invention has been shown and described with respect to a particular embodiment or embodiments, it will be apparent that equivalent changes and modifications will occur to those skilled in the art upon reading and understanding this specification and the accompanying drawings. In particular, with respect to the various functions performed by the above elements (components, assemblies, devices, compositions, etc.), the terms used to describe such elements (including references to "means") are intended, unless otherwise indicated, to correspond to any element that performs the particular function of the described element (i.e., is functionally equivalent), even if it is not structurally equivalent to the disclosed structure that performs the function in the exemplary embodiment or embodiments of the present invention illustrated herein. In addition, although certain features of the present invention may be described above only with respect to one or more of several exemplary embodiments, such features may be combined with other features of one or more of the other embodiments as desired or advantageous for any or a particular application.

Claims

1. A substrate; a dielectric layer supported by the substrate, the dielectric layer having a via hole and a vertical post in the via hole; a conductive vertical interconnect laterally offset from said vertical post; An electrical device comprising: the vertical post is configured to provide a non-tensioned condition to a region of the electrical device underlying the vertical post; The electrical device, wherein the dielectric layer has a thermal expansion coefficient different from a thermal expansion coefficient of the vertical post, and the dielectric layer is configured to at least partially surround the vertical post and interact with the vertical post to impart the non-tensioned state to the region of the electrical device underlying the vertical post.

2. The electrical device of claim 1 , wherein the coefficient of thermal expansion of the dielectric layer is greater than or equal to the coefficient of thermal expansion of the vertical posts.

3. The electrical device of claim 1 or 2, wherein the coefficient of thermal expansion of the dielectric layer is less than the coefficient of thermal expansion of the vertical interconnect.

4. The electrical device of any of claims 1 to 3, wherein the vertical interconnect overlies the dielectric layer and is vertically offset from the vertical post.

5. 5. The electrical device of claim 1, further comprising a bonding layer, the vertical interconnect being disposed in a via hole of the bonding layer, the bonding layer overlying at least a portion of the dielectric layer, and the bonding layer being disposed in the via hole of the dielectric layer to form the vertical post.

6. 5. The electrical device of claim 1, wherein the dielectric layer includes a first dielectric layer portion and a second dielectric layer portion at least partially overlapping the first dielectric layer portion, and a bonding layer at least partially overlapping the second dielectric layer portion, the first dielectric layer portion being deposited to provide a neutral stress, the second dielectric layer portion being deposited to provide a tensile stress, and the bonding layer being deposited to provide a compressive stress.

7. The first dielectric layer portion is AlN, the second dielectric layer portion is AlN, and the bonding layer is SiO ｘ 7. The electrical device of claim 6, wherein:

8. The region of the electrical device underlying the vertical post comprises a brittle material forming at least a portion of the substrate, the brittle material having a strength of at least 1 MPa m １／２ Less than K ＩＣ The electrical device according to any one of claims 1 to 7, which has fracture toughness.

9. The electrical device of claim 8 , wherein the brittle material comprises mercury cadmium telluride.

10. 10. The electrical device of claim 8 or 9, further comprising an electrical contact pad between the vertical post and the brittle material.

11. 10. The electrical device of claim 1, further comprising electrical contact pads underlying the vertical posts and electrical connections extending from the electrical contact pads to the vertical interconnects to provide electrical communication between the electrical contact pads and the vertical interconnects.

12. 12. The electrical device of claim 11, wherein the electrical connection comprises a conductive layer overlying a portion of the dielectric layer and extending over a sidewall of the via hole in the dielectric layer.

13. The electrical device of any preceding claim, wherein when the electrical device is in an operating state, the vertical post provides a neutral or compressive state to the area of ​​the electrical device underlying the vertical post.

14. 1. A three-dimensional integrated electrical device comprising a first electrical device bonded to and electrically integrated with a second electrical device, A bonding layer; a first dielectric layer and a second dielectric layer on either side of each portion of the bonding layer; a first via hole and a second via hole in each of the first and second dielectric layers, the first via hole and the second via hole being disposed opposite each other, and the bonding layer being disposed in the first via hole and the second via hole to form a first post portion and a second post portion of the three-dimensional integrated electrical device, respectively; a conductive vertical interconnect extending through the bonding layer, the vertical interconnect being laterally offset from the first post portion and the second post portion; and a contact pad underlying at least a portion of the first post portion; a conductor layer overlying at least a portion of the first dielectric layer and electrically connecting the contact pad to a first end of the vertical interconnect; The three-dimensional integrated electrical device.

15. the first and second dielectric layers having a coefficient of thermal expansion greater than or equal to a coefficient of thermal expansion of the first and second post portions, respectively; the vertical interconnect has a coefficient of thermal expansion greater than the coefficients of thermal expansion of the first and second dielectric layers and greater than a coefficient of thermal expansion of the bonding layer; At least the first post portion is configured to provide a non-tensioned condition to an area underlying the contact pad; 15. The three-dimensional integrated electrical device of claim 14, wherein at least the first dielectric layer underlies the first end of the vertical interconnect to provide a buffer against tensile stresses imposed under the first end of the vertical interconnect.

16. the first dielectric layer includes a first dielectric layer portion and a second dielectric layer portion at least partially overlying the first dielectric layer portion, the bonding layer at least partially overlying the second dielectric layer portion, 16. The three-dimensional integrated electrical device of claim 14 or claim 15, wherein the first dielectric layer portion is deposited to provide a neutral stress, the second dielectric layer portion is deposited to provide a tensile stress, and the bonding layer is deposited to provide a compressive stress.

17. The first dielectric layer portion is AlN, the second dielectric layer portion is AlN, and the bonding layer is SiO ｘ and the first post portion is SiO ｘ 17. The three dimensional integrated electrical device of claim 16, wherein said vertical interconnect is copper and a region of said electrical device underlying said first post portion comprises mercury cadmium telluride.

18. The three-dimensional integrated electrical device according to any one of claims 14 to 17, wherein the first electrical device is a photodetector and the second electrical device is a readout integrated circuit.

19. 1. A method for manufacturing an electrical device, comprising: Providing a substrate; forming a dielectric layer overlying at least a portion of the substrate; forming a via hole in the dielectric layer; forming a post in the via hole; forming a conductive vertical interconnect laterally offset from said post; Including, the post is configured to provide a non-tensioned condition to a region of the electrical device underlying the post; the dielectric layer has a thermal expansion coefficient different from that of the post, the dielectric layer being configured to at least partially surround the post and interact with the post to impart the non-tensioned state to the region of the electrical device underlying the post.

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