Method for forming a high resistivity handle support for a composite substrate - Patents.com

Abstract

A novel method for forming a high resistivity handle substrate (1) for a composite substrate is provided. The present invention relates to a method for forming a high resistivity handle substrate for a composite substrate, the method comprising providing a base substrate made of silicon, exposing the base substrate to a carbon-only precursor at sub-atmospheric pressure to form a polycrystalline silicon carbide layer of at least 10 nm on a surface of the base substrate, and growing a polycrystalline charge trapping layer on the carbon-containing layer.

Description

[Technical field]

[0001] The present invention relates to a high resistivity handle for a composite substrate. The present invention also relates to a method for forming such a handle substrate. [Background technology]

[0002] WO 2017 / 144821 describes a high resistivity handle substrate for a composite substrate including a charge trapping layer disposed on a base substrate. The composite substrate can be, for example, a silicon-on-insulator substrate including a silicon thin film transferred onto the handle substrate.

[0003] In one embodiment described in the above mentioned document, the charge trapping layer is made of an intermediate layer and a polycrystalline main layer. The intermediate layer is made of a silicon and carbon alloy (or of carbon) and is disposed directly on the base substrate. The main layer is disposed on the intermediate layer and is in contact with the intermediate layer.

[0004] The multi-layer structure of the charge trapping layer makes it possible to prevent the phenomenon of recrystallization of the main polycrystalline layer when the substrate is exposed to high temperatures, for example during the manufacture of the substrate or during the manufacture of integrated devices on the composite substrate. When the trapping layer recrystallizes, even partially, the RF (radio frequency) performance of the substrate and the integrated devices formed thereon is affected, which is obviously undesirable.

[0005] To prepare a high resistivity handle substrate, this document proposes placing the base substrate in a conventional deposition chamber. A flow of a first precursor gas passes through the chamber. The first precursor gas can be a silicon-containing precursor, for example SiH4, for growing the main polycrystalline layer. A second precursor gas containing carbon is introduced into the chamber to form the intermediate layer. This precursor gas can consist of methane (CH4), ethane (C2H6), propane (C3H8), acetylene (C2H2), ethylene (C2H4)...

[0006] When two precursor gases flow simultaneously into the chamber to grow an intermediate silicon and carbon alloy layer, there is a risk of deposits forming on the chamber walls and on the susceptor on which the base substrate resides. Such deposits require extensive cleaning of the chamber, for example by etching, which is time-consuming and reduces the manufacturing throughput. Such problems are documented, for example, in WO 2019 / 002376. Also, deposits of silicon and carbon species can generate particles that can be transferred to the base substrate or handle substrate surface, rendering the substrate unsuitable for further use.

[0007] It has also been observed that doping species such as boron can be incorporated into the intermediate layer and / or the main layer, especially when the base substrate is a standard CZ silicon substrate (i.e., not designed to exhibit high resistivity characteristics). Such CZ silicon substrates contain some residual concentrations of boron and other dopants that can migrate toward the base wafer surface during growth of the charge trapping layer. When present in the charge trapping layer, the dopants reduce the resistivity of the layer and the overall RF performance of the handle substrate. Summary of the Invention [Problem to be solved by the invention]

[0008] The present invention aims to overcome some or all of the above mentioned drawbacks, in particular to provide a method for forming a handle substrate that exhibits high resistivity properties and is easy to manufacture. [Means for solving the problem]

[0009] To this end, the subject matter of the present invention proposes a method for forming a high resistivity handle substrate for a composite substrate, the method comprising the steps of: Providing a base substrate made of single crystal silicon; exposing the base substrate to a carbon single precursor at a pressure less than atmospheric pressure to form a polycrystalline silicon carbide layer of at least 10 nm on a surface of the base substrate; growing a polycrystalline charge trapping layer on the polycrystalline silicon carbide layer; Includes.

[0010] According to other advantageous, non-limiting features of the present invention, taken alone or in any technically feasible combination, the base substrate has a resistivity greater than 1000 Ω·cm; the base substrate has a resistivity of less than 1000 Ω·cm; The method further includes forming a silicon intrinsic epitaxial layer directly on the base substrate prior to exposing the base substrate to the carbon single precursor; the charge trapping layer has a thickness greater than 5 or 10 microns; the charge trapping layer is made of polycrystalline silicon; Carbon single precursors exhibit temperatures comprised between 700°C and 1200°C; The method further includes exposing the base substrate to a reducing atmosphere at a temperature of at least 900° C. prior to exposing the base substrate to the carbon single precursor to remove a native oxide layer from the base substrate; The polycrystalline silicon carbide layer is stoichiometric.

[0011] According to another aspect, the present invention provides a method for producing a method for manufacturing a pharmaceutical composition comprising: A base substrate made of single crystal silicon; a polycrystalline silicon carbide layer having a thickness of at least 10 nm directly on the surface of the base substrate; a polycrystalline charge trapping layer on the polycrystalline silicon carbide layer; The present invention also relates to a high resistivity handle substrate for a composite substrate comprising:

[0012] Optionally, the polycrystalline silicon carbide layer is 14 at / cm 3and the high resistivity handle substrate may further comprise a silicon intrinsic epitaxial layer in contact with the base substrate and the polycrystalline silicon carbide layer. The polycrystalline silicon carbide layer is stoichiometric.

[0013] Finally, the invention also relates to a composite substrate comprising a high resistivity handle substrate as described above and a thin film made of a crystalline material on the handle substrate.

[0014] Advantageously, the composite substrate further comprises a dielectric layer disposed between the handle substrate and the thin film.

[0015] Other features and advantages of the present invention will become apparent from the following detailed description of the invention which refers to the accompanying drawings. [Brief description of the drawings]

[0016] [Figure 1] 1 illustrates diagrammatically a handle substrate for a semiconductor structure according to the invention; [Diagram 2] 1 illustrates a schematic representation of a composite substrate using a handle substrate according to the present invention; [Diagram 3] SRP measurement of one of the two handle substrates. [Figure 4] 13 is a SRP measurement of the other of the two handle substrates. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0017] Figure 1 shows a schematic representation of a high resistivity handle support for a composite substrate according to an embodiment of the present disclosure. The handle substrate 1 can take the form of a circular wafer of standardized size, for example 200 mm or 300 mm or even 450 mm in diameter. However, the invention is in no way limited to these dimensions or to this form.

[0018] The handle substrate 1 typically comprises a monocrystalline silicon base substrate 3 with a thickness of several hundred microns. The silicon base substrate presents a smooth surface with a roughness of less than 0.5 nm RMS. The silicon base substrate preferably has a high resistivity of more than 1000 Ω·cm, more preferably more than 3000 Ω·cm. In this way, the density of mobile charges, holes or electrons in the base substrate is limited. The base substrate can for example be a CZ substrate with a small interstitial oxygen content, with a resistivity of more than 500 Ω·cm or even more than 1000 Ω·cm, as known per se.

[0019] However, the present invention is not limited to silicon base substrates having such resistivities, and also obtains RF performance advantages when the base substrate has more typical resistivities of about several hundred Ω·cm or less, such as less than 1000 Ω·cm or less than 500 Ω·cm, or even less than 10 Ω·cm.

[0020] When the base substrate 3 has the more typical resistivity of less than 1000 or 500 Ω·cm, it may be advantageous to provide a silicon intrinsic epitaxial layer disposed directly on the base substrate 3. "Intrinsic" means that this layer is not intentionally doped. In this case, the silicon epitaxial layer is grown to exhibit a resistivity higher than 2000 Ω·cm, preferably between 2000 Ω·cm and 20000 Ω·cm. Said epitaxial layer 2 typically has a thickness in the range of 2 to 100 microns. This approach is particularly advantageous when the base substrate is made of silicon, since silicon provides a substrate with a suitable surface resistivity without the drawbacks in terms of cost and availability associated with base substrates exhibiting high resistivity over their entire thickness.

[0021] The handle substrate 1 also comprises a polycrystalline charge trapping layer 2 on the base substrate 3. The function of the charge trapping layer is to trap any charge carriers that may be present in the handle substrate 1 and restrict their mobility.

[0022] For reasons of availability and cost, the charge trapping layer 2 is preferentially made of polycrystalline silicon. However, the charge trapping layer 2 may also be formed from other semiconductor and polycrystalline materials or may include parts made from other semiconductor and polycrystalline materials. This may be the case, for example, for germanium, silicon germanium, etc.

[0023] In all cases the polycrystalline charge trapping layer 2 has a high resistivity, typically above 3000 Ω·cm. For this reason this layer is not intentionally doped, i.e. it has a dopant concentration of less than 10E14 atoms per cubic centimeter. This layer may be enriched with nitrogen or carbon to improve resistivity characteristics.

[0024] The high resistivity handle substrate 1 also comprises a polycrystalline silicon carbide layer 4 of at least 10 nm thickness interposed between the base substrate 3 and the polycrystalline charge trapping layer 2. Such a thickness of silicon carbide forms an efficient barrier to the diffusion of dopants such as boron that may be contained in the base substrate 3. This layer typically exhibits a resistivity of more than 1000 Ω·cm. By "silicon carbide layer" it is meant that the silicon and carbon species forming the layer are present in a stoichiometric or nearly stoichiometric ratio within the layer.

[0025] Thus, the high resistivity handle substrate 1 consists of a base substrate 3 (optionally including a silicon intrinsic epitaxial top layer) of a polycrystalline silicon carbide layer 4 in direct contact with the base substrate 3, and a polycrystalline charge trapping layer 2 on and in direct contact with the silicon carbide polycrystalline layer 4. In this particular embodiment, no provision is made for incorporating other layers that may modify the properties of the proposed structure, in particular an electrically insulating layer in or below the polycrystalline charge trapping layer 2.

[0026] The polycrystalline charge trapping layer 2 may have a thickness of more than 1 micron, or more than 5 microns, or even more than 10 microns. Whether its thickness is greater or less than these limits, the charge trapping layer 2 may be composed of grains having a size of 100 to 1000 nanometers.

[0027] Finally, as shown in Figure 1, the handle substrate 1 can optionally have a dielectric layer 5 directly on the trapping layer 2. This optional dielectric layer 5 can facilitate the assembly of the handle substrate 1 with another substrate. The dielectric layer 5 can be made for example from silicon oxide or silicon nitride.

[0028] For completeness, Fig. 2 represents a composite substrate comprising a handle substrate 1 according to the present disclosure. As is very clear from this figure, the composite substrate comprises, on the handle substrate 1, a thin film 6, preferably made of a crystalline material. For example, but not limited to, the thin film 6 can be made of a semiconductor material such as silicon, or a piezoelectric material such as lithium tantalate (LiTaO3), lithium niobate (LiNbO3), lithium aluminum oxide (LiAlO3), barium titanate (BaTiO3), lead zirconate titanate (PbZrTiO3), potassium niobate (KNbO3), barium zirconate (BaZrO3), calcium titanate (CaTiO3), lead titanate (PbTiO3), potassium tantalate (KTaO3), etc.

[0029] The structure of Figure 2 can be formed from the handle substrate 1 in many ways, but advantageously, this formation comprises a step of transferring a thin film 6 onto the handle substrate 1. In a manner known per se, this transfer is typically carried out by assembling a face of a donor substrate onto the handle substrate 1. This can be done with or without the presence of a dielectric layer 5.

[0030] When the thin film 6 is made of a piezoelectric material, the crystal orientation is selected according to the intended application. For SAW filters made of LiTaO3 material, it is customary to select an XY orientation of 30°-60° or an XY orientation of 40°-50°. For LiNbO3 material, it is common to select an XY orientation of about 128°. However, the invention is in no way limited to a particular crystal orientation of the piezoelectric thin film. The donor substrate may be removed from an ingot of ferromagnetic material such that the donor substrate exhibits the selected crystal orientation. Alternatively, the donor substrate may comprise a thin layer of ferromagnetic material assembled to a support substrate.

[0031] After this assembly step, the donor substrate is reduced in thickness to form a thin film 6. This reduction step can be performed by mechanical or chemical thinning. It may also be performed by fracture in a weakened area previously introduced in the donor substrate, for example according to the principles of the Smart Cut™ technology.

[0032] Steps for completing the thin film 6, such as a polishing step, a heat treatment in a reducing or neutral atmosphere or a sacrificial oxidation, can be carried out in conjunction with the thickness reduction step.

[0033] When the donor substrate is a simple substrate, i.e. does not contain any integrated devices, a composite substrate of the "semiconductor on insulator" type is formed, where the thin film 6 is a layer of blank semiconductor that includes the inventive handle substrate 1. The composite substrate can then be used to form integrated devices.

[0034] When the donor substrate has previously been treated to form integrated devices on its surface, at the end of the method a thin film 6 containing these devices is available.

[0035] The manufacture of the handle substrate 1 of the present disclosure is particularly straightforward and can be achieved using industry standard deposition equipment.

[0036] A base substrate 3 is provided and placed in a conventional deposition chamber. In a manner well known per se, the base substrate 3 may be prepared before deposition, for example to remove a layer of native oxide from its surface. This can be done by exposing the base substrate in the chamber to a reducing atmosphere at a temperature of at least 900° C. However, this step is not essential and this oxide may be maintained. 1-2 nm is sufficiently fine to have no insulating effect (conduction through this layer by tunneling effect), unless a future heat treatment completely eliminates it by dissolving it.

[0037] The flat surface of the silicon base substrate 3 is then exposed to a single carbon precursor gas at a subatmospheric pressure, for example comprised between 0.01 Torr and 760 Torr. The carbon precursor gas can be composed of methane (CH4), ethane (C2H6), propane (C3H8), acetylene (C2H2), ethylene (C2H4).... The precursor gas can be flowed into the chamber (or heated into the chamber) at a temperature comprised between 700°C and 1200°C, such that the carbon species nucleate on the base substrate surface. A flow of a transport gas (such as H2) can also be introduced simultaneously into the chamber, but no precursor gases other than the carbon precursor gas are flowed over the base substrate 3. By avoiding reactions of the carbon species with other species of the second precursor, the deposition of carbon compounds on the chamber walls is limited and particle generation is avoided.

[0038] Surprisingly, it has been observed that when this deposition step is carried out under reduced carbon partial pressure (i.e., below atmospheric pressure), the nucleation of this carbon species takes place in isolated islands on the surface. Silicon atoms from the base wafer then diffuse into the carbon islands, forming stoichiometric or near-stoichiometric carbon silicon islands of the 3C / 6H and 4H type. Multiple islands coalesce to form a relatively thick polycrystalline silicon carbide layer of stoichiometric or near-stoichiometric ratios. When the flow of carbon precursor gas is maintained for several minutes, the thickness of the polycrystalline layer grows to several nm.

[0039] In a specific example, a carbon precursor gas of C3H8 mixed with H2 at a ratio of 180 sccm / 5 slm was introduced and flowed in the chamber at a pressure of 10 torr for 5 minutes and heated at 1000° C. A 10 nm polycrystalline layer 4 of silicon carbide was then observed on the surface of the silicon-based substrate 3.

[0040] When the deposition step as documented in WO 2019 / 002376 mentioned in the introduction is carried out above atmospheric pressure, a completely different phenomenon occurs at the surface of the base substrate 3. Carbon species nucleate at high density at the surface of the base wafer and block silicon atoms from diffusing away from that surface. A crystalline or partially crystalline carbon layer then grows slowly at the surface aligned with the silicon lattice in a 3C structure. Such a layer typically exhibits a thickness of 2 nm after 10 minutes of deposition.

[0041] Thus, flowing a single carbon precursor gas at reduced pressure on the base substrate 3 appears to be a very effective way to form a relatively thick (10 nm or more) layer of polycrystalline silicon carbide. Such a layer is advantageous because, due to its polycrystalline nature, it makes it possible to prepare and preserve the polycrystalline properties of the charge trapping layer grown thereon. Also, the relatively large thickness of the silicon carbide polycrystalline layer is formed very fast and builds an effective diffusion barrier to avoid migration of doping species from the base wafer 3 to the charge trapping layer.

[0042] In addition, it was observed that such growth methods under reduced pressure incorporated very little dopant (such as boron) in the silicon carbide intermediate layer. Measurements showed that 10 14 at / cm 3 A boron concentration of less than 1000 nm was demonstrated. It is believed that doping species (which may be present on the surface of the base wafer or incorporated into the base wafer) diffuse out of the silicon carbide layer during its formation and are carried away from the deposition chamber by the precursor and transport gases.

[0043] After the silicon carbide polycrystalline layer is grown on the base substrate, the chamber has a flow of a second precursor gas, e.g., SiH4, passed therethrough at a temperature of about 1000° C. to form a polycrystalline charge trapping layer in a conventional manner. The duration of circulation of the second precursor gas determines the thickness of the polycrystalline layer 2, and this duration can be selected to grow a layer of 5 microns, 10 microns or more.

[0044] The silicon carbide polycrystalline layer and the polycrystalline charge trapping layer are advantageously formed in situ in the same deposition chamber, which avoids contaminating the layer stack with dopants or contaminants from the atmosphere and preserves the high resistivity properties of the handle substrate 1.

[0045] To be complete, the handle substrate 1 may be provided with a dielectric layer 5, for example silicon oxide or silicon nitride, deposited in a conventional manner. This insulator 4 may also be polished.

[0046] When the base substrate 3 is provided with a silicon intrinsic epitaxial layer, the formation of this layer can be realized in-situ by the formation of a silicon carbide polycrystalline layer. This approach avoids vacuum breaks in the deposition chamber, thus improving the raw processing time and the efficiency of the overall method. This approach also prevents the handle substrate from catching contaminations from the ambient atmosphere, such as particles or boron residues that may be present in a clean room. The two layers can also be formed in separate deposition chambers, but the chambers share a common transfer module. In addition to the advantages already mentioned, this approach using separate chambers allows a better control of the necessary chamber cleaning. Obviously, it is also possible to form the two layers in completely separate chambers.

[0047] To illustrate the advantages of the manufacturing method, Fig. 3 represents an SRP measurement (spread resistivity profile) along the depth of a handle wafer according to the invention. In that particular measurement, the base wafer is a high resistivity silicon wafer (3500 Ω·cm) on which a 10 nm silicon carbide polycrystalline layer and a 2 micron silicon polycrystalline charge trapping layer were successively grown. As can be seen from this figure, the resistivity of the layer grown on top of the base substrate exceeds 3500 Ω·cm for the complete depth profile.

[0048] Figure 4 represents the SRP measurements of a handle wafer made from a base substrate exhibiting, in this case, a resistivity of 4000 Ω·cm. On top of this substrate, a 2 nm carbon layer was formed at atmospheric pressure, thus being mostly crystalline, followed by a 2 micron silicon polycrystalline charge trapping layer. It is then evident from Figure 4 that the resistivity of the layer grown on top of the base substrate approaches low values ​​at and near the interface with the base substrate (less than 10 Ω·cm). Such a low resistivity forms a conductive surface in the handle substrate, which affects the performance of the device.

[0049] This comparative example clearly illustrates the interest of exposing a base substrate to a carbon single precursor at subatmospheric pressures.

[0050] Naturally, the invention is not limited to the described embodiments, but variations in realization are possible without going beyond the scope of the invention as defined in the claims.

Claims

1. A method for forming a high resistivity handle substrate (1) for a composite substrate, comprising the steps of: Providing a base substrate (3) made of monocrystalline silicon; exposing the base substrate (3) to a carbon single precursor at sub-atmospheric pressure to form a polycrystalline silicon carbide layer (4) of at least 10 nm on the surface of the base substrate (3) via nucleation of carbon species in isolated islands on the surface of the base substrate (3); growing a polycrystalline charge trapping layer (2) on said polycrystalline silicon carbide layer; A method comprising:

2. The method of claim 1, wherein the base substrate (3) has a resistivity of more than 1000 Ω-cm.

3. The method of claim 1, wherein the base substrate (3) has a resistivity of less than 1000 Ω-cm.

4. 4. The method of claim 3, further comprising forming a silicon intrinsic epitaxial layer directly on the base substrate (3) before exposing the base substrate (3) to the carbon single precursor.

5. The method according to any one of the preceding claims, wherein the charge trapping layer (2) has a thickness greater than 5 microns.

6. The method according to any one of the preceding claims, wherein the charge trapping layer (2) is made of polycrystalline silicon.

7. A method according to any one of the preceding claims, wherein said carbon single precursor exhibits a temperature comprised between 700°C and 1200°C.

8. 8. The method according to any one of claims 1 to 7, further comprising the step of exposing the base substrate (3) to a reducing atmosphere at a temperature of at least 900°C to remove a native oxide layer from the base substrate (3) prior to exposing the base substrate (3) to the carbon single precursor.

9. A method for forming a high resistivity handle substrate (1) for a composite substrate, comprising: Providing a base substrate (3) made of monocrystalline silicon; exposing the base substrate (3) to a carbon single precursor at subatmospheric pressure to form a polycrystalline silicon carbide layer (4) of at least 10 nm on a surface of the base substrate; growing a polycrystalline charge trapping layer (2) on said polycrystalline silicon carbide layer; Including, The method, wherein the polycrystalline silicon carbide layer is stoichiometric.

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