Semiconductor Device

Abstract

To improve the performance of semiconductor devices containing LDMOSFETs.SOLUTION: A semiconductor device has a semiconductor substrate 1, a gate insulating film 12 formed on the semiconductor substrate 1, a gate electrode 16 formed above the gate insulating film 12, a field plate portion 15 integrally formed with the gate electrode 16, a step insulating film 14 in contact with the field plate portion 15, and a high dielectric constant film 30 in contact with the step insulating film 14 and with a higher dielectric constant than silicon.SELECTED DRAWING: Figure 5

Description

[Technical field]

[0001] The present invention relates to a semiconductor device, and more particularly to a technique that is effective when applied to a semiconductor device including a laterally diffused MOSFET (LDMOSFET: Lateral Diffused Metal Oxide Semiconductor Field Effect Transistor). [Background technology]

[0002] Non-Patent Document 1 describes that an LDMOSFET that employs a step insulating film (Step-OX) can suppress an increase in off-leak current caused by hot carrier injection, which increases power consumption and causes malfunctions in circuit operation. [Prior art documents] [Non-patent literature]

[0003] [Non-Patent Document 1] Keita Takahashi, Kanako Komatsu, Toshihiro Sakamoto, Koji Kimura and Fumitomo Matsuoka “Hot-carrier Induced Off-state Leakage CurrentIncrease of LDMOS and Approach to Overcome the Phenomenon”, Proceedings of the 30th International Symposium on Power Semiconductor Devices & ICs May 13-17, 2018, Chicago, USA Summary of the Invention [Problem to be solved by the invention]

[0004] As described in the above-mentioned non-patent document, an LDMOSFET employing a step insulating film can suppress an increase in off-leakage current compared to an LDMOSFET employing an STI structure by replacing the STI structure with a step insulating film.

[0005] However, even in an LDMOSFET that employs a step insulating film, hot carrier injection into the step insulating film cannot be sufficiently suppressed, and therefore there is room for improvement in terms of improving the performance of semiconductor devices that include LDMOSFETs. [Means for solving the problem]

[0006] A semiconductor device in one embodiment includes a semiconductor substrate, a gate insulating film formed on the semiconductor substrate, a gate electrode formed above the gate insulating film, a field plate portion formed integrally with the gate electrode, a step insulating film in contact with the field plate portion, and a high dielectric constant film in contact with the step insulating film and having a dielectric constant higher than that of silicon. Effect of the Invention

[0007] According to one embodiment, the performance of a semiconductor device including an LDMOSFET can be improved. [Brief description of the drawings]

[0008] [Figure 1] 1 is a flowchart for explaining a mechanism by which the on-resistance of an LDMOSFET increases when hot carriers are injected into a step insulating film. [Diagram 2] FIG. 1 is a diagram for explaining a basic idea in an embodiment. [Diagram 3] FIG. 1 is a diagram showing a schematic diagram of electron flow in an LDMOSFET in which a potential control film is not present. [Figure 4] FIG. 1 is a schematic diagram showing how electrons flow in an LDMOSFET in which the basic idea of ​​providing a potential control film is embodied. [Diagram 5]FIG. 2 is a cross-sectional view showing a device structure of an LDMOSFET in an embodiment. [Figure 6] FIG. 1A is a diagram showing a schematic band structure on the surface of an n-type RESURF layer when a gate insulating film made of, for example, a silicon oxide film is formed on the n-type RESURF layer, and FIG. 1B is a diagram showing a schematic band structure on the surface of an n-type RESURF layer when a gate insulating film made of a silicon oxide film and a high dielectric constant film are formed on the n-type RESURF layer. [Figure 7] 6(a) and 6(b) are diagrams showing schematic band structures in which the Fermi levels in FIG. 6(a) and FIG. 6(b) are set to the same energy level. [Figure 8] 3A to 3C are cross-sectional views showing a manufacturing process of the semiconductor device in the embodiment. [Figure 9] 9 is a cross-sectional view showing a manufacturing process of the semiconductor device subsequent to FIG. 8. [Figure 10] 10 is a cross-sectional view showing a manufacturing process of the semiconductor device subsequent to FIG. [Figure 11] 11 is a cross-sectional view showing a manufacturing process of the semiconductor device subsequent to FIG. 10. [Figure 12] FIG. 11 is a cross-sectional view showing a device structure of an LDMOSFET in Modification 1. [Figure 13] 10A to 10C are cross-sectional views showing a manufacturing process of a semiconductor device in Modification 1. [Figure 14] 14 is a cross-sectional view showing a manufacturing process of the semiconductor device subsequent to FIG. 13. [Figure 15] FIG. 11 is a cross-sectional view showing a device structure of an LDMOSFET according to Modification 2. [Figure 16] 10A to 10C are cross-sectional views showing a manufacturing process of a semiconductor device in Modification 2. [Figure 17] 17 is a cross-sectional view showing a manufacturing process of the semiconductor device subsequent to FIG. 16. [Figure 18] 18 is a cross-sectional view showing a manufacturing process of the semiconductor device subsequent to FIG. 17. [Figure 19] FIG. 11 is a cross-sectional view showing a device structure of an LDMOSFET in Modification 3. [Figure 20]11A to 11C are cross-sectional views showing a manufacturing process of a semiconductor device in Modification 3. [Figure 21] 21 is a cross-sectional view showing a manufacturing process of the semiconductor device subsequent to FIG. 20. [Figure 22] 22 is a cross-sectional view showing a manufacturing process of the semiconductor device subsequent to FIG. 21. [Diagram 23] FIG. 13 is a cross-sectional view showing a device structure of an LDMOSFET in Modification 4. [Figure 24] 11A to 11C are cross-sectional views showing a manufacturing process of a semiconductor device in Modification 3. [Diagram 25] 25 is a cross-sectional view showing a manufacturing process of the semiconductor device subsequent to FIG. 24. [Figure 26] 26 is a cross-sectional view showing a manufacturing process of the semiconductor device subsequent to FIG. 25. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] In all the drawings for explaining the embodiments, the same members are generally designated by the same reference numerals, and the repeated explanations thereof will be omitted. In addition, hatching may be applied even to plan views in order to make the drawings easier to understand.

[0010] <Consideration of improvements> The present inventors have newly found room for improvement in LDMOSFETs that employ a step insulating film, in that the on-resistance increases when hot carriers are injected into the step insulating film. Here, we explain the mechanism by which the on-resistance of an LDMOSFET increases when hot carriers are injected into the step insulating film.

[0011] FIG. 1 is a flow chart for explaining the mechanism by which the on-resistance of an LDMOSFET increases when hot carriers are injected into a step insulating film.

[0012] In FIG. 1, first, a gate voltage equal to or higher than a threshold is applied to the gate electrode while a high voltage is applied between the source and drain of the LDMOSFET to turn the LDMOSFET on (S101). This causes electrons to flow from the source through the channel to the drain. At this time, the high voltage applied between the source and drain accelerates the electrons, generating hot carriers (S102). In particular, a high electric field is generated near the corners of the step insulating film, and hot carriers accelerated by this high electric field overcome the potential barrier of the step insulating film and are injected into the step insulating film (S103). This causes fixed charges (negative charges) to be trapped in the step insulating film (S104). As a result, the step insulating film is negatively charged, and a depletion phenomenon occurs on the surface of the n-type RESURF layer in contact with the step insulating film (S105). Since this depletion region functions as an insulating region, electrons flowing from the source through the channel to the drain are detouring to avoid the depletion region formed on the surface of the n-type RESURF layer (S106).

[0013] As described above, the on-resistance of the LDMOSFET increases due to "factor 1," which is the depletion of the n-type RESURF layer caused by the injection of hot carriers into the step insulating film, and "factor 2," which is the increase in the distance of the path through which electrons flow as a detour (S107). Due to this mechanism, in an LDMOSFET that employs a step insulating film, the injection of hot carriers into the step insulating film results in an increase in on-resistance, revealing room for improvement.

[0014] In this embodiment, therefore, a measure is taken to address the room for improvement of the increase in on-resistance present in the LDMOSFET employing the above-mentioned step insulating film. The technical concept of this embodiment in which this measure is taken is described below.

[0015] <Basic Concept of the Embodiment> The basic idea of ​​this embodiment is to provide the LDMOSFET with a potential control film for forming a potential barrier against electrons on the surface of the semiconductor substrate located below the step insulating film. This allows the current path through which electrons flow to be shifted from the "surface of the semiconductor substrate" to the "inside (bulk) of the semiconductor substrate" by the potential barrier formed on the surface of the semiconductor substrate located below the step insulating film. That is, the potential barrier creates a repulsive force that moves electrons away from the surface of the semiconductor substrate, so that the current path through which electrons flow shifts from the "surface of the semiconductor substrate" to the "inside (bulk) of the semiconductor substrate". This means that the current path through which electrons flow is away from the interface between the step insulating film and the semiconductor substrate, which means that the injection of hot carriers into the step insulating film is suppressed. As a result, according to the basic idea, it is possible to suppress an increase in the on-resistance of the LDMOSFET caused by the injection of hot carriers into the step insulating film.

[0016] A specific description will be given below with reference to the drawings.

[0017] FIG. 2 is a diagram for explaining the basic idea of ​​this embodiment. In FIG. 2, the LDMOSFET 100 has a semiconductor substrate 1. In this semiconductor substrate 1, a p-type RESURF layer 10 and an n-type RESURF layer 11 formed on the p-type RESURF layer 10 are formed. The n-type RESURF layer 11 is also called an n-type drift layer. A gate insulating film 12 is formed on the surface of the semiconductor substrate 1, and a potential control film 13 is formed on this gate insulating film 12. This potential control film 13 is in contact with a step insulating film 14, and a field plate portion 15 in contact with the step insulating film 14 and a gate electrode 16 in contact with the potential control film 13 are integrally formed. In addition, a drain region 17 made of an n-type semiconductor region is formed in the n-type RESURF layer 11 so as to match with the step insulating film 14. Furthermore, a p-type body region 18 is formed in the semiconductor substrate 1, and a source region made of an n-type semiconductor region and a body contact region 20 made of a p-type semiconductor region are formed so as to be included in this p-type body region 18.

[0018] The basic idea of ​​this embodiment is to form a potential barrier against electrons on the surface of the semiconductor substrate 1 located below the step insulating film 14 by the potential control film 13 provided in the LDMOSFET 100 configured as described above. Specifically, as shown in the right part of FIG. 2, the presence of the potential control film 13 shifts the potential on the surface of the semiconductor substrate 1 from the solid line A to the broken line B. In this case, the potential on the surface of the semiconductor substrate 1 shifts in a direction toward higher energy as viewed from the electrons. This means that the repulsive force that the electrons receive from the potential shifted in the direction toward higher energy on the surface of the semiconductor substrate 1 increases. As a result, the current path through which the electrons flow shifts from the "surface of the semiconductor substrate 1" to the "inside (bulk) of the semiconductor substrate 1". This means that the current path through which the electrons flow moves away from the interface between the step insulating film and the semiconductor substrate, thereby suppressing the injection of hot carriers into the step insulating film.

[0019] For example, FIG. 3 is a diagram showing a schematic view of the flow of electrons in an LDMOSFET in which the potential control film 13 is not provided.

[0020] As shown in Fig. 3, electrons flow from the source region 19 toward the drain region 17 through a channel formed in the surface of the p-type body region 18. At this time, as shown in Fig. 3, hot carriers generated by a high voltage applied between the drain region 17 and the source region 19 are injected into the step insulating film 14 by a high electric field near the corner of the step insulating film 14. As a result, in the LDMOSFET shown in Fig. 3, an increase in on-resistance is caused by the hot carriers injected into the step insulating film 14.

[0021] In contrast to this, FIG. 4 is a diagram showing a schematic view of the flow of electrons in an LDMOSFET in which the basic idea of ​​providing a potential control film 13 is embodied.

[0022] As shown in FIG. 4, electrons flow from the source region 19 through a channel formed on the surface of the p-type body region 18 toward the drain region 17. At this time, in the LDMOSFET shown in FIG. 4, a potential barrier PB that repels electrons is formed on the surface of the semiconductor substrate 1 by the potential control film 13. As a result, as shown in FIG. 4, the current path through which electrons flow shifts from "the surface of the semiconductor substrate 1" to "the inside of the semiconductor substrate 1 (inside the bulk)". Thereby, since the current path through which electrons flow is separated from the interface between the step insulating film 14 and the semiconductor substrate 1, injection of hot carriers into the step insulating film 14 is suppressed. For this reason, it can be seen that in the LDMOSFET shown in FIG. 4, an increase in on-resistance due to injection of hot carriers into the step insulating film 14 can be suppressed.

[0023] From the above, it can be seen that the basic idea of forming a potential barrier PB for electrons on the surface of the semiconductor substrate 1 located below the step insulating film 14 by the potential control film 13 is an effective technical idea from the viewpoint of reducing on-resistance. Therefore, hereinafter, an example of an embodiment that embodies this basic idea will be described.

[0024] <Device Structure of LDMOSFET> FIG. 5 is a cross-sectional view showing a schematic device structure of an LDMOSFET 100A.

[0025] In FIG. 5, the LDMOSFET has a semiconductor substrate 1 made of, for example, silicon. This semiconductor substrate 1 has a p-type resurf layer 10 and an n-type resurf layer 11 (n-type drift layer) formed on the p-type resurf layer 10. And on the semiconductor substrate 1, a gate insulating film 12 made of, for example, a silicon oxide film is formed.

[0026] A gate electrode 16 made of, for example, an n-type polysilicon film is formed above the gate insulating film 12. Here, the gate electrode 16 formed "above" the gate insulating film 12 is used with a broader meaning to include not only the configuration of the gate electrode 16 formed directly above the gate insulating film 12, but also, for example, as shown in Fig. 5, a high dielectric constant film 30 is formed on the gate insulating film 12 and the gate electrode 16 is formed on this high dielectric constant film 30.

[0027] Specifically, in FIG. 5, a high dielectric constant film 30 is formed on a gate insulating film 12, and a gate electrode 16 is formed on this high dielectric constant film 30. In FIG.

[0028] Here, the "high dielectric constant film 30" in this specification is defined as a film having a higher dielectric constant than silicon. In this embodiment, the high dielectric constant film 30 includes a "first portion" sandwiched between the gate insulating film 12 and the gate electrode 16, and a "second portion" sandwiched between the step insulating film 14 and the gate insulating film 12, as shown in FIG.

[0029] Next, the LDMOSFET 100A has a field plate portion 15 formed integrally with the gate electrode 16, and a step insulating film 14 in contact with the field plate portion 15. The step insulating film 14 is made of, for example, a silicon oxide film. The high dielectric constant film 30 is in contact with the step insulating film 14.

[0030] Next, as shown in FIG. 5, a drain region 17 composed of an n-type semiconductor region that aligns with the step insulating film 14 is formed in the n-type RESURF layer 11. Further, a p-type body region 18 composed of a p-type semiconductor region is formed in the semiconductor substrate 1. In this p-type body region 18, a source region 19 that is an n-type semiconductor region and a body contact region 20 that is a p-type semiconductor region are formed. The source region 19 and the body contact region 20 are electrically connected, and for example, a ground potential (0 V) is supplied. As a result, a ground potential is also supplied to the p-type body region 18 that is electrically connected to the body contact region 20. On the other hand, a positive potential is supplied to the drain region 17.

[0031] Here, the high-k dielectric film 30 shown in FIG. 5 is an example of the potential control film 13 shown in FIG. 2. That is, the high-k dielectric film 30 functions as a potential control film 13 for forming a potential barrier for electrons on the surface of the semiconductor substrate 1 located below the step insulating film 14. Specifically, as will be described later, the high-k dielectric film 30 has a function of forming a potential barrier on the surface by shifting the Fermi level on the surface of the semiconductor substrate 1 located below the step insulating film 14. The high-k dielectric film 30 having such a function contains, for example, any one of HfSiO, HfSiON, HfAlON, Y2O3, and Al2O3.

[0032] In the above manner, the LDMOSFET 100A is configured.

[0033] <Operation of LDMOSFET> Next, the operation of the LDMOSFET 100A will be described.

[0034] First, the on-operation of the LDMOSFET 100A will be described. In Fig. 5, a ground potential is supplied to the source region 19, and a positive potential is supplied to the drain region 17. A gate voltage equal to or higher than the threshold is applied to the gate electrode 16. Then, an inversion layer (n-type layer) that becomes a channel layer is formed on the surface of the p-type body region 18 located below the gate electrode 16. As a result, electrons flow from the source region 19 to the channel layer (inversion layer) to the n-type RESURF layer 11 to the drain region 17. In this way, the LDMOSFET 100A is turned on.

[0035] Next, the off operation of the LDMOSFET 100A will be described. When the LDMOSFET 100A is in the on state, a gate voltage (for example, 0 V) ​​smaller than the threshold voltage is applied to the gate electrode 16. Then, the inversion layer formed on the surface of the p-type body region 18 disappears. As a result, the path through which electrons flow from the source region 19 to the drain region 17 is cut off. In this manner, the LDMOSFET 100A is turned off.

[0036] <Features of the embodiment> Next, features of this embodiment will be described.

[0037] The feature of this embodiment is that, for example, as shown in FIG. 5, a high dielectric constant film 30 is used as a potential control film 13 for forming a potential barrier against electrons on the surface of the semiconductor substrate 1 located below the step insulating film 14. That is, the feature of this embodiment is that a potential barrier is formed on the surface of the semiconductor substrate 1 located below the step insulating film 14 by the high dielectric constant film 30, and this potential barrier shifts the current path through which electrons flow from the "surface of the semiconductor substrate" to the "inside (bulk) of the semiconductor substrate". As a result, according to this embodiment, the path through which electrons flow can be separated from the interface between the step insulating film 14 and the semiconductor substrate 1, and thus the injection of hot carriers into the step insulating film 14 can be suppressed. As a result, according to this embodiment, an increase in the on-resistance of the LDMOSFET caused by the injection of hot carriers into the step insulating film 14 can be effectively suppressed.

[0038] The function of the high dielectric constant film 30 as the potential control film 13 will be described below.

[0039] Fig. 6(a) is a diagram showing a band structure on the surface of the n-type RESURF layer 11 when a gate insulating film 12 made of, for example, a silicon oxide film is formed on the n-type RESURF layer 11. As shown in Fig. 6(a), since the n-type RESURF layer 11 is an n-type semiconductor layer, the Fermi level Ef exists in the vicinity of the bottom of the conduction band.

[0040] However, when not only the gate insulating film 12 made of a silicon oxide film but also a high dielectric constant film 30 containing, for example, HfSiO, HfSiON, HfAlON, Y2O3, Al2O3, or the like as a constituent material and having a higher dielectric constant than silicon is formed on the n-type RESURF layer 11, a phenomenon called "Fermi level pinning" occurs in which the Fermi level Ef moves away from the lower end of the conduction band. Specifically, FIG. 6(b) is a diagram showing a band structure on the surface of the n-type RESURF layer 11 when the gate insulating film 12 made of a silicon oxide film and the high dielectric constant film 30 are formed on the n-type RESURF layer 11. As shown in FIG. 6(b), it can be seen that the Fermi level Ef shifts in a direction away from the lower end of the conduction band due to "Fermi level pinning" caused by the presence of the high dielectric constant film 30, even though the n-type RESURF layer 11 is an n-type semiconductor layer. In this embodiment, a potential barrier is formed on the surface of the semiconductor substrate 1 located below the step insulating film 14 by utilizing this "Fermi level pinning". This point will be explained below.

[0041] When the Fermi levels Ef in Fig. 6(a) and Fig. 6(b) are set to the same energy level, the results are as shown in Fig. 7(a) and Fig. 7(b). Fig. 7(a) is a diagram showing a band structure on the surface of the n-type RESURF layer 11 when, for example, a gate insulating film 12 made of a silicon oxide film is formed on the n-type RESURF layer 11, and Fig. 7(b) is a diagram showing a band structure on the surface of the n-type RESURF layer 11 when a gate insulating film 12 made of a silicon oxide film and a high dielectric constant film 30 are formed on the n-type RESURF layer 11.

[0042] From FIGS. 7(a) and 7(b), it can be seen that when the high-k dielectric film 30 is formed on the n-type RESURF layer 11, the band structure at the surface of the n-type RESURF layer 11 shifts electronically in the direction of higher energy due to "Fermi level pinning". This means that by providing the high-k dielectric film 30, the energy level at the surface of the n-type RESURF layer 11 rises electronically. In other words, it means that a potential barrier for electrons is formed on the surface of the semiconductor substrate 1 located below the step insulating film 14. It can be understood that the high-k dielectric film 30 functions as the potential control film 13 by such a mechanism.

[0043] As described above, the characteristic point in the present embodiment lies in forming a potential barrier on the surface of the semiconductor substrate 1 located below the step insulating film 14 by utilizing the phenomenon of "Fermi level pinning" caused by the high-k dielectric film 30. Due to this characteristic point, the path through which electrons flow can be separated from the interface between the step insulating film 14 and the semiconductor substrate 1 by the repulsive force of the potential barrier. Therefore, according to the present embodiment, the injection of hot carriers into the step insulating film 14 can be suppressed, and as a result, an increase in the on-resistance of the LDMOSFET caused by the injection of hot carriers into the step insulating film 14 can be suppressed.

[0044] <Method for manufacturing a semiconductor device including an LDMOSFET> Next, a method for manufacturing a semiconductor device including an LDMOSFET will be described.

[0045] First, as shown in FIG. 8, for example, a semiconductor substrate 1 made of silicon is prepared. Then, after forming a sacrificial silicon oxide film 35 (through oxide film) on the surface of the semiconductor substrate 1, a p-type RESURF layer 10 and an n-type RESURF layer 11 are formed on the semiconductor substrate 1 by using the ion implantation method. Specifically, the p-type RESURF layer 10 is formed by implanting boron (B), which is a p-type impurity (acceptor), into the semiconductor substrate 1. On the other hand, the n-type RESURF layer 11 is formed by implanting phosphorus (P), which is an n-type impurity (donor), into the semiconductor substrate 1.

[0046] 9, a gate insulating film 12 made of a silicon oxide film is formed on the surface of the semiconductor substrate 1 by, for example, a thermal oxidation method. Then, a high dielectric constant film 30 is formed by, for example, an ALD method (Atomic Layer Deposition) method or a CVD method (Chemical Vapor Deposition) method. Examples of the high dielectric constant film 30 include an HfSiO film, an HfSiON film, an HfAlON film, a Y2O3 film, and an Al2O3 film. Then, a silicon oxide film 14a is formed on the high dielectric constant film 30 by, for example, a CVD method.

[0047] 10, the silicon oxide film 14a is patterned by using photolithography and etching techniques to form the step insulating film 14. Next, for example, by using the CVD method, a polysilicon film is formed on the high dielectric constant film 30 so as to cover the step insulating film 14. Then, by using photolithography and etching techniques, the polysilicon film is patterned. As a result, the gate electrode 16 and the field plate portion 15 made of the polysilicon film are integrally formed. After that, by using photolithography and oblique ion implantation, boron, which is a p-type impurity, is implanted into the semiconductor substrate 1 to form the p-type body region 18.

[0048] 5, photolithography and ion implantation are used to inject phosphorus, which is an n-type impurity, into the semiconductor substrate 1 to form a drain region 17 and a source region 19, and boron, which is a p-type impurity, into the semiconductor substrate 1 to form a body contact region 20. Thereafter, an interlayer insulating film forming step for forming an interlayer insulating film and an interconnect forming step for forming interconnects are performed, thereby manufacturing a semiconductor device including the LDMOSFET 100A.

[0049] <Variation 1> In the above-described embodiment, for example, as shown in FIG. 5, the high-k dielectric film 30 includes a "first portion" sandwiched between the gate insulating film 12 and the gate electrode 16, and a "second portion" sandwiched between the step insulating film 14 and the gate insulating film 12.

[0050] Here, the "second portion" of the high-k dielectric film 30 is important from the viewpoint of forming a potential barrier for electrons on the surface of the semiconductor substrate 1 located below the step insulating film 14. On the other hand, the "first portion" of the high-k dielectric film 30 forms a stacked film with the gate insulating film 12, and this stacked film affects the threshold voltage for forming an inversion layer. That is, the "first portion" of the high-k dielectric film 30 is not essential from the viewpoint of forming a potential barrier for electrons on the surface of the semiconductor substrate 1 located below the step insulating film 14. Rather, there is a demerit that the threshold voltage for forming an inversion layer increases due to "Fermi level pinning" caused by the "first portion" of the high-k dielectric film 30.

[0051] Therefore, FIG. 12 is a cross-sectional view schematically showing the device structure of the LDMOSFET 100B in the first modified example. As shown in FIG. 12, the high-k dielectric film 30 is composed only of the "second portion" sandwiched between the step insulating film 14 and the gate insulating film 12. According to the first modified example, thus, a potential barrier for electrons can be formed on the surface of the semiconductor substrate 1 located below the step insulating film 14, while suppressing the side effect that the threshold voltage for forming an inversion layer increases.

[0052] <<Method for manufacturing a semiconductor device including an LDMOSFET>> Also in the semiconductor device including the LDMOSFET in the first modified example, the steps shown in FIGS. 8 and 9 are the same as those in the above-described embodiment. Next, as shown in FIG. 13, by using an etching technique, the high-k dielectric film 30 exposed from the step insulating film 14 is removed. Thereby, the high-k dielectric film 30 composed only of the "second portion" sandwiched between the step insulating film 14 and the gate insulating film 12 can be formed.

[0053] Subsequently, for example, by using a CVD method, a polysilicon film is formed on the gate insulating film 12 so as to cover the step insulating film 14. Then, the polysilicon film is patterned by using photolithography technology and etching technology. Thereby, the gate electrode 16 and the field plate portion 15 made of the polysilicon film are integrally formed. Thereafter, by using photolithography technology and an oblique ion implantation method, boron, which is a p-type impurity, is implanted into the semiconductor substrate 1 to form a p-type body region 18.

[0054] Next, as shown in FIG. 12, by using photolithography technology and an ion implantation method, phosphorus, which is an n-type impurity, is implanted into the semiconductor substrate 1 to form a drain region 17 and a source region 19, and boron, which is a p-type impurity, is implanted into the semiconductor substrate 1 to form a body contact region 20. Thereafter, through an interlayer insulating film forming step of forming an interlayer insulating film and a wiring forming step of forming wiring, a semiconductor device including the LDMOSFET 100B can be manufactured.

[0055] <Modification Example 2> <<Device Structure of LDMOSFET>> FIG. 15 is a cross-sectional view schematically showing the device structure of the LDMOSFET 100C in this Modification Example 2. In FIG. 15, the characteristic point of this Modification Example 2 is that a high-k dielectric film 30 is formed over the exposed gate insulating film 12, the gate electrode 16, the field plate portion 15, and the exposed step insulating film 14. In particular, the film thickness of the high-k dielectric film 30 in this Modification Example 2 is thicker than the film thickness of the high-k dielectric film 30 in the above-described embodiment and Modification Example 1. This is because, in this Modification Example 2, considering that the effect of forming a potential barrier on the surface of the semiconductor substrate 1 is reduced as a result of the high-k dielectric film 30 being disposed above rather than below the step insulating film 14, the film thickness of the high-k dielectric film 30 is increased to ensure the effect of forming a potential barrier. In this way, the LDMOSFET 100C in this Modification Example 2 is configured.

[0056] <<Manufacturing Method of Semiconductor Device Including LDMOSFET>> Also in the semiconductor device including the LDMOSFET in this Modification 2, the steps shown in FIG. 8 are the same as those in the above-described embodiment. Next, as shown in FIG. 16, for example, by using the CVD method, after forming a silicon oxide film on the semiconductor substrate 1, the silicon oxide film is patterned by using photolithography technology and etching technology to form the step insulating film 14. Thereafter, as shown in FIG. 17, for example, by using the thermal oxidation method, a gate insulating film 12 is formed on the surface of the exposed semiconductor substrate 1.

[0057] Subsequently, as shown in FIG. 18, for example, by using the CVD method, a polysilicon film is formed on the gate insulating film 12 and the step insulating film 14. Then, the polysilicon film is patterned by using photolithography technology and etching technology. Thereby, the gate electrode 16 and the field plate portion 15 made of the polysilicon film are integrally formed. Thereafter, by using photolithography technology and the oblique ion implantation method, boron, which is a p-type impurity, is implanted into the semiconductor substrate 1 to form a p-type body region 18. Next, by using photolithography technology and the ion implantation method, phosphorus, which is an n-type impurity, is implanted into the semiconductor substrate 1 to form a drain region 17 and a source region 19, and boron, which is a p-type impurity, is implanted into the semiconductor substrate 1 to form a body contact region 20. Then, as shown in FIG. 15, a high dielectric constant film 30 is formed so as to cover the exposed gate insulating film 12, the gate electrode 16, the field plate portion 15, and the exposed step insulating film 14. Thereafter, through an interlayer insulating film forming step of forming an interlayer insulating film and a wiring forming step of forming a wiring, a semiconductor device including the LDMOSFET 100C can be manufactured.

[0058] <<Advantages of Modification 2>> Also in the second modification example, while the thick high-dielectric constant film 30 can form a potential barrier for electrons on the surface of the semiconductor substrate 1 located below the step insulating film 14, since there is no high-dielectric constant film 30 below the gate electrode 16, the side effect of the threshold voltage for forming an inversion layer increasing can be suppressed.

[0059] In particular, in the second modification example, since the step of patterning the high-dielectric constant film 30 as in the first modification example becomes unnecessary, without adding a patterning step, while forming a potential barrier for electrons on the surface of the semiconductor substrate 1 located below the step insulating film 14, an increase in the threshold voltage for forming an inversion layer can be suppressed.

[0060] <Modification Example 3> <<Device Structure of LDMOSFET>> FIG. 19 is a cross-sectional view schematically showing the device structure of the LDMOSFET 100D in the third modification example. In FIG. 19, the characteristic point of the third modification example is that on the premise that the step insulating film 14 has a "contact part" in contact with the field plate part 15 and a "non-contact part" protruding from the field plate part 15, the "non-contact part" is composed of a "thin film part" in which a recess is formed and a "thick film part" having a thickness thicker than that of the "thin film part", and a high-dielectric constant film 30 is formed over the exposed gate insulating film 12, the gate electrode 16, the field plate part 15, and the exposed step insulating film 14. At this time, when the thickness of the "thick film part" is "t1" and the thickness of the "thin film part" is "t2", the relationship of t2 < t1 holds.

[0061] <<Manufacturing Method of Semiconductor Device Including LDMOSFET>> In the semiconductor device including the LDMOSFET in the present modified example 3, the process is similar to that of the modified example 2 up to the process shown in Fig. 16. Thereafter, as shown in Fig. 20, a recess 40 is formed in the step insulating film 14 by using photolithography and etching techniques. Then, as shown in Fig. 21, a gate insulating film 12 is formed on the exposed surface of the semiconductor substrate 1 by using, for example, a thermal oxidation method.

[0062] 22, for example, a polysilicon film is formed on the gate insulating film 12 and the step insulating film 14 by using a CVD method. Then, the polysilicon film is patterned by using a photolithography technique and an etching technique. As a result, the gate electrode 16 and the field plate portion 15 made of the polysilicon film are integrally formed. Then, by using a photolithography technique and an oblique ion implantation technique, boron, which is a p-type impurity, is implanted into the semiconductor substrate 1 to form a p-type body region 18. Next, by using a photolithography technique and an ion implantation technique, phosphorus, which is an n-type impurity, is implanted into the semiconductor substrate 1 to form a drain region 17 and a source region 19, and boron, which is a p-type impurity, is implanted into the semiconductor substrate 1 to form a body contact region 20. Then, as shown in FIG. 19, a high dielectric constant film 30 is formed so as to cover the exposed gate insulating film 12, the gate electrode 16, the field plate portion 15, and the exposed step insulating film 14. Thereafter, an interlayer insulating film forming step of forming an interlayer insulating film and an interconnect forming step of forming interconnects are performed, whereby a semiconductor device including the LDMOSFET 100D can be manufactured.

[0063] <<Advantages of Modification 3>> According to the present modified example 3, a "thin film portion" in which a recess is formed is formed in the step insulating film 14, and the high dielectric constant film 30 is also formed inside the recess of this "thin film portion." In this respect, since the effect of forming a potential barrier on the surface of the semiconductor substrate 1 can be ensured, the present modified example 3 has the advantage that the thickness of the high dielectric constant film 30 can be made thinner than that of the modified example 2.

[0064] <Modification Example 4> <<Device Structure of LDMOSFET>> FIG. 23 is a cross-sectional view schematically showing the device structure of the LDMOSFET 100E in this Modification Example 4. In FIG. 23, the characteristic point of this Modification Example 4 is that the film thickness “t2” of the “thin film portion” including the recess provided in the step insulating film 14 is equal to the film thickness of the gate insulating film 12.

[0065] <<Manufacturing Method of Semiconductor Device Including LDMOSFET>> Also in the semiconductor device including the LDMOSFET in this Modification Example 3, up to the steps shown in FIG. 16 are the same as those in the Modification Example 2. Thereafter, as shown in FIG. 24, by using photolithography technology and etching technology, a recess 40 is formed in the step insulating film 14. At this time, the recess 40 is formed such that the bottom of the recess 40 reaches the surface of the semiconductor substrate 1. Then, as shown in FIG. 25, for example, by using the thermal oxidation method, a gate insulating film 12 is formed on the exposed surface of the semiconductor substrate 1. Here, the gate insulating film 12 is also formed on the surface of the semiconductor substrate 1 exposed at the bottom of the recess 40.

[0066] Note that the film thickness of the gate insulating film 12 formed at the bottom of the recess 40 is equal to the film thickness of the gate insulating film 12 formed on the other surface of the semiconductor substrate 1.

[0067] 26, for example, a polysilicon film is formed on the gate insulating film 12 and the step insulating film 14 by using a CVD method. Then, the polysilicon film is patterned by using a photolithography technique and an etching technique. As a result, the gate electrode 16 and the field plate portion 15 made of the polysilicon film are integrally formed. Then, by using a photolithography technique and an oblique ion implantation technique, boron, which is a p-type impurity, is implanted into the semiconductor substrate 1 to form a p-type body region 18. Next, by using a photolithography technique and an ion implantation technique, phosphorus, which is an n-type impurity, is implanted into the semiconductor substrate 1 to form a drain region 17 and a source region 19, and boron, which is a p-type impurity, is implanted into the semiconductor substrate 1 to form a body contact region 20. Then, as shown in FIG. 23, a high dielectric constant film 30 is formed so as to cover the exposed gate insulating film 12, the gate electrode 16, the field plate portion 15, and the exposed step insulating film 14. Thereafter, an interlayer insulating film forming step of forming an interlayer insulating film and an interconnect forming step of forming interconnects are performed, whereby a semiconductor device including the LDMOSFET 100E can be manufactured.

[0068] <<Advantages of Modification 4>> For example, in the third modification, since the thickness "t2" of the "thin film portion" is different from the thickness of the gate insulating film 12, it is necessary to adjust the etching amount of the recess 40 in the formation process of the recess 40 (see FIG. 20). In contrast, in the fourth modification, since the thickness "t2" of the "thin film portion" is made equal to the thickness of the gate insulating film 12, for example, as shown in FIG. 24, in the formation process of the recess 40, the semiconductor substrate 1 may be formed so as to be exposed at the bottom of the recess 40 without delicately adjusting the etching amount of the recess 40. This has the advantage that the etching process for forming the recess 40 is easy because "over-etching" is also allowed. And, in the fourth modification, the thermal oxidation method is applied to the entire exposed surface of the semiconductor substrate 1 including the surface of the semiconductor substrate 1 exposed from the bottom of the recess 40, so that the gate insulating film 12 is also formed at the bottom of the recess 40, and therefore the thickness "t2" of the "thin film portion" can be automatically made equal to the thickness of the gate insulating film 12 in other regions.

[0069] The invention made by the inventor has been specifically described above based on the embodiment thereof. However, it goes without saying that the present invention is not limited to the above embodiment, and various modifications can be made without departing from the spirit of the invention.

[0070] The above embodiment includes the following aspects.

[0071] (Additional Note 1): <Method of Manufacturing a Semiconductor Device in an Embodiment> (a) forming a gate insulating film on a semiconductor substrate; (b) forming a high dielectric constant film having a dielectric constant higher than that of silicon on the gate insulating film; (c) forming a step insulating film in contact with the high dielectric constant film; (d) integrally forming a gate electrode in contact with the high dielectric constant film and a field plate portion in contact with the step insulating film; A manufacturing method of a semiconductor device comprising:

[0072] (Appendix 2): <Method of manufacturing the semiconductor device in Modification 1> (a) forming a gate insulating film on a semiconductor substrate; (b) forming a high dielectric constant film having a dielectric constant higher than that of silicon on the gate insulating film; (c) forming a step insulating film in contact with the high dielectric constant film; (d) removing the high dielectric constant film exposed from the step insulating film; (e) integrally forming a gate electrode in contact with the gate insulating film and a field plate portion in contact with the step insulating film; A manufacturing method of a semiconductor device comprising:

[0073] (Appendix 3): <Method of manufacturing a semiconductor device in Modification 2> (a) forming a step insulating film on a semiconductor substrate; (b) forming a gate insulating film on the semiconductor substrate except for the step insulating film; (c) integrally forming a gate electrode in contact with the gate insulating film and a field plate portion in contact with the step insulating film; (d) forming a high dielectric constant film having a dielectric constant higher than that of silicon so as to be in contact with the gate electrode, the field plate portion, and the step insulating film; A manufacturing method of a semiconductor device comprising:

[0074] (Appendix 4): <Method of manufacturing a semiconductor device in Modification 3> (a) forming a step insulating film on a semiconductor substrate; (b) forming a recess in the step insulating film; (c) forming a gate insulating film on the semiconductor substrate except for the step insulating film; (d) a gate electrode in contact with the gate insulating film and in contact with the step insulating film; forming a field plate portion integrally with the recess and out of contact with the field plate portion; (e) forming a high dielectric constant film having a dielectric constant higher than that of silicon so as to be in contact with the gate electrode, the field plate portion, and the step insulating film; A manufacturing method of a semiconductor device comprising:

[0075] (Appendix 5): <Method of manufacturing a semiconductor device in Modification 4> (a) forming a step insulating film on a semiconductor substrate; (b) forming a recess in the step insulating film that reaches the semiconductor substrate; (c) forming a gate insulating film on the semiconductor substrate including the bottom of the recess; (d) a gate electrode in contact with the gate insulating film and in contact with the step insulating film; forming a field plate portion integrally with the recess and out of contact with the field plate portion; (e) forming a high dielectric constant film having a dielectric constant higher than that of silicon so as to be in contact with the gate electrode, the field plate portion, the step insulating film, and an inner wall of the recess; A manufacturing method of a semiconductor device comprising: [Explanation of symbols]

[0076] 1. Semiconductor substrate 10 p-type RESURF layer 11 n-type RESURF layer 12 Gate insulating film 13 Potential Control Membrane 14 Step Insulation Film 15 Field plate section 16 Gate electrode 17 Drain Region 18 p-type body region 19 Source Area 20 Body Contact Area 30 High dielectric constant film

Claims

1. A semiconductor substrate; a gate insulating film formed on the semiconductor substrate; a gate electrode formed above the gate insulating film; a field plate portion formed integrally with the gate electrode; a step insulating film in contact with the field plate portion; a high dielectric constant film in contact with the step insulating film and having a dielectric constant higher than that of silicon; Equipped with The high dielectric constant film is a first portion sandwiched between the gate insulating film and the gate electrode; a second portion sandwiched between the step insulating film and the gate insulating film; Including, The gate electrode is in contact with the first portion.

2. 2. The semiconductor device according to claim 1, the high dielectric constant film has a function of forming a potential barrier on the surface of the semiconductor substrate by shifting the Fermi level on the surface of the semiconductor substrate located below the step insulating film.

3. 2. The semiconductor device according to claim 1, The material constituting the high dielectric constant film is HfSiO, HfSiON, HfAlON, Y ２ O ３ , Al ２ O ３ A semiconductor device comprising any one of the above.

4. A semiconductor substrate; a gate insulating film formed on the semiconductor substrate; a gate electrode formed above the gate insulating film; a field plate portion formed integrally with the gate electrode; a step insulating film in contact with the field plate portion; a high dielectric constant film in contact with the step insulating film and having a dielectric constant higher than that of silicon; Equipped with The high dielectric constant film is a film that covers the gate electrode, the field plate portion, and the step insulating film.

5. 5. The semiconductor device according to claim 4, The step insulating film is a contact portion in contact with the field plate portion; a non-contact portion protruding from the field plate portion; having The non-contact portion is a thin film portion having a recess formed therein; a thick film portion having a thickness greater than that of the thin film portion; 13. A semiconductor device comprising:

6. 6. The semiconductor device according to claim 5, a thickness of the thin film portion is equal to a thickness of the gate insulating film.

Images