Digital Radio Head Control

Abstract

Techniques related to digital radio control and operation are described. Various techniques described herein enable high-frequency local oscillator (LO) signal generation using an injection-locked clock multiplier (ILCM). The techniques also include the use of LO signals for carrier aggregation applications for phased array front ends. Additionally, the disclosed techniques include the use of array element-level control using per-chain DC-DC converters. Furthermore, the disclosed techniques include an optimal combination of adaptive spatial filtering and analog-to-digital converters (ADCs) to maximize dynamic range in digital beamforming systems.

Description

[Technical field]

[0001] Aspects described herein relate generally to digital radio, and more particularly to digital radio designs implementing frequency multiplication, digital control, and novel radio architectures. [Background technology]

[0002] Modern RF radios generally utilize a local oscillator (LO) that must be distributed to one or more radio chains (e.g., receiver, transmitter, or transceiver). Additionally, modern RF radios may implement beamforming and / or require high frequency signal distribution. The generation, distribution, and processing of such signals introduces design complexities that must be addressed. For example, modern RF radios suffer from signal loss, excessive power usage (and associated heat generation), and the use of expensive, lossy cables and connectors as interconnects between RF radio boards. Current attempts to solve these and other problems have fallen short. [Brief description of the drawings]

[0003] The accompanying drawings, which are incorporated in and form a part of this specification, illustrate aspects of the present disclosure and, together with the description, serve to explain the principles of the aspects and to enable one skilled in the relevant art to make and use the aspects.

[0004] [Figure 1] 1 illustrates an example of multiphase signal injection to generate one or more LO signals via frequency multiplication, in accordance with an aspect of the present disclosure.

[0005] [Diagram 2] 1 illustrates amplification of desired harmonics and suppression of undesired harmonics as part of LO signal generation according to an aspect of the present disclosure.

[0006] [Diagram 3]1 illustrates a block diagram of an example transceiver design implementing local oscillator distribution and generation in accordance with an aspect of the present disclosure.

[0007] [Figure 4] 1 illustrates a block diagram of an example delay locked loop (DLL) implementing a controlled delay line in accordance with an aspect of the present disclosure.

[0008] [Diagram 5] 1 illustrates a block diagram of an exemplary interpolation delay line in accordance with an aspect of the present disclosure.

[0009] [Figure 6] 1 illustrates a block diagram of an example DLL implementing a two-dimensional delay line in accordance with an aspect of the present disclosure.

[0010] [Figure 7] 7 illustrates an example Mx×My matrix illustrating the phases created for a two-dimensional delay line 600 as shown in FIG. 6 in accordance with an aspect of the present disclosure.

[0011] [Figure 8A] 1 illustrates an injection-locked clock multiplier (ILCM) using serial injection according to an aspect of the present disclosure.

[0012] [Figure 8B] 1 illustrates an injection-locked clock multiplier with parallel injection according to an aspect of the present disclosure.

[0013] [Figure 9A] 1 illustrates an example oscillator circuit that may be used as the oscillator portion of an injection-locked clock multiplier (ILCM) in accordance with an aspect of the present disclosure. [Figure 9B] 1 illustrates an example oscillator circuit that may be used as the oscillator portion of an injection-locked clock multiplier (ILCM) in accordance with an aspect of the present disclosure. [Figure 9C] 1 illustrates an example oscillator circuit that may be used as the oscillator portion of an injection-locked clock multiplier (ILCM) in accordance with an aspect of the present disclosure. [Figure 9D] 1 illustrates an example oscillator circuit that may be used as the oscillator portion of an injection-locked clock multiplier (ILCM) in accordance with an aspect of the present disclosure.

[0014] [Figure 10] 1 shows a block diagram of an apparatus according to an aspect of the present disclosure.

[0015] [Figure 11A] 1 illustrates an example transceiver architecture implementing a single-die digital beamformer that uses multiple operating frequency bands in accordance with an aspect of the present disclosure. [Figure 11B] 1 illustrates an example transceiver architecture implementing a single-die digital beamformer that uses multiple operating frequency bands in accordance with an aspect of the present disclosure. [Figure 11C] 1 illustrates an example transceiver architecture implementing a single-die digital beamformer that uses multiple operating frequency bands in accordance with an aspect of the present disclosure.

[0016] [Figure 12A] 1 illustrates an example transceiver architecture implementing a multiple die digital beamformer using a single operating frequency band in accordance with an aspect of the present disclosure. [Figure 12B] 1 illustrates an example transceiver architecture implementing a multiple die digital beamformer using a single operating frequency band in accordance with an aspect of the present disclosure.

[0017] [Figure 13A] 1 illustrates an example transceiver architecture implementing a multiple-die digital beamformer that uses multiple operating frequency bands in accordance with an aspect of the present disclosure. [Figure 13B] 1 illustrates an example transceiver architecture implementing a multiple-die digital beamformer that uses multiple operating frequency bands in accordance with an aspect of the present disclosure. [Figure 13C]1 illustrates an example transceiver architecture implementing a multiple-die digital beamformer that uses multiple operating frequency bands in accordance with an aspect of the present disclosure.

[0018] [Figure 14] 1 shows a block diagram of an apparatus according to an aspect of the present disclosure.

[0019] [Figure 15] 1 illustrates a block diagram of an exemplary transceiver design in accordance with an aspect of the present disclosure.

[0020] [Figure 16A] 1 shows a block diagram of a conventional transceiver architecture that uses a common DC-DC converter between each of the transceiver chains.

[0021] [Figure 16B] FIG. 1 is a block diagram of a transceiver architecture using multiple DC-DC converters, one for each transceiver chain, in accordance with an aspect of the present disclosure.

[0022] [Figure 17A] Simulated far-field radiation patterns for a 4x4 antenna array with no aperture taper are shown.

[0023] [Figure 17B] 13 illustrates simulated far-field radiation patterns for a 4×4 antenna array with aperture taper, showing reduced side lobe levels in accordance with an aspect of the present disclosure.

[0024] [Figure 18A] As part of a conventional transceiver architecture, a constant amplifier supply voltage is shown using a common DC-DC converter.

[0025] [Figure 18B]1 illustrates a modulated amplifier supply voltage using multiple DC-DC converters, according to an aspect of the present disclosure.

[0026] [Figure 19] 1 illustrates a process flow for voltage standing wave ratio (VSWR) correction and cooperation with a digital predistortion (DPD) front-end module according to an aspect of the present disclosure.

[0027] [Figure 20A] 1 illustrates simulated far-field radiation patterns for a 4×4 antenna array with no element failures, in accordance with an aspect of the present disclosure.

[0028] [Figure 20B] Figure 1 shows simulated far-field radiation patterns for a 4 x 4 antenna array, with three elements disabled or deactivated.

[0029] [Figure 21] 1 shows a block diagram of an exemplary apparatus according to an aspect of the present disclosure.

[0030] [Figure 22] 1 shows a block diagram of an example receiver design using multi-element joint estimation of a received (RX) signal in an adaptive spatial filter in accordance with an aspect of the present disclosure.

[0031] [Figure 23A] 1 shows a block diagram of an example receiver design implementing spatial blocker detection with coarse sector scanning in accordance with an aspect of the present disclosure.

[0032] [Figure 23B] 1 illustrates a block diagram of an example ADC design in accordance with an aspect of the present disclosure.

[0033] [Figure 23C] 1 illustrates a block diagram of an example ADC design using a feedback path in accordance with an aspect of the present disclosure.

[0034] [Figure 24] FIG. 1 illustrates a block diagram of an example receiver design implementing a feed-forward spatial filter using coupling between a set of nearest-neighbor RF chains in accordance with an aspect of the present disclosure.

[0035] [Diagram 25] 1 shows a block diagram of an exemplary apparatus according to an aspect of the present disclosure.

[0036] Exemplary aspects of the present disclosure are described with reference to the accompanying drawings, in which the drawing in which an element first appears is typically indicated by the leftmost digit(s) in the corresponding reference number. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0037] In the following description, numerous specific details are set forth to provide a thorough understanding of aspects of the present disclosure. However, it will be apparent to those skilled in the art that aspects including structures, systems, and methods may be practiced without these specific details. The descriptions and representations herein are the general means used by those skilled in the art to most effectively convey the substance of their work to others skilled in the art. In other instances, well-known methods, procedures, components, and circuits have not been described in detail to avoid unnecessarily obscuring aspects of the present disclosure.

[0038] Section I - Injection-locked clock multiplication for mixer local oscillator (LO) generation

[0039] The aspects described in this section relate generally to transceivers, and more particularly, to transceiver designs that implement a combination of a lower frequency delay locked loop (DLL) and an injection locked clock multiplier (ILCM) to generate a local oscillator (LO) signal at a higher frequency.

[0040] RF transceivers require local oscillators at or near the channel frequency for mixing. For example, one or more LO signals need to be generated at each carrier frequency or channel of interest. For high frequency applications such as millimeter wave (mm-Wave) bands, the required LO signals are typically large signals in terms of signal magnitude. As a result, generating and distributing these mm-Wave LO signals in an on-chip implementation is non-trivial and requires significant power. Furthermore, mm-Wave transceiver designs typically utilize orthogonal LOs, and to further complicate this issue, LO beamforming-based transceivers also require multi-phase LOs. Thus, generating the required LO signals for such transceivers is a complex, expensive, and time-consuming task.

[0041] Again, many transceiver designs, such as mmWave transceivers, implement quadrature multi-phase LOs, for example. Typical solutions for generating these LO signals include direct multi-phase quadrature LO generation techniques that aim to generate mmWave LO signals directly from mmWave phase-locked loops, for example using frequency division, 90° hybrid couplers, and poly-phase filters. The LO signals are then distributed to all transceiver chains in the mmWave system. In the case of 2xLO, local frequency dividers are also used to generate quadrature LO clocks. Phase shifting of the quadrature LO clocks is typically performed in various ways, for example by phase shifting the 2xLO clocks before division. The phase shifting is performed using individual phase shifters for the quadrature LO clocks, or by using a Cartesian combination of the quadrature LO clocks to generate the phase-shifted quadrature LOs.

[0042] However, such conventional techniques require the use of mmWave PLLs, which in turn require mmWave voltage-controlled oscillators (VCOs). These are also non-trivial to design, especially considering the stringent phase noise requirements for modulation according to mmWave standards (e.g., "5G" wireless protocols). As a result, mmWave PLLs consume a significant amount of power. Also, additional power is consumed in distributing the mmWave LO (or 2xLO). Thus, the power consumption of conventional direct multiphase quadrature LO generation solutions is prohibitive, making such solutions unreasonable for handheld and mobile applications.

[0043] Other solutions for mmWave quadrature multiphase LO generation include the use of frequency multiplication-based LO signals. Such designs use a central PLL to generate a clock signal at a sub-harmonic of the LO frequency that is distributed to each transceiver chain. This clock signal is then typically multiplied up to the LO frequency using an injection-locked oscillator or a self-mixing multiplier local to each transceiver. Thus, the phase-shifted quadrature LO can be generated by directly implementing a phase shifter and / or by using a quadrature injection-locked oscillator. Another option specific to this frequency multiplication solution includes the use of a phase shift at a sub-frequency of the LO frequency (i.e., before multiplication). In other words, the order of frequency multiplication and phase shifting may be interchanged according to these conventional approaches.

[0044] Such fractional frequency injection locking amplifies the intended harmonics while suppressing other harmonics of the fractional frequency clock. However, with single-phase fractional frequency injection used according to such techniques, the unintended harmonics are only suppressed by the oscillator tank, which may not be sufficient and may lead to the generation of spurious frequencies. This is also true for self-mixing frequency multiplying topologies.

[0045] At higher frequencies (e.g., mmWave frequencies), generating a square wave clock (e.g., with a 25% duty cycle as per typical usage) is highly inefficient or in some cases impossible depending on the technology node fabrication. Thus, to address the need to generate quadrature multiphase LOs, particularly for mmWave transceivers, including those implementing beamforming, aspects herein implement a combination of a low frequency delay-locked-loop (DLL) and an injection-locked clock multiplier (ILCM) to generate a quadrature phase-shifted mmWave mixer LO signal. Advantageously, typical mmWave transceivers utilize active mixers versus passive mixers for downconversion, and the output of the combined DLL and ILCM aspects described herein is a sine wave suitable for active mixer operation.

[0046] As described in further detail below, aspects include a common RF-PLL implemented with odd fractional frequencies of a desired LO that are distributed to different transceiver chains. Local to each transceiver chain, a DLL is used to generate signals at multiple phases of the LO fractional frequency. An ILCM local to each chain is selectively fed a subset of these generated signals at multiple phases of the LO fractional frequency as inputs to be injected. The ILCM generates, as a result of the injected signals, quadrature phase-shifted large swing LO signals at mmWave frequencies with the appropriate LO phase for each transceiver chain while suppressing the fundamental (i.e., the LO fractional frequency) and its undesired harmonics.

[0047] Advantages arising from the aspects described herein include that the PLL and LO distribution are performed at RF frequencies (rather than mmWave frequencies), saving significant power. Furthermore, the VCO / digitally-controlled oscillator (DCO) in the PLL can be designed for optimal phase noise (without extra penalty in Q degradation for mmWave operation). Furthermore, the divider in the PLL feedback may be CMOS-based rather than current mode logic (CML) and may be injection-locked. Both of these designs save power in the PLL. The RF LO distribution network realized as a result of the aspects described herein also saves power compared to mmWave LO distribution. Thus, the local DLL provides a simple way to generate multiple phases (including quadrature) at LO fractional frequencies, which can be used as a replacement for a frequency-multiplying digital-to-analog converter (FM-DAC) that may otherwise be implemented for this purpose.

[0048] Further benefits include the suppression of undesired harmonics as a result of the injection mechanism into the ILCM, which produces a cleaner frequency spectrum compared to conventional techniques. Furthermore, the direct connection of the ILCM output to the active mixer LO input eliminates the need for additional buffering. The mixer LO input load impedance can also be absorbed into the design of the ILCM block.

[0049] As further referenced in this section and other sections, the term "mm-wave frequencies" in which aspects described in this section and other sections may operate may include frequencies and frequency bands, for example, above 20 GHz, 24 GHz, 28 GHz, etc., up to upper frequency limits. For example, mm-wave frequency bands may include frequencies in the range of 20 GHz to 300 GHz, 24 GHz to 300 GHz, etc. This may include various bands known to be associated with mm-wave frequency bands, such as, for example, 24 GHz, 28 GHz, 37 GHz, 39 GHz, 40 GHz, 47 GHz, 60 GHz, etc., or otherwise referred to as mm-wave frequency bands.

[0050] FIG. 1 illustrates an example of multiphase signal injection to generate one or more LO signals via frequency multiplication, according to an aspect of the present disclosure. As shown in FIG. 1, a local oscillator generation 100 is shown having an injection locked clock multiplier (ILCM) 104 into which multiple phase-shifted signals 102 of a low frequency signal are injected. The low frequencies may be fractional frequencies of a desired high frequency LO signal that is the result of the clock multiplication. In general, as shown in FIG. 1, frequency multiplication may be achieved by injection of a specific set of fractional frequency signals with a specific phase shift relative to each other based on the desired frequency multiplication.

[0051] To provide an illustrative example, to achieve a 5x frequency multiplication, the multiple phase shifted signals 102 each have a frequency that is 1 / 5 of the LO frequency output from the ILCM 104. In one aspect, the multiple phase shifted signals 102 also have a phase shift relative to one another that represents the same percentage of the fractional frequency LO signal. For example, FIG. 1 shows that each of the multiple phase shifted signals 102 are evenly spaced from one another with a phase relationship of 1 / 5 of a full clock cycle, or 2π / 5 (i.e., 72 degrees).

[0052] As a result, coherent summation of the desired harmonics and destructive combining of the undesired harmonics is achieved via the ILCM 104. This technique works particularly well when the desired harmonics are odd. Again, in the example shown in FIG. 1 and described further herein, the desired sub-frequency may be selected as a one-fifth sub-frequency of the desired high frequency LO signal, which may correspond, for example, to an LO signal in the mm-wave frequency band. The use of a one-fifth sub-frequency is by way of example and not limitation. The aspects described herein are not limited to a particular sub-frequency and may be implemented according to any suitable sub-frequency of the LO signal.

[0053] For example, as shown in FIG. 2, aspects include summing multiple phase-shifted signals 102 via an ILCM 104 to produce cancellation (e.g., via destructive interference) of the fractional frequency LO / 5 and its odd harmonics (e.g., 3LO / 5, 7LO / 5, etc.). This signal cancellation may include, for example, that the resulting (summed) signal has a significantly attenuated (e.g., 100% attenuation, 95% attenuation, 90% attenuation, etc.) amplitude compared to either of the individually combined phase-shifted signals. Additionally, aspects include combining multiple phase-shifted signals 102 via an ILCM 104. This produces amplification (e.g., via constructive interference) of the fractional frequencies of the LO signal that are equivalent to the odd harmonics (e.g., 5LO / 5=LO, 15LO / 5=3LO, etc.) of the high frequency LO signal. This signal amplification resulting from constructive interference may include, for example, amplification of the summed signals, such that the resulting (summed) signal, when added together, has an amplitude substantially equal (e.g., within 1%, 5%, 10%, etc.) to the amplitude of the individually combined phase shifted signals. This concept is further illustrated in the spectral power distribution diagram 200 and phase diagram 250, as shown in FIG.

[0054] This concept can be generalized mathematically. When a number (2N+1) of multiple phase-shifted signals are combined, each evenly spaced by 2π / (2N+1) at the frequency of LO / (2N+1), the sub-frequency (lower frequency) LO signals will add coherently at the (higher) LO frequency (and harmonics of the LO signal frequency) and cancel all other odd harmonics of LO / (2N+1) as a result of destructive interference, where N represents any integer. In conventional frequency multiplication techniques that implement injection locking or self-mixing, these sub-frequencies are essentially not cancelled, thus leading to the generation of possible spurs within one or more critical frequency bands of interest. It is therefore advantageous to use this polyphase signal injection and phase summing technique to generate a higher frequency LO signal using a lower frequency signal.

[0055] Not shown in FIG. 1, but described further below for ease of illustration, the multiple phase shifted signals 102 may be a selected subset of the superset of additional phase shifted signals that are then injected into the ILCM 104. In certain aspects, the multiple phase shifted signals 102 may include both in-phase and quadrature-phase signal components, as discussed further below. For example, the multiple phase shifted signals 102 shown in FIG. 1 may represent in-phase signal components having relative phases relative to one another of 0°, 72°, 144°, 216°, and 288°. Although not shown in FIG. 1 for simplicity, the multiple phase shifted signals 102 injected into the ILCM 104 may further include quadrature-phase signal components. Continuing with the previous example, the multiple phase shifted signals 102 shown in FIG. 1 may further include such quadrature-phase signal components having relative phases relative to one another of 90°, 162°, 234°, 309°, and 16°.

[0056] 3 illustrates a block diagram of an example transceiver design implementing local oscillator distribution and generation in accordance with certain aspects of the present disclosure. As illustrated in FIG. 3 and further described herein, the transceiver design 300 includes any suitable number K of separate local oscillator generation (LOG) units 304.1-304.K. Each of the LOG units 304.1-304.K may include a respective LOG circuit 306, which includes a delay locked loop (DLL) 306.1, a phase configuration circuit 306.2, and an ILCM 306.3.

[0057] As further described herein with reference to FIG. 10, aspects include a transceiver design 300 implemented as part of an overall transceiver design with some components omitted for brevity and ease of description. For example, the transceiver design 300 allows for a separate set of LO signals to be generated for each receiver chain RX-1 through RX-K in the transceiver design (i.e., each receiver chain present within each transceiver chain or alternatively present as part of a dedicated receiver system), which may then be utilized by each transceiver chain for downconversion and subsequent signal processing of received signals. As shown in FIG. 3 as an example, the set of LO signals generated via each LOG unit 304 may be orthogonal differential LO signals. Also, since each transceiver chain is provided with its own set of LO signals, phase variations between different transceiver chains may be facilitated in this manner. Thus, aspects described herein may be particularly useful for transceivers that implement beamforming via multiple antennas. This is because each transceiver chain may utilize its own dedicated set of orthogonal LO signals with phase tuned for that particular transceiver chain and antenna combination.

[0058] Thus, aspects include each transceiver chain using a respective set of LO signals for downconversion, demodulation, and signal processing. To do so, various aspects include each of the individual receiver chains RX-1 through RX-K including additional components, circuits, processors, antennas, etc., such that the received signals are received and the data contained therein is processed accordingly. For example, these additional components may include mixers, demodulators, filters, amplifiers, processors, etc., and the processing of the received data is performed, for example, via one or more processors (e.g., baseband processors) in combination with any other suitable components. For example, once the LO signals are generated, they may be used according to any suitable technique (e.g., known techniques) to process the data contained within the wirelessly received signals.

[0059] In one aspect, the transceiver design 300 includes a common phase-locked loop (PLL) circuit 302 that generates a reference clock signal that may be used as an input signal by each of the LOG units 304.1-304.K. This input signal may be generated at a sub-harmonic frequency of a desired higher frequency LO signal, as discussed with reference to FIG. 1. In aspects, the higher frequency LO signal may have a frequency associated with the mmWave spectrum, such as the proposed 24 GHz to 86 GHz spectrum, for example. However, aspects are not limited to this particular band, and aspects described herein may be implemented according to any frequency or frequency range suitable for a particular wireless communication application.

[0060] The common PLL circuit 302 may be implemented using any suitable and / or known circuit components to generate the reference clock signal. As shown in FIG. 3, the common PLL circuit 302 generates the reference clock signal at a fractional frequency of the high frequency LO signal represented by LO / (2N+1), where LO is the higher target LO signal frequency, and N is any positive integer value based on the desired frequency multiplication scaling used for a particular application. The input signal generated at the fractional frequency of the high frequency LO signal is then distributed to any suitable number K of individual RX chains RX-1 through RX-K via respective LOG units 304.1 through 304.K.

[0061] Again, the reference signal (or "input signal" as used with respect to the input to the LOG units 304.1-304.K) may be generated at a lower frequency than the target LO signal (e.g., at an RF frequency as opposed to a mmWave frequency) by utilizing frequency multiplication. As a result, the input signal may be distributed to each receiver chain RX-1-RX-K using a power distribution system that advantageously conserves power and requires less design effort compared to implementations used for higher frequency signals. This may be particularly advantageous, for example, when the transceiver design 300 implements "massively" distributed transceiver chains, such as tens, tens, hundreds, etc. In an aspect, each receiver chain RX-1-RX-K implements a respective LOG circuit 304 that performs frequency multiplication and phase shifting using the input signal, as shown in more detail for receiver chain 304.2 and discussed further below.

[0062] For example, LOG unit 306 is shown in FIG. 3 as being associated with receiver chain RX-2 and LOG unit 304.2. Again, aspects include each of receiver chains RX-1 through RX-K implementing a separate LOG unit such as LOG unit 306, but for brevity, only operational details of LOG unit 306 are discussed herein. In an aspect, LOG unit 306 includes a delay locked loop (DLL) 306.1, a phase configuration circuit 306.2, and an ILCM 306.3. In an aspect, LOG unit 306 can receive a reference clock signal generated by a common PLL circuit 302 and provide a set of quadrature LO signals as an output. As shown in FIG. 3, these quadrature LO signals may be, for example, differential quadrature LO clock signals. Although aspects are described herein primarily with reference to LO clock signals as being quadrature and differential in nature, aspects are not limited thereto and may include the generation of any suitable number or type of LO signals having any relationship to one another suitable for signal processing of a received wireless signal.

[0063] In any event, aspects include the generated set of LO signals having a higher target frequency (e.g., a millimeter wave frequency) and the set of LO signals includes a 0 degree in-phase LO signal component (I), a 180 degree in-phase LO signal component (I), and a 180 degree in-phase LO signal component (I).

number

number

[0064] In other words, the generated quadrature LO signals may include LO signal components having phases of 0, 90, 180, and 270 degrees relative to one another, but each of LOG units 204.1-204.K may generate its own set of quadrature LO signals that may be phase shifted relative to another set of quadrature LO signals. For example, the quadrature LO signals generated by LOG unit 304.1 may be 90 degrees apart from one another, but phase shifted by 5, 10, 15, etc. degrees from the quadrature LO signals generated by LOG unit 304.2. Details regarding how the quadrature LO signals are generated via each LOG unit 304.1-304.K are discussed further below.

[0065] In various aspects, the DLL 306.1 may be implemented using a variety of architectures, each offering a tradeoff of increased design complexity in exchange for more precise control over the phases used to generate the quadrature LO signals. In some aspects, the DLL 306.1 may be implemented as a multi-stage controlled delay line, an example of which is shown in FIG. 4 as DLL 400. In some aspects, the DLL 400 may generate multiple fractional phase signals that are input to the phase configuration circuit 306.2. Further, according to such aspects, the DLL 400 may include a phase detector and loop filter 402, which may be implemented as one or more processors configured to execute computer readable instructions, for example, to control the state of one or more of the M delay elements 404.1-404.M included in the M-stage controlled delay line 404. Although the M-stage controlled delay line 404 is illustrated in FIG. 4 as implementing inverters as the delay elements 404.1-404.M, aspects include the M-stage controlled delay line 404 being implemented using any suitable type and / or combination of delay elements 404.1-404.M, such as buffers.

[0066] In one aspect, the phase detector and loop filter 402 can facilitate analog and / or digital control over the M-stage controlled delay line 404, which can be tuned to ensure that the input and output of the delay line are separated by one clock period. The clock signal may include a distributed input signal generated by the common PLL circuit 302, for example, as described with reference to FIG. 3. Additionally, the phase detector and loop filter 402 can control the state of the delay elements implemented by the M-stage controlled delay line 404 using any suitable technique, such as via load control, current starving control, power supply control, etc.

[0067] In any event, aspects include a DLL 400 that provides a set of phase-shifted signals to the phase configuration circuit 306.2. These phase-shifted signals are separated by a phase that is a function of the number M of delay elements 404.1-404.M, as shown in FIG. 4. Thus, the unit phase granularity (i.e., "CLK phase") associated with the amount of phase shift between the set of phase-shifted signals provided by the DLL 400 increases with the number M of delay elements 404.1-404.M. However, the DLL 400 is limited in that, in some cases, the unit phase shift (2π / M) equivalent time delay may be reduced beyond the unit inverter delay of an individual delay element. Thus, to allow finer granularity of unit phase shift, aspects include implementing alternative types of delay lines, as discussed further below with respect to FIGS. 5 and 6.

[0068] FIG. 5 illustrates a block diagram of an exemplary interpolated delay line according to an aspect of the present disclosure. In an aspect, the DLL 306.1 shown in FIG. 3 may be implemented utilizing the interpolated delay line 500 shown in FIG. 5 by modifying the implementation of the DLL 400 shown in FIG. 4. For example, the M-stage controlled delay line 404 may be replaced with other delay element configurations such as the interpolated delay line 500 shown in FIG. 5. Thus, according to such an aspect, the DLL 306.1 may be implemented as a combination of the phase detector and loop filter 402 as shown in FIG. 4 and the interpolated delay line 500 as shown in FIG. 5.

[0069] Interpolated delay line 500 includes delay elements represented as inverters in FIG. 5, although aspects include interpolated delay line 500 implementing any suitable type of delay element. As shown in FIG. 5, a number M of delay elements may be associated with one clock cycle, and number k may represent any element number between 1 and M. For example, the phase at a node labeled (k+1)*(2π / M) may be associated with delay element 502.k. By shifting the inputs between each row as shown in FIG. 5, the set of phase-shifted signals provided by DLL 500 can provide unit phase shifts of (k*2π / M), (k+1)*(2π / M), (k+2)*(2π / M), etc., representing a greater level of phase granularity compared to DLL 400. In other words, DLL 500 utilizes interpolation between sets of delay elements to overcome the limitations imposed by DLL 400, achieving a unit phase shift that is smaller than that associated with the delay of an individual delay element.

[0070] 4 and 5, respectively, each DLL represents a single DLL implemented in a particular configuration (e.g., interpolating DLL 500 versus non-interpolating DLL 400). In other aspects, more than one DLL may be implemented to achieve even finer control over the unit phase shift, as discussed further below.

[0071] FIG. 6 illustrates a block diagram of an example DLL implementing a two-dimensional delay line according to an aspect of the disclosure. In one aspect, DLL 306.1 can be implemented as a two-dimensional delay line 600, as shown in FIG. 6. Two-dimensional DLL 600 can implement two separate delay line control systems, DLL-X core 602 and DLL-Y core 604, each controlling a respective set of delay elements, similar to DLLs 400 and 500. Also, similar to DLLs 400 and 500, two-dimensional delay line 600 can implement any suitable type of control (load control, current starving control, power control, etc.) on the delay elements, which can be implemented as any suitable type of delay element. Thus, like DLLs 400 and 500, two-dimensional DLL 600 can receive at input 606 a reference clock signal generated by a common PLL circuit 302 and output any suitable number of phase-shifted versions of the reference clock signal. These phase-shifted reference clock signals can then be utilized by phase configuration circuit 306.2 to inject a particular subset of phase-shifted signals into ILCM 306.3, as described below. In this manner, ILCM 306.3 facilitates frequency multiplication of the subset of phase-shifted input signals to generate a set of LO signals at a desired frequency and phase.

[0072] However, unlike the DLL 400 and 500, the sides are x ×M y The DLL-X core 602 includes a two-dimensional DLL 600 that includes two orthogonal sets of M delay elements forming a two-dimensional matrix of delay elements having a delay element size of M. Aspects include matrices having any suitable dimensions and need not be symmetrical. In this manner, the delay element matrix is ​​configured as shown in FIG. 6, with the DLL-X core 602 including M x The DLL-Y core controls M delay elements. y Further, as shown in detail portion 608, the two-dimensional matrix of delay elements may be interleaved with one another such that each node in the two-dimensional matrix is ​​fed by two delay elements.

[0073] In certain aspects, each delay element is typically controlled by a DLL (-X or -Y) core output. However, the "up" delay element chain (i.e., the last inverter output returns as an input to the DLL-X core) and the "left" delay element (i.e., the last inverter output returns as an input to the DLL-Y core) are "fully" controlled, i.e., their delays are controlled and constrained by their respective DLLs. Outside of these chains, other delay elements are partially controlled by the DLLs. Thus, aspects include leveraging the configuration of the two-dimensional DLL 600 to reduce delay variation in stages that are not fully controlled by the DLL. As an additional benefit, the two-dimensional DLL 600 allows for more orderly "floorplanning" of the design, which in some aspects may advantageously allow for easier implementation than the DLL 400 or 500. An example M illustrating the phases produced by the two-dimensional delay line 600 is shown in FIG. x ×M y The matrix is ​​shown in FIG.

[0074] In various aspects, the appropriate phase may be generated by any suitable delay line implementation, such as, for example, any of DLLs 400, 500, or 600. In other words, each LOG unit 304 can output the appropriate phase via its respective DLL 306.1, which is then selected by the phase configuration circuit 306.2 portion of the LOG unit 304 as further described below and injected into the ILCM 306.3 to provide the desired LO signal for each receiver chain.

[0075] In other words, referring to FIG. 3, aspects include the DLL 306.1 generating a superset of phases required to ensure frequency multiplication by the ILCM 306.3. Aspects include the DLL 306.1 generating phase shifted input signals with phase differences according to the implemented DLL architecture for all desired beam angle scenarios. The phase configuration circuitry may be controlled via a phase control block 308 that may generate one or more control signals via one or more processors executing stored instructions. In some aspects, the phase control block 308 may represent a pure hardware solution. In any case, the phase configuration circuitry may be implemented with any suitable number and / or type of switching elements to selectively couple and inject the signals generated by the DLL 306.1 into the ILCM 306.3.

[0076] By selectively injecting particular combinations of phase shifted input signals from the superset generated by DLL 306.1 (i.e., a subset of the superset), phase configuration circuit 306.2 ensures that the appropriate phase shifted (in-phase and quadrature) input signals are injected into ILCM 306.3. Thus, by discriminatively selecting certain generated phase shifted input signals, variations in frequency (i.e., proper frequency scaling) and phase of the output quadrature LO signals can be achieved.

[0077] In certain aspects, as described further below, the ILCM 306.3 may implement any suitable type of architecture to ensure frequency multiplication and generate the LO signal at the appropriate frequency and phase shift. As discussed further below with reference to Figures 8A-8B, the ILCM 306.3 may be implemented using any suitable type of hardware circuitry configured to perform injection locking and may implement any suitable type of oscillator topology.

[0078] In certain aspects, the ILCM 306.3 may implement a series or parallel injection architecture, as separately described below with reference to FIGS. 8A-8B. Each architecture presents a tradeoff with respect to current consumption, start-up gain requirements, and lock range capabilities. Regardless of the particular ILCM architecture used, aspects include injecting each of the phase shifted input signals selected by the phase configuration circuit 306.2 into the ILCM 306.3, which implements one or more oscillators tuned to a frequency equal to or substantially the same (e.g., 1%, 5%, 10%, etc.) as the intended LO frequency. In other words, the oscillator(s) implemented within the ILCM 306.3 may be tuned to have a natural oscillation frequency that is a particular harmonic of a sub-harmonic frequency associated with the phase shifted input signals provided by the phase configuration circuit 306.2. To provide an illustrative example using five clock signals as shown in Figures 1 and 2, the oscillator(s) implemented as part of ILCM 306.3 may be tuned to have a natural resonance at the LO frequency, which is a fifth harmonic frequency of the sub-frequency and therefore resonates at said frequency.

[0079] Conventional ILCM circuits are typically designed to inject a signal and lock to the closest harmonic frequency of the injected signal to generate frequency multiplication. However, because the harmonic content of the signal may be somewhat weak, the resulting phase lock range is typically quite narrow and the resulting phase noise may be difficult to track. Furthermore, in some cases, because the harmonics are significant and are not inherently suppressed (as in the case of the aspects described herein), conventional ILCM circuits risk locking to the wrong harmonic and thus resonating at an undesired frequency.

[0080] As discussed herein with reference to FIG. 2, aspects described herein address these issues by using a multiphase signal injection approach that uses phase intervals that can be selectively adjusted based on the desired frequency multiplication desired. By doing so, unwanted harmonics of the fractional frequency signal are rejected or suppressed, which helps prevent false locking that occurs at these unwanted harmonic frequencies. Furthermore, by injecting a specific subset of input signals (i.e., signals with a specific phase relationship to each other) that are phase shifted at fractional frequencies of the LO frequency, constructive interference of these phase shifted input signals produces signals with higher signal strength, making injection locking at the desired higher LO frequency more certain and frequency multiplication easier.

[0081] For example, as shown in FIG. 3, a subset of the phase-shifted input signals provided by the phase configuration circuit 306.2 are coupled to a set of in-phase (I) and quadrature (Q) buffers. Currents provided by these buffers are then injected into the ILCM 306.3. The ILCM 306.3 includes an oscillator configured in either a series or parallel architecture that receives input currents from the I and Q buffers associated with the combined phase-shifted signals. As a result, the oscillator sums the combined phase-shifted signals, resulting in constructive interference at the desired LO frequency, as described herein, assuming the injected signals have the appropriate phase relationship between each other for the desired level of frequency multiplication. This summation can occur in either the current domain or the voltage domain, depending on the particular oscillator implementation used in various aspects.

[0082] FIG. 8A illustrates an injection-locked clock multiplier (ILCM) using series injection according to an aspect of the present disclosure. As shown in FIG. 8A, the series injection ILCM 800 is represented via a feedback path 806 coupled between a tank circuit 804 and an oscillator circuit 802, which provides a transconductance gain Gm that represents the gain used in the oscillator circuit 802 to drive the tank circuit and compensate for natural losses. Details of the oscillator circuit 802 are not shown for brevity, but aspects include the ILCM 800 implementing any suitable type of oscillator topology. For example, aspects include the oscillator circuit 802 implemented using any known configuration of transistors to provide a suitable transconductance gain. This may include, for example, a common source amplifier, cross-coupled transistors, etc. As shown in FIG. 8A, the ILCM 800 uses serial injection locking, which couples multiple combined phase-shifted signals to an oscillator circuit 802, which is in turn coupled to a tank circuit 804.

[0083] FIG. 8B illustrates an injection-locked clock multiplier (ILCM) using parallel injection according to an aspect of the present disclosure. The ILCM 850 as shown in FIG. 8B operates in a similar manner as the ILCM 800 as shown in FIG. 8B. Similar to the ILCM 800 shown in FIG. 8A, the ILCM 850 shown in FIG. 8B is represented via a feedback path 856 coupled between a tank circuit 854 and an oscillator circuit 852, which drives the tank circuit 854 and provides a transconductance gain Gm that represents the gain used in the oscillator circuit 852 to compensate for natural losses. As with the ILCM 800, details of the oscillator circuit 852 for the ILCM 850 are not shown for simplicity, but aspects include the ILCM 850 implementing any type of oscillator topology or known configuration of transistors to provide a suitable transconductance gain. As shown in FIG. 8B, the parallel injection locked configuration of ILCM 850 injects multiple phase shifted input signals directly into tank circuit 854.

[0084] Regardless of whether the ILCM configuration is a series or parallel implementation, the aspects are the same as in this example. LO 8A-8B, for five multi-phase signals, the phase noise of the injected signal is 20log / 5 at the output ("out") of each ILCM 800, 850. 10 (5) = 14 dB. To provide a more general expression, the aspects are 10 Includes untransformed phase noise by a factor of (2N+1)=14 dB, where N is any integer used according to the generation of the particular sub-frequency LO signal frequency (N=2 for 5 in the example shown in FIGS. 8A-8B).

[0085] Although the ILCMs 800, 850 shown in Figures 8A and 8B, respectively, depict a single oscillator circuit, the ILCM 306.3 may be implemented with any suitable number of oscillator circuits to output any suitable number of LO signals. For example, the phase shifted input signals output by the phase configuration circuit 306.2 may be coupled to any suitable number of oscillator circuits implemented via the ILCM 306.3. For example, the ILCM 306.3 may implement two different oscillator circuits, one for the in-phase (I) phase shifted signal output by the phase configuration circuit 306.2 and another for the quadrature (Q) phase shifted component. Providing another example, the ILCM 306.3 may implement a quadrature oscillator system that receives the I and Q phase shifted signals output by the phase configuration circuit 306.2 and generates a higher frequency quadrature phase shifted LO signal, as shown in Figure 3. In one aspect, this may be accomplished by phase shifting the LO signals generated via respective I and Q dedicated oscillator circuits by 180 degrees (e.g., via inverters or other suitable circuit components).

[0086] In one aspect, the LO signal output by the ILCM 306.3 may be fed directly to a higher frequency (e.g., mmWave) mixer, as shown in Figure 3. Advantageously, since the load of an active mixer is typically capacitive in nature, this is absorbed by the oscillator circuitry implemented as part of the ILCM 306.3 as a fixed capacitance during design, eliminating the need for an additional buffer.

[0087] 9A-9D illustrate example oscillator circuits that may be used as an oscillator portion of an injection-locked clock multiplier (ILCM) in accordance with aspects of the present disclosure. In particular, the oscillator circuits illustrated in FIGS. 9A-9D include two different oscillator configurations, by way of example and not by way of limitation. For example, as described further below, FIGS. 9A-9B illustrate two parts of an overall quadrature voltage-controlled oscillator (QVCO) implementation, while FIGS. 9C-9D illustrate a mutually exclusive dual VCO implementation. Again, the example oscillator configurations illustrated in FIGS. 9A-9D are for ease of explanation, and aspects described herein may implement any suitable number and / or type of oscillator configurations as part of an ILCM circuit. For example, aspects include an oscillator implemented as a Colpitts oscillator or a transformer feedback oscillator. In any event, as discussed herein, aspects include an oscillator that is tuned to a frequency equal or substantially the same (eg, within 1%, 5%, 10%, etc.) as the intended LO frequency.

[0088] In certain aspects, the oscillator circuits shown in FIGS. 9A-9B and 9C-9D may be implemented as part of the ILCM 306.3 as shown in FIG. 3, and thus may be identified with the oscillator circuits 802, 852 as shown in FIGS. 8A-8B. The oscillator circuits shown in FIGS. 9A-9D may be implemented according to any suitable known oscillator design techniques. For example, as shown in FIGS. 9A-9D, the QVCO and dual VCO oscillator circuits may include transistors, tunable capacitors and / or inductors forming a tank circuit, and a voltage source Vdd. The tunable components included in the oscillator configuration may be controlled, for example, via an ILCM tuning control module 1010, as further described below with respect to FIG. 10.

[0089] Additionally, each of Figures 9A-9D illustrates a quadrature sub-frequency injection mechanism for coupling a subset of the phase shifted signals generated via phase configuration circuit 306.2 (as shown in Figure 3) to ILCM 306.3 via respective I and Q buffered lines. For example, Figures 9A-9D each illustrate a sub-frequency signal 902 (for the in-phase component) and a sub-frequency signal 904 (for the quadrature component) that are combined via a parallel inverter arrangement. In the example illustrated in Figures 9A-9D, sub-frequency signals 902, 904 are combined via a parallel inverter arrangement as described herein. LO A quadrature five-phase clock signal having a fractional frequency of f / 5 (e.g., a multiple phase shift signal 102 as shown in FIG. 1, f LO 9A-9D , the injection mechanisms are by way of example and not by way of limitation, and aspects include injection mechanisms implemented using any suitable configuration to combine these signals for ILCM injection.

[0090] Reference is now made to Figures 9A-9B. An exemplary QVCO implementation illustrates a quadrature fractional-frequency injection scheme for a subset of phase-shifted signals corresponding to the in-phase (Figure 9A) and quadrature-phase (Figure 9B) signal components provided by phase configuration circuit 306.2 as shown in Figure 3. As shown in Figure 9A, the quadrature fractional-frequency injection scheme generates a phase-shifted signal 902 (referred to herein as I, or I+ in Figures 9A-9D) associated with each of the in-phase components and its 180 degree phase-shifted version (referred to herein as I+ in Figures 9A-9D).

number

number

[0091] Similarly, in FIG. 9B, the quadrature fractional frequency injection mechanism combines the phase shifted signals 904 associated with each of the quadrature phase components Q+ with their 180 degree phase shifted versions (Q-), which are then coupled to the tank circuit input as shown on the left in FIG. 9B. Thus, the QVCO implementation shown in FIG. 9B uses the injected combined subset of the phase shifted signals corresponding to the quadrature phase signal components Q+, Q- to generate the in-phase LO signal components I+, I-. In this manner, the QVCO implementation shown in FIGS. 9A-9B can use the combined fractional frequency phase shifted signals of each signal component I+, I-, Q+, Q- to be frequency multiplied while suppressing unintended harmonics, as discussed herein. This allows the QVCO implementation shown in FIG. 9A-9B to ... LO / 5, or in this example, f LOThe first step is to generate a quadrature differential LO signal (in this example) as shown in FIG.

[0092] 9C-9D, an exemplary dual VCO implementation shows a quadrature fractional-frequency injection mechanism for a subset of phase-shifted signals 902, 904 corresponding to in-phase signal components I+, I- (FIG. 9C) and quadrature-phase components Q, Q+ (FIG. 9D) provided by phase configuration circuit 306.2 as shown in FIG. 3. The quadrature fractional-frequency injection mechanism as shown in FIGS. 9C and 9D can function in the same or substantially similar manner as the quadrature partial-frequency injection mechanism as shown in FIGS. 9A-9B, again by way of example and not limitation. As shown in FIG. 9C, the quadrature fractional-frequency injection mechanism combines the phase-shifted signals 902 associated with the in-phase components I+, I-, which are then coupled to the tank circuit input shown on the right in FIG. 9C. Similarly, in FIG. 9D, the quadrature fractional-frequency injection mechanism combines the phase-shifted signal 904 associated with the quadrature-phase component Q+, which is then coupled to the tank circuit input shown on the left in FIG. 9D. In this manner, each separate VCO configuration shown in FIGS. 9C and 9D, respectively, can generate one half of the overall quadrature differential LO signal (in this example) as shown in FIG.

[0093] FIG. 10 illustrates a block diagram of an apparatus according to an aspect of the disclosure. In various aspects, the apparatus 1000 may be implemented as any suitable type of apparatus configured to transmit and / or receive wireless signals according to any suitable number and / or type of communication protocols. For example, the apparatus 1000 may be implemented as a user equipment (UE), such as a mobile phone, tablet, laptop computer, etc. Providing an additional example, the apparatus 1000 may be implemented as an access point or base station. The apparatus 1000 may implement one or more aspects described herein to facilitate receiving wireless signals according to a frequency or frequency band, such as, for example, a millimeter wave frequency, as described further below.

[0094] In certain aspects, the device 1000 may include a processing circuit 1002, a memory 1004, and any suitable number N of transceiver chains 1012.1-1012.N, each coupled to one or more respective antennas 1014-1-1014.N. The components illustrated in FIG. 10 are provided for ease of explanation, and aspects include device 1000 including additional, fewer, or alternative components to those illustrated in FIG. 10. For example, device 1000 may include one or more power sources, display interfaces, peripherals, ports, etc. To provide additional examples, device 1000 may alternatively include one or more transmitter chains or receiver chains capable of transmitting and receiving wireless signals via antennas 1014.1-1014.N, respectively, instead of one or more of the transceiver chains 1012.1-1012.N.

[0095] In certain aspects, various components of the device 1000 may be equated with functionality described further herein with respect to generation of an LO signal using a common reference signal or input signal at a fractional frequency of the LO frequency. For example, the wireless device 1000 may be configured to receive wireless signals at millimeter wave or other suitable frequencies via one or more of the antennas 1014.1-1014.N and demodulate and process data contained in the wirelessly received signals via the transceiver chains 1012.1-1012.N. One or more of the transceiver chains 1012.1-1012.N shown in FIG. 10 may be equated with a respective transceiver chain including, for example, a respective receiver chain (RX-1-RX-K) as shown in FIG. 3, each of which may include a respective LOG unit (304.1-304.K) as shown in FIG. 3. Thus, the transceiver chains 1012.1-1012.N may include additional components (mixers, demodulators, filters, amplifiers, etc.) to generate LO signals from a common PLL operating at a fractional LO frequency, as discussed herein.

[0096] To do so, the processor circuit 1002 may be configured as any suitable number and / or type of computer processor that may facilitate control of the device 1000 as described herein. In some aspects, the processor circuit 1002 may be identified with a baseband processor (or a suitable portion thereof) implemented by the device 1000. In other aspects, the processor circuit 1002 may be identified with one or more processors implemented by the device 1000 that are separate from the baseband processor. In any event, aspects include a processor circuit 1002 configured to execute instructions to perform arithmetic operations, logical operations, and / or input / output (I / O) operations and / or to control operation of one or more components of the device 1000. For example, the processor circuit 1002 may include one or more microprocessors, memory registers, buffers, clocks, etc. Additionally, aspects include a processor circuit 1002 in communication with and / or controlling functions associated with the memory 1004 and / or the transceiver chains 1012.1-1012.N. This may include, for example, controlling and / or coordinating the transmission and / or reception functions of device 1000 and performing one or more baseband processing functions (e.g., medium access control (MAC), encoding / decoding, modulation / demodulation, data symbol mapping, error correction, etc.).

[0097] In one aspect, the memory 1004 stores data and / or instructions that, when executed by the processor circuitry 1002, cause the processor circuitry 1002 to perform various functions described herein. The memory 1004 can be implemented as any known volatile and / or non-volatile memory including, for example, read only memory (ROM), random access memory (RAM), flash memory, magnetic storage media, optical disks, erasable programmable read only memory (EPROM), programmable read only memory (PROM), etc. The memory 1004 can be non-removable, removable, or a combination of both.

[0098] For example, the memory 1004 may be implemented as a non-transitory computer-readable medium that stores one or more executable instructions, such as, for example, logic, algorithms, executable code, etc. As described further below, the instructions, logic, code, etc. stored in the memory 1004 are represented by various modules, such as those illustrated in FIG. 10, that enable the aspects disclosed herein to be functionally realized. The modules illustrated in FIG. 10 are provided to facilitate the description of the functional associations between the hardware and software components. Thus, the aspects include a processor circuitry 1002 that executes the instructions stored in these respective modules, along with one or more hardware components, to perform various functions associated with the various aspects, as described further herein.

[0099] In one aspect, the executable instructions stored in the phase generation module 1006, in conjunction with the processor circuitry 1002, may facilitate generation of phases via any suitable type of DLL (e.g., DLLs 400, 500, 600, etc.). For example, the executable instructions stored in the phase generation module 1006 may provide functionality associated with a phase detector and loop filter 402, as shown in FIG. 4, to manage control of an M-stage controlled delay line 404 for DLL 400 or DLL 500, depending on the particular implementation used by the apparatus 1000. Providing another example, the executable instructions stored in the phase generation module 1006 may provide functionality associated with each of a DLL-X core 602 and a DLL-Y core 604, as shown in FIG. 6, to control the phase generated by a two-dimensional DLL 600.

[0100] In one aspect, the executable instructions stored in the phase control module 1008, in conjunction with the processor circuitry 1002, can facilitate the selection of phases generated by the DLL implemented by the apparatus 1000. For example, the executable instructions stored in the phase control module 1008 can provide functionality associated with the phase control block 308 as shown in FIG. 3. Thus, the phase control module 1008 enables the selection of a subset of the phase shifted input signals generated by the implemented DLL and ensures that the appropriate subset of phase shifted signals are injected into the ILCM 306.2 to effect frequency multiplication, ensuring that undesired harmonics are suppressed, and that LO signals are generated at the appropriate phase for each of the transceiver chains 1012.1-1012.N. For example, the phase control module 1008 may facilitate the processing circuit 1002 interfacing and communicating with the phase configuration circuit 306.2, as shown in FIG. 3, and generating control signals that cause the phase configuration circuit 306.2 to couple a subset of the superset of the phase shifted signals generated by the DLL 306.1 to the I and Q buffer lines.

[0101] When implemented, the phase control module 1008 may include instructions regarding how certain frequencies and phases are generated from fractional frequency phase combinations. For example, the executable instructions stored in the phase control module 1008 may include lookup tables and / or instructions regarding calculations to be performed to determine a particular set of phases that will generate a desired set of LO signals at a target (multiplied) frequency with a given phase shift. For quadrature LO aspects, these instructions may include instructions for each transceiver chain 1012.1-1012.N to generate the desired LO signal components, as shown in FIG. 3, for signal downconversion, for example.

number

[0102] In certain aspects, the executable instructions stored in the ILCM tuning control module 1010, in conjunction with the processor circuit 1002, can likewise facilitate the processing circuit 1002 interfacing with, communicating with, and / or controlling one or more components of the ILCM 306.3 as shown in FIG. 3. For example, although not shown in the drawings for simplicity, one or more components of the ILCM 306.3 may be electronically adjustable. This may include, for example, one or more components of the tank circuits 804, 854 as shown in FIGS. 8A-8B, or any other suitable components of the ILCM 306.3. Continuing with this example, the executable instructions stored in the ILCM tuning control module 1010 can facilitate the generation of tuning control signals that can vary the inductance, capacitance, resistance, etc. of components implemented by the ILCM 306.3.

[0103] If implemented, the ILCM tuning control module 1010 may include instructions regarding how to tune the ILCM 306.3 for a certain frequency of operation of the apparatus 1000 such that the injected polyphase signal has a particular frequency in a frequency range. For example, the executable instructions stored in the ILCM tuning control module 1010 may include lookup tables and / or instructions regarding calculations to be performed to determine a particular combination of tuning values ​​(e.g., inductance, capacitance, resistance, etc.) that dynamically adapt to changes in the injected polyphase signal frequency.

[0104] Section II - Local Oscillator (LO) Generation for Carrier Aggregation in Phased Array Front-Ends

[0105] The aspects described in this section relate generally to transceivers, and more particularly, to transceiver designs implementing single phase-locked loop LO generation for phased array front-ends.

[0106] RF transceivers require local oscillators (LOs) at or near the channel frequency for mixing. For example, one or more LO signals need to be generated at each carrier frequency or channel of interest, and each transceiver chain may utilize a separate set of LO signals for phased array applications. Furthermore, inter-band carrier aggregation (CA), which requires two LO frequencies simultaneously, increases the number of LO signals implemented by a phased array transceiver design, further complicating the challenges associated with LO signal generation and distribution. For example, for digital phased arrays, the number of LO signals can exceed 16 or more, which leads to LO distribution consuming a large percentage of the system power. As a result, generation and distribution of high frequency LO signals (e.g., mmWave frequencies) in on-chip implementations is non-trivial and requires significant power. Thus, generating the required LO signals for such transceivers is a complex, expensive, and time-consuming task.

[0107] Many RF transceiver designs implement quadrature multiphase LOs for use in phased array applications. For mmWave phased array applications, phase noise can be the dominant contributor to error vector magnitude (EVM) degradation, and therefore transceiver designs need to generate multiple spectrally pure (orthogonal) LOs at mmWave frequencies while maintaining low power consumption. However, as mentioned above, conventional mmWave transceivers utilize LO distribution schemes that consume a lot of power.

[0108] As further referenced in this section and other sections, the term "mm-wave frequencies" in which aspects described in this section and other sections may operate may include frequencies and frequency bands, for example, above 20 GHz, 24 GHz, 28 GHz, etc., up to upper frequency limits. For example, mm-wave frequency bands may include frequencies in the range of 20 GHz to 300 GHz, 24 GHz to 300 GHz, etc. This may include various bands known to be associated with mm-wave frequency bands, such as, for example, 24 GHz, 28 GHz, 37 GHz, 39 GHz, 40 GHz, 47 GHz, 60 GHz, etc., or otherwise referred to as mm-wave frequency bands.

[0109] Typical solutions for generating these signals include the use of multiple high performance fractional phase-locked loops (PLLs). However, especially for digital phased arrays, multiple mmWave LO frequency distribution networks are required. Thus, these traditional solutions consume a large amount of power with a large area overhead.

[0110] Thus, to address these issues, aspects described herein combine fractional dividers, digital to time converters (DTCs), and frequency multipliers to generate several mmWave LO signals at different respective frequencies. As described further below, this may be performed using one or more dies, or "chips." Advantageously, these aspects only require a single low to mid frequency (RF) reference signal generator (i.e., a common frequency synthesizer) that is easier to distribute than higher mmWave signals. Furthermore, the spectral purity of the LO signal may be controlled by the reference signal generator, and thus the high frequency LO generation aspects described herein only introduce a small amount of additional noise during operation.

[0111] The aspects described herein also facilitate LO signal distribution at lower (e.g., RF) frequencies that consume much less power and require much less design effort compared to the distribution of higher, mm-wave LO signals. Furthermore, the aspects described herein are scalable to multiple transceiver chains, which is particularly useful for digital beamforming array operation, and may optionally be distributed off-chip using less expensive, lower frequency cabling or board traces. In this manner, by distributing the LO signal at a lower frequency, the aspects described herein omit the design of a full PLL to generate multiple frequency signals. Thus, the aspects described herein require less die area and consume less power compared to typical phased array designs that use PLLs for higher frequency LO signal generation and distribution.

[0112] As described in further detail below, aspects include distributing a low to mid frequency reference clock generated from a single frequency synthesizer and implementing frequency multiplication directly at each mixer. Aspects further described herein may include further variations. One of the main applications utilizing the aspects described herein includes the use of a large array of mixers in a digital beamformer. Another main application includes a two-die solution with intermediate (IF) LO ​​generation and mmWave LO generation separated by a distance in the overall system. Additionally, the aspects described herein may be particularly useful for carrier aggregation (CA) since CA requires the simultaneous generation of two or more LO frequencies that are not integer related (i.e., not proportional via integer scaling). Thus, to support these various configurations, aspects include the placement and / or addition of various blocks that may include fractional dividers, digital-to-time converters (DTCs), and edge combination frequency multipliers.

[0113] 11A-11C illustrate example transceiver architectures implementing a single-die digital beamformer using multiple operating frequency bands in accordance with certain aspects of the present disclosure. As shown in FIG. 11A, the transceiver architecture 1100 includes f synth The frequency synthesizer 1102 includes a frequency synthesizer configured to generate a reference signal 1108 having a frequency represented as . In certain aspects, the frequency synthesizer 1102 may be implemented using any suitable and / or known circuit components to generate the reference signal 1108, and such circuit components may include a PLL (e.g., a digital PLL) configured to generate a low level of phase noise. Additionally, aspects include a transceiver architecture 1100 having any suitable number of transceiver chains, each transceiver chain coupled to a respective set (e.g., one or more) of antenna elements associated with a phased array front end. Aspects include the frequency synthesizer 1102 being a common reference frequency generator utilized by each transceiver chain.

[0114] In various aspects described herein, a common frequency synthesizer (e.g., frequency synthesizer 1102, 1202, 1302, etc.) may be implemented in various transceiver architectures utilizing different types of conversion techniques. For example, transceiver architecture 1100 as shown in FIGS. 11A-11C uses direct conversion (i.e., homodyne). By using a direct conversion technique, exemplary transceiver architecture 1100 as shown in FIGS. 11A-11C may be advantageously implemented as part of a single die or chip. In other words, the transceiver circuitry and the phased array front-end circuitry may be integrated on a single die. However, transceiver architectures 1200, 1300 shown in FIGS. 12A-12B and 13A-13C and discussed further herein use superheterodyne conversion. For the transceiver architectures 1200, 1300, as described further herein, the transceiver circuitry and the phased array front-end circuitry can advantageously utilize the use of intermediate frequencies (IF) to carry the converted IF signals through cables or traces to a separate die associated with the phased array front-end.

[0115] In any event, the aspects described herein may be implemented using a lower frequency f synth For example, the reference frequency signal may have a frequency of f on the order of several GHz. synth While the transmitted upconverted signal may have a frequency several times this frequency, for example a frequency associated with the mmWave band. In doing so, aspects of the transceiver architecture described herein simplify the design of the PLL circuitry implemented via the frequency synthesizer, allowing for lower power consumption.

[0116] With continued reference to FIG. 11A , to utilize a lower frequency reference signal, the transceiver architecture 1100 may implement different component configurations based on the level of frequency control and / or amount of granularity desired with respect to frequency scaling of the reference signal 1108. In various aspects, these optional components, if implemented, may be implemented alone or in combination with one another. For example, aspects include the reference signal 1108 being provided to a digital-to-time converter (DTC) 1104A, either directly or via an optional frequency divider circuit 1106. The optional frequency divider circuit 1106 may include a frequency divider circuit having a f synth γ may be implemented if additional control or granularity is desired to provide a frequency-divided reference signal having a frequency that is a fraction of f. Thus, aspects include that optional frequency divider circuit 1106 is implemented via any suitable and / or known circuit components configured to perform frequency division of reference signal 1108. For ease of explanation, this frequency division factor is referred to herein as γ, and the frequency of the signal provided to DTC 1104A is reduced by γ when optional frequency divider circuit 1106 is implemented. synth / γ).

[0117] In various aspects, the DTC 1104A controls the frequency f of the reference signal 1108. synth The reference signal 1108 is configured to output a fractionally-multiplied reference signal 1110 having a frequency that is scaled in a non-integer manner relative to the reference signal 1108. As described further herein, the use of a fractional multiplication frequency relationship between the reference signal 1108 and the fractionally-multiplied reference signal 1110 may be particularly useful for transceiver applications in which separate carrier frequencies are used that may have a non-integer scale relationship relative to one another (e.g., for carrier aggregation applications used according to mmWave frequency bands).

[0118] Aspects include the DTC 1104A having any suitable configuration, which may be implemented using any suitable and / or known circuit components configured to translate a received digital phase ramp into a fractional frequency shift. For example, if the optional frequency divider circuit 1106 is not used, aspects include the DTC 1104A converting f synth Aspects include DTC 1104A performing a fractional frequency multiplication of reference signal 1108 by a scaling factor of 1.0, resulting in reference signal 1108 and fractionally multiplied reference signal 1110 having the same frequency. As another example, if optional frequency divider circuit 1106 is used, aspects include DTC 1104A performing a fractional frequency multiplication of reference signal 1108 by a scaling factor of 1.0, resulting in reference signal 1108 and fractionally multiplied reference signal 1110 having the same frequency. synth 11A , the optional frequency divider circuit 1106 may output signals in quadrature relationship to one another, and these outputs from the optional frequency divider circuit 1106 may be utilized to reduce the number of stages in a delay line implemented via the DTC 1104A.

[0119] The transceiver architecture 1100 may optionally include another DTC 1104B configured in a similar or identical manner to the DTC 1104A, but the DTCs 1104A, 1104B may be configured to provide frequency division independently according to respective division values. Thus, the fractionally multiplied reference signal provided in the low-band path shown in FIG. 11A and described further herein may be at the same frequency as the reference signal 1108, or at a lower frequency that is a portion thereof. Additionally or alternatively, the reference signal 1108 provided in the high-band path may be at a frequency f of the reference signal 1108. synthOr it may be a lower frequency that is a part of it, for example through the use of DTC 1104B.

[0120] Aspects include the transceiver architecture 1100 providing a reference signal 1108 and a fractionally multiplied reference signal 1110 via respective high-band and low-band paths at respective frequencies that may be dynamically adjusted and have a non-integer relationship to one another. For example, the DTCs 1104A, 1104B may provide respective fractional frequency multiplications according to received digital phase ramp values. Although optional DTC 1104B is not shown, each of the DTCs 1104A, 1104B may operate in a similar manner in this regard. Thus, the DTCs 1104A and / or DTC 1104B may receive (e.g., via one or more control lines) digital values ​​representing respective digital phase ramps that generate the desired fractional frequency multiplications. These digital phase ramp values ​​may be generated and transmitted via any suitable type of processor circuitry. Processor control of DTC 1104A and / or DTC 1104B may be implemented, for example, via execution of stored instructions by one or more hardware processors, as described further herein. Similarly, optional frequency divider circuit 1106 receives digital control signals via one or more processor components to divide the frequency f of reference signal 1108. synth The frequency division factor applied to can be varied.

[0121] Whether or not the optional frequency divider 1106 is implemented, aspects of the transceiver architecture described herein allow low to medium frequencies to be distributed onto each phased array element in the transceiver architecture. Furthermore, the fractional ratios introduced by the optional frequency divider 1106 and / or the DTCs 1104A, 1104B need not be integer ratios of each other, according to aspects described herein. This can be particularly useful, for example, with respect to fine channelization in cellular band applications (e.g., <1 MHz) and CA applications.

[0122] Reference is now made to Figures 11B-11C, which show a series of high-band (HB) and low-band (LB) paths, respectively. As shown in Figure 11A, transceiver architecture 1100 uses reference signal 1108 and fractionally multiplied reference signal 1110 to generate any suitable number of LO signals. In particular, transceiver architecture 1100 shown in Figure 11B receives reference signal 1108 as an input and generates any suitable number of HB LO signals via injection locked frequency multipliers (ILFMs) 1120.1-1120.A. Additionally, as shown in Figure 11C, transceiver architecture 1100 receives fractionally multiplied reference signal 1110 as an input and generates any suitable number of LB LO signals via ILFMs 1130.1-1130.B.

[0123] In various aspects, the IFLMs 1120, 1130 may be implemented using any suitable type of ILFM circuitry, which may include, for example, known ILFM configurations. In other aspects, the IFLMs 1120, 1130 may be implemented using the ILCM 306.3 discussed herein with reference to FIGS. 1-10. This may be implemented using a series or parallel injection architecture. For example, the frequency synthesizer 1102, as well as the frequency synthesizers 1202, 1302 described further below, may be identified with the PLL 302, as shown in FIG. 3. Continuing with this example, the transceiver architecture 1100 may be identified with a portion of the transceiver design 300 shown in FIG. 3. For example, the HB path as shown in FIG. 11B may be associated with any suitable number of transceiver chains (four are shown in FIG. 11B). Each transceiver chain may include a respective ILFM 1120.1-1120.A, and each IFLM 1120 may be identified with one of the LOG units 304 shown in FIG. 3. Additionally, a LB path as shown in FIG. 11C may be associated with any suitable number of transceiver chains (four are shown in FIG. 11C). Each transceiver chain may include a respective ILFM 1130.1-1130.B, and each IFLM 1130 may be identified with one of the LOG units 304 shown in FIG. 3.

[0124] As discussed further herein, the ILFMs (e.g., IFLMs 1120, 1130, 1205, 1220, 1305A-1305B, 1352, 1356, etc.) implemented in various aspects with respect to Figures 11A-11C and those shown and described in detail below with respect to Figures 12A-12B and Figures 13A-13C may be identified with the ILCM 306.3 described above with respect to Figures 11-10. Additionally, as discussed further herein, aspects include further modifying these ILFMs to incorporate an optional DTC (e.g., IFLM 1220 and DTC 1210 shown in Figure 12B). According to such aspects, the DTC may be designed on a common die or otherwise configured with the respective IFLMs as part of a single integrated design that may be identified as a portion of one of the LOG units 300 shown in Figure 3. In particular, aspects include implementing a DLL 306.1 (which may be implemented as one of the delay lines 400, 500, 600 as shown in FIGS. 4-6) to generate multiple phase-shifted signals for digital time control and for use in an edge-combining multiplier (such as one of the ILCM 306.3 architectures described above with respect to FIGS. 3, 8A and 8B).

[0125] 11B-11C illustrate each of the ILCMs 1120, 1130 generating a respective set of frequency multiplied signals that are coupled to a respective mixer. In certain aspects, the frequency multiplied signals generated by each of the ILCMs 1120, 1130 may correspond to one or more LO signals generated by the ILCM 306.3 discussed herein with reference to FIG. 3. In various aspects, as described above, the LO signals generated by the ILCMs 1120, 1130 may be a single LO signal or a set of orthogonal LO signals. When a set of orthogonal LO signals is generated, aspects may include each mixer shown in FIGS. 11B-11C: It actually consists of a set of mixers, each of which has its own

number

[0126] Aspects include that the ILFMs 1120, 1130 associated with the HB and LB paths shown in Figures 11B and 11C, respectively, are dynamically adjusted with respect to the frequency multiplication of the LO signal input to each mixer. The amount of frequency multiplication may be controlled and adjusted via appropriate processor circuitry as described herein. For example, for aspects implementing the ILFMs 1120, 1130 as the ILCM 306.3, the frequency multiplication of the input signal to each mixer may be controlled via the phase control block 308 to select particular sets of phase-shifted versions of the reference signal 1108 (for the HB path) and particular sets of phase-shifted versions of the fractionally multiplied reference signal 1110 (for the LB path). This type of frequency multiplication, discussed in the previous section with respect to Figures 1-10, may be referred to herein as edge combination frequency multiplication.

[0127] 11B, each transceiver chain in the HB path may downconvert a signal (the RX signal). The ILCM 1120 may directly downconvert the frequency f of the input signal 1108 to substantially match the frequency of the RX signal in the HB path to facilitate the downconversion. synth11C, each transceiver chain in the LB path may downconvert the RX signal, which may also have a frequency, for example, related to the mmWave band frequencies. Thus, the ILCM 1130 may provide an integer frequency multiplication f of the frequency of the fractionally multiplied reference signal 1110 to substantially match the frequency of the RX signal in the LB path. synth (α / β) (or in some cases (f synth In one aspect, the frequency division factor γ, as well as the variables α, β used to establish the fractional frequency multiplication factor, may be defined as any suitable integers. As a result, the resulting fractional frequency multiplication factor (e.g., (α / β) (or (α / β)(1 / γ))) may be a rational number.

[0128] In other words, a frequency multiplier is used in each ILFM 1120, 1130 implemented in each of the HB and LB paths to multiply the received reference signal frequency by an integer ratio to the desired higher frequency (e.g., mmWave frequency). As described above, since each transceiver chain in the transceiver architecture 100 can generate its own set of LO signals, aspects include integer multiplications performed by each of the ILFMs 1120, 1130 being programmable and / or dynamically adjusted to allow each transceiver chain to independently adapt to support different bands. Additionally, due to the use of programmable ratios as described with reference to FIG. 11A, aspects include setting the frequencies of the reference signal 1108 and the fractionally multiplied reference signal 1110 to any suitable value lower than the frequency synthesizer frequency. Aspects include these frequencies being set, for example, using a priori knowledge of the cellular or other communication channel used for connectivity and / or using feedback measured during operation. This may facilitate adaptive use of frequencies to avoid interference, freeing up preferred frequencies for use without complex frequency planning.

[0129] 12A-12B illustrate examples of transceiver architectures implementing a multi-die digital beamformer using a single operating frequency band according to certain aspects of the present disclosure. Again, the transceiver architecture 1200 illustrated in FIGS. 12A-12B uses superheterodyne conversion. Additionally, unlike the transceiver architecture 1100, the transceiver architecture 1200 illustrated in FIGS. 12A-12B uses a multi-die implementation in which the transceiver circuitry and the phased array front-end circuitry are implemented on separate dies. Additionally, the exemplary transceiver architectures 1200, 1300 described below illustrate an up-conversion and transmit path in the transceiver chain, as opposed to the down-conversion and receive path described above with respect to the transceiver architecture 1100. Of course, the aspects described herein may be equally applicable to either the down-conversion / receive path or the up-conversion / transmit path, and the processes described herein are reversible.

[0130] In some aspects, the portion of the transceiver architecture 1200 shown in FIG. 12A has a similar structure and uses similar components as the portion of the transceiver architecture 1100 shown in FIG. 11A. Thus, only the differences between these transceiver portions will be discussed further herein. For example, the transceiver architecture 1200 as shown in FIG. 12A, like the transceiver architecture 1100 as shown in FIG. 11A, uses a common frequency synthesizer 1202, an optional frequency divider circuit 1206, and one or more DTCs 1204A-1204B to generate fractional frequency multiplication of a reference signal generated via the frequency synthesizer 1202 and / or further frequency-divided versions of the reference signal if the optional frequency divider circuit 1206 is used.

[0131] Further, the portion of the transceiver architecture 1200 shown in FIGURE 12A may additionally include a DTC 1204B, which may be coupled to an input of the mixer circuit as shown, to provide additional flexibility as to the desired frequency of the upconverted IF signal 1208. Additionally or alternatively, the portion of the transceiver architecture 1200 as shown in FIGURE 12A may include an optional IFLM 1205, which may be coupled to an input of the mixer circuit as shown, to provide additional flexibility as to the desired frequency of the upconverted IF signal 1208.

[0132] The optional IFLM 1205 may be implemented using any suitable type of circuitry configured to provide integer frequency multiplication of the signal generated via the frequency synthesizer 1202. In some aspects, the optional IFLM 1205 may be implemented using known circuit components and / or known configurations to facilitate this functionality. In other aspects, the optional IFLM 1205 may be implemented as an IFCM 306.3 as described above for the ILFMs 1120, 1130 shown in FIGS. 11B-11C. In any case, if implemented, the ILFM 1205 may provide a frequency multiplication value that is dynamically adjusted via processor control. Additionally, as discussed herein with reference to FIG. 11C, the IFLM 1205 may generate any suitable number of LO signals. In certain aspects, the IF mixing stage (e.g., an up-conversion and down-conversion mixing stage between baseband (BB) and intermediate frequency (IF)) may utilize orthogonal LO signals, while additional up-conversion and down-conversion stages in the RF mixing stage (i.e., up-conversion and down-conversion between IF frequencies and other higher frequencies) do not require orthogonal LO signals (e.g., in a TX mixing stage providing up-conversion from IF to a transmit frequency, as shown in FIG. 12B, or a down-conversion RX mixing stage, not shown, from a transmit frequency to an IF frequency). In any case, where orthogonal LO signals are generated (e.g., by ILCM 1205), aspects may be considered to be construed as constituting an IF mixing stage as shown in FIG. 12A that actually constitutes a set of mixers, each mixer:

number

[0133] In various aspects, any combination of optional frequency divider circuit 1206, DTC 1204A-1204B, and / or IFLM 1205 may be implemented. In some aspects, two or more of these components may be present in a transceiver implementation, but may be selectively implemented to facilitate greater control over the frequency of analog IF signal 1208. For example, DTC 1204B and IFLM 1205 may both be implemented in series with one another in a particular design, while other implementations may include each being selectively activated or coupled to the mixer LO input. In the latter case, DTC 1204B may be used to fractionally multiply (i.e., divide) the frequency of a reference signal generated by frequency synthesizer 1202 that is used as the LO signal to the IF mixer, while IFLM 1205 may be activated if frequency multiplication is desired. Regardless of the components implemented, aspects include the transceiver architecture 1200 generating an upconverted analog IF reference signal 1208 and a fractionally multiplied reference signal 1210.

[0134] Again, to limit the number of frequency synthesizers to reduce power, area, crosstalk, and design complexity, the frequency synthesizer 1202 may be common to several transceiver chains, and a digital interface may be implemented to dynamically adjust the programmable ratios provided by the DTC 1204A, 1204B, frequency divider circuit 1206, IFLM 1205, etc. By doing so, the frequencies of the upconverted analog IF reference signal 1208 and the fractionally multiplied reference signal 1210 may be dynamically adjusted.

[0135] As shown in FIG. 12B, the transceiver architecture 1200 spans multiple dies and interfaces, with one portion (transceiver 1200A) associated with one die and another transceiver portion (phased array front-end 1200B) associated with a different die. Because the transceiver architecture 1200 implements a superheterodyne system, the die associated with the transceiver portion 1200A and the die associated with the phased array front-end portion 1200B each include an IF interface to facilitate distribution of the upconverted analog IF reference signal 1208 and the fractionally multiplied reference signal 1210 between each die. As shown in FIG. 12B, this IF interface may include, for example, one or more cables, traces, etc.

[0136] Because the upconverted analog IF reference signal 1208 and the fractionally multiplied reference signal 1210 are lower frequency signals compared to the transmitted signal, the IF interface may be implemented with lower cost components that have lower loss and are easier to design than higher frequency solutions. Additionally, to limit connections between dies, as shown in FIG. 12B, aspects include multiplexing the signals onto a single cable or trace using a multiplexing block 1214 and a demultiplexing block 1216. Although referred to herein as a multiplexer and a demultiplexer, the multiplexing block 1214 and the demultiplexing block 1216 may be implemented using any suitable type of known components configured to combine and separate signals, respectively.

[0137] For example, the multiplexing block 1214 and the demultiplexing block 1216 may be implemented using any number of electronically tunable components controlled via one or more processors via digital control signals 1212, 1218. In various aspects, the multiplexing block 1214 and the demultiplexing block 1216 may be implemented using any suitable type of components that facilitate one or more of a tunable low pass filter, a tunable band-stop filter, a tunable high pass filter, a tunable band-pass filter, etc. that may be combined on the IF interface 1201 and tuned and frequency shifted depending on the particular band of the IF signal extracted from the IF interface 1201. For example, since the reference signal generated via the frequency synthesizer 1202 is typically a continuous wave (CW) signal, the fractionally multiplied reference signal 1210 may also be a CW signal, and the demultiplexer 1216 may be tuned to remove the fractionally multiplied reference signal 1210 from the analog IF signal passed through the IF interface 1201 to the phased array front-end 1200B. This can be achieved, for example, by using deep and narrow tunable notch filter profiles.

[0138] 12B, aspects include a phased array front end 1200B splitting the signal passed through IF interface 1201 into an upconverted analog IF reference signal 1208 and a fractionally multiplied reference signal 1210. Again, the fractionally multiplied reference signal 1210 is at the frequency f of the reference signal generated by frequency synthesizer 1202. synth The phased array front end 1200B may further include an ILFM 1220, which may be substantially similar or identical to the IFLM 1205 and may be implemented as an ILCM 306.3 as discussed herein. Accordingly, additional details of the ILFM 1220 are not provided for the sake of brevity.

[0139] Aspects include an ILFM 1220 receiving a fractionally multiplied reference signal 1210 as shown in FIG 12B and frequency multiplying the fractionally multiplied reference signal 1210 using an integer frequency multiplier to generate a multiplied, higher frequency LO signal 1221. The phased array front end 1200B may optionally include a DTC 1211, which may operate in a similar or identical manner to the DTCs 1204A-1204B to provide fractional frequency shifts of the already fractionally multiplied reference signal 1210 to facilitate greater control and tunability of the high frequency transmit signal.

[0140] Additionally, although not shown in FIG. 12B for simplicity, aspects may include an ILFM 1220 generating any suitable number of high frequency LO signals 1221 from the fractionally multiplied reference signal 1210 (which may further be fractionally frequency shifted via optional DTC 1211), which may be distributed to any suitable number of mixers within the TX mixing stage, as shown, with each mixer receiving the upconverted analog IF reference signal 1208 as an input to generate a higher frequency signal for transmission. For example, because the ILFM 1220 is implemented within the final mixing stage of a superheterodyne architecture, the ILFM 1220 may provide a single phase LO signal versus a multi-phase LO signal (i.e., the BB-IF interface requires quadrature modulation, while the IF-RF interface requires only frequency conversion). Thus, these higher frequency transmit signals may be generated at any suitable frequency based on fractional multiplication performed within transceiver 1200A (and optionally DTC 1211 implemented within phased array front end 1200B) and integer multiplication performed via phased array front end 1200B (e.g., via ILFM 1220). For example, the high frequency transmit signal may have a frequency within the millimeter wave frequency band.

[0141] 13A-13C illustrate an example transceiver architecture implementing a multi-die digital beamformer using multiple operating frequency bands in accordance with an aspect of the present disclosure. Again, the transceiver architecture 1200 as shown in FIGs. 12A-12B uses superheterodyne upconversion. Similar to the transceiver architecture 1200, the transceiver architecture 1300 shown in FIGs. 13A-13C uses a multi-die implementation in which the transceiver circuitry and the phased array front-end circuitry are implemented on separate dies.

[0142] In some aspects, the transceiver architecture 1300 as shown in Figures 13A-13C has a similar structure and uses similar components as the transceiver architecture 1200 as shown in Figures 12A-12B. Thus, only the differences between these transceiver portions will be discussed further herein. For example, the transceiver architecture 1300 as shown in Figure 13A, like the transceiver architecture 1200 as shown in Figure 12A, uses a common frequency synthesizer 1302, optional frequency divider circuit 1306, and DTC 1304A to generate fractional frequency multiplication of the reference signal generated via the frequency synthesizer 1302 and / or further frequency divided versions of the reference signal if the optional frequency divider circuit 1306 is used. Additionally, the transceiver architecture 1300 shown in FIG. 13A, similar to the transceiver architecture 1200 shown in FIG. 12A, may implement one or more optional DTCs 1304B-C and IFLMs 1305A-B that can provide fractional or integer multiplication of a reference signal generated via the frequency synthesizer 1302.

[0143] In this manner, the transceiver architecture 1300 shown in FIG. 13A can independently feed two different sets of LO signals (or individual signals, as the case may be) to each IF mixer. Thus, the portion of the transceiver architecture 1300 shown in FIG. 13A may be configured to pass two separate IF analog signals, each at its own frequency, to the phased array front end, as shown in FIG. 13B. Again, as discussed with respect to FIGS. 12A-12B, if orthogonal LO signals are generated by the IFLMs 1305A, 1305B, the analog IF signals shown in FIG. 13A may include a set of orthogonal signal components. However, the transceiver architecture 1300 as shown in FIG. 13A may provide an additional IF signal (or set of IF signals) compared to the transceiver architecture 1200 as shown in FIG. 12A. This may be particularly useful for applications that simultaneously utilize two independent carrier frequencies for communication, such as CA applications. Regardless of the various optional components implemented, aspects include the transceiver architecture 1300 generating two upconverted analog IF signals 1308, 1309 and a fractionally multiplied reference signal 1310.

[0144] 13B, similar to the transceiver architecture 1200, the transceiver architecture 1300 also spans multiple dies and interfaces, with the transceiver portion 1300A associated with one die and the phased array front-end portion 1300B associated with a different die. The transceiver architecture 1300 also includes an IF interface 1301 to facilitate distribution of the upconverted analog IF signals 1308, 1309 and the fractionally multiplied reference signal 1310 between each die. Additionally, as shown in FIG. 13B, the transceiver architecture 1300 includes a multiplexing block 1314 and a demultiplexing block 1316 to facilitate the upconverted analog IF signals 1308, 1309 and the fractionally multiplied reference signal 1310 being combined on the IF interface 1301 and extracted from the IF interface 1301 to provide separate signals, as shown in FIG. 13B.

[0145] Referring now to FIG. 13C, aspects relate to a frequency f of a reference signal generated by a frequency synthesizer 1302. synth 13C includes a fractionally multiplied reference signal 1310 having a fractional frequency shift compared to the upconverted analog IF signal 1308, 1309. The phased array front end 1300B may further include two separate mixers (or sets of mixers; where each mixer shown represents an in-phase and quadrature path, as described above with respect to FIG. 12B) to upconvert the upconverted analog IF signals 1308, 1309 to HB and LB transmit signals, respectively. For example, each mixer shown in FIG. 13C may be associated with a separate upconversion frequency, with one mixer generating the HB transmit signal and the other being the LB transmit signal. In one aspect, these high and low band transmit signals may be millimeter wave frequencies implemented according to a CA communication scheme, although the aspects described herein are not limited to this particular application and may be implemented according to any suitable frequency band and / or communication protocol.

[0146] Additionally, the phased array front end 1300B may include ILFMs 1352, 1356, where the ILFM 1352 provides an HB LO signal to the HB mixer input. The HB LO signal 1353 may represent an integer frequency multiplication of the fractionally multiplied reference signal 1310 (or a further fractional multiplication thereof, if the optional DTC 1350 is also implemented). Similarly, the ILFM 1356 may provide an LB LO signal 1357 to the LB mixer input. The LB LO signal 1357 may represent an integer frequency multiplication of the fractionally multiplied reference signal 1310 (or a further fractional multiplication thereof, if the optional DTC 1350 is also implemented).

[0147] The optional DTCs 1350, 1354 may be substantially similar or identical to the optional DTC 1211 shown in FIG. 12B, as described herein, while the IFLMs 1352, 1356 may be substantially similar or identical to the IFLM 1220 shown in FIG. 12B. In other words, the IFLMs 1352, 1356 may also be implemented as an ILCM 306.3, as discussed herein. Additionally, as discussed herein for the transceiver architectures 1100, 1200, aspects include the ILFMs 1352, 1356 using a fractionally multiplied reference signal 1310 (which may be further fractionally frequency shifted via the optional DTCs 1350, 1354) to generate any suitable number of high frequency LO signals 1353, 1357. As mentioned above, the high frequency LO signal 1353, 1357 may be one of multiple LO signals distributed to any suitable number of respective mixers, with each of the HB and LB mixers receiving as an input the upconverted analog IF signals 1308 and 1309, respectively, to generate a higher frequency signal for transmission.

[0148] Aspects include that the frequency ratios provided by the DTCs 1304A-C, 1350, 1354, the frequency multiplications provided by the IFLMs 1305A, 1305B, 1354, 1356, and / or the frequency divisions provided by the frequency divider circuit 1306 are programmable and dynamically changeable during communication or another suitable period of time, such that several different frequency bands may be dynamically selected and adjusted. As a result of this flexibility, hardware associated with the transceiver architecture 1300 may be reused to provide different operating frequency bands and / or may be used simultaneously to provide different operating frequency bands (e.g., for CA applications). Thus, the high and low frequency bands may be independently set and adjusted, and the frequencies may be selected to avoid crosstalk or other sources of known or detected interference.

[0149] FIG. 14 illustrates a block diagram of an apparatus according to an aspect of the disclosure. In various aspects, the apparatus 1400 may be implemented as any suitable type of apparatus configured to transmit and / or receive wireless signals according to any suitable number and / or type of communication protocols. For example, the apparatus 1400 may be implemented as a user equipment (UE), such as a mobile phone, tablet, laptop computer, etc. Providing an additional example, the apparatus 1400 may be implemented as an access point or base station. The apparatus 1400 may implement one or more aspects described herein to facilitate receiving wireless signals according to a frequency or frequency band, such as, for example, a millimeter wave frequency, as described further below. In various aspects, the apparatus 1400 may include additional or alternative functionality to the apparatus 1000 described with respect to FIG. 10.

[0150] In certain aspects, the apparatus 1400 may include a processing circuit 1402, a memory 1404, and any suitable number N of transceiver chains 1412.1-1412.N, each coupled to one or more respective antennas 1414-1-1414.N. The components depicted in FIG. 14 are provided for ease of explanation, and aspects include apparatus 1400 including additional, fewer, or alternative components to those depicted in FIG. 14. For example, the apparatus 1400 may include one or more power sources, display interfaces, peripherals, ports, and the like. Providing additional examples, the apparatus 1400 may further include one or more transmitters and / or receivers, or alternatively, the transceiver chains 1412.1-1412.N may be implemented as transmitters configured to transmit wireless signals via the antennas 1414.1-1414.N.

[0151] In some aspects, various components of the device 1400 may be equated with functionality described further herein with respect to generation of LO signals using fractional frequency multiplication. For example, the wireless device 1400 may be configured to transmit wireless signals at millimeter wave or other suitable frequencies via one or more of the antennas 1414.1-1414.N, and to demodulate and process data contained in the signals received wirelessly via the transceiver chains 1412.1-1412.N. The transceiver chains 1412.1-1412.N may be equated with respective receiver chains (RX-1-RX-K) as shown in FIG. 3, for example, and each may include a respective LOG unit (304.1-304.K) as shown in FIG. 3.

[0152] In certain aspects, the processor circuitry 1402 may be configured as any suitable number and / or type of computer processor that may facilitate control of the device 1400 as described herein. In some aspects, the processor circuitry 1402 may be identified with a baseband processor (or a suitable portion thereof) implemented by the device 1400. In other aspects, the processor circuitry 1402 may be identified with one or more processors implemented by the device 1400 that are separate from the baseband processor. In any event, aspects include a processor circuitry 1402 configured to execute instructions to perform arithmetic operations, logical operations, and / or input / output (I / O) operations and / or to control operation of one or more components of the device 1400. For example, the processor circuitry 1402 may include one or more microprocessors, memory registers, buffers, clocks, etc. Additionally, aspects include a processor circuitry 1402 in communication with and / or controlling functions associated with the memory 1404 and / or the transceiver chains 1412.1-1412.N. This may include, for example, controlling and / or coordinating the transmission and / or reception functions of device 1400 and performing one or more baseband processing functions (e.g., medium access control (MAC), encoding / decoding, modulation / demodulation, data symbol mapping, error correction, etc.).

[0153] In one aspect, the memory 1404 stores data and / or instructions that, when executed by the processor circuitry 1402, cause the processor circuitry 1402 to perform various functions described herein. The memory 1404 can be implemented as any known volatile and / or non-volatile memory including, for example, read only memory (ROM), random access memory (RAM), flash memory, magnetic storage media, optical disks, erasable programmable read only memory (EPROM), programmable read only memory (PROM), etc. The memory 1404 can be non-removable, removable, or a combination of both.

[0154] For example, the memory 1404 may be implemented as a non-transitory computer-readable medium that stores one or more executable instructions, such as, for example, logic, algorithms, executable code, etc. As described further below, the instructions, logic, code, etc. stored in the memory 1404 are represented by various modules, such as those illustrated in FIG. 14, that enable the aspects disclosed herein to be functionally realized. The modules illustrated in FIG. 14 are provided to facilitate the description of the functional associations between the hardware and software components. Thus, the aspects include a processor circuitry 1402 that executes the instructions stored in these respective modules, along with one or more hardware components, to perform various functions associated with the various aspects, as described further herein.

[0155] In an aspect, executable instructions stored in the DTC control module 1406, in conjunction with the processor circuitry 1402, can facilitate generation of digital phase ramp data that is transmitted to various DTCs implemented via the transceiver architectures 1100, 1200, 1300 described herein. For example, executable instructions stored in the DTC control module 1406 can control one or more DTCs to generate a fractional phase shift as a function of the digital phase ramp data. In an aspect, the digital phase ramp data may be selected based on a correlation to a desired fractional frequency shift, which may be calculated, for example, via a suitable algorithm, function, look-up table (LUT), etc. stored in the memory 1404 or otherwise accessible by the processor circuitry 1402.

[0156] In an aspect, executable instructions stored in frequency multiplier / divider control module 1408, in conjunction with processor circuitry 1402, may facilitate the generation and transmission of control signals to set appropriate values ​​for frequency divider circuits (e.g., 1106, 1206, 1306, etc.) and / or ILFMs (e.g., IFLMs 1120, 1130, 1205, 1220, 1305A, 1305B, 1352, 1356, etc.) implemented via transceiver architectures 1100, 1200, 1300, etc. discussed herein. For example, executable instructions stored in frequency multiplier / divider control module 1408 may allow a generated reference frequency to be divided and / or fractionally multiplied before or after upconversion via the frequency divider circuits and frequency multipliers, depending on the particular implementation of the transceiver architecture. As another example, functionality associated with the frequency multiplier / divider control module 1408 may establish a desired integer multiplication via various ILFMs discussed herein. Again, these values ​​may be dynamically changed, providing flexibility with respect to the transmit frequency or frequencies used during operation of the device 1400. The frequencies may be selected based on, for example, the desired transmit frequency, prior knowledge of operation, measured feedback, etc., as discussed herein. In an aspect, the values ​​generated by the frequency multiplier / divider control module 1408 may be selected based on a correlation to a desired change in frequency of the input signal for each controlled component. This may be calculated, for example, via a suitable algorithm, function, LUT, etc. stored in memory 1404 or otherwise accessible by the processor circuitry 1402.

[0157] In an aspect, the executable instructions stored in the tuning control module 1410, together with the processor circuit 1402, can facilitate the generation and transmission of control signals for tuning the multiplexers (e.g., multiplexers 1214, 1314) and demultiplexers (e.g., demultiplexers 1216, 1316) to facilitate an IF interface between separate transceiver and phased array front-end dies, e.g., as discussed herein with respect to FIGs. 12B and 13B. In an aspect, the executable instructions stored in the tuning control module 1410 can include instructions for suitable algorithms, functions, LUTs, etc., and / or calculations to be performed to derive a set of tuning parameters that may result in a particular filter type and / or filter response that allows for combining signals at the transceiver die and extracting and separating those signals at the phased array front-end die. These tuning parameters can thus facilitate appropriate bandwidths, filter coefficients, etc., based on the current IF frequency bands being transmitted over the IF interface. Again, aspects include these tuning parameters being dynamically adjusted based on measured feedback, etc., depending on the currently used IF frequency, which may be changed depending on operating conditions to avoid blocker signals.

[0158] Section III - Array Element Level Control Using Per-Chain DC-DC Converters

[0159] Aspects described in this section relate generally to transceivers, and more particularly, to a multi-transceiver chain architecture that implements a dedicated DC-DC converter for each transceiver chain.

[0160] The RF front-end can implement phased array antennas for beam steering on both the user equipment (UE) side and the base station side. For the UE side, a typical configuration implements an analog phased array where signals from multiple (e.g., four or more) antennas are coherently combined with appropriate phase and amplitude weights to steer a beam in a particular direction. However, due to the requirement for coherent power combining, tuning at the element level (i.e., components within each transceiver chain) is limited. As a result, current transceiver architectures can suffer from performance limitations that cannot be easily addressed.

[0161] As discussed herein, current transceiver architectures can be subject to performance limitations that are not easily addressed. Some examples of these performance limitations include effects of enclosures, semiconductor process and aging variations, packaging process variations, air link conditions, mutual coupling between antennas, etc., which can cause mismatches between antennas and amplifiers that change when the beam is steered away from broadside. Typically, this causes output power variations, increased side lobes, and beam pointing errors. Another example of a performance limitation in current transceiver designs includes the creation of suboptimal bias settings for some amplifiers in certain transceiver chains relative to other transceiver chains when amplitude tapering is implemented to reduce side lobe levels, which can result in DC power waste and overheating.

[0162] Additionally, temperature differences across the die implemented in traditional transceiver architectures can cause performance differences between transceiver chains. Also, process variations, although limited within a single chip, can further degrade these effects. Additionally, traditional transceiver architectures can suffer from individual element failures or shutdowns due to temperatures exceeding thermal thresholds, which can result in issues with the overall array operation (pointing errors, lower Pout, side lobes, grating lobes, etc.).

[0163] To further complicate this issue, traditional transceiver architectures typically use one or two data streams (for multiple input multiple output (MIMO) operation) that are fed into separate analog phased arrays that are used to perform beam scanning by setting the appropriate phase and amplitude weights on the various transceiver chains. For these traditional transceiver architectures, a small number of DC-DC converters are used to provide different voltages for the various transceiver components. Traditionally, each of these DC-DC converters provides an output voltage that is used to power certain elements that are common to each of the transceiver chains. In other words, the DC-DC converters are shared between the different transceiver chain components within the overall transceiver architecture.

[0164] For example, a conventional transceiver architecture may use one DC-DC converter to provide a first supply voltage used for the digital circuitry, a second DC-DC converter to provide a second supply voltage for the majority of the analog / RF components (such as low noise amplifiers (LNAs), switches, active mixers, etc.), and a third DC-DC converter to provide a third supply voltage for the power amplifier (PA). Typically, the first, second, and third supply voltages output different supply voltages, such that the first DC-DC converter provides the lowest supply voltage, the third DC-DC converter provides the highest supply voltage, and the second DC-DC converter provides an intermediate supply voltage between the first and third supply voltages. Furthermore, for conventional transceiver architectures, each transceiver chain shares the same first, second, and third supply voltages provided by the first, second, and third DC-DC converters, respectively. For example, the same third supply voltage (i.e., the highest voltage) may be applied to all active power amplifiers in a transceiver array architecture, i.e., to all active power amplifiers associated with each transceiver chain in the array.

[0165] Generally, for phased array operation, transceivers utilize a preset codebook that is typically loaded into the chip memory. This codebook may define various transceiver parameters for each transceiver chain to operate in the context of a particular communication protocol, frequency band, and the number and type of antenna elements in the phased array. For example, the codebook may include transceiver parameters such as optimal amplifier bias, amplitude, and phase settings depending on frequency, beam pointing angle, data modulation and waveform, current die temperature, etc. These codebooks are typically based on a pre-calibration of the array at the factory and cannot compensate for changes that occur at the element level after calibration (e.g., random element failures, individual element shutdowns due to temperature overshoots, changes in antenna voltage standing wave ratio (VSWR) due to external conditions, etc.).

[0166] In other words, the main drawback of conventional transceiver architectures is the inability to individually tune and control each transceiver chain in a phased array system, which has several implications. First, as the antenna beam is scanned, the VSWR between each power amplifier and their corresponding antenna changes. This VSWR change affects the power amplifier output power, gain, and dissipated power. Thus, the transmitted power from each amplifier changes as the beam is scanned through space, and this change can be different for each amplifier in the array. This also affects the power amplifier nonlinearities (amplitude modulation (AM)-AM and AM-phase modulation (PM) errors), thus reducing the benefits of using digital pre-distortion (DPD).

[0167] Secondly, as the antenna beam is scanned, the mutual coupling between the antennas changes, which also affects the VSWR between the power amplifier and the antenna, further compounding the problems mentioned above.

[0168] Third, to reduce the sidelobe levels, the amplitude transmitted from each transceiver chain is typically "tapered", i.e., the amplitude transmitted by each chain relative to each other may be varied. This tapering is typically achieved by adding a variable attenuator at the output of each transceiver chain, which reduces the magnitude of the transmitted signal according to a predefined codebook. This is discussed further below with reference to FIG. 16A. However, this means that in most cases, when aperture tapering is applied, the amplifiers are not biased at their optimal settings. Instead, each amplifier is biased at the same voltage, and thus power is wasted by the use of attenuators.

[0169] Fourth, temperature differences across the die can cause performance differences between various transceiver chains. For example, transceiver chains at the center of a chip typically operate at higher junction temperatures compared to transceiver chains at the edge of the chip because they are not surrounded by other high-temperature components. This temperature variation affects the gain, output power, and efficiency of power amplifiers as well as the gain and noise figure of low-noise amplifiers (LNAs). Because traditional transceiver designs only allow the bias settings of all amplifiers to be controlled as a single entity, the bias can only be set as an average value based on the average temperature across the chip. In other words, there is no way to individually apply optimal bias conditions to amplifiers based on their individual junction temperatures.

[0170] Fifth, as the junction temperature increases further, failure or shutdown of individual elements may occur (due to temperature exceeding thermal thresholds), which may create problems with the operation of the entire array. In particular, the transceiver system coherently combines operational transceiver chain signals, which may include chains that are turned off (e.g., due to failure or shutdown) and chains that are operating in a non-optimal state due to high temperatures. As a result, this leads to performance degradation at the system level, manifested as pointing errors, lower Pout, side lobes, grating lobes, lower throughput, higher error vector magnitude (EVM), etc.

[0171] Thus, to address the problems present in conventional transceiver architecture solutions, aspects disclosed in this section are directed to transceiver implementations that utilize multiple DC-DC converters to control individual digital transceiver chains associated with a digital RF head. In particular, the aspects described herein eliminate the need for multiple DC-DC converters to provide different supply voltages shared among individual components across all transceiver chains. Instead, the aspects described herein allow each transceiver chain, sometimes referred to herein as a transceiver "slice" or transceiver "portion," to implement a single DC-DC converter that may be used for each component within that transceiver chain. This provides the ability to control the bias of each transceiver chain, providing multiple advantages in optimizing performance and reducing the effects of performance degradation when individual transceiver chains fail or are operating under non-optimal conditions.

[0172] As discussed further below, various aspects described in this section facilitate a digitally controlled RF head with the ability to individually tune and bias each transceiver chain depending on the particular application and / or current operating conditions. For example, as the beam is steered off broadside, the bias of each transceiver chain can be adapted to account for aperture tapering, VSWR changes, mutual coupling between elements, process and temperature variations, and the use of DPD. Thus, the amplifiers associated with each of the transceiver chains are biased at respective values ​​to achieve the best RF performance and provide substantial DC power savings.

[0173] FIG. 15 illustrates a block diagram of an example transceiver design in accordance with certain aspects of the disclosure. In general terms, the transceiver design illustrated in FIG. 15 illustrates a digital RF head including a common digital front end (DFE) 1502 and any suitable number of digital transceiver slices 1504.1-1504.N. The digital RF head is connected to a modem via a digital interface (e.g., a flex cable or other suitable connection) such that digital data is communicated between the modem and the digital RF head. The common DFE 1502 may be configured to manage digital processing, while the multiple digital transceiver slices 1504.1-1504.N may function to convert digital transmit signals to analog and upconvert these analog signals for transmission via corresponding coupled antennas (and during reception, downconvert receive analog signals via the coupled antennas and digitize the downconverted receive analog signals). Thus, signals transmitted and received via antennas in the phased array are passed through switching components 1514 between the common DFE 1502 and each coupled antenna 1-N (or group of antennas).

[0174] As discussed further herein, aspects include that the transceiver design 1500 is implemented as part of an overall transceiver architecture having some components omitted for brevity and ease of description. In certain aspects, the common DFE 1502 may be coupled to any suitable number, N, of the digital transceiver slices 1504.1-1504.N. The transceiver design 1500 shown in FIG. 15 illustrates the shared DFE 1502 as coupled to only one of the digital transceiver slices 1504 for simplicity. However, aspects include the shared DFE 1502 being coupled to each of the digital transceiver slices 1504.1-1504.N via any suitable number and / or types of wired or wireless links, which may include a wired bus configured to carry digital baseband data streams between the digital transceiver slices 1504.1-1504.N (e.g., “digital RX data” and “digital TX data”).

[0175] In any event, the DFE 1502 may include any suitable number and / or type of components configured to perform functions known to be associated with a digital front end. For example, the DFE 1502 may be implemented as a processing circuit, a portion of a processing circuit, one or more portions of an on-board chip (e.g., a digital signal processor) having dedicated digital front end functionality, etc. For example, the DFE 1502 may provide digital baseband data for transmission to each of the digital transceiver slices 1504.1-1504.N via respective coupled antennas, as discussed further below. Providing another example, the common DFE 1502 may facilitate receiving digital baseband data from each of the digital transceiver slices 1504.1-1504.N, which may be processed to recover data contained in an over-the-air data transmission.

[0176] To do so, the common DFE 1502 may be implemented with components suitable for performing reconfigurable computing (e.g., virtual reconfigurable circuit (VRC)) and processing circuitry configured to perform / subject to decimators and impairment corrections such as DC offset correction, IQ imbalance correction, and ADC skew. Providing further examples, the common DFE 1502 can further facilitate adjacent channel rejection (ACR) filtering, receiver digital gain control (DGC), downsampling, etc.

[0177] To provide yet another example, the common DFE 1502 may be implemented with a VRC and an interpolator coupled to each digital transceiver slice 1504.1-1504.N. Additionally, the common DFE 1502 may include other components related to data transmission, such as, for example, LO correction, IQ imbalance, digital pre-distortion (DPD) calculations, correction factor (CF) calculations, and transmitter impairment correction such as pre-emphasis (pre. emp.) calculations. To provide further examples, the DFE common 1502 may facilitate transmitter DGC, upsampling, zero-crossing detection algorithms, phase modulation, and the like. Additionally, aspects include the common DFE 1502 being implemented with components suitable for performing beam management, digital blocker cancellation, received signal strength indicator (RSSI) measurements, DPD and calibration accelerators, test signal generation, and the like.

[0178] In any event, aspects include the common DFE 1502 selectively performing certain functions based on an operational mode of the transceiver design 1500. In particular, as discussed further below, the common DFE 1502 and / or the slice DFEs 1510, 1522 implemented within each digital transceiver slice 1504.1-1504.N can dynamically recalculate and / or update DPD coefficients based on measured feedback during operation of the wireless device in which the transceiver design 1500 is implemented. Additionally or alternatively, aspects included the common DFE 1502 and / or the slice DFEs 1510, 1522 dynamically adjusting various transceiver parameters associated with one or more of each digital transceiver slices 1504.1-1504.N. In various aspects, as discussed further below, the DPD coefficients and / or transceiver parameters may be adjusted for each transceiver chain by utilizing the use of DC-DC converters 1520.1-1520.N per transceiver chain, as shown in FIG. 15.

[0179] In an aspect, the transceiver design 1500 may include a digital phase-locked loop circuit (DPLL) 1550, which may be implemented using any suitable known circuit components to generate a reference signal 1551, which may include a low phase noise DPLL. Additionally, aspects include the reference signal 1551 being distributed to a frequency multiplier / shifter circuit 1506 and a phase generator circuit 1508. Thus, aspects include the phase generator circuit 1508 being identified with, for example, the phase configuration circuit 306.2 shown in FIG. 3. Additionally, the frequency multiplier / shifter 1506 may be implemented as any suitable type of frequency multiplier that may provide any suitable number of LO signals to the mixer 1518, such as an edge-coupled frequency multiplier (e.g., ILCM 306.3) discussed in previous sections. Further aspects include that the frequency multiplying radio frequency digital-to-analog converter (FM-RFDAC) 1512 is implemented as any suitable known FM-RFDAC design.

[0180] Again, the transceiver design 1500 includes any suitable number, N, of transceiver slices 1504. In one aspect, each of the transceiver slices 1504 has separate transmit and receive paths. For simplicity and ease of explanation, each transceiver slice 1504 is shown throughout the figures in this section as being coupled to a single respective antenna. However, in various aspects, each transceiver slice 1504 may be coupled to any suitable number of antennas, low noise amplifiers, and the like in any suitable configuration to facilitate transmission and reception of data according to a phased array architecture.

[0181] With continued reference to FIG. 15, transceiver slice 1504.N may implement a transmit path including a TX slice DFE 1510 coupled to an FM-RFDAC 1512. The FM-RFDAC 1512 is coupled to a power amplifier (PA) 1517 and an antenna N via a switching component 1514. The switching component may represent any suitable type of component to facilitate TX and RX mode switching. In an aspect, the transmit path of each transceiver slice 1504 may include a TX slice DFE 1510, which functions to provide additional DFE functions per transmit chain (i.e., a separate TX DFE 1510 may be implemented for each transceiver slice 1504). The additional DFE functions may include, for example, interpolation, digital pre-distortion, I / Q compensation, and gain control.

[0182] Further, aspects include each transceiver slice 1504 also including a receive path coupled to a switching component 1514. For example, the receive path may include one or more amplifiers 1516 (e.g., LNAs), a frequency multiplier / shifter circuit 1506, one or more mixers 1508, an I / Q ADC and baseband filter circuit 1520, and an RX slice DFE 1522. Again, aspects include each transceiver slice 1504 implementing a separate receive path, each having components similar to those represented by transceiver slice 1504.N, as shown in FIG. 15. Thus, aspects further include each of the components associated with the receive path being independently controlled for each receive chain (i.e., each transceiver slice 1504 may have receive paths having components that are controlled separately from each other).

[0183] In one aspect, each transceiver slice 1504 may include its own DC-DC converter 1520.1-1520.N, which may be implemented as any suitable type of circuitry configured to output a stable DC supply voltage using a reference input voltage. This reference input voltage may include any suitable DC voltage generated within transceiver design 1500 using known techniques, and such connections and reference input voltages are not shown in the figures for simplicity. In various aspects, each of DC-DC converters 1520.1-1520.N may provide supply voltages independent of one another, such that DC-DC converters 1520.1-1520.N may provide the same or different supply voltages to each transceiver slice 1504.

[0184] Aspects include the supply voltage output from each DC-DC converter 1520.1-1520.N being fixed or adjustable (e.g., adjusted via a control signal from suitable processor circuitry, as discussed further below). In certain aspects, the DC-DC converters 1520 may be formed on the same chip or die as other components implemented within each transceiver slice 1504. For example, the DC-DC converters 1520.N may be integrated as part of the same die (i.e., formed as part of the same silicon) used for the mixers 1518, amplifiers 1516, etc. As another example, one or more of the transceiver slices 1504.1-1504.N may be integrated as part of the same chip as a common or shared DFE 1502 (and / or modem, as referenced in FIG. 15 but not otherwise shown), although other aspects include the DFE 1502 and one or more of the transceiver slices 1504.1-1504.N (and / or modem, as referenced in FIG. 15) being integrated as separate chips. Thus, any functionality provided by the transceiver slices 1504.1-1504.N, the shared DFE 1502, and / or the modem, as referenced in FIG. 15, may be performed by one or more of these components on the same chip on which these components are integrated or on different chips. Although not shown in FIG. 15 for simplicity, each transceiver slice 1504 may include additional components that may also share a power supply provided by each respective DC-DC converter 1520. Further aspects include one or more of the transceiver slices 1504.1-1504.N including two or more DC-DC converters 1520, with particular components within each transceiver slice utilizing supply voltages provided by different DC-DC converters implemented within that particular transceiver slice.

[0185] In one aspect, each transceiver slice 1504 further includes any suitable number N of feedback components FC1-FC NEach transceiver slice 1504 may include its own collection of feedback components FC, represented as . The various interconnections of the feedback components are not shown in FIG. 15 for simplicity. However, as discussed further below, these feedback components may include any suitable number and / or type of known sensors, measuring devices, sampling devices, couplers, etc. that may monitor various conditions of each transceiver slice 1504 during operation. For example, these feedback components may include temperature monitors at one or more die locations to facilitate measurement of junction temperatures of various components associated with each transceiver slice 1504, power meters to measure forward and / or reverse power in the transmit and / or receive paths, element fault detectors, etc.

[0186] 16A-16B show general block diagrams of digital transceiver slices. In particular, FIG. 16A shows a block diagram of a conventional transceiver architecture that uses a common DC-DC converter between each of the transceiver chains. However, FIG. 16B shows a block diagram of a transceiver portion that uses multiple DC-DC converters, one per transceiver slice, as shown in FIG. 15. Thus, the block diagram shown in FIG. 16 may represent an alternative representation of transceiver slices 1504.1-1504.N, as shown in FIG. 15.

[0187] As mentioned above, one benefit of the aspects of the DC-DC converters per transceiver slice described herein relates to aperture tapering. In a typical phased array, the amplitude transmitted through each transceiver chain is tapered to reduce the power leaking into the side lobes. This can be observed in the radiation patterns shown in Figures 17A-17B. Figures 17A-17B show simulated far-field radiation patterns of a 4x4 array (Figure 17A) without (Figure 17A) and with (Figure 17B) aperture tapering. Simulations show that the application of amplitude tapering reduces the side lobe levels by approximately 15 dB.

[0188] As shown in FIG. 16A, conventional transceiver design approaches use common DC-DC converters for components across all transceiver slices, which are implemented to bias all transceiver slice components. However, FIG. 16B illustrates a block diagram of a transceiver architecture using multiple DC-DC converters, one for each transceiver chain, in accordance with an aspect of the present disclosure. Aspects include that per-transceiver chain DC-DC converters as shown in FIG. 16B facilitate various options for tuning and optimizing bias settings for each transceiver slice, allowing the digital RF head to obtain optimal RF performance using lower dissipated DC power.

[0189] For example, as shown in FIG. 16A, a single shared DC supply voltage (VRF) is used. This supply voltage may be utilized, for example, to bias the receive and transmit amplifiers in each transceiver chain. The receive and transmit amplifiers in all transceiver chains are then biased with the same voltage VRF. Any change to the VRF supply voltage will thus affect the amplifiers in all transceiver chains. As mentioned above, to reduce the level of side lobes, the amplitude transmitted from each transceiver chain is typically "tapered," i.e., the amplitude transmitted by each chain relative to each other may be changed. However, since the same supply voltage VRF is distributed to all transceiver chains, a conventional solution utilizes variable attenuators ("Variable Att.") in the transmit and receive paths of each transceiver chain while the amplifiers are fully biased. This allows the magnitude of the transmit and / or receive signals to be reduced to a desired value according to a predefined codebook. In other words, the traditional approach of using the same supply voltage to fully bias each amplifier wastes power because all amplifiers in a transceiver must be biased at the same level and operated at full power while transmitting attenuated power. This inefficient solution requires that the same amount of DC power be utilized even though lower RF power may actually be required to be received or transmitted from some transceiver slices (e.g., based on codebook values).

[0190] In contrast, the transceiver architecture shown in FIG. 16B may be identified with the transceiver architecture 1500 shown in FIG. 15, with further details shown with respect to DC-DC converters. Thus, DC-DC converters 1, 2, and N, respectively associated with “VRF_Slice 1”, “VRF_Slice 2”, “VRF_Slice N”, etc., may be identified with DC-DC converters 1520.1 through 1520.N. Thus, these supply voltages may be used to bias the amplifiers in each transceiver slice using different voltage values, as shown in FIG. 16B. In so doing, aspects eliminate variable attenuators that would otherwise be implemented as part of a conventional transceiver architecture, saving power and allowing for a more efficient transceiver design. In particular, instead of attenuating the signal in each transceiver chain, aspects include facilitating amplitude tapering directly through the amplifiers by adjusting the respective bias conditions to obtain the appropriate output power. In this way, each amplifier can be individually biased at its optimum depending on the output power it actually needs to transmit or receive based on the desired tapering. This improves the overall DC-RF efficiency of the transceiver since DC power is not wasted through the attenuator.

[0191] In other words, referring to FIG. 15, the aspects described in this section may improve the efficiency of the PA 1517 included in one or more of the digital transceiver slices 1504.1-1504.N. In particular, the particular supply voltage provided by the DC-DC converters 1520.1-1520.N may control the individual power supply rails used through each PA 1517 to produce an optimal load line for the transceiver design 1500. Because the slice DC-DC converters 1520.1-1520.N may be independently controlled in each of the digital transceiver slices 1504.1-1504.N, the aspects described in this section may enable the transceiver design 1500 to maintain an optimal load line over the entire range of transmitter output power levels. That is, it is undesirable (i.e., not optimal) for the PA 1517 to use a high power supply to transmit at a low power level, as power is wasted during this process, resulting in low PA efficiency. The embodiments described herein facilitate individualized adjustment of the power supply rails for each PA 1517, thereby enabling the transceiver design 1500 to operate at optimal efficiency for all output power levels.

[0192] Another advantage of aspects of the per-transceiver slice DC-DC converters described herein, further related to aperture tapering, is described below with reference to FIGS. 18A-18B. In particular, when the transceiver slices 1504 are implemented for the transmission of signals according to some communication protocol (e.g., OFDM signals), the transmitter output power varies significantly over time as a function of the modulation and waveform being transmitted. Thus, if the same DC-DC power supply is used across each of the transceiver slices, as in the conventional approach, this results in a constant voltage being applied during signal transmission, as shown in FIG. 18A. This is typically done to compensate for the highest level of output power, but results in wasted DC power when the amplifier is transmitting at a lower output power level.

[0193] However, in accordance with aspects described herein, an individual DC-DC converter 1520 integrated within each transceiver slice can independently power each amplifier within the respective transceiver slice. As a result, aspects include modulating the amplifier bias voltages such that the DC bias levels track the envelope of the transmit signal, as shown in FIG. 18B, thereby providing improved DC-to-RF efficiency.

[0194] Yet another advantage of the aspects of the DC-DC converters per transceiver slice described herein is that the individual bias control for each transceiver slice can serve to mitigate some of the effects of antenna-to-amplifier VSWR mismatch and mutual coupling between antennas. Both of these effects can vary from transceiver chain to transceiver chain and as the radiation beam is steered away from broadside. For example, a transceiver design having N transceiver slices (as shown in Figures 15 and 16B) is coupled to N antennas. Additionally, each antenna has a slightly different impedance due to its physical location within the phased array, mutual coupling with adjacent antennas, and the overall environment (e.g., where the antenna is located, direction of radiation, type of enclosure, enclosure material, distance between the antenna element and its enclosure, presence of large reflectors in the near field of the UE, etc.).

[0195] For each transceiver slice, these different impedances generate different VSWRs at each interface between the amplifier and the coupled antenna, which affects amplifier performance (e.g., output power, gain, and efficiency). Changes to the VSWR can also affect amplifier nonlinearities (i.e., introduction of AM-AM and AM-PM errors). Additionally, as previously mentioned, the VSWR observed through each transceiver slice changes when the antenna steers its beam off-broadside. Thus, being able to track changes in VSWR and then adjust amplifier bias conditions to account for these changes is advantageous in maintaining high performance while the beam is steered and the system radiates in non-optimal environments.

[0196] Additionally, semiconductor process variations may result in different power amplifiers with different AM-AM and AM-PM characteristics. To account for such differences, different back-off values ​​may be required for each power amplifier (PA) (e.g., PA 1517 as shown in FIG. 15). However, without a mechanism to increase the linearity of the weaker PA, the PAs for the entire transceiver system would be required to operate at a transmit power back-off to support the weakest PA, thereby reducing overall efficiency and transmitting less power. Thus, another advantage of the per-transceiver slice DC-DC converter aspects described herein is that the supply bias for the lower performance PAs in the individual transceiver chains may be increased in the overall transceiver array to maintain output power and efficiency for the entire system. This process is discussed further below with respect to the process flow shown in FIG. 19.

[0197] FIG. 19 illustrates a process flow for voltage standing wave ratio (VSWR) correction and cooperation with a digital predistortion (DPD) front-end module according to an aspect of the present disclosure. In an aspect, the process flow 1900 may be implemented via one or more portions of the transceiver design 1500 illustrated and described herein with reference to FIG. 15. Although the process flow 1900 is described herein with respect to transmitting signals, this is by way of example and not limitation. The aspects described herein may include modification of various DPD coefficients and / or transceiver parameters associated with each transceiver slice implemented as part of a transceiver architecture as discussed herein that may be utilized as part of a receiver chain and / or transmit chain components.

[0198] 15, each transceiver slice 1504.1-1504.N may implement a slice DFE 1522, 1510 in each of the receive and transmit paths, respectively. In an aspect, the process flow 1900 may be performed via any suitable combination of processing circuitry and / or other suitable components implemented by the common DFE 1502 and / or the shared DFEs 1510, 1522 associated with each transceiver slice 1504. For example, the slice DFEs 1510, 1522 may further modify, update, override, and / or adjust DPD coefficients and / or transceiver parameters initially established by the common DFE 1502.

[0199] As shown in FIG. 19, the process flow 1900 may begin with the generation of a digital transmit signal (block 1902). This may include, for example, a computation of digital data as shown in FIG. 15, which may be performed by a modem or other suitable signal processing component coupled to a common DFE 1502. Thus, the digital transmit signal may represent a digital data bit stream that is first processed by the common DFE 1502, which applies an initial DPD correction or a common DPD correction to the digital transmit signal, and then redistributes the digital transmit signal with DPD correction (e.g., "digital TX data") to each transceiver slice 1504.1-1504.N via slice DFEs 1510, 1522 as shown in FIG. 15. The application of the initial DPD correction via the common DFE 1502 may be performed, for example, using pre-calibrated information.

[0200] Again, each of the transceiver architectures 1500 includes a dedicated DFE slice 1510, 1522 for each transmit and receive path, as well as a dedicated DC-DC converter 1520.1-1520.N implemented within each transceiver slice 1504. Thus, aspects relate to each transceiver slice further modifying settings of transceiver components and / or providing additional DPD correction to the transmit (or receive) signal (which, in the case of a transmit signal, may already have some DPD correction via the shared DFE 1502). Thus, the process flow 1900 includes an initial application of DPD parameters for an initial transmission of data via the phased array using each of the transceiver slices 1504.1-1504.N (block 1904). This may include, for example, initializing each of the transceiver slices 1504 for data transmission according to a preset codebook setting.

[0201] Further aspects include the process flow 1900 further applying initial transceiver parameters via each transceiver slice 1504 (block 1906). These additional transceiver parameters may be separate from the DPD applied by the DFE slices 1510, 1522 associated with each transceiver slice 1504 (and / or the common DFE 1502). For example, the initial transceiver parameters may include various transceiver component settings for each transceiver slice 1504 to use when transmitting the respective DPD corrected digital transmit signal. The initial transceiver parameters may be specified by a stored preset codebook and may include any suitable component settings that may be adjusted in each transceiver slice 1504 to improve system performance. Examples of these transceiver parameters include initial amplifier bias conditions, phase shifter settings, the type of signal that needs to be transmitted (e.g., modulation type, waveform, signal bandwidth, etc.), in which frequency band, and in which direction (e.g., amplitude tapering parameters), and the gain required by each of the transceiver slices 1502 based on that type of signal.

[0202] Again, as shown in FIG. 15, each of the transceiver chains 1504.1-1504.N may include any suitable number of feedback components FC1-FC NIn various aspects, these feedback components may include power monitoring circuitry, such as couplers, power detectors, and the like. Such power monitoring circuitry may be implemented in the transmit and / or receive paths of each transceiver slice 1504 and may include any suitable type of known circuitry for facilitating measurements of forward and reverse power for the respective paths. These power monitoring circuitry may enable the slice DFE 1510, 1522 in each transceiver slice 1504 (or other suitable components of the transceiver architecture 1500, such as, for example, the shared DFE 1502) to monitor the forward and reverse power in the transmit path for each transceiver slice 1504 during signal transmission. These measurements may facilitate calculation and tracking of the VSWR between each transmitting transceiver slice 1504 and its coupled antenna in the phased array during transmission (block 1908). In other words, the VSWR between the amplifier and antenna output in each transceiver slice 1504 may be calculated in known fashion using values ​​derived from forward and reverse power measurements.

[0203] In one aspect, if the monitored VSWR changes unexpectedly or exceeds a predetermined threshold, the biasing of that particular transceiver chain amplifier may be adjusted to compensate. In one aspect, this may be accomplished via the slice DFE 1510, 1522 in each transceiver slice 1504 (or other suitable components of the transceiver architecture 1500, such as the shared DFE 1502) adjusting (block 1910) the settings of a DC-DC converter that powers the amplifiers on that particular transceiver slice. The DC-DC converter may then bias the amplifiers at the adjusted DC voltage value.

[0204] Aspects also include the slice DFE 1510, 1522 (or shared DFE 1502, etc.) in each transceiver slice 1504 updating (block 1912) the initial DPD parameters using the VSWR calculation (block 1908) simultaneously with, before, or after the DC-DC converter settings adjustment. Doing so may alter the pre-distortion of a subsequently transmitted signal to compensate for amplifier nonlinearities. Thus, aspects include VSWR retuning compensation being performed in one or more of the transceiver slices 1504. This retuning process may include adjusting the power supply provided by the DC-DC converter 1520 on one or more transceiver chains 1504 and applying the updated DPD via each slice DFE 1510, 1522 on one or more transceiver chains 1504 to retune the power amplifier with the adjusted bias setting while adjusting the amplifier performance for the new VSWR. This overall retuning process advantageously facilitates transmission of improved quality signals while utilizing a smaller amount of DC power. As shown in FIG. 19, process flow 1900 includes dynamically retuning the transceiver chain 1504 by repeating this process over time as changes in VSWR values ​​are detected. Of course, aspects are not limited to performing both transceiver parameter updates and DPD parameter updates in response to tracked VSWR changes, and aspects include either performing the transceiver parameter updates or the DPD parameter updates independently of one another, or performing one but not the other.

[0205] The tuning procedure shown in FIG. 19 is with respect to detected VSWR changes and is one example of a dynamic tuning process that may be possible using the dedicated DC-DC converter transceiver slice architecture described in this section. However, other aspects include dynamically tuning the transceiver slice components to compensate for other conditions that may not be considered during factory calibration. For example, the amplifier bias provided by each dedicated DC-DC converter 1520 may provide temperature compensation for each transceiver slice 1504, taking into account the aperture tapering and the location of each antenna element within the phased array die. For example, amplifiers located in the center are typically hotter than amplifiers located at the edge of the die. This temperature difference may result in performance differences between antenna elements in terms of Pout, gain, noise figure, noise factor, error vector magnitude (EVM), etc.

[0206] As an illustrative example, the transceiver architecture 1500 as shown in FIG. 15 may be implemented on a chip or die. N may include multiple temperature sensors to track temperature at various locations during normal operation. Aspects described herein may additionally or alternatively enable each dedicated DC-DC converter to adjust the amplifier bias of each transceiver slice (e.g., via a slice DFE 1510, 1522 in each transceiver slice 1504, a shared DFE 1502, etc.) using temperature measurements from an associated sensor located proximate to that particular transceiver chain 1504, thereby compensating for temperature variations between different transceiver slices.

[0207] Aspects described herein may also utilize dedicated DC-DC power converters to compensate for degradation in transceiver array performance when individual components fail or are shut down for exceeding a maximum operating temperature threshold. Such shutdown may occur as a safety measure during operation of the transceiver. For example, feedback components FC1-FC N may include multiple voltage / current sensors at various die locations. Aspects include using tracking data obtained via multiple temperature, voltage, and / or current sensors to adjust bias settings provided by dedicated DC-DC converters 1520.1-1520.N.

[0208] For example, if a particular transceiver slice 1504 component (e.g., a power amplifier) ​​exceeds a temperature threshold, the DC-DC converter 1520 can temporarily shut off that component, while other transceiver slice power amplifiers can continue to function according to the bias provided by their respective dedicated transceiver slice DC-DC converters. Additionally, if a transceiver slice 1504 begins to fail (e.g., draws current above a predetermined threshold) or one or more measured voltage values ​​are outside of a predetermined operating range of voltage values, that component may be turned off by having its respective DC-DC converter 1520 turn off its DC supply power.

[0209] In so doing, aspects include reducing the impact of a failed transceiver slice (or a transceiver slice that is temporarily shut down) by adjusting the DC-DC converters for the other transceiver slices, thereby adjusting the individual performance of the adjacent transceiver slices. Without the fine granularity of control facilitated by the aspects of the dedicated DC-DC converters described herein, such correction would not be possible. Again, losing individual elements in the array can cause pointing angle errors and increased side lobes. An example of the impact of a lost or failed element on the radiation pattern is shown in FIGS. 20A-20B. In particular, FIG. 20A shows a fully operational 4×4 antenna array, and FIG. 20B shows the same 4×4 antenna array with three elements failed or turned off. As shown in FIG. 20B, the failure of these three elements results in a loss of 1.5 dB of gain, as well as significant distortion of the radiation pattern.

[0210] FIG. 21 illustrates a block diagram of an example device according to an aspect of the disclosure. In various aspects, the device 2100 may be implemented as any suitable type of device configured to transmit and / or receive wireless signals according to any suitable number and / or type of communication protocols. For example, the device 2100 may be implemented as a user equipment (UE), such as a mobile phone, tablet, laptop computer, etc. Providing an additional example, the device 2100 may be implemented as an access point or base station. The device 2100 may implement one or more aspects as described herein to facilitate transmission of wireless signals according to a particular frequency or frequency band, such as millimeter wave frequencies, for example, as further described herein.

[0211] As further referenced in this section and other sections, the term "mm-wave frequencies" in which aspects described in this section and other sections may operate may include frequencies and frequency bands, e.g., above 20 GHz, 24 GHz, 28 GHz, etc., up to some upper frequency limit. For example, mm-wave frequency bands may include frequencies in the range of 20 GHz to 300 GHz, 24 GHz to 300 GHz, etc. This may include various bands known to be associated with, or otherwise referred to as, mm-wave frequency bands, e.g., 24 GHz, 28 GHz, 37 GHz, 39 GHz, 40 GHz, 47 GHz, 60 GHz, etc.

[0212] In one aspect, the device 2100 may include a processing circuit 2102, a memory 2104, and any suitable number N of transceiver slices or chains 2112.1-2112.N, each coupled to one or more respective antennas 2114.1-2114.N. The components depicted in FIG. 21 are provided for ease of explanation, and aspects include the device 2100 including additional, fewer, or alternative components to those depicted in FIG. 21. For example, the device 2100 may include one or more power sources, display interfaces, peripherals, ports, etc.

[0213] In certain aspects, various components of apparatus 2100 may be identified with functionality further described herein with reference to dynamic application of DPD and / or transceiver parameters. Each of transceiver slices 2112.1-2112.N may be identified with, for example, a respective one of transceiver slices 1504.1-1504.N discussed with reference to transceiver design 1500 as shown in FIG. 15. Thus, aspects include each of transceiver slices 2112.1-2112.N implementing its own dedicated DC-DC converter to provide supply voltages to each of the transceiver components integrated as part of each respective transceiver slice 2112.

[0214] Aspects include that the processing circuitry 2102 is configured as any suitable number and / or type of computer processor that can facilitate control of the apparatus 2100 as discussed herein. In some aspects, the processing circuitry 2102 may be identified with a baseband processor (or a suitable portion thereof) implemented by the apparatus 2100. In other aspects, the processing circuitry 2102 may be identified with one or more processors implemented by the apparatus 2100 that are separate from the baseband processor (e.g., one or more digital signal processors, one or more processors associated with the shared DFE 1502 and / or the transceiver slice DFEs 1510, 1522, etc.). In still other aspects, the functionality of the apparatus 2100 may be combined with the functionality discussed herein with reference to the apparatus 1400, which may have functionality combined with the functionality discussed herein with reference to the apparatus 1000 as discussed above. Additionally or alternatively, aspects may include that various functions discussed herein with reference to apparatus 2100 are performed by one or more components associated with apparatus 1400 and / or apparatus 1000.

[0215] In any event, aspects include the processing circuit 2102 being configured to execute instructions to perform arithmetic operations, logical operations, and / or input / output (I / O) operations and / or control operation of one or more components of the device 2100. For example, the processing circuit 2102 may include one or more microprocessors, memory registers, buffers, clocks, etc. Additionally, aspects include the processing circuit 2102 communicating with and / or controlling functions associated with the memory 2104 and / or the transceiver slices 2112.1-2112.N.

[0216] This may include, for example, controlling and / or arbitrating the transmit and / or receive functions of the apparatus 2100, facilitating measurement of data provided by various feedback components discussed herein, and adjusting the supply bias and / or DPD parameters provided by the DC-DC converter using measurement data obtained via the feedback components as discussed herein. Additionally, the processing circuitry 2102 may facilitate calculation of initial transceiver parameters, adjusted transceiver parameters, and / or initial and / or adjusted DPD parameters for one or more of the one or more transceiver slices 2112, control the state of the apparatus 2100 to operate in a receive mode or a transmit mode, perform one or more baseband processing functions (e.g., medium access control (MAC), encoding / decoding, modulation / demodulation, data symbol mapping, error correction, etc.), identify groups of transceiver slices for DPD management, as well as any other suitable functionality for performing functions related to the aspects described herein.

[0217] In one aspect, the memory 2104 stores data and / or instructions that, when executed by the processing circuitry 2102, cause the processing circuitry 2102 to perform various functions described herein. The memory 2104 can be implemented as any well-known volatile and / or non-volatile memory including, for example, read only memory (ROM), random access memory (RAM), flash memory, magnetic storage media, optical disks, erasable programmable read only memory (EPROM), programmable read only memory (PROM), etc. The memory 2104 can be non-removable, removable, or a combination of both.

[0218] For example, the memory 2104 may be implemented as a non-transitory computer-readable medium that stores one or more executable instructions, such as, for example, logic, algorithms, code, etc. As discussed further below, the instructions, logic, code, etc. stored in the memory 2104 may be represented by various modules, such as those shown in FIG. 21, that may enable aspects disclosed herein to be functionally realized. The modules shown in FIG. 21 are provided to facilitate the description of the functional association between the hardware and software components. Thus, the aspects include the processing circuitry 2102 executing the instructions stored in these respective modules in association with one or more hardware components to perform various functions related to the aspects discussed further herein. Again, the modules shown in FIG. 21 are provided to facilitate the description with respect to the aspects described in this section of the disclosure.

[0219] In an aspect, executable instructions stored in the transceiver parameter tuning control module 2108, in conjunction with the processing circuit 2102, may facilitate the apparatus 2100 adjusting DC-DC converter settings of one or more of the dedicated per-transceiver chain DC-DC converters implemented within the transceiver slices 2112.1-2112.N. This may include, for example, generating appropriate control signals that are transmitted to one or more of the DC-DC converters via a suitable communication medium and protocol. These control signals may, in response, cause each DC-DC converter to change some aspect of its operation. For example, the control signals may adjust the settings of the DC-DC converters to modify the output supply voltage for a particular transceiver chain 2112, as discussed herein. Providing another example, the control signals may turn off one or more of the DC-DC converters or reactivate a DC-DC converter that was previously turned off to an on state.

[0220] Again, the DC-DC converter settings may be adjusted in various ways to adjust transceiver parameters associated with one or more of the transceiver chains 2112. Thus, as used herein, the term "transceiver parameters" may refer to any type of transceiver component setting that may be modified as a result of a change in DC-DC converter settings or state. For example, the DC-DC converter settings for a particular transceiver chain 2112.1-2212.N may be adjusted to change amplifier bias settings to compensate for various external factors such as VSWR mismatch or temperature, to follow codebook settings for a desired amplitude taper, to compensate for a lower performing PA, and to modulate amplifier bias settings to track the modulation envelope. This may additionally or alternatively include adjusting bias settings of transceiver components other than amplifiers, such as mixers.

[0221] In certain aspects, transceiver parameters may be adjusted to achieve a desired result based on measurements provided via feedback components as discussed herein. This may include, for example, the use of look-up tables (LUTs), algorithms, etc. stored in memory 2104 or otherwise accessible to processing circuitry 2102. For example, the LUTs or algorithms may define sets of bias settings for each transceiver slice 2112 based on particular detected conditions. The desired, adjusted transceiver parameters may then be correlated or otherwise derived from the measurement data obtained via the feedback components.

[0222] In an aspect, the executable instructions stored in the DPD parameter tuning control module 2110, in conjunction with the processing circuit 2102, may facilitate the apparatus 2100 to perform various functions related to calculating and applying DPD parameters to a baseband signal. For example, aspects include the executable instructions stored in the DPD parameter tuning control module using measurements provided via a feedback component as discussed herein in conjunction with nonlinearity mismatch, temperature mismatch, VSWR mismatch, or the like, or other mismatch characteristics between the transceiver slices 2112.1-2112.N. Additionally, the executable instructions stored in the DPD parameter tuning control module 2110 may enable the processing circuit 2102 to determine whether the common DFE 1502 or individual transceiver slice DFEs (e.g., DFEs 1510, 1522) should calculate and / or apply DPD parameters at each transceiver slice 2112. In any event, the executable instructions stored in the DPD parameter tuning control module can facilitate the processing circuit 2102 adjusting initial DPD parameters (e.g., those provided in a factory calibration and / or those provided by the common DFE 1502) to achieve per-transceiver chain DPD correction, as described herein.

[0223] In certain aspects, similar to the transceiver parameters, the DPD parameters may be adjusted to achieve a desired result based on measurements provided via the feedback component as discussed herein. This may include, for example, the use of look-up tables (LUTs), algorithms, etc. stored in the memory 2104 or otherwise accessible to the processing circuit 2102. For example, the LUTs or algorithms may define DPD coefficients for each transceiver slice 2112 based on a particular detected condition or mismatch. The desired, adjusted DPD parameters may then be correlated or otherwise derived from the measurement data obtained via the feedback component.

[0224] Although some examples discussed herein are provided with respect to a transmit path associated with each transceiver slice, this is by way of example and not limitation. The aspects described herein may be equally applicable to any suitable components in the transmit or receive path in each individual transceiver slice, which may utilize the same DC-DC converter or different DC-DC converters (e.g., two DC-DC converters per transceiver slice) on the same transceiver chain. In aspects where a single DC-DC converter is used, the setting of the DC-DC converter may further be adapted when switching between transmit and receive modes. For example, the amplifier bias discussed herein with respect to the PA 1517 may also be applied to the amplifier 1516 in the receive path circuitry as shown in FIG. 15 to bias the amplifier 1516 to match a codebook setting, or for any other suitable reason as discussed herein with respect to the transmit path circuitry. As another example, the aspects described herein may be used to track the VSWR between the antenna and the receive amplifier 1516 and adjust the bias of the amplifier 1516 to compensate for the VSWR mismatch.

[0225] Section IV - Optimal Combination of Adaptive Spatial Filtering and ADCs to Maximize Dynamic Range in Digital Beamforming Systems

[0226] The aspects described in this section relate generally to wireless receivers, and more particularly, to wireless receiver architectures that implement adaptive spatial filtering.

[0227] Compared to traditional phased arrays, where signals from multiple antenna elements are combined with gain and phase shifts in the RF or analog domain, digital beamforming requires a duplication of the complete transceiver chain for each antenna element, and signals are combined only in the digital domain. Such duplication of hardware results in higher power dissipation and, since there is no array gain in the RF stage, requires additional gain stages to maintain the level plan.

[0228] Again, traditional digital beamforming solutions result in higher power dissipation. Furthermore, to add to this problem, traditional receivers do not provide immunity to spatial blockers, since each transceiver chain is omnidirectional. As a result, each complete transceiver chain is required to support a higher effective dynamic range, with the biggest impact being on the data converters. The higher dynamic range required in each chain, combined with the additional circuitry, results in a noticeable increase in power dissipation.

[0229] In some communication protocols, such as those implementing mmWave communication frequencies, digital beamforming (DBF) allows the system to fully utilize certain benefits offered by mmWave bands. In particular, a complete DBF radio is expected to be able to form and independently control multiple simultaneous beams to support connections to multiple UEs and / or base stations. This is a necessary capability to support inter-vehicle networks for autonomous vehicles and drones. It is also a key component of base station solutions. Furthermore, the multi-beam capability facilitates fast beam acquisition and tracking, especially for mobiles. Multiple independently controlled simultaneous beams can also be useful when implemented for diversity in uplink and downlink. For example, secondary beams can scan in parallel for better link directions while maintaining connectivity through the primary beam.

[0230] Despite its system-level benefits, digital beamforming has not yet been deployed in commercial systems, mainly due to the significant power penalty and the challenge of meeting severe blocker scenarios. Specifically, with regard to mmWave systems, traditional mmWave systems typically implement phased arrays. Such traditional phased arrays generate a single TX or RX beam that can only be switched sequentially to different directions, resulting in slow acquisition and handoff and limiting the number of users that can be supported simultaneously.

[0231] As further referenced in this section and other sections, the term "mm-wave frequencies" in which aspects described in this section and other sections may operate may include frequencies and frequency bands, e.g., above 20 GHz, 24 GHz, 28 GHz, etc., up to some upper frequency limit. For example, mm-wave frequency bands may include frequencies in the range of 20 GHz to 300 GHz, 24 GHz to 300 GHz, etc. This may include various bands known to be associated with, or otherwise referred to as, mm-wave frequency bands, e.g., 24 GHz, 28 GHz, 37 GHz, 39 GHz, 40 GHz, 47 GHz, 60 GHz, etc.

[0232] Other approaches to implementing beamforming systems include so-called "brute force implementations" that aim to perform an exhaustive signal search using a large combination of steered beam directions. However, this technique suffers from power overhead resulting from the need for one mixer and one data converter per antenna element. As explained above, each receive chain, and especially each data converter, needs to support a higher dynamic range due to the lack of spatial selectivity in the RF and analog sections of the transceiver, and the missing array gain from the RX line-up / level plan. This further magnifies the power dissipation penalty.

[0233] With these future developments and advantages of digital beamforming in mind, the aspects presented in this section of the disclosure are directed to ways to address these issues by optimally combining the signals from each element to implement a DBF system with spatial blocker suppression and dynamic range mitigation in each transceiver chain. In particular, the aspects described in this section address the dynamic range constraints that currently pose problems for digital beamforming systems in various ways. First, dynamic range may be addressed by performing multi-element estimation of the RX signal in an adaptive spatial filter to suppress correlated ADC quantization noise. Second, coarse sectorized scans may be performed simultaneously (in parallel) in different directions to detect spatial blockers. Third, detected spatial blockers may act to provide attenuation of the blocker signal and / or nulling of specific spatial directions through low latency feedback around the ADC or through feedforward coupling between multiple RX elements.

[0234] As discussed in more detail throughout this section, some advantages from the aspects as described include fast beam acquisition and tracking, simultaneous support of multiple beams, and interference nulling. Furthermore, to enable mmWave communications in mobile devices and base stations, it is paramount to have very low power consumption (battery life, heat, etc.). The aspects described in this section allow this to be achieved, along with the other advantages mentioned above.

[0235] FIG. 22 illustrates a block diagram of an example receiver design using multi-element joint estimation of a received signal in an adaptive spatial filter according to an aspect of the disclosure. The receiver design 2200 as shown in FIG. 22 may form part of a larger overall receiver design, or may additionally or alternatively form part of a larger overall transceiver design. For example, the receiver design 2200 may be part of a transceiver design as discussed herein with reference to other Sections 1-3. In an aspect, the receiver design 2200 may include any suitable number N of receive chains 2201.1-2201.N, with each receive chain 2201 being implemented within a separate transceiver chain. Additionally, aspects include each of the receive chains 2202.1-2202.N being implemented as part of a separate transceiver slice in a transceiver design utilizing a transceiver slice architecture as described above in one or more of Sections 1-3.

[0236] As an illustrative example, each of receiver chains 2201.1-2201.N may be implemented as a receive chain associated with each of transceiver slices 1504.1-1504.N as shown and discussed above in Section 3 with reference to FIG. 15. In other words, receive chain 2201.1 may be implemented as a receive chain associated with transceiver slice 1504.1, receive chain 2201.2 may be implemented as a receive chain associated with transceiver slice 1504.2, etc. Providing a further example, each of receive chains 2201.1-2201.N may be implemented as a receive chain associated with each of transceiver chains 1012.1-1012.N as shown and discussed above in Section 1 with reference to FIG. 10. As another example, each of receiver chains 2201.1-2201.N may be implemented as a receiver chain associated with each of transceiver slices 1412.1-1412.N shown and discussed in Section 2 above with reference to Figure 14. Of course, the aspects described in other Sections 1-3 may or may not be combined in various respects with the functionality as discussed in this section.

[0237] The receiver design 2200 as shown in Figure 22 omits certain connections and components for ease of explanation. Thus, aspects of the receiver design 2200 described herein may include additional, fewer, or alternative components to those as shown in Figure 22 and elsewhere in this disclosure.

[0238] As shown in FIG. 22, each receive chain 2201.1-2201.N is coupled to a respective antenna, which is further coupled to a respective low noise amplifier (LNA). The output of the LNA in each receive chain 2201 is further coupled to a respective in-phase (I) and quadrature (Q) phase branch. Each I branch and Q branch includes a mixer that may be coupled to a local oscillator (not shown) to downconvert the receive signal to baseband (or another suitable lower frequency). An ADC in each of the I branch and Q branch is configured to convert the downconverted receive signal to a digital signal (e.g., a digital data stream), which is then processed via a digital front end (DFE) 2202. In various aspects, each of the ADCs in each receive chain 2201.1-2201.N may be implemented in any suitable manner to provide a digital output to the DFE 2202. For example, the ADC may be implemented as a successive approximation (SAR), sigma-delta, pipeline, flash ADC, etc. to support a sufficiently wide channel bandwidth.

[0239] In various aspects, the adaptive joint estimator block 2204 may be implemented by any suitable combination of processing circuitry and / or software implemented by the DFE 2202, which may include execution of suitable algorithms to perform the associated functions described throughout this section. The DFE 2202 may include any suitable number and / or type of components configured to perform functions known to be associated with a digital front end. For example, the DFE 2202 may be implemented as a processing circuit, a portion of a processing circuit, one or more portions of an on-board chip (e.g., a digital signal processor) having dedicated digital front end functionality, etc. For example, the DFE 2202 may receive digital baseband data (e.g., digital RX signals as shown) from each receive chain 2201.1-2201.N, which may be processed to recover data included in an over-the-air data transmission. The DFE 2202 may perform other functions not shown or described herein for brevity, such as, for example, over-the-air data transmission functions. Alternatively, the DFE 2202 may be implemented as one of the DFEs discussed in any of the previous Sections 1-3. To provide an illustrative example, the adaptive joint estimation block 2202 may be part of a DFE 2202 similar to or identical to the DFE 1502 as shown and described in Section 3 with reference to FIG.

[0240] Additionally, the DFE 2202 may be integrated with one or more other components of the receiver design 2200 to form part of a common IC (e.g., an RFIC), or these components may be located on separate chips. As an illustrative example, the DFE 2202 and one or more of the receive chains 2201.1-2201.N may be integrated on a common RFIC, which may be particularly useful to address signal bandwidth and latency that may exist if these components are located on separate chips. This may also be true for the DFE and other components discussed elsewhere in this section and in other sections. For example, the sectorized scanning circuit block 2304 and the blocker extraction circuit block 2306 may be integrated as part of a DFE that is part of the same IC as the receive chains 2301.1-2301.N as discussed with reference to FIG. 23A. As another example, the DFE circuit block 2404 may be integrated as part of a DFE that is part of the same IC as the receive chains 2401.1-2401.N as discussed with reference to FIG. 24.

[0241] For a digital beamforming solution, each of the antennas as shown in FIG. 22 may be omnidirectional and thus do not distinguish signals received in one direction from signals received in another direction. In other words, each individual antenna element may be omnidirectional and beamforming is achieved as an aggregate function of gain and phase shift resulting from digital processing in the DFE 2202. As a result of the omnidirectional nature of each antenna element, the antenna elements of each receive chain 2201.1-22021.N may receive a desired signal of interest from one direction (e.g., main beam direction) and blocker signals in a different direction. These blocker signals may be associated with various sources of signal interference independent of the signal of interest and may have frequencies very close to the signal of interest (e.g., co-channel), but are often largely static with respect to the receiver design 2200. This fact may be exploited as discussed further below to facilitate adaptive spatial filtering.

[0242] In contrast, traditional digital beamforming systems do not implement spatial filtering, and in-channel asynchronous spatial blockers, which may include an exemplary blocker signal as shown in Figure 22, remain largely unfiltered. Furthermore, in fully digital beamforming systems, the array gain associated with combining signals from multiple antenna elements occurs in the digital domain and does not have the benefit of gain applied in the analog domain, resulting in lower gain in the receive chain. These two issues result in the need for more ADCs, each with a higher dynamic range.

[0243] However, the aspects described in this section recognize that the RX error vector magnitude (EVM) budget is typically dominated by phase noise and ADC quantization noise. Because each receive chain 2201.1-2201.N receives signals omnidirectionally to support digital beamforming, each receive chain 2201 receives correlated signals with unknown, signal-dependent delays. And while ADC quantization noise is often modeled as additive uniform noise, the aspects described herein take advantage of the fact that it arises from the nonlinear properties of the ADC quantizers. Thus, the ADC quantization noise is signal dependent, and because the ADCs see correlated signals, their quantization noise is also correlated.

[0244] For example, each receive chain 2201.1-2202.N is shown receiving a desired signal of interest (S) and a blocker signal (B), which may be received at each antenna element at different angles of arrival. These signals are summed at each of the I and Q branches in each receive chain 2201, respectively, but for clarity, FIG. 22 shows two separate signals in signal graph 2206. Signal graph 2206 may correspond to either the I or Q branch, as an example, and illustrates that for each receive chain 2201.1-2201.N, the desired signal and the blocker signal may have different delays relative to each other within a single receive chain 2201 and relative to other receive chains 2201, the delays depending on the different angles of incidence of the desired signal and the blocker signal at each antenna element and the physical location of each antenna element relative to each other.

[0245] In other words, each of the receive chains 2201.1-2201.N receives the desired signal A and the blocker signal B with a different delay that depends on the angle of arrival of each particular signal. Continuing with the example, each signal graph 2206 shows the desired signal having a larger delay as it travels from receive chain 2201.1 to 2201.N, with receive chain 2201.1 receiving signal S first and receive chain 2201.1 receiving signal S last. For blocker signal B in this example, the opposite is true, with receive chain 2201.N receiving blocker signal B first and receive chain 2201.1 receiving blocker signal B last. Generally, this time relationship depends on the angle of arrival of the two signals at each antenna element associated with each receive chain 2201.1-2201.N, but the delays associated with the desired signal S and blocker signal B between receive chains are generally not known in advance.

[0246] However, the delay between each receive chain 2201.1-2201.N is unknown, but each antenna element operates in an omnidirectional manner, i.e., each receive chain 2201.1-2201.N receives essentially the same signal, except for the (unknown) time-shifted delay between them. Thus, in one aspect, the adaptive joint estimation circuit block 2204 receives digital RX data signals in parallel from each ADC associated with the receive chains 2201.1-2201.N. The RX data signals thus received include a combination of both the desired signal S and the blocker signal B received at each receive chain 2201. According to this aspect, the adaptive joint estimation circuit block 2204 is configured to jointly detect both the signal S and the blocker signal B while rejecting the blocker signal.

[0247] For ease of explanation, a hypothetical example is provided in which the delay between the desired signal S and the blocker signal B is known for each of the receive chains 2201.1 and 2201.2, and also the delay between the receive chains 2201.1-2201.N for the desired signal S and the blocker signal S is known. In such a case, a time shift may be introduced as part of the processing of the digital RX signal (i.e., digital samples) received from the ADC in the receive chain 2201.1 for each of the desired signal S and the blocker signal B, and the results are independently correlated to the actual received RX signal provided by the ADC of the receive chain 2201.1. These two sets of correlations each amplify the desired signal in one case and the blocker signal in the other case. Thus, this correlation can be repeated for each receive chain to select a correlation result that amplifies only the desired signal S and not the blocker signal B.

[0248] However, as mentioned above, the delay between the desired signal S and the blocker signal B, and the delay between each of the receive chains 2201.1-2201.N, is unknown. In this case, the signal delay also needs to be estimated for each receive chain 2201.1-2201.N. Aspects described in this section facilitate this via a joint estimation technique performed via an adaptive joint estimation circuit block 2204. In one aspect, the adaptive joint estimation circuit block 2204 may estimate the delay associated with the desired signal S and the blocker signal B for each receive chain 2201.1-2201.N using the digital RX signals received in parallel from each ADC as shown in FIG. 22. The result of this delay estimation is then used to correlate the result of performing a phase shift or time delay on the desired signal S and the blocker signal B for each receive chain 2201.1-2201.N with the received digital RX signals received from the ADC of each receive chain 2201.1-2201.N.

[0249] That is, aspects described herein perform the delay and correlation steps together since delay and correlation each affect each other. In one aspect, this may include, for example, using maximum likelihood estimation (MLE) to determine the estimated signal and blocker delay that best correlates to the received digital RX signal received from the ADC of each receive chain 2201.1-2201.N. For example, correlation may be performed via the adaptive joint estimator circuit block 2204 for each receive chain 2201.1-2202.N as follows: The desired signal S received via the ADC for that particular receive chain 2201 is time shifted with an initial estimated delay, which is then multiplied with an unshifted version of the same desired signal S in the same receive chain 2201 and integrated over a time period. Thus, the accuracy of each estimated delay used to perform the time shift may be determined based on which estimated delay provides the largest result when multiplied in the manner described above and integrated over each time period.

[0250] In one aspect, the above-mentioned technique may be performed in the adaptive joint estimation circuit block 2204 in parallel with the correlation for each of the other receive chains 2201.1-2201.N. In other words, the estimated delays for the desired signal S and the blocker signal B for each receive chain 2201.1-2201.N may be correlated in parallel for each receive chain and for all other receive chains 2201.1-2201.N. That is, instead of sequentially and individually performing delay estimation and signal correlation for each receive chain 2201.1-2201.N, a time-shifted version of each desired signal S and blocker signal B may be correlated in parallel (e.g., in parallel) against the (unshifted) ADC output of each other receive chain 2201.1-2201.N until a solution is obtained that includes a set of estimated time delays for the desired signal S and the blocker signal B for each receive chain 2201.1-2201.N. This solution set of estimated delays may be obtained by analyzing the results of the receive chain correlation to identify the set of estimated delays that gives the smallest error, e.g., in a maximum likelihood sense, relative to the distribution of the digital RX signal received via the adaptive joint estimation circuit block 2204.

[0251] The use of correlation via the adaptive joint estimation circuit block 2204 is just one example of a technique that may be utilized to estimate the signal delay in each receive chain and is provided herein by way of example and not by way of limitation. Aspects include the adaptive joint estimation circuit block 2204 adaptively and jointly estimating the delay of the desired signal S and the blocker signal B from each of the receive chains 2201.1-2201.N in any suitable manner.

[0252] Once a set of estimated delays is obtained in this manner, aspects include an adaptive joint estimation circuit block 2204 canceling out the delays associated with the desired signal S and the blocker signal B in each receive chain 2201.1-2201.N. After this is done, the signals received as digital RX signals from the ADCs of each of the receive chains 2201.1-2201.N will be substantially identical to one another, since the delays have been taken into account and the signals are otherwise received omnidirectionally via each antenna element as described above. This advantageously allows for an improvement in the signal to noise ratio of the receiver design 2200.

[0253] Furthermore, if the signals received from different antenna elements are combined in the digital domain by applying gain and phase shifts, the RX signal-to-noise ratio (SNR) is improved by a factor √Nelem, where Nelem is the number of elements. As described further below, aspects described herein implement a multi-element joint estimation of the received signal in an adaptive spatial filter to exploit the correlation properties between the receive chains 2200.1-2201.N, as shown in FIG. 22. In doing so, correlated noise, such as quantization noise and sampling jitter, is suppressed. Thus, aspects described in this section improve the effective ADC resolution while implementing a digital beamforming solution, allowing the use of lower resolution converters in each receive chain 2201.1-2201.N. In doing so, the total power dissipation is advantageously reduced, allowing practical implementation of a full DBF system. To clarify this point, system simulations were performed for different array sizes according to the adaptive joint estimation technique as described in this section. The SNR gain from the joint estimation is summarized in Table 1 below. [Table 1]

[0254] In other words, the aspects described in this section utilize parallel (e.g., concurrent or joint) estimation of both the desired signal S, the blocker signal B, and the time delay associated with both of these signals, and correlate those results with each of the other receive chains 2201.1-2201.N. Doing so utilizes the fact that the received signals in receiver design 2200 are partially correlated with each other, thereby allowing the quantization requirements of the ADC to be relaxed, and the overall power consumption of the receiver may be reduced.

[0255] The receiver design 2200 may be configured to use information from the channel estimation to steer the main beam towards the signal of interest. For example, a short preamble that is part of the communication protocol may contain channel estimation information that allows the main beam direction to be calculated. Once the direction of the signal of interest is known, the DFE 2202 may digitally apply gain and phase to the digital RX signal to achieve beamforming of the main beam in this direction. However, since the signals are received omnidirectionally by the receive chain as described above, the analog-to-digital converter (ADC) in the DBF may be saturated from blocker signals that are incident from directions different from the main beam. Thus, as discussed further below in Figures 23A-C and 24. Aspects of the receiver design described in this section may enable spatial blocker detection, and once detected, feedback or feedforward corrections can be applied to provide spatial filtering.

[0256] FIG. 23A illustrates a block diagram of an example receiver design implementing spatial blocker detection using coarse sector scanning in accordance with an aspect of the present disclosure. The receiver design 2300 illustrated in FIG. 23 may include any suitable number of receive chains 2301.1-2301.N. The receive chains 2301.1-2301.N may be the same as or substantially similar to the receive chains 2202.1-2201.N as illustrated and described above with reference to FIG. 22. Thus, only the differences between receive chains 2201 and 2301 will be discussed further herein.

[0257] The ADC implemented by each of the receive chains 2301.1-2301.N may be configured to first digitize the most significant bits of the downsampled received signal. Aspects described with reference to Figures 23A-23C use a coarse resolution to detect in parallel the high-speed envelope signal along directions other than the main beam direction (known from the received packet preamble) and exploit this capability of the ADC to estimate the blocker signal using only the MSB or additional bits following the MSB and perform partial cancellation of the blocker signal.

[0258] To do so, the receiver design 2300 may include a sectorized scanning circuit block 2304 and a blocker extraction circuit block 2306. The sectorized scanning circuit block 2304 and the blocker extraction circuit block 2306 may be implemented as part of the DFE 2202 in a manner similar to that discussed with reference to the adaptive joint estimation circuit block 2204. This is described in further detail with reference to FIGS. 23B-C, which show further details of one of the ADCs shown in FIG. 23A. Thus, the sectorized scanning circuit block 2304 may facilitate a coarse scan operation that may be implemented using a digital parallel rotation scheme as shown in FIG. 23A. The blocker extraction circuit block 2306 may be configured to analyze the results of the coarse scan from each ADC in parallel using only the MSBs output from one or more ADCs, or any suitable number of MSBs output from one or more of the ADCs. Thus, the blocker signal can be estimated from the partially digitized data (e.g., partially digitized data resulting from processing only a portion of the bits output by the ADC), which represents a coarse estimate of the blocker signal. Blocker extraction circuit block 2306 may then use the estimate of the blocker signal to provide digital feedback to each ADC via ADC feedback path 2308, as shown in FIG. 23A.

[0259] To do so, the receive design 2300 may utilize an architecture of an ADC implemented in each receive chain 2301. Referring now to FIG. 23B, an exemplary ADC design implementing a SAR-based design is shown, including a quantizer 2320 (e.g., a comparator circuit) configured to quantize a signal received at an input node 2310. This signal may be received, for example, via a combined mixer output in an I branch and a Q branch of one or more of the receive chains 2301.1-2301.N. In other words, the exemplary ADC design shown in FIGS. 23B and 23C may be implemented in each ADC. However, this particular ADC topology is an example and not a limitation. The ADCs may be configured in any suitable configuration in various aspects, so long as the MSB is digitized first in such a configuration.

[0260] Thus, an ADC such as that shown in Figures 23B-C outputs digital data representing a digitized sampled version of the downsampled analog data in the I and Q branches of one or more (e.g., all) of receive chains 2301.1-2301.N. According to the example SAR topology shown in Figures 23B-C, the received signal may be sampled at any suitable sampling frequency f s The received signal is sampled by the quantizer 2320 at a sampling frequency of N·f in FIG. 23B-C. Further, the ADC quantizer 2320 is configured to output a digitized bit stream corresponding to each sampling period of the received signal according to the sampling frequency. Thus, as shown in FIG. 23B-C, the ADC quantizer 2320 may provide an N-bit output of the received signal within each sampling period. Thus, the quantizer 2320 may provide an N·f s The data bits may be output at a higher frequency, denoted as N bit cycles.

[0261] In a SAR configuration such as that shown in Figures 23B-C, a coarse estimate of the signal is performed via quantizer 2320. This estimate is then output and used as feedback to subtract from the input signal, which is again quantized, and so on. Thus, as each bit is output by quantizer 2320 in an N-bit cycle, the most recently output bit may be used as feedback via logic circuitry 2330, which provides a voltage at node 2310 to quantizer 2330. Logic circuitry 2330 may include any suitable configuration of components to selectively couple a desired adjustable voltage to node 2310 in accordance with a SAR ADC technique, which may include known techniques for doing so.

[0262] For example, logic circuit 2330 may include a digital-to-analog (DAC) converter (not shown) configured to vary the voltage applied to node 2310 by selectively switching couplings of capacitors, in this example, according to known techniques used for SAR-based ADCs. This is merely one example of logic circuit 2330, and aspects include the use of any suitable technique and / or DAC for providing a variable voltage to node 2310. In any case, logic circuit 2330 may thus utilize the bit output from quantizer 2320 as feedback. This feedback is utilized by logic circuit 2330 in conjunction with the current sampling of the received signal at node 2310 to enable quantizer 2320 to generate the next successive approximation of the received signal as the next bit of the N-bit cycle. This is done until the entire current received signal at node 2310 has been completely sampled and digitized. Again, the first bit output by quantizer 2320 in this manner may be the MSB of the N-bit cycle.

[0263] 23A, providing an illustrative example, the desired signal in this example has an angle of incidence of approximately 30 degrees, while the blocker signal has an angle of incidence of approximately -45 degrees. The output of each ADC in each receive chain 2301.1-2301.N is provided in parallel to a sectorized scanning circuit block 2304 and contains digitized data representing the sum of the desired signal and the blocker signal, taking into account the omnidirectional nature of the operation of receiver design 2300.

[0264] Continuing with this example, aspects include the sectorized scanning circuit block 2304 performing a "coarse" sectorized scan in parallel over several regions of space, although as an alternative aspect sequential scanning may be used. This may include performing a coarse parallel scan over a larger region of space, such as a quadrant, octant, etc., which may be implemented via the sectorized scanning circuit block 2304 using digital rotation as shown in FIG. 23A, for example. In the example shown in FIG. 23A, the receiver design performs a coarse parallel sectorized scan of eight different octants, each associated with a beam angle of -135°, -90°, -45°, +0°, +45°, +90°, +135°, and +180°. However, aspects include any suitable number of regions being scanned in this manner in parallel with one another, and the scan may take into account the known angle of incidence of the desired signal to calculate adjacent regions for the sectorized scan when the entire space does not need to be scanned. Thus, rather than analyzing the energy along every possible angle of incidence, the MSB(s) is used to perform a coarser scan of several larger areas.

[0265] Continuing with this example, the sectorized scanning circuit block 2304 may provide a partially digitized output from each ADC to the blocker extraction circuit block 2306 as a result of the coarse scanning operation. This partially digitized output may include a representation of the energy received in parallel from each ADC using the MSB(s) initially output from each ADC. In this manner, using the MSB(s) output from one or more of the parallel ADCs, the blocker extraction circuit block 2306 may quickly ascertain whether additional signal energy is present (e.g., above a threshold) in one of the coarsely scanned regions that corresponds to a region other than the known main beam position. If so, the sectorized scanning circuit block 2304 may use this information to determine the presence of a blocker signal in that particular scan region having the additional signal energy. Additionally, the blocker extraction circuit block 2306 may use the MSB(s) output by the one or more ADCs to calculate an estimate of the blocker signal in one or more of the coarsely scanned regions. Advantageously, because this coarse scan utilizes the MSB(s) of the ADC instead of the entire digital ADC output, the coarse scan process can provide results with low latency, which allows the coarse scan to be performed in parallel with signal processing operations associated with communication via the main beam.

[0266] Again, if a blocker is detected in this manner, aspects include a blocker extraction circuit block 2306 that estimates the blocker signal and uses this estimated blocker signal to attenuate the actual received blocker signal. According to one aspect, this may be performed by adding a cancellation signal through a switch-cap DAC in the feedback path of the ADC, as shown in FIG. 23C. FIG. 23C shows details of an example ADC design similar to that shown in FIG. 23B. The example ADC design shown in FIG. 23C operates in a similar manner to the example ADC design shown in FIG. 23B, and therefore only the differences between these example ADC designs will be discussed further.

[0267] In contrast to the exemplary ADC design shown in FIG. 23B, the exemplary ADC design shown in FIG. 23C includes a summer circuit block 2340 introduced into the ADC quantizer feedback path, which may be present in each ADC in each receive chain 2301.1-2301.N, as shown in FIG. 23A. Thus, a spatial blocker estimate may represent a digitized estimate of the blocker signal based on a coarse scan and analysis of the MSBs output by one or more of the ADCs, as described above, and may be provided to each ADC via the ADC feedback path 2308. The digitized spatial blocker estimate, when added to the output of the ADC via the summer circuit block 2340, may be formatted to offset the output of the quantizer 2320 provided to the logic circuit 2330 used to drive the ADC. In this way, the blocker signal energy is not quantized by the ADC, preventing saturation.

[0268] Aspects further include providing switch-cap DAC feedback to the N-path RF / IF for further optimization. For example, the exemplary receiver architecture shown and discussed in this section provides a single ADC per receive chain. However, embodiments are not limited to these examples and include the use of any suitable number N of ADCs coupled in parallel in one or more of the receive chains. For example, receive chain 2201.1 may include any suitable number of ADCs in parallel in each of the I and Q branches. With reference to FIGS. 23B, 23C, the use of digitized spatial blocker estimates discussed in this section may be implemented and extended to any suitable number of such parallel ADCs, for example, where applicable. In this manner, power consumption may be reduced since each ADC can operate with a lower resolution for the required RX signal EVM. Advantageously, given the nature of the coarse scan, aspects include selectively applying blocker cancellation (e.g., via DFE) only when an active blocker is detected (e.g., via sectorized scan circuit block 2304), thus conserving power during normal operation.

[0269] Although the exact angle of incidence of the blocker signal may not be determined using the coarse scan described above, and the estimated blocker signal may not perfectly match the actual blocker signal using only the ADC output MSB(s), the estimated blocker signal may still sufficiently attenuate the blocker signal to mitigate saturation of the ADC. Furthermore, the use of the MSB(s) for blocker signal estimation provides a latency low enough to ensure that the blocker is sufficiently attenuated within the current sampling window processed by each ADC. Using only the MSB provides the lowest latency in this regard, although aspects are not limited to this implementation. Indeed, additional bits following the MSB may be utilized as part of the blocker signal estimation. This increases the latency, but also increases the accuracy of estimating the blocker signal. Thus, aspects recognize the tradeoff between lower latency and higher accuracy and include using only the MSB for coarse beam scanning, or alternatively, using any suitable number of bits following the MSB depending on the application.

[0270] The use of coarse scanning provides an additional advantage in that detection of blocker signals can be entirely contained in the radio head itself (e.g., the component in which the DFE 2202 is implemented). Thus, the coarse beam scanning described herein can be performed without incurring the latency introduced through baseband signal processing. This is particularly important to enable correction for asynchronous blocker signals. In other words, a coarse spatial scan should be sufficient for blocker detection since the blocker signal does not need to be precisely digitized, but only needs to be estimated enough to reduce the dynamic range required to handle it. In this way, coarse blocker signal scanning advantageously provides quick (e.g., low latency) results of blocker signal estimation and requires low hardware complexity. For example, in contrast to conventional brute force techniques that scan each possible angle of arrival, the embodiments described in this section perform a coarse scan to detect blocker signals. Doing so advantageously detects blocker signals in a less computationally intensive manner than conventional blocker signal detection techniques, resulting in greater power savings.

[0271] In summary, as discussed in this section with reference to FIG. 22, spatial filtering may be performed using correlated adaptive joint estimates of the desired signal and any accompanying blocker signals to suppress correlated ADC quantization noise. Further, as discussed in this section with reference to FIG. 23A-C. Coarse sectorized scanning may be performed simultaneously (in parallel) in different directions to detect spatial blockers, which may be estimated using the MSB(s) output from the ADC and used to at least partially cancel the blocker signals. As described further below, aspects include alternately performing spatial filtering via the digital front end or at the downconverted output (e.g., baseband) of the mixer output prior to the ADC in one or more receive chains. This is further described below with reference to FIG. 24.

[0272] FIG. 24 illustrates a block diagram of an example receiver design implementing a feed-forward spatial filter using coupling between a set of nearest neighboring RF chains in accordance with an aspect of the present disclosure. In an aspect, the receiver design 2400 illustrated in FIG. 24 may function to perform a coarse sectorized scan to detect blockers in directions deviating from the main beam direction in a similar or identical manner as described above with reference to the receiver design 2300 illustrated in FIG. 23A. However, instead of using the MSB output via the ADC to build an estimate of the blocker signal used for blocker attenuation via feedback, the receiver design 2400 may implement the spatial filter using a feed-forward implementation, as discussed further below.

[0273] The use of a feed-forward design may provide additional benefits such as further reducing overall system latency. For example, receiver design 2300 may use only the MSB output by one or more ADCs in the receiver chain, yet still introduce minimal latency to facilitate subsequent attenuation of the blocker signal. Thus, aspects include using a coarse sectorized scan as described herein to detect the angle of arrival of the blocker signal. However, instead of reconstructing the blocker signal to cancel the signal, the implementation described with reference to receiver design 2400 tunes a spatial notch filter along the identified blocker direction, as identified in the coarse spatial scan described above.

[0274] To do so, receiver design 2400 implements an interconnected feed-forward combination of adjacent receiver chains to introduce a notch filter in the spatial response. For example, as shown in FIG. 24, receiver design 2400 may include any suitable number of receiver chains 2401.1-2401.N, which may be configured in a manner similar to receiver chains 2301.1-2301.N, as described in connection with receiver design 2300, and thus only the differences between these components will be further described. Additionally, receiver design 2400 may include a DFE circuit block 2404, which may be implemented as part of any suitable type of DFE, and may include a sectorized scanning circuit block 2304, as discussed herein with reference to FIG. 23. As with the other DFEs discussed herein with reference to FIG. 22 and FIG. 23A-C, the DFE in which sectorized scanning circuit block 2304 is implemented may be part of one of the other DFEs described in this section or one of the other Sections 1-3 in various aspects.

[0275] Aspects also include each of the receive chains 2401.1-2401.N implementing any suitable number of tuning circuit blocks 2420.1-2420.N that may be interconnected from adjacent receive chains. While the example receiver design 2400 shown in FIG. 24 includes an interconnection of two adjacent receive chains for ease of explanation, aspects described herein are not limited in this respect and any suitable number of receive chains may be interconnected in a feed-forward manner. Furthermore, any suitable number of tuning circuit blocks 2420 may be implemented for each adjacent receive chain that is coupled in this manner. To take advantage of the correlation between the interconnected receive chains, aspects include the interconnected adjacent receive chains being associated with antenna elements that are physically close to one another.

[0276] For example, if the antenna shown in FIG. 24 is part of a one-dimensional antenna array, three interconnected tuning circuit blocks 2420.1, 2420.2, and 2420.N may be associated with receive chains 2401 that are coupled to physically adjacent antennas, e.g., associated with the top, middle, and bottom antennas in the array, respectively. As another example, if the antenna shown in FIG. 24 is part of a two-dimensional antenna array, eight or more interconnected tuning circuit blocks 2420.1-2420.N may be coupled in a feed-forward manner. For example, eight adjacent antenna elements are coupled to each of the surrounding antenna elements in the 2D antenna array. Aspects include receive designs 2400 that implement an interconnection architecture of any suitable number of receive chains 2401 coupled in a feed-forward manner based on adjacent connected antenna elements. However, as additional antenna elements are interconnected in this manner, there is a point of diminishing returns, so aspects include recognizing a trade-off between system complexity and cost and the benefits of coupling additional interconnected receive chains.

[0277] The tuning circuit blocks 2420.1-2420.N may be implemented as any suitable number and type of circuit components to facilitate application of adjustable gain weights and / or adjustable phase shifts to the downsampled signals received via the respective receive chains 2401. For example, the tuning circuit blocks 2420.1-2420.N may include several amplifiers as shown in FIG. 24, with each tuning circuit block 2420 having an amplifier with a respective gain that is independently and electronically adjustable for each of the I and Q branches that is coupled to the downsampled received data output from the mixer in each receive chain 2401. Referring to receive chain 2401.2 as an example, this may include three tuning circuit blocks 2420.1, 2420.2, and 2420.N. The implementation of the tuning circuit blocks 2420.1-2420.N as shown in FIG. 24 is by way of example and not limitation. Thus, although tuning circuit blocks 2420.1-2420.N may be implemented with additional or alternative components to facilitate adjustable phase shifting of the baseband signal, using the configuration shown in FIG. 24 with cross-coupled I and Q branches allows the phase to be adjusted by adjusting only the amplifier gain of a particular amplifier within each tuning circuit block 2420.1-2420.N.

[0278] For example, for an adjacent combining configuration as shown in FIG. 24, where two adjacent antennas are combined in a feed-forward architecture, tuning circuit block 2420.1 includes a combined tunable amplifier and summing circuit configuration, with adjustable weighting W -1The weighted outputs of the circuit block 2420.1 are coupled to summing circuits associated with the inputs of the ADCs for each of the I and Q branches of the receiver chain 2401.1. Further, the tuning circuit block 2420.2 includes a combined tunable amplifier and summing circuit arrangement and outputs a downsampled received signal having an adjustable weighting W0, where the weighted outputs of the tuning circuit block 2420.2 are coupled to summing circuits associated with the inputs of the ADCs for each of the I and Q branches of the receiver chain 2401.2. Further, the tuning circuit block 2420.N includes a combined tunable amplifier and summing circuit arrangement and outputs a downsampled received signal having an adjustable weighting W0, where the weighted outputs of the tuning circuit block 2420.2 are coupled to summing circuits associated with the inputs of the ADCs for each of the I and Q branches of the receiver chain 2401.2. +1 Here, the weighted outputs of tuning circuit block 2420.N are coupled to summing circuits associated with the inputs of the ADCs for each of the I and Q branches of the third receiver chain 2401.2. This coupling is not shown in FIG. 24 for simplicity, but may be coupled in the same manner as the coupling between tuning circuit block 2420.1 and receive chain 2401.1, as shown. Thus, the exemplary receiver design 2400 implements a feed-forward architecture that combines within each receive chain 2401.1-2401.N the weighted downconverted signal received via its own antenna with the weighted downconverted signal received via each of the two adjacent antennas.

[0279] In various aspects, the summing circuits (e.g., ADC 2440) coupled to the inputs of each ADC shown in FIG. 24, examples of which are shown with reference to receiver chain 2041.2 as summing circuits 2430.1, 2430.2, may include any suitable configuration of circuit components to combine weighted signals from any suitable number of adjacent receiver chains 2401.1-2401.N. In so doing, aspects of receiver design 2400 include implementing hybrid beamforming techniques as opposed to using a fully digital beamforming system. In other words, the weighting associated with tuning circuit blocks 2420.1-2420.N may be applied in the analog domain, e.g., at baseband, or via a downconverted, lower frequency, separate from the signals received via each receiver chain antenna. The interconnects that make up the overall feedforward architecture of receiver design 2400 may be connected at an overall level or as part of a system plan. However, aspects include selectively combining weighted signals from one or more adjacent antennas by controlling the gain of each tuning circuit block 2420. For example, the gain of one or more amplifiers in tuning circuit block 2420 may be set to a sufficiently low value such that a weighted output from tuning circuit block 2420 is not combined with other weighted outputs. Thus, different weights may be applied using tuning circuit blocks 2420.1-2420.N such that ADCs in one or more of receive chains 2401.1-2401.N receive different analog weighted signals from adjacent antennas.

[0280] Aspects include a DFE circuit block 2404 that receives digital data output from one or more of the ADCs 2440 according to any suitable subset of the antennas that make up the overall antenna array. In doing so, the DFE circuit block 2404 can calculate a resulting beamforming pattern to facilitate spatial filtering by forming nulls in the pattern in the detected direction of the blocker signal. Also, since the coarse spatial scan may identify the direction of the blocker signal based on the detected energy in each scan direction, the various interconnections of adjacent receive chains 2401-1 to 2401.N may facilitate the application of various weights using the tuning circuit block 2420 based on the detected direction of the blocker signal. The beamforming implemented via the DFE 2404 may be implemented in any suitable manner to thus form a spatial notch filter, which may use knowledge of the main beam direction and the detected spatial blocker direction (from the coarse scan described herein) to formulate a resulting pattern, with spatial notches, if desired. In one embodiment, the weightings applied to the tuning circuitry blocks 2420 may be calculated using the detected direction of the spatial blockers and may be applied per receive chain based on the detected energy values. For example, the results of the coarse scan described above may be used to estimate the angle of the blocker signal. Using this information, a suitable combination of weights may be applied via the tuning circuitry blocks 2420.1-2420.N to produce a beamforming shape that acts as a spatial filter with respect to the estimated blocker signal direction.

[0281] As an example, the DFE 2404 can utilize the weighted outputs received in parallel with one another via the ADCs of each receiver chain 2401.1-2401.N and use the weighted and combined data to formulate suitable beamforming weights such that blocker signals are cancelled or at least partially attenuated as a result of the spatial filters. By combining signals between multiple adjacent antenna elements in this manner, tunable spatial notches can be formed without significantly limiting the field of view of each receive chain 2401.1-2401.N while providing ADC dynamic range relief.

[0282] FIG. 25 illustrates a block diagram of an example device according to an aspect of the disclosure. In various aspects, the device 2500 may be implemented as any suitable type of device configured to transmit and / or receive wireless signals according to any suitable number and / or type of communication protocols. For example, the device 2500 may be implemented as a user equipment (UE), such as a mobile phone, tablet, laptop computer, etc. Providing a further example, the device 2500 may be implemented as an access point or base station. The device 2500 may implement one or more aspects as described herein to facilitate receiving and / or transmitting wireless signals according to a particular frequency or frequency band, such as a millimeter wave frequency, as described further herein, for example.

[0283] In one aspect, device 2500 may include a processing circuit 2502, a memory 2504, and any suitable number N of transceiver slices or chains 2516.1-2516.N, each coupled to one or more respective antennas 2518.1-2518.N. The components depicted in FIG. 25 are provided for ease of explanation, and aspects include device 2500 including additional, fewer, or alternative components to those depicted in FIG. 25. For example, device 2500 may include one or more power sources, display interfaces, peripherals, ports, etc.

[0284] In certain aspects, various components of the apparatus 2500 may be equated with functionality further described herein, which may be described with reference to performing multi-element estimation of the RX signal in an adaptive spatial filter to suppress correlated ADC quantization noise, performing coarse sectorized scans simultaneously (in parallel) in different directions to detect spatial blockers, and / or suppressing spatial blockers through low latency feedback around the ADC or via feed-forward coupling between multiple RX elements to provide attenuation / nulling in specific spatial directions, as discussed in more detail throughout this section. Each of the transceiver slices 2516.1-2516.N may be identified with, for example, a respective one of the transceiver slices 1504.1-1504.N discussed with reference to the transceiver design 1500 shown in FIG. 15 and discussed in Section 3, and / or one of the receiver chains discussed throughout this section (e.g., receiver chains 2201.1-2201.N, 2301.1-2301.N, 2401.1-2401.N, etc.).

[0285] Aspects include a processing circuit 2502 configured as any suitable number and / or type of computer processor that may facilitate control of the apparatus 2500 as discussed herein. In some aspects, the processing circuit 2502 may be identified with a baseband processor (or a suitable portion thereof) implemented by the apparatus 2500. In other aspects, the processing circuit 2502 may be identified with one or more processors implemented by the apparatus 2500 that are separate from the baseband processor (e.g., one or more digital signal processors, one or more processors associated with a DFE, such as DFE 2202, 2404, DFE 1502, etc., described in Section 3). In still other aspects, the functionality of apparatus 2500 may be combined with functionality discussed herein with reference to apparatus 2100 (as discussed in Section 3), apparatus 2100 may have functionality combined with apparatus 1400 (as discussed in Section 2), and apparatus 1400 may have functionality combined with functionality discussed herein with reference to apparatus 1000 (as discussed in Section 1). Additionally or alternatively, aspects include various functions discussed herein with reference to apparatus 2500 being performed by one or more components associated with apparatus 2100, apparatus 1400, and / or apparatus 1000.

[0286] In any event, aspects include processing circuitry 2502 being configured to execute instructions to perform arithmetic operations, logical operations, and / or input / output (I / O) operations and / or control operation of one or more components of device 2500. For example, processing circuitry 2502 may include one or more microprocessors, memory registers, buffers, clocks, etc. Additionally, aspects include processing circuitry 2502 communicating with and / or controlling functionality associated with memory 2504 and / or transceiver slices 2516.1-2516.N.

[0287] This may include, for example, controlling and / or arbitrating the transmit and / or receive functions of the apparatus 2500 to facilitate detection of blocker signals as described herein, using detection of blocker signals to attenuate or cancel blocker signals, etc., as described herein. Additionally, the processing circuitry 2502 may facilitate calculation of beamforming weights that may be applied digitally (e.g., via a suitable DFE) and / or in the analog domain via tuning circuitry block 2420, adjusting various parameters such as phase and / or gain of tuning circuitry block 2420, adjusting parameters for one or more of the one or more transceiver slices 2516, controlling the state of the apparatus 2500 to operate in a receive mode or a transmit mode, performing one or more baseband processing functions (e.g., medium access control (MAC), encoding / decoding, modulation / demodulation, data symbol mapping, error correction, etc.), identifying a subset of interconnected receiver chains for application of analog weights for spatial filtering, as well as any other suitable functionality for performing functions related to the aspects described herein.

[0288] In one aspect, the memory 2504 stores data and / or instructions such that, when executed by the processing circuitry 2502, the processing circuitry 2502 performs various functions described herein. The memory 2504 can be implemented as any known volatile and / or non-volatile memory including, for example, read only memory (ROM), random access memory (RAM), flash memory, magnetic storage media, optical disks, erasable programmable read only memory (EPROM), programmable read only memory (PROM), etc. The memory 2504 can be non-removable, removable, or a combination of both.

[0289] For example, the memory 2504 may be implemented as a non-transitory computer-readable medium that stores one or more executable instructions, such as, for example, logic, algorithms, code, etc. As described further below, the instructions, logic, code, etc. stored in the memory 2504 may be represented by various modules, such as those illustrated in FIG. 25, that may functionally realize the aspects disclosed herein. The modules illustrated in FIG. 25 are provided to facilitate the description of the functional associations between the hardware and software components. Thus, the aspects include the processing circuitry 2502 executing the instructions stored in these respective modules in association with one or more hardware components to perform various functions associated with the aspects, as described further herein. Again, the modules illustrated in FIG. 25 are provided to facilitate the description of the aspects described in this section of the disclosure.

[0290] In an aspect, executable instructions stored in the adaptive joint estimation computation module 2508, in conjunction with the processing circuitry 2502, may facilitate the apparatus 2500 to perform multi-element estimation of the received signal in an adaptive spatial filter to suppress correlated ADC quantization noise. This may include, for example, processing digitized signals received via ADCs associated with each receiver chain 2201.1-2201.N, as discussed herein with reference to FIG.

[0291] In an aspect, executable instructions stored in the sectorized scanning control module 2510, in conjunction with the processing circuitry 2502, may facilitate the device 2500 to perform coarse scans of various regions of space to detect blocker signals in directions deviating from the direction of the main beam. For example, aspects include the executable instructions stored in the sectorized scanning control module 2510 facilitating digital rotation of the scan angle of data received via each receiver chain 2301 as described in this section with reference to FIGS. 23A-23C. The sectorized scanning control module 2510, in conjunction with the processing circuitry 2502, as discussed herein, may facilitate the device 2500 to receive digital data representing received signal energy across scanned regions of space for each of the receive chains in parallel.

[0292] In an aspect, executable instructions stored in the blocker signal estimation and cancellation module 2512, in conjunction with the processing circuit 2502, may facilitate the apparatus 2500 to analyze digitized data obtained via the coarse scanning operations described herein. This may include, for example, the DFE (e.g., DFE 2202) analyzing received signal energy across various scanned directions according to the MSB(s) output by the ADC in each receive chain, e.g., as discussed herein with reference to FIGS. 23A-23C.

[0293] Additionally, the blocker signal estimation and cancellation module 2512 may facilitate calculation of signal energy in each scanned region. For scanned regions (other than the region occupied by the main beam) in which an energy level exceeding a threshold energy value is detected, an estimate of the detected blocker signal may be calculated using the signal energy received across the various scanned directions according to the MSB output by the ADC in each receive chain, as discussed herein with reference to FIGS. 23A-23C discussed herein. Again, once the blocker signal estimate is calculated, the blocker signal estimate may be used as feedback to one or more ADCs in the receive chains to prevent the blocker signal energy from being quantized, thus preventing ADC saturation.

[0294] In an aspect, the executable instructions stored in the spatial filter computation module 2514, in conjunction with the processing circuitry 2502, may facilitate the device 2500 dynamically and adaptively adjust the spatial filter to avoid receiving a portion (or the entirety) of a blocker signal in one or more detected directions. This may include, for example, generating and providing control signals to adjust various parameters such as the phase and / or gain of the tuning circuitry block 2420, as discussed herein with reference to, for example, FIG. 24. Again, the output of the tuning circuitry block 2420 may be combined in a weighted manner from adjacent receiver chains and used in a feed-forward architecture, as discussed herein with reference to FIG. 24.

[0295] The various aspects described in this section, as well as in Sections 1-3, may be combined with one another in any suitable manner to provide further improvements. For example, the aspects described herein with reference to Figure 22 aimed at jointly estimating the signals and time delays received via each receive chain 2201 may be combined with ADC feedback aspects as described with reference to Figures 23A-23C and / or spatial filtering aspects as described with reference to Figure 24. EXAMPLES

[0296] Example I The following examples relate to further aspects.

[0297] Example 1. A local oscillator (LO) signal generator comprising: a delay locked loop (DLL) configured to generate a set of phase shifted input signals at a fractional frequency from an input signal having a fractional frequency that is a portion of an output signal frequency; a phase making circuit coupled to the DLL, the phase making circuit configured to output a subset of phase shifted signals from the set of phase shifted input signals; and an injection locked clock multiplier (ILCM) configured to receive the subset of phase shifted signals as injected inputs and combine and frequency multiply the subset of phase shifted signals to generate a set of LO signals at the output signal frequency.

[0298] Example 2. The LO signal generator of example 1, wherein the phase shifted signals of the subset have equally spaced phase shifts relative to one another that are a fraction of a full clock cycle, the fraction of the full clock cycle being equal to the fraction of the output signal frequency.

[0299] Example 3. The LO signal generator of any combination of Examples 1-2, wherein the ILCM is configured to combine the subsets of the phase shifted signals to destructively interfere with each other to suppress harmonics of the fractional frequency except for harmonics of the fractional frequency signal equal to the output signal frequency, and the subsets of the phase shifted signals that destructively interfere with each other provide a sum signal that is attenuated as a result of a phase relationship between the phase shifted signals compared to individual phase shifted signals before being combined.

[0300] Example 4. The signal generator of any combination of Examples 1-3, wherein the ILCM is configured to combine the subsets of the phase shifted signals to constructively interfere with each other in a sub-frequency signal equal to the output signal frequency, the subsets of the phase shifted signals that constructively interfere with each other provide a sum signal that is amplified as a result of a phase relationship between the phase shifted signals compared to the individual combined phase shifted signals before being combined.

[0301] Example 5. The LO signal generator of any combination of Examples 1 to 4, wherein said set of LO signals are quadrature differential LO signals.

[0302] Example 6. The LO signal generator of any combination of Examples 1 to 5, wherein the output signal frequency is in the millimeter wave frequency range.

[0303] Example 7. The LO signal generator of any combination of Examples 1-6, wherein the DLL includes a controlled delay line having a number of delay elements, and a unit phase shift associated with the set of the phase shifted input signals is a function of the number of delay elements.

[0304] Example 8. The LO signal generator of any combination of Examples 1-7, wherein the DLL includes an interpolation delay line having a plurality of delay elements, and a unit phase shift associated with the set of phase shifted input signals is less than a delay associated with a single delay element of the plurality of delay elements.

[0305] Example 9. The LO signal generator of any combination of examples 1-8, wherein the DLL includes a two-dimensional matrix of delay elements interleaved with each other, each node in the matrix being fed by two delay elements.

[0306] Example 10. The LO signal generator of any combination of Examples 1-9, wherein the ILCM comprises: an oscillator circuit; a tank circuit coupled to an output of the oscillator circuit; and a feedback path coupled between an output of the oscillator circuit and an input of the oscillator circuit, the input of the oscillator circuit being coupled to the subset of the phase shifted signals.

[0307] Example 11. The LO signal generator of any combination of Examples 1-10, wherein the ILCM comprises: an oscillator circuit; a tank circuit coupled to an output of the oscillator circuit; and a feedback path coupled between an output of the oscillator circuit and an input of the oscillator circuit, wherein the output of the oscillator circuit is coupled to the subset of the phase shifted signals, and the subset of the phase shifted signals is coupled to the tank circuit.

[0308] Example 12. A wireless device having a plurality of transceiver chains; a processing circuit; and a memory configured to store executable instructions that, when executed by the processing circuit, cause each transceiver chain from the plurality of transceiver chains to perform the following steps: generate, from an input signal having a fractional frequency that is a portion of an output signal frequency, a set of phase-shifted input signals at the fractional frequency; output a subset of phase-shifted signals from the set of phase-shifted input signals; and combine and frequency multiply the subset of phase-shifted signals via an injection-locked clock multiplier (ILCM) to generate a set of LO signals at the output signal frequency.

[0309] Example 13. The wireless device of example 12, wherein the phase shifted signals of the subset have equally spaced phase shifts relative to one another that are a fraction of a full clock cycle, the fraction of a full clock cycle being equal to the fraction of the output signal frequency.

[0310] Example 14. The radio device of any combination of Examples 12-13, wherein each transceiver chain of the plurality of transceiver chains is configured to generate a respective set of LO signals at the output signal frequency that are phase shifted relative to the set of LOs generated via other transceiver chains.

[0311] Example 15. The wireless device of any combination of Examples 12-14, wherein each transceiver chain of the plurality of transceiver chains is configured to combine subsets of the phase shifted signals to destructively interfere with each other such that harmonics of the fractional frequency, except for harmonics of the fractional frequency signal equal to the output signal frequency, are suppressed, and the subsets of the phase shifted signals that destructively interfere with each other provide a total signal that is attenuated as a result of a phase relationship between the phase shifted signals compared to individual phase shifted signals before being combined.

[0312] Example 16. The wireless device of any combination of Examples 12-15, wherein each transceiver chain of the plurality of transceiver chains is configured to combine the subsets of the phase shifted signals to constructively interfere with each other in a fractional frequency signal equal to the output signal frequency, and the subsets of the phase shifted signals that constructively interfere with each other provide a sum signal that is amplified as a result of a phase relationship between the phase shifted signals compared to the individual combined phase shifted signals before being combined.

[0313] Example 17. The wireless device of any combination of Examples 12-16, wherein the set of LO signals are quadrature differential LO signals, and the output signal frequencies are in the millimeter wave frequency range.

[0314] Example 18. The wireless device of any combination of Examples 12-17, wherein each transceiver chain of the plurality of transceiver chains includes a delay locked loop (DLL) including a controlled delay line having a number of delay elements, and a unit phase shift associated with the set of phase shifted input signals is a function of the number of delay elements.

[0315] Example 19. The wireless device of any combination of Examples 12-18, wherein each transceiver chain of the plurality of transceiver chains includes a delay locked loop (DLL) including an interpolating delay line having a plurality of delay elements, and a unit phase shift associated with the set of phase shifted input signals is less than a delay associated with a single delay element of the plurality of delay elements.

[0316] Example 20. The radio of any combination of Examples 12-19, wherein each transceiver chain of the plurality of transceiver chains includes a delay locked loop (DLL) including a two-dimensional matrix of delay elements interleaved with each other, each node in the matrix being fed by two delay elements.

[0317] Example 21. The wireless device of any combination of Examples 12-20, wherein the ILCM associated with each transceiver chain of the plurality of transceiver chains comprises: an oscillator circuit; a tank circuit coupled to an output of the oscillator circuit; and a feedback path coupled between an output of the oscillator circuit and an input of the oscillator circuit, the input of the oscillator circuit being coupled to the subset of the phase shifted signals.

[0318] Example 22. The wireless device of any combination of Examples 12-21, wherein the ILCM associated with each transceiver chain of the plurality of transceiver chains comprises: an oscillator circuit; a tank circuit coupled to an output of the oscillator circuit; and a feedback path coupled between an output of the oscillator circuit and an input of the oscillator circuit, wherein the output of the oscillator circuit is coupled to the subset of phase shifted signals, and the subset of phase shifted signals is coupled to the tank circuit.

[0319] Example 23. A local oscillator (LO) signal generator comprising: a delay locked loop (DLL) configured to generate a set of phase shifted input signals at an output signal frequency using a reference clock signal having a fractional frequency that is a fraction of the output signal frequency; a phase configuration circuit coupled to the DLL and to a plurality of buffers, the phase configuration circuit selectively coupling each phase shifted signal from a subset of the set of phase shifted signals to a respective buffer of the plurality of buffers; and an injection locked clock multiplier (ILCM) including an oscillator circuit coupled to the plurality of buffers, the oscillator circuit being tuned to the output signal frequency, the oscillator circuit being configured to utilize currents provided by respective ones of the plurality of buffers associated with the subset of the set of phase shifted signals to combine and frequency multiply the subset of the phase shifted signals to thereby generate a set of LO signals at the output signal frequency.

[0320] Example 24. The LO signal generator of example 23, wherein the phase shifted signals of the subset of the set have equally spaced phase shifts relative to one another that are a fraction of a full clock cycle, the fraction of the full clock cycle being equal to the fraction of the output signal frequency.

[0321] Example 25. A local oscillator (LO) signal generator means comprising: a delay locked loop (DLL) means for generating, from an input signal having a fractional frequency that is a fractional frequency of an output signal frequency, a set of phase shifted input signals at the fractional frequency, a phase configuration means coupled to the DLL and configured to output a subset of phase shifted signals from the set of phase shifted input signals, and an injection locked clock multiplier (ILCM) means for receiving the subset of phase shifted signals as injected inputs and combining and frequency multiplying the subset of phase shifted signals to generate a set of LO signals at the output signal frequency.

[0322] Example 26. The LO signal generator means of example 25, wherein the phase shifted signals of the subset have equally spaced phase shifts relative to one another that are a fraction of a full clock cycle, the fraction of the full clock cycle being equal to the fraction of the output signal frequency.

[0323] Example 27. The LO signal generator means of any combination of examples 25-26, wherein the ILCM means combines the subsets of the phase shifted signals to destructively interfere with each other so as to suppress harmonics of the fractional frequency except for harmonics of the fractional frequency signal equal to the output signal frequency, and the subsets of the phase shifted signals that destructively interfere with each other provide a sum signal that is attenuated as a result of the phase relationship between the phase shifted signals compared to the individual phase shifted signals before being combined.

[0324] Example 28. The signal generator means of any combination of examples 25-27, wherein the ILCM means combines the subsets of the phase shifted signals to constructively interfere with each other in a sub-frequency signal equal to the output signal frequency, and the subsets of the phase shifted signals that constructively interfere with each other provide a sum signal that is amplified as a result of the phase relationship between the phase shifted signals compared to the individual combined phase shifted signals before being combined.

[0325] Example 29. The LO signal generator means of any combination of examples 25-28, wherein said set of LO signals are quadrature differential LO signals.

[0326] Example 30. The LO signal generator means of any combination of examples 25-29, wherein the output signal frequency is in the range of millimeter wave frequencies.

[0327] Example 31. The LO signal generator means of any combination of examples 25-30, wherein the DLL means includes controlled delay line means having a number of delay elements, and a unit phase shift associated with the set of the phase shifted input signals is a function of the number of delay elements.

[0328] Example 32. The LO signal generator means of any combination of Examples 25-31, wherein the DLL means includes an interpolation delay line having a plurality of delay elements, and a unit phase shift associated with the set of phase shifted input signals is less than a delay associated with a single delay element of the plurality of delay elements.

[0329] Example 33. The LO signal generator means of any combination of examples 25-32, wherein the DLL means includes a two-dimensional matrix of delay elements interleaved with each other, each node in the matrix being fed by two delay elements.

[0330] Example 34. The LO signal generator means of any combination of Examples 25-33, wherein the ILCM means comprises: an oscillator circuit; a tank circuit coupled to an output of the oscillator circuit; and a feedback path coupled between an output of the oscillator circuit and an input of the oscillator circuit, the input of the oscillator circuit being coupled to the subset of the phase shifted signals.

[0331] Example 35. The LO signal generator means of any combination of Examples 25-34, wherein the ILCM means comprises: an oscillator circuit; a tank circuit coupled to an output of the oscillator circuit; and a feedback path coupled between an output of the oscillator circuit and an input of the oscillator circuit, wherein the output of the oscillator circuit is coupled to the subset of the phase shifted signals and the subset of the phase shifted signals is coupled to the tank circuit.

[0332] Example 36. A wireless device having a plurality of transceiver chain means; a processing means; and a memory configured to store executable instructions which, when executed by the processing means, cause each transceiver chain means from the plurality of transceiver chain means to perform the steps of: generating a set of phase shifted input signals at a fractional frequency from an input signal having a fractional frequency that is a portion of an output signal frequency; outputting a subset of phase shifted signals from the set of phase shifted input signals; and combining and frequency multiplying the subset of phase shifted signals via an injection locked clock multiplier (ILCM) to generate a set of LO signals at the output signal frequency.

[0333] Example 37. The wireless device of example 36, wherein the phase shifted signals of the subset have equally spaced phase shifts relative to one another that are a fraction of a full clock cycle, the fraction of the full clock cycle being equal to the fraction of the output signal frequency.

[0334] Example 38. The radio device means of any combination of Examples 36-37, wherein each transceiver chain of the plurality of transceiver chains is configured to generate a respective set of LO signals at the output signal frequency that are phase shifted relative to the set of LOs generated via other transceiver chains.

[0335] Example 39. The radio device means of any combination of Examples 36-38, wherein each transceiver chain means of the plurality of transceiver chain means is configured to combine subsets of the phase shifted signals to destructively interfere with each other such that harmonics of the fractional frequency except harmonics of the fractional frequency signal equal to the output signal frequency are suppressed, and the subsets of the phase shifted signals that destructively interfere with each other provide a total signal that is attenuated as compared to individual phase shifted signals before being combined as a result of a phase relationship between the phase shifted signals.

[0336] Example 40. The radio device means of any combination of Examples 36-39, wherein each transceiver chain means of the plurality of transceiver chain means is configured to combine the subsets of the phase shifted signals to constructively interfere with each other in a fractional frequency signal equal to the output signal frequency, the subsets of the phase shifted signals that constructively interfere with each other provide a sum signal that is amplified as a result of a phase relationship between the phase shifted signals compared to the individual combined phase shifted signals before being combined.

[0337] Example 41. The radio device means of any combination of Examples 36-40, wherein the set of LO signals are quadrature differential LO signals and the output signal frequencies are in the range of millimeter wave frequencies.

[0338] Example 42. The radio device means of any combination of Examples 36-41, wherein each transceiver chain means of the plurality of transceiver chain means includes a delay locked loop (DLL) means including a controlled delay line having a number of delay elements, and a unit phase shift associated with the set of phase shifted input signals is a function of the number of delay elements.

[0339] Example 43. The radio device means of any combination of Examples 36-42, wherein each transceiver chain means of the plurality of transceiver chain means includes a delay locked loop (DLL) means including an interpolating delay line having a plurality of delay elements, and a unit phase shift associated with the set of phase shifted input signals is less than a delay associated with a single delay element of the plurality of delay elements.

[0340] Example 44. The radio device means of any combination of Examples 36-43, wherein each transceiver chain means of the plurality of transceiver chain means includes a delay locked loop (DLL) including a two-dimensional matrix of delay elements interleaved with each other, each node in the matrix being fed by two delay elements.

[0341] Example 45. The radio device means of any combination of Examples 36-44, wherein the ILCM associated with each transceiver chain means of the plurality of transceiver chain means comprises: an oscillator circuit; a tank circuit coupled to an output of the oscillator circuit; and a feedback path coupled between an output of the oscillator circuit and an input of the oscillator circuit, the input of the oscillator circuit being coupled to the subset of the phase shifted signals.

[0342] Example 46. The radio device means of any combination of Examples 36-45, wherein the ILCM associated with each transceiver chain means of the plurality of transceiver chain means comprises: an oscillator circuit; a tank circuit coupled to an output of the oscillator circuit; and a feedback path coupled between an output of the oscillator circuit and an input of the oscillator circuit, wherein the output of the oscillator circuit is coupled to the subset of phase shifted signals and the subset of phase shifted signals is coupled to the tank circuit.

[0343] Example 47. A local oscillator (LO) signal generator means comprising: delay locked loop (DLL) means for generating a set of phase shifted input signals at an output signal frequency using a reference clock signal having a fractional frequency that is a fraction of the output signal frequency; phase configuring means coupled to the DLL means and to a plurality of buffer means for selectively coupling each phase shifted signal from a subset of the set of phase shifted signals to a respective buffer means of the plurality of buffer means; and injection locked clock multiplier (ILCM) means including an oscillator circuit coupled to the plurality of buffer means, the oscillator circuit being tuned to the output signal frequency, the oscillator circuit being configured to utilize currents provided by respective buffer means of the plurality of buffer means associated with the subset of the set of phase shifted signals to combine and frequency multiply the subset of the phase shifted signals to thereby generate a set of LO signals at the output signal frequency.

[0344] Example 48. The LO signal generator means of example 47, wherein the phase-shifted signals of the subset of the set have equally spaced phase shifts relative to one another that are a fraction of a full clock cycle, the fraction of a full clock cycle being equal to the fraction of the output signal frequency.

[0345] Apparatus as shown and described.

[0346] The method as shown and described. EXAMPLES

[0347] Example II The following examples relate to further aspects.

[0348] Example 49. A local oscillator (LO) signal generator comprising: a frequency synthesizer configured to generate a first reference signal having a first frequency; a digital-to-time converter (DTC) configured to generate a second reference signal based on the first reference signal, the second reference signal having a second frequency that is a fractional multiple of the first frequency; a high-band (HB) path including an HB injection-locked frequency multiplier (ILFM), the HB ILCM configured to generate one or more HB local oscillator (LO) signals having an HB LO frequency based on the first frequency related to the first reference signal; and a low-band (LB) frequency path including a LB ILFM, the LB ILCM configured to generate one or more LB local oscillator (LO) signals having an LB LO frequency based on the second frequency related to the second reference signal.

[0349] Example 50. The LO signal generator of example 49, wherein the HB ILCM is one of a plurality of HB ILCMs in the HB path, each of the plurality of HB ILCMs associated with a respective transceiver chain, and the LB ILCM is one of a plurality of LB ILCMs in the LB path, each of the plurality of LB ILCMs associated with a respective transceiver chain.

[0350] Example 51. The LO signal generator of any combination of Examples 49-50, wherein the HB ILCM is configured to generate a set of orthogonal LO signals as the one or more HB LO signals, and the LB ILCM is configured to generate a set of orthogonal LO signals as the one or more LB LO signals.

[0351] Example 52. The LO signal generator of any combination of Examples 49-51, wherein the HB ILCM is coupled to one or more mixers configured to perform direct downconversion of a received signal to baseband using the one or more HB LO signals, and the LB ILCM is coupled to one or more mixers configured to perform direct downconversion of a received signal to baseband using the one or more LB LO signals.

[0352] Example 53. The LO signal generator of any combination of Examples 49 to 52, wherein a receive signal that is directly downconverted to baseband via the one or more mixers in an HB path and a receive signal that is directly downconverted to baseband via the one or more mixers in an LB path are in the millimeter wave frequency range.

[0353] Example 54. The LO signal generator of any combination of Examples 49-53, wherein the HB ILFM is configured to generate the one or more HB LO signals having an HB LO frequency that is an integer multiple of the first frequency related to the first reference signal.

[0354] Example 55. The LO signal generator of any combination of Examples 49-54, further comprising: another DTC configured to generate, from the first reference signal, a fractionally multiplied first reference signal having a frequency that is a fractional multiple of the first frequency, and the HB ILFM configured to generate the one or more HB LO signals having the HB LO frequency that is an integer multiple of the fractional multiple of the first frequency associated with the fractionally multiplied first reference signal.

[0355] Example 56. The LO signal generator of any combination of Examples 49-55, further comprising a frequency divider circuit configured to perform a frequency division on the first reference signal to generate a frequency-divided reference signal, and the DTC is further configured to perform a fractional multiplication of the frequency-divided reference signal to generate the second reference signal.

[0356] Example 57. The LO signal generator of any combination of examples 49-56, wherein the DTC is configured to receive digital phase ramp data that is modified to adjust the fractional multiple of the first frequency, thereby adjusting the second frequency relative to the second reference signal.

[0357] Example 58. A first local oscillator (LO) signal generator including: a frequency synthesizer configured to generate a first reference signal having a first frequency; a first digital-to-time converter (DTC) configured to generate a second reference signal based on the first reference signal, the second reference signal having a second frequency that is a fractional multiple of the first frequency; an intermediate frequency (IF) mixing stage configured to generate (i) a first upconverted analog IF signal based on the first reference signal and (ii) a second upconverted analog IF signal based on the first reference signal; and a transmit mixing stage, the transmit mixing stage generating one or more HB TX local oscillator (LO) signals; a first highband (HB) injection locked frequency multiplier (ILFM) configured to upconvert the first upconverted analog IF signal to a first transmit frequency, the HB TX LO signal having an HB TX LO frequency based on the second frequency of the second reference signal. a first low-band (LB) ILFM configured to generate one or more LB TX local oscillator (LO) signals and upconvert the second upconverted analog IF signal to a second transmit frequency, the first LB ILFM having a LB TX LO frequency based on the second frequency of the second reference signal;

[0358] Example 59. The LO signal generator of Example 58, wherein the HB TX LO frequency is based on a first integer multiple of the first reference signal and the LB TX LO frequency is based on a second integer multiple of the second reference signal, the first integer multiple being different from the second integer multiple.

[0359] Example 60. The LO signal generator of any combination of Examples 58-59, further comprising: a second DTC coupled to the first HB ILFM, the second DTC configured to further fractionally multiply the second frequency associated with the second reference signal, and the first HB ILFM configured to generate the one or more HB TX LO signals having the HB LO TX frequency that is a first integer multiple of the further fractional multiple of the second frequency of the second reference signal generated via the second DTC.

[0360] Example 61. The LO signal generator of any combination of Examples 58-60, further comprising a third DTC coupled to the first LB ILFM, the third DTC configured to fractionally multiply the second frequency associated with the second reference signal, and the first LB ILFM configured to generate the one or more LB TX LO signals having the LB TX LO frequency that is a second integer multiple of the further fractional multiple of the second frequency of the second reference signal generated via the third DTC.

[0361] Example 62. The LO signal generator of any combination of Examples 58-61, further comprising: a frequency divider circuit configured to perform a frequency division of the first reference signal to generate a frequency-divided reference signal, the first DTC further configured to perform a fractional multiplication of the frequency-divided reference signal to generate the second reference signal.

[0362] Example 63. The LO signal generator of any combination of Examples 58-62, further comprising: a second HB ILFM configured to frequency multiply the first reference signal to generate one or more HB IF LO signals for upconverting a first baseband signal to the first upconverted analog IF signal via the IF mixing stage; and a second LB ILFM configured to frequency multiply the first reference signal to generate one or more LB IF LO signals for upconverting a second baseband signal to the second upconverted analog IF signal via the IF mixing stage.

[0363] Example 64. The LO signal generator of any combination of Examples 58-63, wherein the second HB ILCM is configured to generate a set of orthogonal LO signals as the one or more HB IF LO signals, and the second LB ILCM is configured to generate a set of orthogonal LO signals as the one or more LB IF LO signals.

[0364] Example 65. The LO signal generator of any combination of Examples 58-64, wherein the first transmit frequency and the second transmit frequency are in a range of millimeter wave frequencies.

[0365] Example 66. A wireless device having a plurality of transceiver chains; a processing circuit; and a memory configured to store executable instructions that, when executed by the processing circuit, cause each transceiver chain from the plurality of transceiver chains to perform the following steps: generate a first reference signal having a first frequency; generate a second reference signal based on the first reference signal via a digital-to-time converter (DTC), the second reference signal having a second frequency that is a fractional multiple of the first frequency; generate one or more HB local oscillator (LO) signals via a high-band (HB) injection-locked frequency multiplier (ILFM) having an HB LO frequency based on the first frequency related to the first reference signal; and generate one or more LB local oscillator (LO) signals via a low-band (LB) ILFM having a LB LO frequency based on the second frequency related to the second reference signal.

[0366] Example 67. The wireless device of Example 66, wherein the HB ILCM is configured to generate a set of orthogonal LO signals as the one or more HB LO signals, and the LB ILCM is configured to generate a set of orthogonal LO signals as the one or more LB LO signals.

[0367] Example 68. The wireless device of any combination of Examples 66-67, wherein the memory is further configured to store executable instructions that, when executed by the processing circuit, cause each transceiver chain from the plurality of transceiver chains to: generate, via a separate DTC, a fractionally multiplied first reference signal from the first reference signal having a frequency that is a fractional multiple of the first frequency; and generate, via the HB ILFM, the one or more HB LO signals having the HB LO frequency that is an integer multiple of the fractional multiple of the first frequency associated with the fractionally multiplied first reference signal.

[0368] Example 69. A local oscillator (LO) signal generator means comprising: a frequency synthesizer means for generating a first reference signal having a first frequency; a digital-to-time converter (DTC) means for generating a second reference signal based on the first reference signal, the second reference signal having a second frequency that is a fractional multiple of the first frequency; a high-band (HB) path including an HB injection-locked frequency multiplier (ILFM) means, the HB ILCM means configured to generate one or more HB local oscillator (LO) signals having an HB LO frequency based on the first frequency related to the first reference signal; and a low-band (LB) frequency path including a LB ILFM means, the LB ILCM means configured to generate one or more LB local oscillator (LO) signals having an LB LO frequency based on the second frequency related to the second reference signal.

[0369] Example 70. The LO signal generator means of example 69, wherein the HB ILCM means is one of a plurality of HB ILCM means in the HB path, each of the plurality of HB ILCM means associated with a respective transceiver chain means, and the LB ILCM means is one of a plurality of LB ILCM means in the LB path, each of the plurality of LB ILCM means associated with a respective transceiver chain means.

[0370] Example 71. The LO signal generator means of any combination of Examples 69-70, wherein the HB ILCM means generates a set of orthogonal LO signals as the one or more HB LO signals, and the LB ILCM means generates a set of orthogonal LO signals as the one or more LB LO signals.

[0371] Example 72. The LO signal generator means of any combination of Examples 69-71, wherein the HB ILCM means is coupled to one or more mixers configured to perform direct downconversion of a received signal to baseband using the one or more HB LO signals, and the LB ILCM means is coupled to one or more mixers configured to perform direct downconversion of a received signal to baseband using the one or more LB LO signals.

[0372] Example 73. The LO signal generator means of any combination of Examples 69-72, wherein the receive signal that is directly downconverted to baseband via the one or more mixers in the HB path and the receive signal that is directly downconverted to baseband via the one or more mixers in the LB path are in the millimeter wave frequency range.

[0373] Example 74. The LO signal generator means of any combination of examples 69-73, wherein the HB ILFM means generates the one or more HB LO signals having an HB LO frequency that is an integer multiple of the first frequency related to the first reference signal.

[0374] Example 75. The LO signal generator means of any combination of Examples 69-74, further comprising: another DTC means for generating, from the first reference signal, a fractionally multiplied first reference signal having a frequency that is a fractional multiple of the first frequency, and wherein the HB ILFM means generates the one or more HB LO signals having the HB LO frequency that is an integer multiple of the fractional multiple of the first frequency associated with the fractionally multiplied first reference signal.

[0375] Example 76. The LO signal generator means of any combination of examples 69-75, further comprising frequency divider means for performing a frequency division on the first reference signal to generate a frequency-divided reference signal, the DTC means further performing a fractional multiplication of the frequency-divided reference signal to generate the second reference signal.

[0376] Example 77. The LO signal generator means of any combination of examples 69-76, wherein the DTC means is configured to receive digital phase ramp data that is modified to adjust the fractional multiple of the first frequency and thereby adjust the second frequency relative to the second reference signal.

[0377] Example 78. A first HB TX local oscillator (LO) signal generator including frequency synthesizer means for generating a first reference signal having a first frequency; first digital-to-time converter (DTC) means configured to generate a second reference signal based on the first reference signal, the second reference signal having a second frequency that is a fractional multiple of the first frequency; intermediate frequency (IF) mixing means for generating (i) a first upconverted analog IF signal based on the first reference signal and (ii) a second upconverted analog IF signal based on the first reference signal; and transmit mixing means, the transmit mixing means generating one or more HB TX local oscillator (LO) signals and first highband (HB) injection locked frequency multiplier (ILFM) means for upconverting the first upconverted analog IF signal to a first transmit frequency, the HB TX LO signal having an HB TX LO frequency based on the second frequency of the second reference signal. and first low band (LB) ILFM means configured to generate one or more LB TX local oscillator (LO) signals and upconvert the second upconverted analog IF signal to a second transmit frequency, the LB TX LO signals having a LB TX LO frequency based on the second frequency of the second reference signal.

[0378] Example 79. The LO signal generator means of example 78, wherein the HB TX LO frequency is based on a first integer multiple of the first reference signal and the LB TX LO frequency is based on a second integer multiple of the second reference signal, the first integer multiple being different from the second integer multiple.

[0379] Example 80. The LO signal generator means of any combination of Examples 78-79, further comprising: a second DTC means coupled to the first HB ILFM, the second DTC means further fractionally multiplying the second frequency associated with the second reference signal, and the first HB ILFM means generating the one or more HB TX LO signals having the HB LO TX frequency that is a first integer multiple of the further fractional multiple of the second frequency of the second reference signal generated via the second DTC.

[0380] Example 81. The LO signal generator means of any combination of Examples 78-80, further comprising a third DTC means coupled to the first LB ILFM means, the third DTC configured to fractionally multiply the second frequency associated with the second reference signal, the first LB ILFM means generating the one or more LB TX LO signals having the LB TX LO frequency that is a second integer multiple of the further fractional multiple of the second frequency of the second reference signal generated via the third DTC.

[0381] Example 82. The LO signal generator means of any combination of Examples 78-81, further comprising: frequency divider means for performing a frequency division of the first reference signal to generate a frequency-divided reference signal, the first DTC means further performing a fractional multiplication of the frequency-divided reference signal to generate the second reference signal.

[0382] Example 83. The LO signal generator means of any combination of Examples 78-82, further comprising: second HB ILFM means for frequency multiplying the first reference signal to generate one or more HB IF LO signals for upconverting a first baseband signal to the first upconverted analog IF signal via the IF mixing means; and second LB ILFM means for frequency multiplying the first reference signal to generate one or more LB IF LO signals for upconverting a second baseband signal to the second upconverted analog IF signal via the IF mixing stage.

[0383] Example 84. The LO signal generator means of any combination of Examples 78-83, wherein the second HB ILCM means generates a set of orthogonal LO signals as the one or more HB IF LO signals, and the second LB ILCM means generates a set of orthogonal LO signals as the one or more LB IF LO signals.

[0384] Example 85. The LO signal generator means of any combination of examples 78-84, wherein the first transmit frequency and the second transmit frequency are in a range of millimeter wave frequencies.

[0385] Example 86. A wireless device means having a plurality of transceiver chain means; a processing circuit; and a memory configured to store executable instructions which, when executed by the processing circuit, cause each transceiver chain means from the plurality of transceiver chain means to perform the steps of: generating a first reference signal having a first frequency; generating a second reference signal based on the first reference signal via a digital-to-time converter (DTC) means, the second reference signal having a second frequency that is a fractional multiple of the first frequency; generating one or more HB local oscillator (LO) signals via a high-band (HB) injection-locked frequency multiplier (ILFM) means having an HB LO frequency based on the first frequency related to the first reference signal; and generating one or more LB local oscillator (LO) signals via a low-band (LB) ILFM means having an LB LO frequency based on the second frequency related to the second reference signal.

[0386] Example 87. The wireless device means of Example 86, wherein the HB ILCM means generates a set of orthogonal LO signals as the one or more HB LO signals, and the LB ILCM means generates a set of orthogonal LO signals as the one or more LB LO signals.

[0387] Example 88. The radio device means of any combination of Examples 86-87, wherein the memory is further configured to store executable instructions that, when executed by the processing circuit, cause each transceiver chain means from the plurality of transceiver chain means to: generate, via another DTC means, a fractionally multiplied first reference signal from the first reference signal having a frequency that is a fractional multiple of the first frequency; and generate, via the HB ILFM means, the one or more HB LO signals having the HB LO frequency that is an integer multiple of the fractional multiple of the first frequency associated with the fractionally multiplied first reference signal.

[0388] Apparatus as shown and described.

[0389] The method as shown and described. EXAMPLES

[0390] Example III The following examples relate to further aspects.

[0391] Example 89. A transceiver including a plurality of digital transceiver units, each digital transceiver unit of the plurality of digital transceiver units having: a transmit path circuit coupled to an antenna, the transmit path circuit configured to convert digital transmit data to an analog transmit signal transmitted via the antenna; a DC-DC converter corresponding to each digital transceiver unit, the DC-DC converter configured to provide a supply voltage; and one or more feedback components configured to provide a feedback measurement regarding operation of each respective digital transceiver unit; and a processor circuit configured to adjust the supply voltage of the DC-DC converter based on the feedback measurement.

[0392] Example 90. The transceiver of example 89, wherein the processor circuitry is configured to adjust the supply voltage of the DC-DC converter to change an amplifier bias setting of an amplifier associated with the transmit path circuitry.

[0393] Example 91. The transceiver of any combination of examples 89-90, wherein the processor circuit is configured to adjust the supply voltage of the DC-DC converter to change the amplifier bias setting of the amplifier to track a modulation envelope of the analog transmit signal transmitted via the antenna.

[0394] Example 92. The transceiver of any combination of Examples 89-91, wherein the one or more feedback components are configured to measure forward and reverse power in the transmit path circuitry associated with the analog transmit signal transmitted via the antenna, and the processor circuitry is configured to (i) use the measured forward and reverse power to track a voltage standing wave ratio (VSWR) between the transmit path circuitry and the antenna, and (ii) change an amplifier bias setting of an amplifier associated with the transmit path circuitry based on the tracked VSWR.

[0395] Example 93. The transceiver of any combination of Examples 89-92, wherein each digital transceiver section of the plurality of digital transceiver sections further includes a digital front end (DFE) corresponding to each digital transceiver section in the transmit path circuitry, the digital DFE configured to apply digital pre-distortion (DPD) parameters to the digital transmit data, and the processor circuit configured to adjust the DPD parameters based on the feedback measurement.

[0396] Example 94. The transceiver of any combination of Examples 89-93, wherein each digital transceiver section of the plurality of digital transceiver sections further includes a digital front end (DFE) corresponding to each digital transceiver section in the transmit path circuitry, the digital DFE configured to apply digital pre-distortion (DPD) parameters to the digital transmit data, and the processor circuit configured to adjust the DPD parameters based on the tracked VSWR.

[0397] Example 95. The transceiver of any combination of Examples 89-94, wherein the one or more feedback components are configured to measure a junction temperature of an amplifier associated with the transmit path circuitry, and the processor circuit is configured to adjust a supply voltage of the DC-DC converter to change an amplifier bias setting of the amplifier based on the measured junction temperature.

[0398] Example 96. The transceiver of any combination of examples 89-95, wherein the processor circuit is configured to adjust the supply voltage of the DC-DC converter to change a bias setting of the amplifier such that the analog transmit signal transmitted via the antenna has a magnitude according to a stored codebook value.

[0399] Example 97. The transceiver of any combination of Examples 89-96, wherein the DC-DC converter included in each digital transceiver unit of the plurality of digital transceiver units provides a separate, independently adjustable supply voltage to the other digital transceiver units via the processor circuitry.

[0400] Example 98. The transceiver of any combination of Examples 89-97, further comprising a receive path circuit coupled to the antenna, wherein the processor circuit is configured to adjust the supply voltage of the DC-DC converter to change an amplifier bias setting of an amplifier associated with the receive path circuit.

[0401] Example 99. A computer-implemented method in a transceiver including a plurality of digital transceiver sections, comprising: applying initial transceiver parameters associated with settings of one or more transceiver components included in one of the plurality of digital transceiver sections via a DC-DC converter associated with one of the plurality of digital transceiver sections, the one or more transceiver components being powered via the DC-DC converter; tracking via processing circuitry a voltage standing wave ratio (VSWR) between an amplifier and an antenna associated with the one of the plurality of digital transceiver sections; and adjusting via the processing circuitry a setting of the DC-DC converter to modify the initial transceiver parameters based on the tracked VSWR.

[0402] Example 100. The computer-implemented method of example 99, further comprising: applying initial digital pre-distortion (DPD) parameters to digital data representing a signal to be transmitted via a common digital front-end (DFE) shared among the plurality of digital transceiver units; and updating the DPD parameters based on the tracked VSWR via a DFE associated with the one of the plurality of digital transceiver units.

[0403] Example 101. The computer-implemented method of any combination of examples 99-100, wherein (i) adjusting a setting of the DC-DC converter and (ii) adjusting the DPD parameters based on the tracked VSWR occur simultaneously.

[0404] Example 102. The computer-implemented method of any combination of Examples 99-101, further comprising repeating (i) adjusting a setting of the DC-DC converter and (ii) updating the DPD parameters during operation of the transceiver over time as the tracked VSWR changes.

[0405] Example 103. The computer-implemented method of any combination of examples 99-102, wherein each of the plurality of transceiver units includes a DC-DC converter.

[0406] Example 104. A wireless device including: a plurality of digital transceiver units, each digital transceiver unit of the plurality of digital transceiver units configured to provide a supply voltage via a respective DC-DC converter and to provide a feedback measurement regarding operation of each respective digital transceiver unit; and a processor circuit configured to adjust the supply voltage of each DC-DC converter of each respective digital transceiver unit based on the feedback measurement from each respective digital transceiver unit.

[0407] Example 105. The wireless device of example 104, wherein the processor circuitry is configured to adjust the supply voltage of each DC-DC converter of each respective digital transceiver section to change an amplifier bias setting of an amplifier associated with a transmit path circuit included in each respective digital transceiver section.

[0408] Example 106. The wireless device of any one of Examples 104-105, wherein the processor circuitry is configured to adjust the supply voltage of each DC-DC converter of each respective digital transceiver unit to change an amplifier bias setting of an amplifier associated with a receive path circuit included in each respective digital transceiver unit.

[0409] Example 107. The wireless device of any combination of Examples 104-106, wherein the processor circuitry is configured to change the amplifier bias settings of the amplifiers associated with transmit path circuitry included in each respective digital transceiver section to track a modulation envelope of a transmit signal associated with each respective digital transceiver section.

[0410] Example 108. The wireless device of any combination of Examples 104-107, wherein the one or more feedback components included in each respective digital transceiver section are configured to measure forward and reverse power in a transmit path circuit associated with each respective digital transceiver section, and the processor circuit is configured to (i) track a voltage standing wave ratio (VSWR) using the measured forward and reverse power, and (ii) change an amplifier bias setting of an amplifier associated with the transmit path circuit included in each respective digital transceiver section based on the tracked VSWR.

[0411] Example 109. The wireless device of any combination of Examples 104-108, wherein each digital transceiver unit of the plurality of digital transceiver units further includes a digital front end (DFE) in transmit path circuitry included in each respective digital transceiver unit, the digital DFE configured to apply digital pre-distortion (DPD) parameters to digital transmit data, and the processor circuit configured to adjust the DPD parameters based on the feedback measurements.

[0412] Example 110. The wireless device of any combination of Examples 104-109, wherein each digital transceiver unit of the plurality of digital transceiver units further includes a digital front end (DFE) in a transmit path circuit included in each respective digital transceiver unit, the digital DFE configured to apply digital pre-distortion (DPD) parameters to digital transmit data, and the processor circuit configured to adjust the DPD parameters based on the tracked VSWR.

[0413] Example 111. The wireless device of any combination of Examples 104-110, wherein the one or more feedback components included in each respective digital transceiver section are configured to measure a junction temperature of an amplifier associated with a transmit path circuit included in each respective digital transceiver section, and the processor circuit is configured to adjust a supply voltage of the DC-DC converter to change an amplifier bias setting of the amplifier based on the measured junction temperature.

[0414] Example 112. The wireless device of any combination of Examples 104-111, wherein the processor circuitry is configured to adjust the supply voltage of each DC-DC converter included in each respective digital transceiver section to change an amplifier bias setting of an amplifier associated with a transmit path circuit included in each respective digital transceiver section such that a transmit signal has a magnitude according to a stored codebook magnitude value.

[0415] Example 112B. The radio device of any combination of Examples 104-112, wherein each DC-DC converter of each respective digital transceiver unit provides a separate, independently adjustable supply voltage to other digital transceiver units of the plurality of digital transceiver units via the processor circuitry.

[0416] Example 113. A transceiver means for a plurality of digital transceiver units, each digital transceiver unit of the plurality of digital transceiver units including: a transmit path means coupled to an antenna, the transmit path means converting digital transmit data into an analog transmit signal transmitted via the antenna; a DC-DC converter means corresponding to each digital transceiver unit, the DC-DC converter means providing a supply voltage; and one or more feedback means for providing a feedback measurement regarding operation of each respective digital transceiver unit; and a processor circuit configured to adjust the supply voltage of the DC-DC converter based on the feedback measurement.

[0417] Example 114. The transceiver means of example 113, wherein the processor circuitry is configured to adjust the supply voltage of the DC-DC converter means to change an amplifier bias setting of an amplifier associated with the transmit path means.

[0418] Example 115. The transceiver means of any combination of Examples 113-114, wherein the processor circuit is configured to adjust the supply voltage of the DC-DC converter means to change the amplifier bias setting of the amplifier to track a modulation envelope of the analog transmit signal transmitted via the antenna.

[0419] Example 116. The transceiver means of any combination of Examples 113-115, wherein the one or more feedback means are configured to measure forward and reverse power in the transmit path means associated with the analog transmit signal transmitted via the antenna, and the processor circuit is configured to (i) use the measured forward and reverse power to track a voltage standing wave ratio (VSWR) between the transmit path means and the antenna, and (ii) change amplifier bias settings of amplifiers associated with the transmit path means based on the tracked VSWR.

[0420] Example 117. The transceiver means of any combination of Examples 113-116, wherein each digital transceiver section of the plurality of digital transceiver sections further includes a digital front-end (DFE) means corresponding to each digital transceiver section in the transmit path means, the digital DFE means applying digital pre-distortion (DPD) parameters to the digital transmit data, and the processor circuitry configured to adjust the DPD parameters based on the feedback measurements.

[0421] Example 118. The transceiver means of any combination of Examples 113-117, wherein each digital transceiver section of the plurality of digital transceiver sections further includes a digital front-end (DFE) means corresponding to each digital transceiver section in the transmit path circuitry, the digital DFE means applying digital pre-distortion (DPD) parameters to the digital transmit data, and the processor circuitry is configured to adjust the DPD parameters based on the tracked VSWR.

[0422] Example 119. The transceiver means of any combination of Examples 113-118, wherein the one or more feedback means are configured to measure a junction temperature of an amplifier associated with the transmit path means, and the processor circuit is configured to adjust a supply voltage of the DC-DC converter means to change an amplifier bias setting of the amplifier based on the measured junction temperature.

[0423] Example 120. The transceiver means of any combination of examples 113-119, wherein the processor circuit is configured to adjust the supply voltage of the DC-DC converter means to change a bias setting of the amplifier such that the analog transmit signal transmitted via the antenna has a magnitude according to a stored codebook value.

[0424] Example 121. The transceiver means of any combination of Examples 113-120, wherein the DC-DC converter means included in each digital transceiver unit of the plurality of digital transceiver units provides separate, independently adjustable supply voltages to the other digital transceiver units via the processor circuitry.

[0425] Example 122. The transceiver means of any combination of examples 113-121, further comprising receive path means coupled to the antenna, wherein the processor circuitry is configured to adjust the supply voltage of the DC-DC converter means to change an amplifier bias setting of an amplifier associated with the receive path means.

[0426] Example 123. A computer-implemented method in a transceiver means including a plurality of digital transceiver units, comprising: applying initial transceiver parameters associated with a setting of one or more transceiver means included in the one of the plurality of digital transceiver units via a DC-DC converter means associated with one of the plurality of digital transceiver units, the one or more transceiver means being powered via the DC-DC converter; tracking via processing circuitry a voltage standing wave ratio (VSWR) between an antenna and an amplifier associated with the one of the plurality of digital transceiver units; and adjusting via the processing circuitry a setting of the DC-DC converter means to modify the initial transceiver parameters based on the tracked VSWR.

[0427] Example 124. The computer-implemented method of example 123, further comprising: applying initial digital pre-distortion (DPD) parameters to digital data representing a signal to be transmitted via a common digital front-end (DFE) means shared among the plurality of digital transceiver units; and updating the DPD parameters based on the tracked VSWR via a DFE means associated with the one of the plurality of digital transceiver units.

[0428] Example 125. The computer-implemented method of any combination of Examples 123-124, wherein (i) adjusting a setting of the DC-DC converter and (ii) adjusting the DPD parameters based on the tracked VSWR occur simultaneously.

[0429] Example 126. The computer-implemented method of any combination of Examples 123-125, further comprising repeating (i) adjusting a setting of the DC-DC converter means and (ii) updating the DPD parameters during operation of the transceiver means over time as the tracked VSWR changes.

[0430] Example 127. The computer-implemented method of any combination of examples 123-126, wherein each of the plurality of transceiver units includes a DC-DC converter means.

[0431] Example 128. A wireless device means including: a plurality of digital transceiver sections, each digital transceiver section of the plurality of digital transceiver sections configured to provide a supply voltage via a respective DC-DC converter means and to provide a feedback measurement regarding operation of each respective digital transceiver section; and a processor circuit configured to adjust the supply voltage of each DC-DC converter means of each respective digital transceiver section based on the feedback measurement from each respective digital transceiver section.

[0432] Example 129. The wireless device of example 104, wherein the processor circuitry is configured to adjust the supply voltage of each DC-DC converter means of each respective digital transceiver section to change an amplifier bias setting of an amplifier associated with a transmit path means included in each respective digital transceiver section.

[0433] Example 130. The wireless device of any one of Examples 128-129, wherein the processor circuitry is configured to adjust the supply voltage of each DC-DC converter means of each respective digital transceiver section to change an amplifier bias setting of an amplifier associated with a receive path means included in each respective digital transceiver section.

[0434] Example 131. The wireless device of any combination of Examples 128-130, wherein the processor circuitry is configured to change the amplifier bias settings of the amplifiers associated with a transmit path means included in each respective digital transceiver section to track a modulation envelope of a transmit signal associated with each respective digital transceiver section.

[0435] Example 132. The wireless device of any combination of Examples 128-131, wherein the one or more feedback means included in each respective digital transceiver section are configured to measure forward and reverse power in a transmit path means associated with each respective digital transceiver section, and the processor circuit is configured to (i) track a voltage standing wave ratio (VSWR) using the measured forward and reverse power, and (ii) change an amplifier bias setting of an amplifier associated with the transmit path means included in each respective digital transceiver section based on the tracked VSWR.

[0436] Example 133. The wireless device of any combination of Examples 128-132, wherein each digital transceiver unit of the plurality of digital transceiver units further includes a digital front-end (DFE) means in the transmit path means included in each respective digital transceiver unit, the digital DFE means applying digital pre-distortion (DPD) parameters to digital transmit data, and the processor circuitry configured to adjust the DPD parameters based on the feedback measurements.

[0437] Example 134. The wireless device of any combination of Examples 128-133, wherein each digital transceiver unit of the plurality of digital transceiver units further includes a digital front-end (DFE) means in a transmit path means included in each respective digital transceiver unit, the digital DFE means applying digital pre-distortion (DPD) parameters to digital transmit data, and the processor circuitry is configured to adjust the DPD parameters based on the tracked VSWR.

[0438] Example 135. The wireless device of any combination of Examples 128-134, wherein the one or more feedback means included in each respective digital transceiver section are configured to measure a junction temperature of an amplifier associated with a transmit path means included in each respective digital transceiver section, and the processor circuit is configured to adjust a supply voltage of the DC-DC converter to change an amplifier bias setting of the amplifier based on the measured junction temperature.

[0439] Example 136. The wireless device of any combination of Examples 128-135, wherein the processor circuitry is configured to adjust the supply voltage of each DC-DC converter means included in each respective digital transceiver section to change an amplifier bias setting of an amplifier associated with a transmit path means included in each respective digital transceiver section such that a transmit signal has a magnitude according to a stored codebook magnitude value.

[0440] Apparatus as shown and described.

[0441] The method as shown and described. EXAMPLES

[0442] Example IV The following examples relate to further aspects.

[0443] Example 137. A receiver having a digital front end (DFE); and multiple receive chains, each of the multiple receive chains configured to receive a signal and downconvert the signal to a baseband signal, each of the multiple receive chains including at least one analog-to-digital converter (ADC) configured to output a digitized version of the downconverted baseband signal to the DFE, the DFE further configured to process the digitized versions of the downconverted baseband signal received from each of the multiple receive chains in parallel with each other to estimate a time delay associated with the signal received via each of the multiple receive chains.

[0444] Example 138. The receiver of example 137, wherein the DFE is configured to process digitized versions of the downconverted baseband signal received from each of the multiple receive chains in parallel with one another by exploiting correlation of the signals received at each of the multiple receive chains.

[0445] Example 139. The receiver of any combination of Examples 137-138, wherein the DFE is configured to process digitized versions of the downconverted baseband signals received from each of the multiple receive chains in parallel with one another to further estimate the signals received via each of the multiple receive chains in conjunction with the estimate of the time delay associated with the signals received via each of the multiple receive chains.

[0446] Example 140. The receiver of any combination of Examples 137-139, wherein a correlation between a signal received via each of the plurality of receive chains and the time delay associated with the signal received via each of the plurality of receive chains is used to suppress quantization noise associated with one or more analog-to-digital converters (ADCs) associated with one or more of the plurality of receive chains.

[0447] Example 141. The receiver of any combination of examples 137-140, wherein the received signal has a frequency within a millimeter wave frequency range.

[0448] Example 142. The receiver of any combination of examples 137-141, wherein the at least one ADC included in each receive chain of the plurality of receive chains includes a successive approximation (SAR) ADC.

[0449] Example 143. A receiver having a digital front end (DFE); and a plurality of receive chains, each of the plurality of receive chains configured to receive a signal and downconvert the signal to a baseband signal, each of the plurality of receive chains including at least one analog-to-digital converter (ADC) configured to output a digitized version of the downconverted baseband signal to the DFE, the DFE further configured to perform sectorized scanning to detect received blocker signals in a direction different from a signal in a main beam direction associated with the signal by analyzing, in parallel with one another, signal energies represented by the digitized versions of the downconverted baseband signals from each of the plurality of receive chains and determining whether the preanalyzed signal energies exceed a threshold energy level.

[0450] Example 144. The receiver of example 143, wherein the DFE is further configured to perform sectorized scanning across each of a spatial octant.

[0451] Example 145. The receiver of any combination of Examples 143-144, wherein the DFE is further configured, upon detecting a received blocker sig...

Claims

1. A plurality of digital transceiver sections coupled to a common digital front end (DFE), each digital transceiver section of the plurality of digital transceiver sections configured to operate according to a same communications protocol using data communicated using the common DFE, the plurality of digital transceiver sections comprising: data transmission means coupled to an antenna for converting digital transmit data received from the common DFE into an analog transmit signal that is transmitted via the antenna; a DC-DC converter coupled to each digital transceiver portion, the DC-DC converter configured to provide a supply voltage; one or more feedback means for providing feedback measurements regarding operation of each respective digital transceiver section; and processing means for adjusting the supply voltages provided by the DC-DC converters for each respective associated digital transceiver section independently of one another based on the feedback measurements; the one or more feedback means measure forward and reverse power within the data transmission means associated with the analog transmit signal transmitted via the antenna; the processing means is configured to (i) track a voltage standing wave ratio (VSWR) between the data transmission means and the antenna using the measured forward and reverse power, and (ii) change an amplifier bias setting of an amplifier associated with the data transmission means based on the tracked VSWR. Transceiver.

2. 2. The transceiver of claim 1, wherein the processing means adjusts the supply voltage provided by the DC-DC converter of at least one respective coupled digital transceiver section to change amplifier bias settings of amplifiers associated with the data transmitting means.

3. 3. The transceiver of claim 1, wherein the processing means adjusts the supply voltage provided by the DC-DC converter of at least one respective coupled digital transceiver section to change the amplifier bias settings of the amplifiers so as to track the modulation envelope of the analog transmit signal transmitted via the antenna.

4. A transceiver as described in any one of claims 1 to 3, further comprising adjusting DC-DC converters for other transceiver units to reduce the effect of a failed digital transceiver unit.

5. Each digital transceiver unit of the plurality of digital transceiver units: further comprising a digital front-end (DFE) section corresponding to each digital transceiver section within the data transmitting means, each respective digital DFE section being configured to apply digital pre-distortion (DPD) parameters to the digital transmission data; the processing means independently adjusts the DPD parameters for each respective digital transceiver section based on the feedback measurements. A transceiver according to any one of claims 1 to 4.

6. Each digital transceiver unit of the plurality of digital transceiver units: further comprising a digital front-end (DFE) section corresponding to each digital transceiver section within the data transmitting means, each respective DFE section being configured to apply digital pre-distortion (DPD) parameters to the digital transmission data; the processing means independently adjusts the DPD parameters for each respective digital transceiver section based on the tracked VSWR. A transceiver according to any one of claims 1 to 4.

7. the one or more feedback means measuring a junction temperature of an amplifier associated with the transmit path circuit; and wherein the processing means adjusts a supply voltage provided by the DC-DC converter of at least one respective associated digital transceiver portion to change an amplifier bias setting of the amplifier based on the measured junction temperature. A transceiver according to any one of claims 1 to 6.

8. 8. The transceiver of claim 1 , wherein the processing means adjusts the supply voltage provided by the DC-DC converter for at least one respective associated digital transceiver section to change the amplifier bias setting such that the analog transmit signal transmitted via the antenna has a magnitude in accordance with a stored codebook value.

9. further comprising a data receiving means coupled to said antenna; said processing means adjusting the supply voltage provided by the DC-DC converter of at least one respective coupled digital transceiver portion to change amplifier bias settings of amplifiers associated with said data receiving means; A transceiver according to any one of claims 1 to 8.

10. each digital transceiver section of the plurality of digital transceiver sections further includes a digital front end (DFE) section separate from the common DFE, the common DFE and the DFE section corresponding to each digital transceiver section being configured to perform different functions relating to a same communications protocol. A transceiver according to any one of claims 1 to 9.

11. each digital transceiver section of the plurality of digital transceiver sections is coupled to a different respective antenna element in a phased antenna array; said processing means adjusts the supply voltages provided by the DC-DC converters of each respective coupled digital transceiver section to effect amplitude tapering across different respective antenna elements of the phased antenna array by independently adjusting bias conditions of amplifiers associated with each respective coupled digital transceiver section. A transceiver according to any one of the preceding claims.

12. A plurality of digital transceiver sections coupled to a common digital front end (DFE), each digital transceiver section of the plurality of digital transceiver sections: operating according to a same communications protocol using data communicated using said common DFE; providing a supply voltage via a respective coupled DC-DC converter; a plurality of digital transceiver sections configured to provide feedback measurements relating to operation of each respective digital transceiver section; and a processor circuit configured to adjust the supply voltage provided by a respective DC-DC converter of each respective digital transceiver section based on the feedback measurement from each respective digital transceiver section; one or more feedback components included in each respective digital transceiver section configured to measure forward and reverse power in a transmit path circuit associated with each respective digital transceiver section; the processor circuitry is configured to (i) track a voltage standing wave ratio (VSWR) using the measured forward and reverse power, and (ii) change amplifier bias settings of amplifiers associated with the transmit path circuitry included in each respective digital transceiver section based on the tracked VSWR. Radio equipment.

13. 13. The wireless device of claim 12, wherein the processor circuitry is configured to adjust the supply voltages provided by each DC-DC converter of each respective digital transceiver section to change amplifier bias settings of amplifiers associated with transmit path circuitry included in each respective digital transceiver section.

14. 14. The wireless device of claim 12 or 13, wherein the processor circuitry is configured to adjust the supply voltage provided by a respective DC-DC converter of each respective digital transceiver section to change amplifier bias settings of amplifiers associated with receive path circuitry included in each respective digital transceiver section.

15. 15. The wireless device of claim 13, wherein the processor circuitry is configured to change the amplifier bias settings of the amplifiers associated with transmit path circuitry included in each respective digital transceiver section to track a modulation envelope of a transmit signal associated with each respective digital transceiver section.

16. A wireless device as described in any one of claims 12 to 15, wherein the processor circuit is configured to adjust DC-DC converters for other transceiver units to reduce the effect of a failed digital transceiver unit.

17. Each digital transceiver unit of the plurality of digital transceiver units: a digital front-end (DFE) section within a transmit path circuit included in each respective digital transceiver section, each respective DFE section configured to apply digital pre-distortion (DPD) parameters to the digital transmit data received from the common DFE; the processor circuitry is configured to adjust the DPD parameters for each respective digital transceiver section independently of one another based on the feedback measurements.

17. Wireless device according to one or more of claims 12 to 16.

18. Each digital transceiver unit of the plurality of digital transceiver units: a digital front-end (DFE) section within a transmit path circuit included in each respective digital transceiver section, each respective DFE section configured to apply digital pre-distortion (DPD) parameters to the digital transmit data received from the common DFE; the processor circuitry is configured to independently adjust the DPD parameters for each respective digital transceiver section based on the tracked VSWR.

17. A radio device according to any one of claims 12 to 16.

19. one or more feedback components included in each respective digital transceiver section are configured to measure a junction temperature of an amplifier associated with a transmit path circuit included in each respective digital transceiver section; the processor circuit is configured to adjust a supply voltage provided by the DC-DC converter for each respective digital transceiver portion to change an amplifier bias setting of the amplifier based on the measured junction temperature.

19. A wireless device according to any one of claims 12 to 18.

20. 20. The wireless device of claim 12, wherein the processor circuitry is configured to independently adjust the supply voltages provided by each DC-DC converter included in each respective digital transceiver section to change amplifier bias settings of amplifiers associated with transmit path circuits included in each respective digital transceiver section such that a transmit signal has a magnitude according to a stored codebook magnitude value.

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