SET-resistant reinforced phase frequency detector

Abstract

The invention belongs to the field of electronic devices, particularly relates to an anti-SET reinforced phase frequency detector, and aims to solve the problems that the existing SET injection can change the output logic state of a PFD (phase frequency detector), and a post-stage circuit obtains a wrong phase difference indication signal. According to the invention, an output UP signal and an output DOWN signal of a first-stage unit are used as the input of an input control logic, and the input control logic outputs four indication signals; the input of the first output control logic is four indication signals, and the output of the first output control logic is a first conduction control signal; the second-stage unit is used for carrying out rising edge sampling on the UP signal and the DOWN signal respectively and outputting two indication signals; the input of the phase selector is a reference clock signal, a feedback clock signal and two indication signals, the output of the phase selector is the input of the second output control logic, and the second output control logic outputs a second conduction control signal. According to the invention, the output logic state is not changed during SET injection, and a correct phase difference indication signal is obtained at a rear stage.

Description

Technical Field

[0001] The invention belongs to the field of electronic devices, and in particular relates to a frequency and phase detector with SET resistance reinforcement. Background Art

[0002] With the rapid development of aerospace and other applications, more and more electronic systems need to work in radiation environments. As a clock generation and synchronization circuit, phase locked loop (PLL) is widely used in electronic systems. PLL exposed to radiation environment will produce phase deviation and frequency deviation under SET events, and in severe cases will cause oscillation termination. SET has become the most important radiation effect threatening PLL. The reliability problem caused by SET effect makes PLL a weak link in the anti-radiation reinforcement of electronic systems. Phase frequency detector (PFD) is an important module in the phase locked loop. PFD obtains the corresponding phase difference relationship by performing phase detection on two clock or data signals. According to the different input signals, it can be divided into two categories, one is PFD used for periodic signal calibration, and the other is PFD based on pseudo-random digital code signal calibration. NAND gate PFD is often used for periodic signal calibration, and the PFD circuit used for pseudo-random digital code calibration is more complex, which is divided into linear phase detector and nonlinear phase detector. Among them, the common linear phase detectors are Hogge phase detectors, and the nonlinear phase detectors are Alexander phase detectors. SET injection will change the output logic state of the PFD, causing the subsequent circuit to obtain an erroneous phase difference indication signal, causing the entire PLL circuit to work abnormally. PFD anti-SET reinforcement is an important design link to improve the PLL's anti-SET capability.

[0003] Therefore, the existing phase frequency detector has the problem that SET injection will change the output logic state of the PFD, causing the subsequent circuit to obtain an erroneous phase difference indication signal, resulting in abnormal operation of the entire PLL circuit. Summary of the invention

[0004] In order to solve the above-mentioned problem in the prior art, that is, the existing phase frequency detector has the problem that SET injection will change the output logic state of the PFD, so that the subsequent circuit obtains an erroneous phase difference indication signal, causing the entire PLL circuit to work abnormally, the present invention provides a phase frequency detector with SET resistance reinforcement, and the phase frequency detector comprises:

[0005] A first-stage PFD unit, an input control logic, a second-stage PFD unit, a first output control logic, a phase selector, and a second output control logic;

[0006] The first-stage PFD unit includes: the input clock signal of the first D flip-flop is the reference clock signal CLK1, and the input clock signal of the second D flip-flop is the feedback clock signal CLK2; the D input terminal of the first D flip-flop and the D input terminal of the second D flip-flop are both connected to VDD; the output UP signal of the first D flip-flop and the output DOWN signal of the second D flip-flop are used as two inputs of the first NAND gate, and the output terminal of the first NAND gate is connected to the RESET terminal of the first D flip-flop and the RESET terminal of the second D flip-flop;

[0007] The output UP signal of the first D flip-flop and the output DOWN signal of the second D flip-flop are used as inputs of the two input ends of the input control logic, and the input control logic outputs four indication signals; the four indication signals output by the input control logic are used as input signals of the four input ends of the first output control logic, and the first output control logic outputs the first conduction control signal CK1; the second-stage PFD unit performs rising edge sampling on the output UP signal of the first D flip-flop and the output DOWN signal of the second D flip-flop, respectively, and outputs two indication signals; the reference clock signal CLK1, the feedback clock signal CLK2 and the two indication signals are used as input signals of the four input ends of the phase selector; the phase selector outputs a high-frequency clock signal CLK_HIGH and a low-frequency clock signal CLK_LOW; the phase selector output is used as the input of the input end of the second output control logic, and the output end of the second output control logic outputs the second conduction control signal CK2.

[0008] In a preferred embodiment, the input control logic includes: two inputs of the first XOR gate are the output UP signal of the first D flip-flop and the output DOWN signal of the second D flip-flop; the output of the first XOR gate is the reference clock of the third D flip-flop and the first latch; the input of the first inverter is the output of the third D flip-flop and the input of the first latch, and the output of the first inverter is used as the input of the third D flip-flop; the output of the first latch is used as the input of the second inverter, the first input of the second NAND gate, and the first input of the third NAND gate; the output UP signal of the first D flip-flop is used as the second input of the second NAND gate, and the output DOWN signal of the second D flip-flop is used as the second input of the third NAND gate; the output of the second inverter is used as the first input of the fourth NAND gate and the first input of the fifth NAND gate; the output UP signal of the first D flip-flop is used as the second input of the fourth NAND gate, and the output DOWN signal of the second D flip-flop is used as the second input of the fifth NAND gate; the second NAND gate outputs the first indication signal UP1, the third NAND gate outputs the first indication signal DOWN1, the fourth NAND gate outputs the second indication signal UP2, and the fifth NAND gate outputs the second indication signal DOWN2.

[0009] In a preferred embodiment, the second-stage PFD unit includes: a fourth D flip-flop, a fifth D flip-flop, a first NOR gate and a second NOR gate;

[0010] The input clock signal of the fourth D flip-flop is the reference clock signal CLK1, the input of the fourth D flip-flop is the output UP signal of the first D flip-flop, and the output UP signal of the first D flip-flop is sampled on the rising edge; the input clock signal of the fifth D flip-flop is the feedback clock signal CLK2, the input of the fifth D flip-flop is the output DOWN signal of the second D flip-flop, and the output DOWN signal of the second D flip-flop is sampled on the rising edge; the input and output of the fourth D flip-flop are the two inputs of the first NOR gate NOR, the input and output of the fifth D flip-flop are the two inputs of the second NOR gate NOR; the first NOR gate outputs a third indication signal UP3, and the second NOR gate outputs a third indication signal DOWN3.

[0011] In a preferred embodiment, the first output control logic includes: a second XOR gate, a third XOR gate, a third NOR gate and a sixth D flip-flop:

[0012] The outputs of the second NAND gate and the third NAND gate are the inputs of the second XOR gate, the outputs of the fourth NAND gate and the fifth NAND gate are the inputs of the third XOR gate, the outputs of the second XOR gate and the third XOR gate are the inputs of the third NOR gate, the outputs of the third NAND gate are the inputs of the sixth D flip-flop, the output D terminal of the sixth D flip-flop is connected to the power supply voltage terminal VDD, and the sixth D flip-flop outputs the first conduction control signal CK1.

[0013] In a preferred embodiment, the phase selector comprises: a second SR latch and a two-way selection unit;

[0014] The two inputs of the second SR latch are the second indication signal UP3 and the second indication signal DOWN3; the Q output end of the second SR latch is connected to the SELECT ends of the two selection units; the two inputs of the two selection units are respectively connected to the reference clock signal CLK1 and the feedback clock signal CLK2, and the two outputs of the two selection units are the high-frequency clock signal CLK_HIGH and the low-frequency clock signal CLK_LOW.

[0015] In a preferred embodiment, the second control logic includes: a seventh D flip-flop, a third inverter, an eighth D flip-flop, a ninth D flip-flop, a tenth D flip-flop, an eleventh D flip-flop, a twelfth D flip-flop, a fourth inverter, a thirteenth D flip-flop, a fourteenth D flip-flop, a fifteenth D flip-flop, a sixteenth D flip-flop, and a four-input OR gate;

[0016] In a preferred embodiment, the clock input of the seventh D flip-flop is the high-frequency clock signal CLK_HIGH output by the two-way selection unit, and the output of the seventh D flip-flop is used as the input of the third inverter, the input of the RESET terminal of the eighth D flip-flop, and the input of the RESET terminal of the ninth D flip-flop; the output of the third inverter is used as the input of the D input terminal of the seventh D flip-flop, the input of the RESET terminal of the tenth D flip-flop, and the input of the RESET terminal of the eleventh D flip-flop; the inputs of the CLK input terminal of the eighth D flip-flop, the CLK input terminal of the ninth D flip-flop, the CLK input terminal of the tenth D flip-flop, and the CLK input terminal of the eleventh D flip-flop are all the output DOWN signal of the second D flip-flop; the D input terminal of the eighth D flip-flop is connected to VDD, and the Q output terminal of the eighth D flip-flop is used as the D input terminal of the ninth D flip-flop; the D input terminal of the tenth D flip-flop is connected to VDD, and the Q output terminal of the tenth D flip-flop is connected to the D input terminal of the eleventh D flip-flop; the Q output terminal of the ninth D flip-flop is connected to the first input terminal of the four-input OR gate, and the Q output terminal of the eleventh D flip-flop is connected to the second input terminal of the four-input OR gate;

[0017] The clock input of the twelfth D flip-flop is the low-frequency clock signal CLK_LOW outputted by the two-way selection unit. The output of the twelfth D flip-flop is used as the input of the fourth inverter, the input of the RESET terminal of the thirteenth D flip-flop, and the input of the RESET terminal of the fourteenth D flip-flop; the output of the fourth inverter is used as the input of the D input terminal of the twelfth D flip-flop, the input of the RESET terminal of the fifteenth D flip-flop, and the input of the RESET terminal of the sixteenth D flip-flop; the CLK input terminal of the thirteenth D flip-flop, the CLK input terminal of the fourteenth D flip-flop, and the CLK input terminal of the fifteenth D flip-flop The inputs of the CLK input terminals of the 13th D flip-flop and the 16th D flip-flop are both the output UP signal of the first D flip-flop; the D input terminal of the 13th D flip-flop is connected to VDD, and the Q output terminal of the 14th D flip-flop serves as the D input terminal of the 15th D flip-flop; the D input terminal of the 15th D flip-flop is connected to VDD, and the Q output terminal of the 15th D flip-flop is connected to the D input terminal of the 16th D flip-flop; the Q output terminal of the 14th D flip-flop is connected to the third input terminal of the four-input OR gate, and the Q output terminal of the 16th D flip-flop is connected to the fourth input terminal of the four-input OR gate; the four-input AND-OR gate outputs a second conduction control signal CK2.

[0018] In a preferred embodiment, the phase frequency detector control CP unit includes:

[0019] The first-stage PFD unit controls the first CP unit CP1 and the second CP unit CP2; the second-stage PFD unit controls the third CP unit CP3;

[0020] The two inputs of the first CP unit are a first indication signal UP1 and a first indication signal DOWN1;

[0021] The two inputs of the second CP unit are a second indication signal UP2 and a second indication signal DOWN2;

[0022] The two inputs of the third CP unit are a third indication signal UP3 and a third indication signal DOWN3;

[0023] The outputs of the first CP unit CP1, the second CP unit CP2, and the third CP unit CP3 are all connected to the control end of the subsequent stage VCO; when the first conduction control signal CK1 is high, the output ends of the first CP unit CP1 and the second CP unit CP2 are all pulled to VDD and disconnected from the VCO control end; when the second conduction control signal CK2 is high, the output ends of the first CP unit CP1, the second CP unit CP2, and the third CP unit CP3 are all pulled to VDD and disconnected from the control end of the subsequent stage VCO.

[0024] In a preferred embodiment, the phase frequency detector control CP unit includes:

[0025] The first-stage PFD unit realizes that only one of the first indication signal UP1, the first indication signal DOWN1 or the second indication signal UP2, the second indication signal DOWN2 is flipped on in each cycle, and the other is turned off; therefore, the first CP unit and the second CP unit controlled by the first-stage phase detector work periodically alternately.

[0026] In a preferred embodiment, the phase frequency detector control CP unit includes:

[0027] When the first indication signal UP1 and the second indication signal UP2 input to the first CP unit and the second CP unit are both high or the first indication DOWN1 and the second indication signal DOWN2 are both high, it means that the two CP units are turned on at the same time. At this time, the CP is disturbed by SET, the CP works abnormally, the first conduction control signal CK1 is turned on, and the output levels of the two CP units are pulled to VD, which are disconnected from the control end of the subsequent VCO.

[0028] In a preferred embodiment, the phase frequency detector control CP unit includes:

[0029] The second output control logic counts the DOWN signal in each high-frequency clock cycle and counts the UP signal in each low-frequency clock cycle. When the signal of the high-frequency clock cycle reaches 2 or the UP signal of the low-frequency clock cycle reaches 2, it is considered that SET interference has occurred. At this time, the second conduction control CK2 signal is pulled high, and the outputs of the first CP unit CP1, the second CP unit CP2, and the third CP unit CP3 are pulled to VDD and disconnected from the control end of the subsequent VCO.

[0030] Beneficial effects of the present invention:

[0031] (1) The anti-SET reinforced phase frequency detector provided by the present invention realizes that when there is a large phase difference and frequency difference between the reference clock frequency CLK1 and the feedback clock frequency CLK2, the second-stage PFD unit instructs CP3 to output a wide pulse control signal, thereby realizing rapid capture of the VCO output frequency.

[0032] (2) When the phase frequency detector of the present invention is used, the output logic state of the PFD is not changed when the SET is injected, so that the subsequent circuit obtains the correct phase difference indication signal, and the working state of the entire PLL circuit is stable;

[0033] (3) Based on the phase frequency detector of the present invention, when the phase difference is small, the first-stage PFD unit instructs CP1 and CP2 to work alternately to achieve phase tracking. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] Other features, objects and advantages of the present application will become more apparent by reading the detailed description of non-limiting embodiments made with reference to the following drawings:

[0035] Figure 1 1 is a circuit structure diagram of a frequency and phase detector reinforced against SET according to an embodiment of the present application;

[0036] Figure 2 is a circuit diagram of the input control logic and the first output control logic of an embodiment of the present application;

[0037] Figure 3 is a circuit structure diagram of a phase selector according to an embodiment of the present application;

[0038] Figure 4 is a circuit structure diagram of the second output control logic of an embodiment of the present application;

[0039] Figure 5 It is an output simulation diagram of the first indication signal UP1, the first indication signal DOWN1, the second indication signal UP2, and the second indication signal DOWN2 outputted in the embodiment of the present application;

[0040] Figure 6 is an output simulation diagram of the third indication signal UP3 and the third indication signal DOWN3 outputted in the embodiment of the present application;

[0041] Figure 7 is a simulation diagram of the first output control logic under SET injection interference;

[0042] Figure 8 It is a simulation diagram of the second output control logic under SET injection interference. DETAILED DESCRIPTION

[0043] The present application will be further described in detail below in conjunction with the accompanying drawings and embodiments. It is to be understood that the specific embodiments described herein are only used to explain the relevant invention, rather than to limit the invention. It is also necessary to explain that, for ease of description, only the parts related to the relevant invention are shown in the accompanying drawings.

[0044] It should be noted that, in the absence of conflict, the embodiments and features in the embodiments of the present application can be combined with each other. The present application will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0045] The present invention provides a phase frequency detector with SET resistance reinforcement, characterized in that the phase frequency detector comprises:

[0046] A first-stage PFD unit, an input control logic, a second-stage PFD unit, a first output control logic, a phase selector, and a second output control logic;

[0047] The first-stage PFD unit includes: the input clock signal of the first D flip-flop 101 is the reference clock signal CLK1, and the input clock signal of the second D flip-flop 102 is the feedback clock signal CLK2; the D input terminal of the first D flip-flop 101 and the D input terminal of the second D flip-flop 102 are both connected to VDD; the output UP signal of the first D flip-flop 101 and the output DOWN signal of the second D flip-flop 102 are used as two inputs of the first NAND gate 103, and the output terminal of the first NAND gate 103 is connected to the RESET terminal of the first D flip-flop 101 and the RESET terminal of the second D flip-flop 102;

[0048] The output UP signal of the first D flip-flop 101 and the output DOWN signal of the second D flip-flop 102 are used as inputs of the two input ends of the input control logic, and the input control logic outputs four indication signals; the four indication signals output by the input control logic are used as input signals of the four input ends of the first output control logic, and the first output control logic outputs the first conduction control signal CK1; the second-stage PFD unit performs rising edge sampling on the output UP signal of the first D flip-flop 101 and the output DOWN signal of the second D flip-flop 102, respectively, and outputs two indication signals; the reference clock signal CLK1, the feedback clock signal CLK2 and the two indication signals are used as input signals of the four input ends of the phase selector; the phase selector outputs a high-frequency clock signal CLK_HIGH and a low-frequency clock signal CLK_LOW; the phase selector output is used as the input of the input end of the second output control logic, and the output end of the second output control logic outputs the second conduction control signal CK2.

[0049] In order to more clearly explain the frequency and phase detector of the present invention with anti-SET reinforcement, Figure 1Each part in the embodiment of the present invention is described in detail.

[0050] The various parts of the frequency and phase detector reinforced against SET according to the first embodiment of the present invention are described in detail as follows:

[0051] A first-stage PFD unit, an input control logic, a second-stage PFD unit, a first output control logic, a phase selector, and a second output control logic;

[0052] The first-stage PFD unit includes: the input clock signal of the first D flip-flop 101 is the reference clock signal CLK1, and the input clock signal of the second D flip-flop 102 is the feedback clock signal CLK2; the D input terminal of the first D flip-flop 101 and the D input terminal of the second D flip-flop 102 are both connected to VDD; the output UP signal of the first D flip-flop 101 and the output DOWN signal of the second D flip-flop 102 are used as two inputs of the first NAND gate, and the output terminal of the first NAND gate is connected to the RESET terminal of the first D flip-flop 101 and the RESET terminal of the second D flip-flop 102;

[0053] The output UP signal of the first D flip-flop 101 and the output DOWN signal of the second D flip-flop 102 are used as inputs of the two input ends of the input control logic, and the input control logic outputs four indication signals; the four indication signals output by the input control logic are used as input signals of the four input ends of the first output control logic, and the first output control logic outputs the first conduction control signal CK1; the second-stage PFD unit performs rising edge sampling on the output UP signal of the first D flip-flop 101 and the output DOWN signal of the second D flip-flop 102, respectively, and outputs two indication signals; the reference clock signal CLK1, the feedback clock signal CLK2 and the two indication signals are used as input signals of the four input ends of the phase selector; the phase selector outputs a high-frequency clock signal CLK_HIGH and a low-frequency clock signal CLK_LOW; the phase selector output is used as the input of the input end of the second output control logic, and the output end of the second output control logic outputs the second conduction control signal CK2.

[0054] like Figure 2As shown, in this embodiment, the input control logic includes: the two inputs of the first XOR gate 112 are the output UP signal of the first D flip-flop 101 and the output DOWN signal of the second D flip-flop 102; the output of the first XOR gate 112 is the reference clock of the third D flip-flop 113 and the first latch 115; the input of the first inverter 114 is the output of the third D flip-flop 113 and the input 115 of the first latch, and the output of the first inverter 114 is used as the input of the third D flip-flop 113; the output of the first latch 115 is used as the input of the second inverter 116, the first input of the second NAND gate 117, and the first input of the third NAND gate 118; the output UP signal of the first D flip-flop 101 is used as the reference clock of the third D flip-flop 113 and the first latch 115; The second input of the second NAND gate 117, the output DOWN signal of the second D flip-flop 102 is used as the second input of the third NAND gate 117; the output of the second inverter 116 is used as the first input of the fourth NAND gate 119 and the first input of the fifth NAND gate 120; the output UP signal of the first D flip-flop 101 is used as the second input of the fourth NAND gate 119, and the output DOWN signal of the second D flip-flop 102 is used as the second input of the fifth NAND gate 120; the second NAND gate 117 outputs the first indication signal UP1, the third NAND gate 118 outputs the first indication signal DOWN1, the fourth NAND gate 119 outputs the second indication signal UP2, and the fifth NAND gate 120 outputs the second indication signal DOWN2.

[0055] In this embodiment, if Figure 1 As shown, the second-stage PFD unit includes: a fourth D flip-flop 104, a fifth D flip-flop 105, a first NOR gate 106 and a second NOR gate 107; the input clock signal of the fourth D flip-flop 104 is the reference clock signal CLK1, the input of the fourth D flip-flop 104 is the output UP signal of the first D flip-flop 101, and the output UP signal of the first D flip-flop 101 is sampled at a rising edge; the input clock signal of the fifth D flip-flop 105 is the feedback clock signal CLK2, the input of the fifth D flip-flop 105 is the output DOWN signal of the second D flip-flop 102, and the output DOWN signal of the second D flip-flop 102 is sampled at a rising edge; the input and output of the fourth D flip-flop 104 are two inputs of the first NOR gate NOR106, the input and output of the fifth D flip-flop 105 are two inputs of the second NOR gate NOR107; the first NOR gate 106 outputs a third indication signal UP3, and the second NOR gate 107 outputs a third indication signal DOWN3.

[0056] In this embodiment, the first output control logic includes: a second XOR gate 121, a third XOR gate 122, a third NOR gate 123 and a sixth D flip-flop 124;

[0057] The outputs of the second NAND gate 117 and the third NAND gate 118 are the inputs of the second XOR gate 121, the outputs of the fourth NAND gate 119 and the fifth NAND gate 120 are the inputs of the third XOR gate 122, the outputs of the second XOR gate 121 and the third XOR gate 122 are the inputs of the third NOR gate 123, the output of the third NOR gate 124 is the input of the sixth D flip-flop 124, the output D terminal of the sixth D flip-flop 124 is connected to the power supply voltage terminal VDD, and the sixth D flip-flop 124 outputs the first conduction control signal CK1.

[0058] In this embodiment, if Figure 3 As shown, the phase selector includes: a second SR latch and a two-way selection unit;

[0059] The two inputs of the second SR latch 125 are the second indication signal UP3 and the second indication signal DOWN3; the Q output end of the second SR latch 125 is connected to the SELECT end of the two-way selection unit; the two inputs of the two-way selection unit 126 are respectively connected to the reference clock signal CLK1 and the feedback clock signal CLK2, and the two outputs of the two-way selection unit 126 are the high-frequency clock signal CLK_HIGH and the low-frequency clock signal CLK_LOW.

[0060] In this embodiment, if Figure 4 As shown, the second control logic includes: a seventh D flip-flop 127, a third inverter 128, an eighth D flip-flop 131, a ninth D flip-flop 132, a tenth D flip-flop 128, an eleventh D flip-flop 129, a twelfth D flip-flop 133, a fourth inverter 134, a thirteenth D flip-flop 137, a fourteenth D flip-flop 138, a fifteenth D flip-flop 135, a sixteenth D flip-flop 136, and a four-input OR gate 139;

[0061] The clock input of the seventh D flip-flop 127 is the high-frequency clock signal CLK_HIGH outputted by the two-way selection unit 126. The output of the seventh D flip-flop 127 is used as the input of the third inverter 128, the input of the RESET terminal of the eighth D flip-flop 131, and the input of the RESET terminal of the ninth D flip-flop 132; the output of the third inverter 128 is used as the input of the seventh D flip-flop D127 input terminal, the input of the RESET terminal of the tenth D flip-flop 129, and the input of the RESET terminal of the eleventh D flip-flop 130; the CLK input terminal of the eighth D flip-flop 131, the CLK input terminal of the ninth D flip-flop 132, and the tenth D flip-flop The inputs of the CLK input terminal of 129 and the CLK input terminal of the eleventh D flip-flop 130 are both the output DOWN signal of the second D flip-flop 102; the D input terminal of the eighth D flip-flop 131 is connected to VDD, and the Q output terminal of the eighth D flip-flop 131 is used as the D input terminal of the ninth D flip-flop 132; the D input terminal of the tenth D flip-flop 129 is connected to VDD, and the Q output terminal of the tenth D flip-flop 129 is connected to the D input terminal of the eleventh D flip-flop 130; the Q output terminal of the ninth D flip-flop 132 is connected to the first input terminal of the four-input OR gate 139, and the Q output terminal of the eleventh D flip-flop 130 is connected to the second input terminal of the four-input OR gate 139;

[0062] The clock input of the twelfth D flip-flop 133 is the low-frequency clock signal CLK_LOW outputted by the two-way selection unit. The output of the twelfth D flip-flop 133 is used as the input of the fourth inverter 134, the input of the RESET terminal of the thirteenth D flip-flop 137, and the input of the RESET terminal of the fourteenth D flip-flop 138; the output of the fourth inverter 134 is used as the input of the D input terminal of the twelfth D flip-flop 133, the input of the RESET terminal of the fifteenth D flip-flop 135, and the input of the RESET terminal of the sixteenth D flip-flop 136; the CLK input terminal of the thirteenth D flip-flop 137, the CLK input terminal of the fourteenth D flip-flop 138, and the CLK input terminal of the fifteenth D flip-flop 135 are used as the input of the D input terminal of the twelfth D flip-flop 133, the input of the RESET terminal of the fifteenth D flip-flop 135, and the input of the RESET terminal of the sixteenth D flip-flop 136. The inputs of the CLK input terminals of the thirteenth D flip-flop 137 and the sixteenth D flip-flop 136 are both the output UP signal of the first D flip-flop 101; the D input terminal of the thirteenth D flip-flop 137 is connected to VDD, and the Q output terminal of the fourteenth D flip-flop 138 serves as the D input terminal of the fifteenth D flip-flop 135; the D input terminal of the fifteenth D flip-flop 135 is connected to VDD, and the Q output terminal of the fifteenth D flip-flop 135 is connected to the D input terminal of the sixteenth D flip-flop 136; the Q output terminal of the fourteenth D flip-flop 138 is connected to the third input terminal of the four-input OR gate 139, and the Q output terminal of the sixteenth D flip-flop 136 is connected to the fourth input terminal of the four-input OR gate 139; the four-input AND-OR gate 139 outputs a second conduction control signal CK2.

[0063] The phase frequency detector control CP unit includes:

[0064] The first-stage PFD unit controls the first CP unit CP1 and the second CP unit CP2; the second-stage PFD unit controls the third CP unit CP3;

[0065] The two inputs of the first CP unit are a first indication signal UP1 and a first indication signal DOWN1;

[0066] The two inputs of the second CP unit are a second indication signal UP2 and a second indication signal DOWN2;

[0067] The two inputs of the third CP unit are a third indication signal UP3 and a third indication signal DOWN3;

[0068] The outputs of the first CP unit CP1, the second CP unit CP2, and the third CP unit CP3 are all connected to the control end of the subsequent stage VCO; when the first conduction control signal CK1 is high, the output ends of the first CP unit CP1 and the second CP unit CP2 are all pulled to VDD and disconnected from the VCO control end; when the second conduction control signal CK2 is high, the output ends of the first CP unit CP1, the second CP unit CP2, and the third CP unit CP3 are all pulled to VDD and disconnected from the control end of the subsequent stage VCO.

[0069] In this embodiment, the phase frequency detector control CP unit includes:

[0070] The first-stage PFD unit realizes that only one of the first indication signal UP1, the first indication signal DOWN1 or the second indication signal UP2, the second indication signal DOWN2 is flipped on in each cycle, and the other is turned off; therefore, the first CP unit and the second CP unit controlled by the first-stage phase detector work periodically alternately.

[0071] When the first indication signal UP1 and the second indication signal UP2 input to the first CP unit and the second CP unit are both high or the first indication DOWN1 and the second indication signal DOWN2 are both high, it means that the two CP units are turned on at the same time. At this time, the CP is disturbed by SET, the CP works abnormally, the first conduction control signal CK1 is turned on, and the output levels of the two CP units are pulled to VDD, which are disconnected from the control end of the subsequent VCO.

[0072] The second output control logic counts the DOWN signal in each high-frequency clock cycle and counts the UP signal in each low-frequency clock cycle. When the signal of the high-frequency clock cycle reaches 2 or the UP signal of the low-frequency clock cycle reaches 2, it is considered that SET interference has occurred. At this time, the second conduction control CK2 signal is pulled high, and the outputs of the first CP unit CP1, the second CP unit CP2, and the third CP unit CP3 are pulled to VDD and disconnected from the control end of the subsequent VCO.

[0073] Figure 5 This is the output simulation diagram of the first-stage PFD unit of the present invention. The phase of the reference clock signal CLK1 is ahead of the phase of the feedback clock signal CLK2. The intermediate logic outputs a DOWN pulse signal. After the input control logic, the first indication signal DOWN1 and the second indication signal DOWN2 pulse indication signals are output alternately. The subsequent first CP unit CP1 and the subsequent second CP unit CP2 work alternately.

[0074] Figure 6 The output simulation diagram of the second-stage frequency and phase detector unit of the present invention is shown in FIG. The phase of the reference clock signal CLK1 is ahead of the phase of the feedback clock signal CLK2, the third indication signal DOWN3 is a high pulse indication signal, and the third indication signal UP3 is low.

[0075] The present invention adopts the SET reinforcement method of the first output control logic to act on the first-level PFD unit. Figure 7 The figure shows the simulation diagram of the first output control logic. At 35ns, a SET interference signal with an energy value of 60MeV is injected into the path of the first indication signal DOWN1. At this time, the first indication signal DOWN1 and the second indication signal DOWN2 are both high. The first output control logic outputs a high pulse turn-on control signal at CK1. The high pulse indication signal CK1 is set to 0 after the DOWN2 pulse ends, and the subsequent CP1 and CP2 circuits resume working.

[0076] The present invention adopts a SET reinforcement method controlled by a second output logic to act on the first-stage and second-stage PFD units. Figure 8 The figure shows the simulation diagram of the second output control logic. At 55ns, a SET interference signal with an energy value of 60MeV is injected into the DOWN signal path. Then, two DOWN pulse indication signals appear in the counting cycle, and the CK2 indication signal output is high. The output levels of the first CP unit CP1, the second CP unit CP2, and the third CP unit CP3 are pulled up and disconnected from the control end of the subsequent VCO. The conduction indication signal CK2 is reset to 0 after the counting cycle ends, and the circuit resumes normal operation.

[0077] The terms "first", "second", etc. are used to distinguish similar objects rather than to describe or indicate a particular order or sequence.

[0078] The term "comprise" or any other similar term is intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus / device that includes a list of elements includes not only those elements but also other elements not expressly listed, or also includes elements inherent to such process, method, article, or apparatus / device.

[0079] So far, the technical solutions of the present invention have been described in conjunction with the preferred embodiments shown in the accompanying drawings. However, it is easy for those skilled in the art to understand that the protection scope of the present invention is obviously not limited to these specific embodiments. Without departing from the principle of the present invention, those skilled in the art can make equivalent changes or substitutions to the relevant technical features, and the technical solutions after these changes or substitutions will fall within the protection scope of the present invention.

Claims

1. A phase frequency detector reinforced against SET, characterized in that: The phase frequency detector comprises: A first-stage PFD unit, an input control logic, a second-stage PFD unit, a first output control logic, a phase selector, and a second output control logic; The first-stage PFD unit includes: the input clock signal of the first D flip-flop is the reference clock signal CLK1, and the input clock signal of the second D flip-flop is the feedback clock signal CLK2; the D input terminal of the first D flip-flop and the D input terminal of the second D flip-flop are both connected to VDD; the output UP signal of the first D flip-flop and the output DOWN signal of the second D flip-flop are used as two inputs of the first NAND gate, and the output terminal of the first NAND gate is connected to the RESET terminal of the first D flip-flop and the RESET terminal of the second D flip-flop; The output UP signal of the first D flip-flop and the output DOWN signal of the second D flip-flop are used as inputs of the two input ends of the input control logic, and the input control logic outputs four indication signals; the four indication signals output by the input control logic are used as input signals of the four input ends of the first output control logic, and the first output control logic outputs the first conduction control signal CK1; the second-stage PFD unit performs rising edge sampling on the output UP signal of the first D flip-flop and the output DOWN signal of the second D flip-flop, respectively, and outputs two indication signals; the reference clock signal CLK1, the feedback clock signal CLK2 and the two indication signals are used as input signals of the four input ends of the phase selector; the phase selector outputs a high-frequency clock signal CLK_HIGH and a low-frequency clock signal CLK_LOW; the phase selector output is used as the input of the input end of the second output control logic, and the output end of the second output control logic outputs the second conduction control signal CK2.

2. The SET-resistant phase frequency detector according to claim 1, characterized in that: The input control logic includes: The two inputs of the first XOR gate are the output UP signal of the first D flip-flop and the output DOWN signal of the second D flip-flop; the output of the first XOR gate is the reference clock of the third D flip-flop and the first latch; the input of the first inverter is the output of the third D flip-flop and the input of the first latch, and the output of the first inverter is used as the input of the third D flip-flop; the output of the first latch is used as the input of the second inverter, the first input of the second NAND gate, and the first input of the third NAND gate; the output UP signal of the first D flip-flop is used as the second input of the second NAND gate, and the output DOWN signal of the second D flip-flop is used as the second input of the third NAND gate; the output of the second inverter is used as the first input of the fourth NAND gate and the first input of the fifth NAND gate; the output UP signal of the first D flip-flop is used as the second input of the fourth NAND gate, and the output DOWN signal of the second D flip-flop is used as the second input of the fifth NAND gate; the second NAND gate outputs the first indication signal UP1, the third NAND gate outputs the first indication signal DOWN1, the fourth NAND gate outputs the second indication signal UP2, and the fifth NAND gate outputs the second indication signal DOWN2.

3. The SET-resistant phase frequency detector according to claim 2, characterized in that: The second-stage PFD unit includes: a fourth D flip-flop, a fifth D flip-flop, a first NOR gate and a second NOR gate; The input clock signal of the fourth D flip-flop is the reference clock signal CLK1, the input of the fourth D flip-flop is the output UP signal of the first D flip-flop, and the output UP signal of the first D flip-flop is sampled on the rising edge; the input clock signal of the fifth D flip-flop is the feedback clock signal CLK2, the input of the fifth D flip-flop is the output DOWN signal of the second D flip-flop, and the output DOWN signal of the second D flip-flop is sampled on the rising edge; the input and output of the fourth D flip-flop are the two inputs of the first NOR gate NOR, the input and output of the fifth D flip-flop are the two inputs of the second NOR gate NOR; the first NOR gate outputs a third indication signal UP3, and the second NOR gate outputs a third indication signal DOWN3.

4. The SET-resistant phase frequency detector according to claim 3, characterized in that: The first output control logic includes: a second XOR gate, a third XOR gate, a third NOR gate and a sixth D flip-flop: The outputs of the second NAND gate and the third NAND gate are the inputs of the second XOR gate, the outputs of the fourth NAND gate and the fifth NAND gate are the inputs of the third XOR gate, the outputs of the second XOR gate and the third XOR gate are the inputs of the third NOR gate, the outputs of the third NAND gate are the inputs of the sixth D flip-flop, the output D terminal of the sixth D flip-flop is connected to the power supply voltage terminal VDD, and the sixth D flip-flop outputs the first conduction control signal CK1.

5. The SET-resistant phase frequency detector according to claim 4, characterized in that: The phase selector comprises: a second SR latch and a two-way selection unit; The two inputs of the second SR latch are the second indication signal UP3 and the second indication signal DOWN3; the Q output end of the second SR latch is connected to the SELECT ends of the two selection units; the two inputs of the two selection units are respectively connected to the reference clock signal CLK1 and the feedback clock signal CLK2, and the two outputs of the two selection units are the high-frequency clock signal CLK_HIGH and the low-frequency clock signal CLK_LOW.

6. The SET-resistant phase frequency detector according to claim 5, characterized in that: The second control logic includes: a seventh D flip-flop, a third inverter, an eighth D flip-flop, a ninth D flip-flop, a tenth D flip-flop, an eleventh D flip-flop, a twelfth D flip-flop, a fourth inverter, a thirteenth D flip-flop, a fourteenth D flip-flop, a fifteenth D flip-flop, a sixteenth D flip-flop, and a four-input OR gate; The clock input of the seventh D flip-flop is the high-frequency clock signal CLK_HIGH outputted by the two-way selection unit, and the output of the seventh D flip-flop is used as the input of the third inverter, the input of the RESET terminal of the eighth D flip-flop, and the input of the RESET terminal of the ninth D flip-flop; the output of the third inverter is used as the input of the D input terminal of the seventh D flip-flop, the input of the RESET terminal of the tenth D flip-flop, and the input of the RESET terminal of the eleventh D flip-flop; the inputs of the CLK input terminals of the eighth D flip-flop, the ninth D flip-flop, the tenth D flip-flop, and the eleventh D flip-flop are all the output DOWN signal of the second D flip-flop; the D input terminal of the eighth D flip-flop is connected to VDD, and the Q output terminal of the eighth D flip-flop is used as the D input terminal of the ninth D flip-flop; the D input terminal of the tenth D flip-flop is connected to VDD, and the Q output terminal of the tenth D flip-flop is connected to the D input terminal of the eleventh D flip-flop; the Q output terminal of the ninth D flip-flop is connected to the first input terminal of the four-input OR gate, and the Q output terminal of the eleventh D flip-flop is connected to the second input terminal of the four-input OR gate; The clock input of the twelfth D flip-flop is the low-frequency clock signal CLK_LOW outputted by the two-way selection unit. The output of the twelfth D flip-flop is used as the input of the fourth inverter, the input of the RESET terminal of the thirteenth D flip-flop, and the input of the RESET terminal of the fourteenth D flip-flop; the output of the fourth inverter is used as the input of the D input terminal of the twelfth D flip-flop, the input of the RESET terminal of the fifteenth D flip-flop, and the input of the RESET terminal of the sixteenth D flip-flop; the CLK input terminal of the thirteenth D flip-flop, the CLK input terminal of the fourteenth D flip-flop, and the CLK input terminal of the fifteenth D flip-flop The inputs of the CLK input terminals of the 13th D flip-flop and the 16th D flip-flop are both the output UP signal of the first D flip-flop; the D input terminal of the 13th D flip-flop is connected to VDD, and the Q output terminal of the 14th D flip-flop serves as the D input terminal of the 15th D flip-flop; the D input terminal of the 15th D flip-flop is connected to VDD, and the Q output terminal of the 15th D flip-flop is connected to the D input terminal of the 16th D flip-flop; the Q output terminal of the 14th D flip-flop is connected to the third input terminal of the four-input OR gate, and the Q output terminal of the 16th D flip-flop is connected to the fourth input terminal of the four-input OR gate; the four-input AND-OR gate outputs a second conduction control signal CK2.

7. The SET-resistant phase frequency detector according to claim 5, characterized in that: The phase frequency detector control CP unit comprises: The first-stage PFD unit controls the first CP unit CP1 and the second CP unit CP2, and the second-stage PFD unit controls the third CP unit CP3; The two inputs of the first CP unit are a first indication signal UP1 and a first indication signal DOWN1; The two inputs of the second CP unit are a second indication signal UP2 and a second indication signal DOWN2; The two inputs of the third CP unit are a third indication signal UP3 and a third indication signal DOWN3; The outputs of the first CP unit CP1, the second CP unit CP2, and the third CP unit CP3 are all connected to the control end of the subsequent stage VCO; when the first conduction control signal CK1 is high, the output ends of the first CP unit CP1 and the second CP unit CP2 are all pulled to VDD and disconnected from the VCO control end; when the second conduction control signal CK2 is high, the output ends of the first CP unit CP1, the second CP unit CP2, and the third CP unit CP3 are all pulled to VDD and disconnected from the control end of the subsequent stage VCO.

8. The SET-resistant phase frequency detector according to claim 7, characterized in that: The phase frequency detector control CP unit comprises: The first-stage PFD unit realizes that only one of the first indication signal UP1, the first indication signal DOWN1 or the second indication signal UP2, the second indication signal DOWN2 is flipped on in each cycle, and the other is turned off; therefore, the first CP unit and the second CP unit controlled by the first-stage phase detector work periodically and alternately.

9. The SET-resistant phase frequency detector according to claim 8, characterized in that: The phase frequency detector control CP unit comprises: When the first indication signal UP1 and the second indication signal UP2 input to the first CP unit and the second CP unit are both high or the first indication DOWN1 and the second indication signal DOWN2 are both high, it means that the two CP units are turned on at the same time. At this time, the CP is disturbed by SET, the CP works abnormally, the first conduction control signal CK1 is turned on, and the output levels of the two CP units CP1 and CP2 are pulled to VDD and disconnected from the control end of the subsequent VCO.

10. The SET-resistant phase frequency detector according to claim 9, characterized in that: The phase frequency detector control CP unit comprises: The second output control logic counts the DOWN signal in each high-frequency clock cycle and counts the UP signal in each low-frequency clock cycle. When the signal of the high-frequency clock cycle reaches 2 or the UP signal of the low-frequency clock cycle reaches 2, it is considered that SET interference has occurred. At this time, the second conduction control CK2 signal is pulled high, and the outputs of the first CP unit CP1, the second CP unit CP2, and the third CP unit CP3 are pulled to VDD and disconnected from the control end of the subsequent VCO.

Images