POWER CONVERSION DEVICE AND METHOD FOR CONTROLLING POWER CONVERSION DEVICE

Abstract

In the present invention, using a hysteresis width (BW) and a current command value (ia*) that have been set in accordance with a target value (ftrg) of a switching frequency, adders (52, 54) output an upper limit value (Iup) and lower limit value (Ilw) of a hysteresis band. A hysteresis comparator (60) outputs the results of comparing a reactor current (ia) with the upper limit value (Iupc) and lower limit value (Ilwc) after dead-time compensation by dead-time compensation units (72, 74). A dead time generator (70) generates gate signals (S1a, S1b) of a switching element such that dead time is given on the basis of an output signal of the hysteresis comparator (60). Depending on whether the reactor current (ia) is positive or negative, the dead-time compensation units (72, 74) add compensation amounts of different polarities, to either the upper limit value (Iup) or the lower limit value (Ilw) which differ.

Description

[Technical field]

[0001] The present disclosure relates to a power conversion device and a control method for the power conversion device. [Background technology]

[0002] As one technique for power conversion devices, hysteresis control is known in which a semiconductor switching element (hereinafter also simply referred to as a "switching element") is turned on and off in response to a comparison between a current or voltage to be controlled and a threshold value.

[0003] For example, Japanese Patent Laid-Open Publication No. 2005-341712 (Patent Document 1) describes a current hysteresis control that determines the on / off timing of a switching element by comparing either a first or second threshold value with a signal according to an inductor current. In the current hysteresis control of Patent Document 1, the first and second threshold values ​​are set to have a center value based on the output voltage and a width according to a target value of the switching frequency. Furthermore, the document describes a control that sets the switching frequency to a target value by changing the width of a hysteresis band corresponding to the difference between the first and second threshold values ​​according to the output voltage. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] JP 2005-341712 A Summary of the Invention [Problem to be solved by the invention]

[0005] The hysteresis control of Patent Document 1 is a single switching elementOn the other hand, in a power conversion device having a plurality of switching elements that are connected in series between two electric wires and constitute a so-called leg, when two semiconductor switching elements that constitute the same leg are alternately turned on and off, a period during which both are turned off, called a dead time, is generally provided.

[0006] In a power semiconductor device having a leg, there is a concern that the dead time period may affect the circuit behavior, and therefore, if the current hysteresis control described in Patent Document 1 is simply applied, there is a concern that it may become difficult to control the switching frequency to a target value.

[0007] The present disclosure has been made to solve such problems, and an object of the present disclosure is to provide hysteresis control of a power conversion device that is capable of stably controlling a switching frequency to a target value even when a dead time is provided. [Means for solving the problem]

[0008] According to an aspect of the present disclosure, there is provided a power conversion device. The power conversion device includes a power conversion circuit and a control circuit. The power conversion circuit has first and second switching elements connected in series between first and second electric wires. The control circuit controls the on / off of the first and second switching elements by hysteresis control based on a comparison between a detection value of an amount of electricity handled in power conversion by the power conversion circuit and an upper limit value and a lower limit value of a hysteresis band including a command value of the amount of electricity. The on / off of the first and second switching elements is controlled so that a dead time is provided during which both the first and second switching elements are turned off when the switching between on and off is switched on. The control circuit includes a hysteresis band generating unit, an upper and lower limit value setting unit, a dead time compensating unit, a hysteresis comparator, and a dead time generator. The upper and lower limit value setting unit sets the upper limit value and the lower limit value according to the hysteresis band width and the command value. The dead time compensation unit adds a compensation amount to the upper limit and lower limit set by the upper / lower limit setting unit to prevent the detection value from going outside the hysteresis band during the dead time. The hysteresis comparator compares the upper limit and lower limit values ​​processed by the dead time compensation unit with the detection value. The dead time generator generates control signals for turning on and off the first and second switching elements based on the output signal of the hysteresis comparator so that the dead time is provided. The dead time compensation unit executes a process of adding a compensation amount of a different polarity to one of the upper limit and lower limit values ​​that differs between when the detection value is positive and when it is negative.

[0009] According to another aspect of the present disclosure, there is provided a method for controlling a power conversion device. The power conversion device includes a power conversion circuit having first and second switching elements connected in series between first and second electric wires, and the first and second switching elements are controlled to be turned on and off such that a dead time is provided during which both the first and second switching elements are turned off when the first and second switching elements are switched on and off. The control method includes a step of controlling the on and off of the first and second switching elements by hysteresis control based on a comparison between a detection value of an amount of electricity handled in power conversion by the power conversion circuit and an upper limit value and a lower limit value of a hysteresis band including a command value of the amount of electricity. The controlling step includes the steps of: generating a hysteresis band width in the hysteresis control according to target values ​​of the switching frequencies of the first and second switching elements; setting an upper limit value and a lower limit value according to the hysteresis band width and a command value; executing dead-time compensation for adding a compensation amount to the set upper limit value and lower limit value to prevent the detection value from going out of the hysteresis band during the dead time; operating a hysteresis comparator to compare the upper limit value and lower limit value after the dead-time compensation with the detection value; and generating an on / off control signal for the first and second switching elements so that the dead time is provided based on an output signal of the hysteresis comparator. In the dead-time compensation, a compensation amount of a different polarity is added to one of the upper limit value and the lower limit value, which is different when the detection value is positive and when it is negative. Effect of the Invention

[0010] According to the present disclosure, by selectively adding a positive or negative compensation amount to one of the upper and lower limit values ​​of the hysteresis band set in accordance with the target value of the switching frequency depending on the polarity of the detection value to be controlled, it is possible to prevent the detection value from going outside the hysteresis band due to changes in the detection value during the dead time period, thereby realizing hysteresis control that can eliminate the effects of the dead time and stably control the switching frequency to the target value. [Brief description of the drawings]

[0011] [Figure 1] 1 is a schematic configuration diagram of a power conversion device according to a first embodiment. [Diagram 2] FIG. 4 is a functional block diagram illustrating hysteresis control according to a comparative example. [Diagram 3] 3 is an example of a waveform diagram of a reactor current under the hysteresis control of FIG. 2. [Figure 4] FIG. 11 is a functional block diagram illustrating hysteresis control having a function of providing a dead time. [Diagram 5] 5 is a signal waveform diagram for explaining the operation of the dead time generator shown in FIG. 4. [Figure 6] FIG. 11 is a waveform diagram of a reactor current for explaining the influence of a dead time on hysteresis control. [Figure 7] FIG. 2 is a functional block diagram illustrating hysteresis control according to the first embodiment. [Figure 8] 4 is a first example of a control waveform of a reactor current for illustrating hysteresis control according to the first embodiment. [Figure 9] 6 is a second control waveform example of a reactor current for illustrating hysteresis control according to the first embodiment. [Figure 10] 4 is a flowchart illustrating a process for setting upper and lower limit values ​​of hysteresis control according to the first embodiment. [Figure 11] FIG. 11 is a functional block diagram illustrating hysteresis control according to a modification of the first embodiment. [Figure 12] 6 is a flowchart illustrating a process of hysteresis control according to a modification of the first embodiment. [Figure 13] FIG. 11 is a schematic configuration diagram of a power conversion device according to a second embodiment. [Figure 14] FIG. 11 is a functional block diagram illustrating hysteresis control according to a second embodiment. [Figure 15] 15 is a functional block diagram illustrating a configuration example of a neutral point voltage calculation unit shown in FIG. 14. [Figure 16]16 is a conceptual waveform diagram for explaining the operation of a leg voltage calculation unit shown in FIG. 15. [Figure 17] 10 is a flowchart illustrating a current comparison process of hysteresis control according to the second embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0012] Hereinafter, the embodiments of the present disclosure will be described in detail with reference to the drawings. In the following, the same or corresponding parts in the drawings will be denoted by the same reference numerals, and the description thereof will not be repeated in principle. In addition, the configurations of the embodiments described below are not limited to being applied independently, and can be applied in combination with the configurations of other embodiments as long as no contradiction occurs.

[0013] Embodiment 1 (Circuit configuration example) First, a configuration example of the power conversion device according to the first embodiment will be described.

[0014] Fig. 1 shows a schematic configuration diagram of a power conversion device 100 according to the first embodiment. The power conversion device 100 is connected between a DC power source 10 and an AC power source 20, and transmits power between the DC power source 10 and the AC power source 20. In the example of Fig. 1, the AC power source 20 is configured with a three-phase AC, and a neutral point Nnw is grounded.

[0015] The power conversion device 100 includes DC link capacitors 131, 132 having the same capacitance value, a three-phase inverter circuit 120, current control reactors 141a to 141c having the same inductance value, and a control circuit 150. The three-phase inverter circuit 120 executes power conversion (DC / AC conversion) between the DC power supply 10 and the AC power supply 20.

[0016] The three-phase inverter circuit 120 has a first leg 121 to a third leg 123 for three phases connected in parallel between the positive electrode wire 111 and the negative electrode wire 112. The first leg 121 has switching elements Q1A and Q1B connected in series between the positive electrode wire 111 and the negative electrode wire 112. The second leg 122 has switching elements Q2A and Q2B connected in series between the positive electrode wire 111 and the negative electrode wire 112. Similarly, the third leg 123 has switching elements Q3A and Q3B connected in series between the positive electrode wire 111 and the negative electrode wire 112.

[0017] That is, the first leg 121 is a series connection circuit of a positive switching element Q1A and a negative switching element Q1B. The second leg 122 is a series connection circuit of a positive switching element Q2A and a negative switching element Q2B. The third leg 123 is a series connection circuit of a positive switching element Q3A and a negative switching element Q3B. Each of the positive and negative switching elements of the first leg 121 to the third leg 123 may be composed of a plurality of switching elements.

[0018] Each of the switching elements Q1A, Q1B, Q2A, Q2B, Q3A, and Q3B is a semiconductor element capable of controlling the on and off timing, such as an IGBT (Insulated Gate Bipolar Transistor) or a MOSFET (Metal Oxide Semiconductor Field Effect Transistor). A diode 21 (hereinafter referred to as an anti-parallel diode 21) is connected in anti-parallel to each of the switching elements Q1A, Q1B, Q2A, Q2B, Q3A, and Q3B. Each of the positive switching elements Q1A to Q3A corresponds to an embodiment of a "first switching element", and each of the negative switching elements Q1B to Q3B corresponds to an embodiment of a "second switching element".

[0019] The positive electrode wire 111 and the negative electrode wire 112 are respectively connected to the positive electrode and the negative electrode of the DC power supply 10. The DC link capacitors 131 and 132 are connected in series between the positive electrode wire 111 and the negative electrode wire 112 in parallel with the DC power supply 10. In the example of Fig. 1, the neutral point Nnp of the DC power supply 10, which is the connection point of the DC link capacitors 131 and 132, is grounded similarly to the neutral point Nnw of the AC power supply 20. That is, in the example of Fig. 1, both the neutral point Nnp and the neutral point Nnw are grounded and are at the same potential.

[0020] An intermediate point Na of the first leg 121, i.e., a connection point between switching elements Q1A and Q1B, is connected to one terminal of a current control reactor 141a. Similarly, an intermediate point Nb of the second leg 122, i.e., a connection point between switching elements Q2A and Q2B, is connected to one terminal of a current control reactor 141b, and an intermediate point Nc of the third leg 123, i.e., a connection point between switching elements Q3A and Q3B, is connected to one terminal of a current control reactor 141c. Hereinafter, the ground potentials of the intermediate points Na to Nc are denoted as voltages ua to uc.

[0021] The other terminals of the current control reactors 141a to 141c are connected to the respective phases of the AC power supply 20. The AC power supply 20 mainly operates as a voltage source having a-phase to c-phase AC voltage sources Ea to Ec, and power transmission between the DC power supply 10 and the AC power supply 20 is realized by power conversion by the three-phase inverter circuit 120.

[0022] Current sensors 145a to 145c are provided corresponding to the current control reactors 141a to 141c, respectively, for detecting reactor currents i a to ic of each phase passing through the current control reactors 141a to 141c and flowing into the AC power supply 20. Furthermore, a voltage sensor (not shown) for detecting voltages (AC) va to vc output to each phase is provided in the AC power supply 20. The voltages va to vc can be detected, for example, by providing a voltage sensor (not shown) that detects a potential to earth, but the detection value of the voltage sensor (not shown) that detects the line voltage may be converted into the voltages va to vc indicating the potential to earth in the control circuit 150.

[0023] The detection values ​​by various sensors including the above-mentioned current sensors 145a to 145c and a voltage sensor (not shown) are input to a control circuit 150. Based on the input sensor detection values, the control circuit 150 outputs gate signals for controlling the on / off of each of the switching elements Q1A, Q1B, Q2A, Q2B, Q3A, and Q3B. This controls the power conversion by the three-phase inverter circuit 120.

[0024] 1 shows an example of a hardware configuration of the control circuit 150. For example, as shown in FIG. 1, the control circuit 150 is configured on a computer base so as to include a CPU (Central Processing Unit) 155, a memory 156, and an input / output (I / O) circuit 157. The CPU 155, the memory 156, and the I / O circuit 157 can exchange data with each other via a bus 158. A program is stored in advance in a part of the memory 156, and the CPU 155 executes the program to perform hysteresis control, which will be described later. The I / O circuit 157 inputs and outputs signals and data to and from the outside of the control circuit 150 (for example, a group of sensors including the three-phase inverter circuit 120 and the current sensors 145a to 145c).

[0025] 1, at least a part of the control circuit 150 can be configured using a digital electronic circuit such as a field programmable gate array (FPGA) or an application specific integrated circuit (ASIC). At least a part of the control circuit 150 can be configured using an analog electronic circuit including a comparator, an operational amplifier, a differential amplifier circuit, etc. The functions of each block constituting each of the multiple hysteresis control units described below are realized by at least one of software processing and hardware processing by the control circuit 150.

[0026] (Example of hysteresis control) Next, a description will be given of the hysteresis control executed by the control circuit 150. First, a hysteresis control according to a comparative example in which the dead time is not taken into consideration will be described with reference to Figs.

[0027] In the following description, of the first to third legs 121 to 123, a representative description will be given of hysteresis control for controlling on / off of the switching elements Q1A and Q1B constituting the first leg 121 based on the reactor current ia. However, for each hysteresis control described below, the second leg 122 and the third leg 123 can also similarly perform hysteresis control for controlling on / off of the switching elements Q2A, Q2B and the switching elements Q3A, Q3B based on the reactor currents ib and ic, respectively.

[0028] FIG. 2 shows a functional block diagram illustrating hysteresis control according to a comparative example. The hysteresis control unit 30 a according to the comparative example includes adders 52 and 54 , a hysteresis comparator 60 , and an inverter 61 .

[0029] Here, the hysteresis bandwidth BW is a setting value for setting the switching period to a target value Ttrg (Ttrg=1 / ftrg) that corresponds to the target value ftrg of the switching frequency, and the setting method is arbitrary. +(BW / 2) and -(BW / 2) are input to adders 52 and 54, respectively.

[0030] The adder 52 adds the current command value ia* of the reactor current ia to (BW / 2) to calculate the upper limit value Iup of the hysteresis band. The adder 54 adds the current command value ia* to -(BW / 2) to calculate the lower limit value Ilw of the hysteresis band. For example, the current command value ia* is a sinusoidal current having the same frequency as the three-phase AC voltage of the AC power source 20.

[0031] The hysteresis comparator 60 outputs a pulse signal having a logical high level (hereinafter, "H level") or a logical low level (hereinafter, "L level"), which indicates a comparison result between the reactor current ia (detection value) detected by the current sensor 145a and the upper limit value Iup and the lower limit value Ilw of the hysteresis band. The output signal S1a* of the hysteresis comparator 60 is used as it is as the gate signal S1a of the switching element Q1A on the positive pole side.

[0032] The inverter 61 inverts the output signal of the hysteresis comparator 60. The inverted output signal S1a*, S1b*, is used as the gate signal S1b of the negative switching element Q1B. During the H level period of each gate signal, the corresponding switching element is turned on, and during the L level period, the corresponding switching element is turned off. The gate signals S1a and S1b in FIG. 2 are gate signals for theoretical on / off control without dead time. In the first leg 121, the positive switching element Q1A and the negative switching element Q1B are complementarily turned on and off in response to the gate signals S1a and S1b that use S1a* and S1b* as they are.

[0033] Fig. 3 shows an example of a waveform diagram of the reactor current under the hysteresis control of Fig. 2. Here, it is assumed that the output voltage of the three-phase inverter circuit 120, i.e., the voltage of the DC power supply 10, is sufficiently large relative to the voltage va of the AC power supply 20, and the potential (E / 2) of the positive wire 111 exceeds the potential of the a-phase of the AC power supply 20. At this time, as shown in Fig. 3, the reactor current ia increases during the on-period of the positive switching element Q1A. Conversely, the reactor current decreases during the on-period of the negative switching element Q1B (the off-period of the switching element Q1A).

[0034] In hysteresis control, every time the reactor current ia rises to the upper limit value Iup or drops to the lower limit value Ilw, the output signal of the hysteresis comparator 60 changes, so that the on-periods of the positive-side switching element Q1A and the negative-side switching element Q1B are alternately provided, and the direction of change of the reactor current ia is reversed.

[0035] Before time t1, it is the on-period of the positive-side switching element Q1A. The rising reactor current ia is compared with the upper limit value Iup, and while ia < Iup, the output signal of the hysteresis comparator 60 is maintained at the H level.

[0036] At time t1, when ia ≥ Iup, the output signal of the hysteresis comparator 60 changes from the H level to the L level. As a result, the positive-side switching element Q1A is turned off and the negative-side switching element Q1B is turned on, so that the reactor current ia starts to decrease.

[0037] After time t2 when the reactor current ia starts to decrease, the reactor current ia is compared with the lower limit value Ilw, and while ia > Ilw, the output signal of the hysteresis comparator 60 is maintained at the L level. At time t2, when ia ≤ Ilw, the output signal of the hysteresis comparator 60 changes from the L level to the H level. As a result, the negative-side switching element Q1B is turned off and the positive-side switching element Q1A is turned on, so that the reactor current ia starts to increase.

[0038] At time t3, when the rising reactor current ia reaches the upper limit value Iup again, the output signal of the hysteresis comparator 60 changes from the H level to the L level, so that the on-period of the negative-side switching element Q1B is provided.

[0039] The on-period length Ton and off-period length Toff of the positive-side switching element under hysteresis control are determined by the slope (rate of change) of the reactor current ia and the hysteresis band width BW. Therefore, it can be understood that the switching period Tsw (Tsw=Ton+Toff) can be controlled to the target value Ttrg by appropriately setting the hysteresis band width BW.

[0040] In the following description, the ratio of the on-period length Ton of the switching element Q1A to the switching cycle Tsw is defined as the duty D. The off-period of the switching element Q1A (i.e., the on-period of the switching element Q1B) to the switching cycle Tsw is the length of The ratio of the off period length Toff is given by (1-D).

[0041] (Effect of dead time on hysteresis control) FIG. 4 shows a functional block diagram of hysteresis control having a dead time providing function.

[0042] The hysteresis control unit 30b shown in Fig. 4 further includes a dead time generator 70 in comparison with the configuration of the hysteresis control unit 30a shown in Fig. 2. The dead time generator 70 receives the output signals S1a*, S1b* of the hysteresis comparator 60 and the inverter 61, and generates gate signals S1a, S1b to which a dead time is added.

[0043] FIG. 5 shows a signal waveform diagram for explaining the operation of the dead time generator 70. In FIG. As shown in FIG. 5, the output signal S1a* of the hysteresis comparator 60 and its inverted signal S1b* are alternately set to either the H level or the L level.

[0044] As shown in Figure 1, the positive and negative poles of the same leg negative When both of the switching elements on the positive and negative pole sides are turned on, a short circuit path is formed between the positive pole wire 111 and the negative pole wire 112, which is called an arm short circuit. negativeTo prevent arm short circuit caused by slight difference in ON timing and OFF timing between the switching elements on the positive and negative poles, negative It is known to provide a dead time during which an OFF command is generated for both pole side switching elements.

[0045] When the positive and negative switching elements are switched on and off, the dead time generator 70 generates a turn-off command at the same timing, while adding a predetermined delay time Td to the turn-on command. As a result, both gate signals S1a and S1b are set to the L level, i.e., negative A dead time can be provided during which an OFF command is given to both of the switching elements on the pole side. Hereinafter, the length of the dead time will also be simply referred to as dead time Td.

[0046] An example of a reactor current waveform diagram for explaining the influence of dead time on hysteresis control is shown in Fig. 6. Fig. 6 shows an example of a reactor current waveform when hysteresis control is performed using the gate signals S1a and S1b in Fig. 4 and the upper limit value Iup and the lower limit value Ilw that are set without considering the dead time.

[0047] As shown in FIG. 6, during the off period of the positive-side switching element Q1A, when the reactor current ia falls to the lower limit value Ilw at time t2, in response to this, the output signal S1a* of the hysteresis comparator 60 changes to an H level in order to increase the reactor current ia.

[0048] 5, the gate signal S1a is maintained at the L level from time t2 until the dead time Td has elapsed. Therefore, during the dead time, the reactor current ia continues to decrease. Then, at time t2x after the dead time Td has elapsed, the gate signal S1a changes from the L level to the H level, causing the reactor current ia to start increasing.

[0049] Therefore, the time length until the reactor current ia reaches the upper limit value Iup increases in accordance with the amount of current change Xd between time t2 and time t2x, compared to the time length from time t2 to t3 in Fig. 3. This shows that an error occurs in the actual switching period Tsw by the hysteresis control, due to the influence of the dead time, with respect to the target value Ttrg corresponding to the hysteresis bandwidth BW.

[0050] (Hysteresis Control According to the First Embodiment) In the first embodiment, a hysteresis control that compensates for the influence of the above-mentioned dead time will be described.

[0051] FIG. 7 is a functional block diagram illustrating the hysteresis control according to the first embodiment. The hysteresis control unit 31 according to the first embodiment includes a hysteresis band generating unit 50, adders 52 and 54, a hysteresis comparator 60, a dead time generator 70, and dead time compensating units 72 and 74. That is, compared to the hysteresis control unit 30b shown in FIG.

[0052] The hysteresis band generating unit 50 has a function of calculating the hysteresis band width BW for controlling the switching frequency to the target value ftrg, as well as a function of calculating the duties D and (1-D) used in the compensation calculations in the dead time compensating units 72 and 74.

[0053] Here, an example of calculating the hysteresis band width BW and the duty D will be described below. The gradient (dia / dt) of the reactor current ia shown in FIG. 3 can be calculated from the following equation (1) using the inductance value L of the current control reactor 141a, the voltage va, and the voltage ua at the midpoint of the first leg 121.

[0054] (dia / dt)=(ua-va) / L …(1) In equation (1), the voltage ua is ua=(E / 2) during the on-period of the positive switching element Q1A, and ua=-(E / 2) during the on-period of the negative switching element Q1B.

[0055] Therefore, the on-period length Ton and the off-period length Toff of the positive-side switching element Q1A can be expressed by the following equations (2) and (3).

[0056] Ton = BW·L / (va+(E / 2)) …(2) Toff = BW·L / ((E / 2)-va) …(3) Therefore, the switching period Tsw is expressed by the following equation (4).

[0057] Tsw=(BW·L·E) / ((E / 2)^2-(va)^2) …(4) Substituting Tsw=Ttrg=1 / ftrg in equation (4) and solving for the hysteresis band width BW gives equation (5).

[0058] BW=Ttrg·((E / 2)^2-(va)^2) / (L·E) …(5) The hysteresis band width BW for setting the switching frequency to the target value ftrg under the gradient of the current reactor current ia is calculated by the equation (5). That is, the hysteresis band generating unit 50 calculates the hysteresis band width BW from the detection value of the voltage va, the voltage E (constant or detection value) of the DC power supply 10, the inductance value L of the current control reactor 141a, and the target value ftrg of the switching frequency. Hysteresis band width BW calculation do .

[0059] Moreover, from equations (2) and (3), D=Ton / (Ton+Tff) and 1-D=Toff / (Ton+Toff) can be calculated by the following equation (6).

[0060] D = ((E / 2) - v a ) / E … (6) 1-D=((E / 2)+va) / E …(7) The hysteresis band generating section 50 inputs +(BW / 2) to the adder 52 and inputs −(BW / 2) to the adder 54 based on the hysteresis band width BW calculated by the equation (5).

[0061] As a result, the adders 52 and 54 output the upper limit value Iup (Iup=ia*+(BW / 2)) and lower limit value Ilw (Ilw=ia*-(BW / 2)) of the hysteresis band before dead time compensation, as in Fig. 2. That is, the adders 52 and 54 correspond to one example of an "upper and lower limit value setting unit", and it is understood that the hysteresis band defined by the upper limit value Iup and lower limit value Ilw includes the current command value ia*. In this embodiment, the reactor current ia corresponds to one example of an "electrical quantity" that is the target of hysteresis control, and the current command value ia* corresponds to one example of a "command value" of the electrical quantity.

[0062] The dead time compensation unit 72 generates an upper limit value Iupc after dead time compensation based on the upper limit value Iup (before dead time compensation) from the adder 52, the duty D generated by the hysteresis band generation unit 50, and the polarity (positive / negative) of the reactor current ia.

[0063] The dead time compensation unit 74 generates a lower limit value Ilwc after the dead time compensation based on the lower limit value Ilw (before the dead time compensation) from the adder 54, the duty (1-D) generated by the hysteresis band generation unit 50, and the polarity (positive / negative) of the reactor current ia. 74 In this case, the polarity (positive / negative) of the reactor current ia is determined using the current command value ia*, so that the positive / negative determination result can be stabilized.

[0064] The hysteresis comparator 60 compares the upper limit value Iupc and the lower limit value Ilwc of the hysteresis band after the processing by the dead time compensation units 72, 74 with the reactor current ia (detection value) detected by the current sensor 145a.

[0065] 4, the output signal S1a* and its inverted signal S1b* of the hysteresis comparator 60 are input to the dead time generator 70, which outputs the gate signals S1a and S1b to which the dead time is added. That is, the hysteresis control unit 31 in FIG7 generates the gate signals S1a and S1b using the upper limit value Iupc and lower limit value Ilwc of the hysteresis band after the dead time compensation, similarly to the hysteresis control unit 30b shown in FIG4.

[0066] Calculation of the amount of dead time compensation by the dead time compensators 72 and 74 will be described with reference to Fig. 6 again. Fig. 6 illustrates calculation of the amount of compensation for the lower limit Ilw to deal with the influence of the dead time.

[0067] As shown in FIG. 6, during the off period of switching element Q1A (the on period of switching element Q1B), even if the output signal (S1a*) of hysteresis comparator 60 changes from L level to H level at time t2 when reactor current ia falls to lower limit value Ilw, reactor current ia continues to fall until time t2x when dead time Td has elapsed.

[0068] As a result, the on-period of switching element Q1A for increasing reactor current i is not started, and reactor current i falls below lower limit Ilw by Xd. That is, a control error of reactor current i with respect to the lower limit of the hysteresis band occurs. In this way, when the behavior (increase / decrease) of the reactor current during the dead time differs from that after the end of the dead time, a control error occurs with respect to the upper or lower limit of the hysteresis band.

[0069] Considering the control error at this time, since the gradient of the reactor current ia is the same between times t1 to t2 and t2 to t2x, the proportional relationship of the following equation (8) holds between the above Xd and the hysteresis band width BW.

[0070] BW:Xd=Toff:Td …(8) By substituting the on-period length of switching element Q1B immediately before the dead time, i.e., the off-period length of switching element Q1A, Toff=(1-D)·Tsw, into equation (8) and solving equation (8) for Xd, the following equation (9) is obtained.

[0071] Xd = BW Td / (Tsw (1-D)) … (9) 6, the lower limit value Ilwc after dead-time compensation can be set to Ilw+Xd, with Xd being the compensation amount for the lower limit value Ilx. This makes it possible to control the lower limit value of the reactor current ia at the timing when the gate signal S1a changes from L level to H level after the dead time Td has elapsed since the output signal (S1a*) of the hysteresis comparator 60 changes from L level to H level, to the lower limit value Ilw (before compensation) based on the hysteresis band width BW, based on the compensated lower limit value Ilwc.

[0072] Next, dead time compensation corresponding to the polarity (positive / negative) of the reactor current ia will be described with reference to FIGS.

[0073] FIG. 8 shows an example of a control waveform of the reactor current when the reactor current ia is positive (ia>0).

[0074] When the reactor current i a is positive, on the lower limit side of the hysteresis band, the behavior (increase / decrease) of the reactor current i a differs between during the dead time and during the on-period of the switching element Q1A after the end of the dead time. This causes a control error (Xd) of the reactor current i a during the dead time, as shown in Fig. 6. As a result, as shown by the dotted line in Fig. 8, in hysteresis control according to the upper limit value Iup and lower limit value Ilw before compensation, the reactor current i a goes outside the hysteresis band on the lower limit side during the dead time.

[0075] Therefore, when the dead time compensation unit 74 determines that the reactor current ia is positive based on the current command value ia*, it generates the lower limit value Ilwc to be input to the hysteresis comparator 60 by adding the positive compensation amount Xd calculated by equation (9) to the lower limit value Ilw according to the hysteresis band width BW calculated by the hysteresis band generation unit 50 (Ilwc=Ilw+Xd).

[0076] On the other hand, on the upper limit side of the hysteresis band, when both switching elements Q1A and Q1B are turned off during the dead time Td, the reactor current ia decreases. That is, the behavior of the reactor current ia is the same during the dead time and during the off period of the switching element Q1A (the on period of the switching element Q1B) after the end of the dead time. Therefore, there is no need to compensate for the upper limit value Iup according to the hysteresis band width BW calculated by the hysteresis band generation unit 50.

[0077] Therefore, when the dead time compensation unit 72 determines that the reactor current ia is positive based on the current command value ia*, it simply sets the upper limit value Iup according to the hysteresis band width BW calculated by the hysteresis band generation unit 50 as the upper limit value Iupc input to the hysteresis comparator 60. Therefore, the compensation amount Xd# on the upper limit side by the dead time compensation unit 72 is set to Xd#=0, and Iupc=Iup+Xd#=Iup.

[0078] As a result, the substantial hysteresis band width BW# after the dead time compensation is narrower by the compensation amount Xd than the hysteresis band width BW calculated by the hysteresis band generating unit 50 (BW#=BW-Xd). As a result, as shown by the solid line in Fig. 8, hysteresis control using the lower limit value Ilwc compensated on the upward side can prevent the reactor current ia from going out of the hysteresis band (hysteresis band width BW) during the dead time period.

[0079] FIG. 9 shows an example of a control waveform of the reactor current when the reactor current ia is negative (ia<0).

[0080] When the reactor current i a is negative, contrary to Fig. 8, the reactor current i a increases during the dead time. Therefore, on the upper limit side of the hysteresis band, the behavior (increase / decrease) of the reactor current i a differs between during the dead time and during the off period of the switching element Q1A after the end of the dead time. This causes a control error of the reactor current i a during the dead time. As a result, as shown by the dotted line in Fig. 9, in hysteresis control according to the upper limit value Iup and lower limit value Ilw before compensation, the reactor current i a goes outside the hysteresis band on the upper limit side during the dead time.

[0081] Therefore, when the dead time compensation unit 72 determines that the reactor current ia is negative based on the current command value ia*, it generates the upper limit value Iupc to be input to the hysteresis comparator 60 by adding a negative compensation amount Xd# to the upper limit value Iup according to the hysteresis band width BW calculated by the hysteresis band generation unit 50 (Iupc = Iup + Xd#).

[0082] The compensation amount Xd# in this case can be obtained by replacing the duty (1-D) with D in equation (9) using the following equation (10).

[0083] Xd♯=-BW·Td / (Tsw·D) …(10) On the other hand, on the lower limit side of the hysteresis band, the behavior of the reactor current ia is the same during the dead time and during the on-period of the switching element Q1A after the end of the dead time. Therefore, there is no need to compensate for the lower limit Ilw according to the hysteresis band width BW calculated by the hysteresis band generating unit 50.

[0084] Therefore, when the dead time compensation unit 74 determines that the reactor current ia is negative based on the current command value ia*, it simply sets the lower limit value Ilw according to the hysteresis band width BW calculated by the hysteresis band generation unit 50 as the lower limit value Ilwc input to the hysteresis comparator 60. Therefore, the compensation amount Xd on the lower limit side by the dead time compensation unit 74 is set to Xd=0, and Ilwc=Ilw+Xd=Ilw.

[0085] As a result, the substantial hysteresis band width BW# after the dead time compensation is narrower by the compensation amount Xd than the hysteresis band width BW calculated by the hysteresis band generating unit 50 (BW#=BW-|Xd#|). As a result, as shown by the solid line in Fig. 9, hysteresis control using the upper limit value Iupc compensated for on the downward side can prevent the reactor current ia from going out of the hysteresis band (hysteresis band width BW) during the dead time period.

[0086] 8 and 9, the compensation amount Xd (Xd>0) or Xd# (Xd#<0) is added to one of the different upper and lower limit values ​​depending on the polarity (positive / negative) of the reactor current i a. In other words, the polarity (positive / negative) of the compensation amount and whether the compensation amount is added to the upper limit value Iup or the lower limit value Ilw differ depending on whether the reactor current i a is positive or negative.

[0087] Furthermore, from equations (9) and (10), it can be seen that the absolute values ​​of the compensation amounts Xd and Xd# are proportional to the duties D and (1-D), and more specifically, proportional to the ratio of the dead time Td to the on-period length of the switching element Q1A or Q1B immediately before the dead time Td.

[0088] 10 shows a flowchart illustrating the process of setting the upper and lower limit values ​​of the hysteresis control according to the embodiment 1. The control process of FIG.

[0089] In step (hereinafter simply referred to as "S") 110, the control circuit 150 obtains voltages va to vc from the sensor outputs, and also obtains current command values ​​ia* to ic*.

[0090] The control circuit 150 calculates the hysteresis band width BW according to the above-mentioned formula (5) in S120, and calculates the duty D, (1-D) used in the dead time compensation in S130. The duty can be calculated, for example, using the above-mentioned formulas (6) and (7), but can also be calculated by other methods. As an example, the duty D, (1-D) can be calculated from the ratio of the bus voltage (E / 2, -(E / 2)) of the positive electrode wire 111 and the negative electrode wire 112 to the system voltage (va to vb) of the AC power source 20. For example, the duty D, (1-D) can be separately calculated so that the output voltage (average value according to the duty) at the midpoints Na to Nc of the first leg 121 to the third leg 123 is balanced with the voltages va to vc, taking into consideration the voltages generated in the current control reactors 141a to 141c when the currents according to the current command values ​​ia* to ic* pass through. The processing in S120 to S130 corresponds to the operation of the hysteresis band generating section 50 in FIG.

[0091] In S140, the control circuit 150 calculates the upper limit value Iup and the lower limit value Ilw of the hysteresis band in each phase based on the hysteresis band width BW and the current command values ​​ia* to ic* calculated in S120. The process in S140 corresponds to the output operation of BW / 2 and −(BW / 2) from the hysteresis band generation unit 50 and the operation of the adders 52 and 54.

[0092] In S150, the control circuit 150 calculates the upper limit value Iupc and the lower limit value Ilwc of the hysteresis band after the dead time compensation. S150 includes S152, S154, and S156.

[0093] In S152, the control circuit 150 determines the polarity (positive / negative) of the reactor currents i a - ic in each phase based on the current command values ​​i a * - ic *. If the reactor current is positive (YES in S152), the process proceeds to S154, and if the reactor current is negative (NO in S152), the process proceeds to S156.

[0094] In S154, the control circuit 150 performs dead time compensation so that the upper limit value is maintained at Iupc=Iup while the lower limit value is increased to Ilwc=Ilw+Xd(Xd>0) as described in Fig. 8. In contrast, in S156, the control circuit 150 performs dead time compensation so that the lower limit value is maintained at Ilwc=Ilw while the upper limit value is decreased to Iupc=Iup+Xd#(Xd#<0) as described in Fig. 9. The process of S150 corresponds to the operation of the dead time compensation units 72 and 74 in Fig. 7.

[0095] The upper limit value Iupc and lower limit value Ilwc of the hysteresis band set by the control process of Figure 10 are input to the hysteresis comparator 60, and a gate signal for the switching element of each leg to which a dead time Td has been added is generated so as to hysteresis control the detection values ​​(instantaneous values) of the reactor currents ia to ic of each phase in accordance with the hysteresis band after dead time compensation.

[0096] In this way, the power conversion device according to the first embodiment can prevent the reactor current from going outside the hysteresis band during the dead time period by selectively adding a positive or negative compensation amount to one of the upper and lower limits of the hysteresis band set according to the target value of the switching frequency. As a result, it is possible to realize hysteresis control using the instantaneous value of an electrical quantity such as a current or a voltage in order to stably control the switching frequency to a target value.

[0097] A variation of the first embodiment. FIG. 11 is a functional block diagram illustrating hysteresis control according to a modification of the first embodiment.

[0098] As shown in FIG. 11, the hysteresis control unit 32 according to the modification of the first embodiment is different in that it further includes a protection circuit 80 as compared with the hysteresis control unit 31 (FIG. 7) according to the first embodiment.

[0099] The protection circuit 80 is provided to prevent the hysteresis bandwidth BW♯ (BW♯ = Iupc - Ilwc) based on the upper limit value Iupc and the lower limit value Ilwc after the processing by the dead time compensation units 72 and 74 from becoming less than the limit value BWmin. The limit value BWmin can be determined in advance based on the slope of the reactor current ia that depends on the inductance value of the current control reactor 141a, taking into account that the switching operation does not become unstable.

[0100] For example, when BW♯ < BWmin, the upper limit value Iupc and the lower limit value Ilwc (after dead time compensation) of the hysteresis band input to the hysteresis comparator 60 can be corrected by adding (BWmin - BW♯) / 2 to the upper limit value Iupc and subtracting (BWmin - BW♯) / 2 from the lower limit value Ilwc.

[0101] As a result, it becomes possible to ensure that BW♯ ≥ BWmin for the upper limit value Iupc and the lower limit value Ilwc of the hysteresis band. Since the other configurations in FIG. 11 are the same as those of the hysteresis control unit 31 in FIG. 7, detailed descriptions will not be repeated.

[0102] FIG. 12 shows a flowchart for explaining the hysteresis control process according to the modification of the first embodiment.

[0103] As shown in FIG. 12, in the modification of the first embodiment, after S110 to S150 similar to those in FIG. 10, the control circuit 150 executes the process of S160 for protecting the hysteresis bandwidth. S160 includes S162, S164, and S166.

[0104] In S162, the control circuit 150 compares the hysteresis bandwidth BW♯ based on the upper limit value Iupc and the lower limit value Ilwc after the processing by the dead time compensation units 72 and 74 with a predetermined limit value BWmin. When BW♯ < BWmin (when the determination in S162 is YES), the process proceeds to S164. When BW♯ ≧ BWmin (when the determination in S162 is NO), the process proceeds to S166.

[0105] In S164, the control circuit 150 corrects the upper limit value Iupc and the lower limit value Ilwc of the hysteresis band input to the hysteresis comparator 60 so that BW♯ ≧ BWmin is ensured. For example, as described above, the upper limit value Iupc and the lower limit value Ilwc can be corrected such that the upper limit value Iupc is increased and the lower limit value Ilwc is decreased.

[0106] On the other hand, in S166, the control circuit 150 inputs the upper limit value Iupc and the lower limit value Ilwc after the processing by the dead time compensation units 72 and 74 to the hysteresis comparator 60 without correcting them. The process of S160 corresponds to the operation of the protection circuit 80 in FIG. 11.

[0107] In the power conversion device according to the modification of Embodiment 1, the switching operation can be stabilized by maintaining the hysteresis width at a certain value or more.

[0108] Embodiment 2. FIG. 13 is a schematic configuration diagram of a power conversion device 101 according to Embodiment 2.

[0109] The power conversion device 101 shown in FIG. 13 is different from the power conversion device 100 according to Embodiment 1 in that the neutral point Nnp on the DC side of the three-phase inverter circuit 120 (that is, the neutral point of the DC power supply 10) is not grounded. Since the other configurations of the power conversion device 101 are the same as those of the power conversion device 100, detailed description will not be repeated.

[0110] In the power conversion device 101, the potential difference between the neutral point Nnw on the AC side and the neutral point Nnp on the DC side (hereinafter also referred to as the neutral point voltage vnp) changes. As a result, the same amount of current change is superimposed on each of the reactor currents ia to ic due to the influence of the fluctuation in the neutral point voltage vnp. Since the amount of current change caused by such a fluctuation in the neutral point voltage affects the hysteresis control in which the reactor current is the control target, when the neutral point voltage fluctuates, it is necessary to remove the amount of current change caused by this.

[0111] In the example of Fig. 13, the neutral point Nnw on the AC side is grounded while the neutral point Nnp on the DC side is not grounded, and the above-mentioned fluctuation in the neutral point voltage vnp occurs because the above-mentioned neutral point Nnp or the neutral point Nnw is not grounded. In the second embodiment, hysteresis control of the reactor current for removing the influence of such a neutral point voltage fluctuation will be described. That is, the neutral point Nnp of the DC power supply 10 corresponds to an example of a "first neutral point", and the neutral point Nnw of the AC power supply 20 corresponds to an example of a "second neutral point".

[0112] FIG. 14 shows a functional block diagram illustrating the hysteresis control according to the second embodiment.

[0113] As shown in FIG. 14, the hysteresis control unit 33 of the second embodiment differs from the hysteresis control unit 31 (FIG. 7) of the first embodiment in that it further includes a current compensation unit 90 for removing the neutral point voltage fluctuation component of the reactor current i a.

[0114] The configuration of other parts of the hysteresis control unit 33 is similar to that of the hysteresis control unit 31, and therefore will not be repeated. Alternatively, the hysteresis control unit 33 may also be provided with a protection circuit 80 similar to that shown in FIG. 14 (a modification of the first embodiment) downstream of the dead time compensation units 72 and 74. Therefore, in the hysteresis control unit 33 as well, the upper limit value Iupc and the lower limit value Ilwc of the hysteresis band input to the hysteresis comparator 60 are calculated in the same manner as in the first embodiment or its modification.

[0115] The current compensation unit 90 has a neutral point voltage calculation unit 92, a current fluctuation component calculation unit 95, and a subtractor 98. The neutral point voltage calculation unit 92 calculates a neutral point voltage Vnp corresponding to the theoretical value of the neutral point voltage vnp from the switching patterns of the switching elements Q1A to Q3A and Q1B to Q3B.

[0116] As is well known, the neutral point voltage Vnp has a stepped voltage waveform that changes according to the switching pattern. In general, in the first leg 121 to the third leg 123, during a period when two of the positive switching elements (Q1A to A3A) are on and one of the negative switching elements (Q1B to Q3B) is on, Vnp=+(E / 6) is satisfied, and conversely, during a period when one of the positive switching elements is on and two of the negative switching elements are on, Vnp=-(E / 6) is satisfied. Also, during a period when all three positive switching elements are on, Vnp=+(E / 2) is satisfied, and during a period when all three negative switching elements are on, Vnp=-(E / 2) is satisfied.

[0117] Specifically, the neutral point voltage Vnp is determined by a combination of voltages ua to uc, which are the ground potentials of midpoints Na to Nc of the first leg 121 to the third leg 123. Hereinafter, the theoretical values ​​of the voltages ua to uc determined by the switching pattern in each leg are also referred to as leg voltages Ua* to Uc*.

[0118] FIG. 15 shows an example of the configuration of the neutral point voltage calculation unit 92 shown in FIG. The neutral point voltage calculation unit 92 has leg voltage calculation units 93a to 93c and a Vnp calculation unit 94.

[0119] The leg voltage calculation unit 93a calculates a leg voltage Ua* that is a theoretical value of the ground potential at the midpoint Na of the first leg 121, using the gate signals S1a, S1b of the switching elements Q1A, Q1B and the reactor current ia.

[0120] FIG. 16 shows a conceptual waveform diagram for explaining the operation of the leg voltage calculation unit 93a of the first leg 121.

[0121] As shown in FIG. 16, during the period when the gate signal S1a is at H level and the gate signal S1b is at L level, the positive side switching element Q1A is turned on, and the midpoint Na is electrically connected to the positive wire 111, so that the leg voltage Ua* becomes +(E / 2).

[0122] Conversely, during the period when the gate signal S1b is at H level and the gate signal S1a is at L level, the negative side switching element Q1B is turned on, and the midpoint Na is electrically connected to the negative wire 112, so that the leg voltage Ua* is -(E / 2).

[0123] During the dead time period when both of the gate signals S1a and S1b are at the L level, the anti-parallel diode 21 of the switching element Q1A or Q1B is conductive, so that the midpoint Na is electrically connected to the positive electrode wire 111 or the negative electrode wire 112. Therefore, the leg voltage Ua* differs depending on the polarity (positive / negative) of the reactor current ia.

[0124] Specifically, before time tz when the reactor current ia is positive, the anti-parallel diode 21 of switching element Q1B is conductive in Fig. 13, so that during the dead time period the leg voltage Ua*=-(E / 2). On the other hand, after time tz when the reactor current ia is negative, the anti-parallel diode 21 of switching element Q1A is conductive in Fig. 13, so that during the dead time period the leg voltage Ua*=+(E / 2).

[0125] In this way, the leg voltage calculation unit 93a can calculate the leg voltage Ua* based on the gate signals S1a, S1b of the switching elements Q1A, Q1B and the reactor current ia (polarity).

[0126] 15 again, the leg voltage calculation unit 93b uses the gate signals S2a, S2b of the switching elements Q2A, Q2B and the reactor current ib to calculate the leg voltage Ub*, which is the ground potential (theoretical value) of the midpoint Nb of the second leg 122. Similarly, the leg voltage calculation unit 93c uses the gate signals S3a, S3b of the switching elements Q3A, Q3B and the reactor current ic to calculate the leg voltage Uc*, which is the ground potential (theoretical value) of the midpoint Nc of the third leg 123.

[0127] In each of the leg voltage calculation units 93b and 93c, in FIG. 16, by replacing the gate signal S1a with the gate signal S2a or S3a, replacing the gate signal S1b with the gate signal S2b or S3b, and further replacing the reactor current ia with the reactor current ib or ic, it is possible to obtain the leg voltage Ub* or Uc* instead of the leg voltage Ua*.

[0128] The Vpn calculation unit 94 calculates the neutral point voltage Vnp using the leg voltages Ua*-Uc* from the leg voltage calculation units 93a-93c. When the neutral point Nnp on the DC side is not grounded, no current path is formed via the neutral points Nnp and Nnw, so the neutral point voltage Vnp changes stepwise as described above according to the combination of the leg voltages Ua*-Uc*. Then, the zero-phase current is added to each of the reactor currents ia-ic, and the sum of the reactor currents ia-ic after the addition of the zero-phase current becomes zero.

[0129] Therefore, in order to perform hysteresis control accurately, it is necessary to remove from the reactor current of each phase the current fluctuation component resulting from fluctuations in the neutral point voltage Vnp, which corresponds to the zero-phase current.

[0130] 14, the current fluctuation component calculation unit 95 calculates the current fluctuation component i0 caused by fluctuations in the neutral point voltage Vnp based on the neutral point voltage Vnp calculated by the neutral point voltage calculation unit 92. The subtractor 98 subtracts the current fluctuation component i0 calculated by the current fluctuation component calculation unit 95 from the detection value of the reactor current ia, and thereby outputs the reactor current iac in which the current fluctuation component caused by fluctuations in the neutral point voltage Vnp has been cancelled. The reactor current iac from the subtractor 98 is input to the hysteresis comparator 60.

[0131] In the hysteresis control unit 33 according to the second embodiment, the hysteresis comparator 60 can perform hysteresis control of the reactor current in the same manner as in the first embodiment or its modified example by comparing the reactor current iac compensated by the current compensation unit 90 with the upper limit value Iupc and the lower limit value Ilwc of the hysteresis band.

[0132] 14, the current fluctuation component calculation unit 95 can be configured with an integral element having a time constant according to the inductance value L of the current control reactors 141a to 141c. Alternatively, in order to prevent accumulation of DC errors, the current fluctuation component calculation unit 95 can be configured to calculate the current fluctuation component i0 by further adding a high-pass filter (preferably a second-order or higher high-pass filter) having a cutoff frequency sufficiently lower than the switching frequency and inputting the output value of the high-pass filter to the above-mentioned integral element. Alternatively, the current fluctuation component calculation unit 95 can be configured using a first-order low-pass filter instead of the above-mentioned integral element.

[0133] 17 shows a flowchart illustrating a current comparison process of the hysteresis control according to the embodiment 2. The control process of FIG.

[0134] The control circuit 150 acquires the upper limit value Iupc and the lower limit value Ilwc of the hysteresis band in S210. The process of S210 is realized by reading in the values ​​obtained in the control process shown in FIG.

[0135] When the control circuit 150 acquires the detection value (ia to ic) of the reactor current from the sensor output in S220, it removes the fluctuation component due to the influence of the neutral point potential fluctuation from the detection value of the reactor current in S230. S230 has S232 and S234.

[0136] In S232, the control circuit 150 calculates a current fluctuation component caused by fluctuations in the neutral point voltage Vnp, and in S234, cancels the current fluctuation component calculated in S232 from the detection value (S220) of the reactor current. The process of S232 corresponds to the operation of the neutral point voltage calculation unit 92 and the current fluctuation component calculation unit 95 in Fig. 14, and the process of S234 corresponds to the operation of the subtractor 98 in Fig. 14.

[0137] The control circuit 150 executes a process of comparing the reactor current (S234) with the upper limit value Iupc and the lower limit value Ilwc (S210) in steps S250 to S290. In step S250, the control circuit 150 branches the process according to the level of an output signal indicating the comparison result (corresponding to the output signal of the hysteresis comparator 60).

[0138] When the output signal is at the L level (YES in S250), the control circuit 150 compares it with the lower limit Ilwc of the hysteresis band in S260. While the reactor current is higher than the lower limit Ilwc (NO in S260), the output signal is maintained at the L level in S290. On the other hand, when the reactor current falls to the lower limit Ilwc (YES in S260), the output signal is inverted from the L level to the H level in S280.

[0139] In contrast, when the output signal is at H level (NO in S250), the control circuit 150 compares the reactor current with the upper limit value Iupc in S270. While the reactor current is lower than the upper limit value Iupc (NO in S270), the output signal is maintained at H level in S290. On the other hand, when the reactor current rises to the upper limit value Iupc (YES in S270), the output signal is inverted from H level to L level in S280. The processes of S250 to S290 correspond to the operation of the hysteresis comparator 60 in FIG. 14.

[0140] The control circuit 150 generates gate signals for each switching element of the three-phase inverter circuit 120 in a manner to provide a dead time based on the output signal of the hysteresis comparator 60 obtained in steps S250 to S290 in S300. The process of S300 corresponds to the operation of the dead time generator 70.

[0141] 17, control circuit 150 can execute the current comparison process of the hysteresis control according to the first embodiment and its modifications. In this case, in S250 to S290, the detection value of the reactor current (S210) is compared with the upper limit value Iupc and the lower limit value Ilwc (S210). In this case, the processes of S250 to S290 correspond to the operation of each of the hysteresis comparators 60 in FIG. 7 and FIG. 11.

[0142] In this way, in the power conversion device according to the second embodiment, even in a configuration in which the neutral point potential fluctuates because the neutral point Nnw of the AC power supply 20 or the neutral point Nnp on the DC side of the three-phase inverter circuit 120 is not grounded, the effect of the hysteresis control according to the first embodiment or its modification can be obtained.

[0143] As described above, according to the power conversion device of this embodiment, the influence of dead time can be eliminated and the switching elements can be turned on and off in accordance with the hysteresis bandwidth BW that reflects the target value ftrg of the switching frequency, so that the switching frequency can be stably controlled to the target value ftrg.

[0144] By setting the target value ftrg to a constant value as mentioned in the present embodiment, the fluctuation of the switching frequency can be suppressed and the operation of the power conversion device can be stabilized. By stabilizing the switching frequency, the microcomputer or F that constitutes the control circuit 150 can be made to operate more smoothly as the switching frequency increases. PG This can prevent the calculation load at A etc. from increasing.

[0145] In general, P W.M. When using switching control that requires high-speed calculation such as a Pulse Width Modulation (DSP) method, it is necessary to introduce a DSP (Digital Signal Processor), and it is possible to use multiple control devices to support both abnormality monitoring and switching control. In contrast, if the hysteresis control according to the present embodiment is applied instead of the PWM method, a single control device can maintain characteristics such as frequency and utilize constant current monitoring by hysteresis control. This makes it possible to realize high-speed response of control for abnormality response without requiring a special external circuit even when an abnormality occurs. Furthermore, since the switching frequency is constant, it is possible to reuse design know-how such as EMC (Electromagnetic Compatibility) measures, and the thermal design of the switching elements and reactors is facilitated, which contributes to improving the reliability of the power conversion device.

[0146] On the other hand, the target value ftrg of the switching frequency may be set variably over time. For example, it is possible to operate the power conversion device so as to reduce the peak of the noise level on the frequency spectrum by changing the target value ftrg at regular intervals. It is also possible to set the target value ftrg so as to reduce the noise level of a specific frequency in cooperation with an external device of the power conversion device.

[0147] Alternatively, the target value ftrg of the switching frequency may be variably set according to the temperature state of the power conversion device. For example, since the amount of heat generated by the current control reactors 141a-141c depends on the magnitude of the ripple current components of the reactor currents ia-ic, that is, the switching frequency of the three-phase inverter circuit 120, it is possible to change the target value ftrg based on a comparison between the element temperatures of the switching elements Q1A-Q3A, Q1B-Q3B and the temperatures of the current control reactors 141a-141c.

[0148] In this embodiment, an example in which the hysteresis control is applied to a three-phase inverter circuit has been described, but the configuration of the power conversion device to which the hysteresis control according to this embodiment is applied may be any configuration as long as it has a plurality of switching elements connected so that a dead time is required. For example, the hysteresis control according to this embodiment can be applied to a single-phase inverter circuit having two legs, a chopper circuit that performs DC / DC conversion, or a PWM rectifier circuit that performs AC / DC conversion.

[0149] Furthermore, in the present embodiment, an example has been described in which the reactor currents i a - ic output from the three-phase inverter circuit 120 are subject to hysteresis control, but if the electric quantity (including current, voltage, and power) handled in power conversion by a power conversion device including switching elements is compared with the upper limit and lower limit of a hysteresis band including a command value of the electric quantity, the hysteresis control according to the present embodiment can be realized. For example, the electric quantity handled in the power conversion described above, which is subject to hysteresis control, includes electric quantities input / output to / from the power conversion device, such as the reactor current and DC link voltage (the voltage of the DC link capacitors 131 and 132) in the present embodiment, and electric quantities detected inside the power conversion device.

[0150] The embodiments disclosed herein should be considered to be illustrative and not restrictive in all respects. The technical scope of the present disclosure is defined by the claims, not the above description, and is intended to include all modifications within the meaning and scope of the claims. [Explanation of symbols]

[0151] 10 DC power supply, 20 AC power supply, 21 anti-parallel diode, 30a, 30b, 31, 32, 33 hysteresis control unit, 50 hysteresis band generation unit, 52, 54 adder, 60 hysteresis comparator, 61 inverter, 70 dead time generator, 72, 74 dead time compensation unit, 80 protection circuit, 90 current compensation unit, 92 neutral point voltage calculation unit, 93a, 93b, 93c leg voltage calculation unit, 94 Vpn calculation unit, 95 current fluctuation component calculation unit, 98 subtractor, 100, 101 power conversion device, 111 positive pole wire, 112 negative pole wire, 120 three-phase inverter circuit, 121 first leg, 122 second leg, 123 third leg, 131, 132 DC link capacitor, 141a to 141c current control reactor, 145a to 145c current sensor, 150 control circuit, 158 bus, BW hysteresis band width, Ea, Ec AC voltage source, Ilw, Ilwc lower limit (hysteresis band), Iup, Iupc upper limit V, L inductance value, Nnp neutral point (DC side), Nnw neutral point (AC side), Q1A, Q1B, Q2A, Q2B, Q3A, Q3B switching elements, S1b, S1a, S2a, S2b, S3a, S3b gate signal, Td dead time, Tsw switching period, Ttrg target value (switching period), ftrg target value (switching frequency), Vnp, vnp neutral point voltage, ia* current command value, ia to ic Reactor current.

Claims

1. a power conversion circuit having first and second switching elements connected in series between first and second electric wires; a control circuit that controls on / off of the first and second switching elements by hysteresis control based on a comparison between a detection value of an amount of electricity handled in power conversion by the power conversion circuit and an upper limit value and a lower limit value of a hysteresis band including a command value of the amount of electricity, The on / off of the first and second switching elements is controlled so that a dead time is provided during which both the first and second switching elements are turned off when the first and second switching elements are switched on and off; The control circuit includes: a hysteresis band generating unit that generates a hysteresis band width in the hysteresis control in accordance with target values ​​of switching frequencies of the first and second switching elements; an upper / lower limit value setting unit that sets the upper limit value and the lower limit value in accordance with the hysteresis band width and the command value; a dead time compensation unit that adds a compensation amount to the upper limit value and the lower limit value set by the upper and lower limit value setting unit to prevent the detection value from going outside the hysteresis band during the dead time; a hysteresis comparator that compares the upper limit value and the lower limit value after processing by the dead time compensation unit with the detection value; a dead time generator that generates on / off control signals for the first and second switching elements based on an output signal of the hysteresis comparator so that the dead time is provided; The dead time compensating unit executes a process of adding the compensation amount of a different polarity to one of the upper limit value and the lower limit value, which differs between when the detection value is positive and when it is negative.

2. 2. The power conversion device according to claim 1, wherein the dead time compensator sets the compensation amount to be positive so as to increase the lower limit value when the detection value is positive, and sets the compensation amount to be negative so as to decrease the upper limit value when the detection value is negative.

3. 3 . The power conversion device according to claim 1 , wherein the dead time compensator changes the compensation amount in accordance with a ratio of on periods of the first and second switching elements to switching periods of the first and second switching elements.

4. The absolute value of the compensation amount is set to be proportional to a ratio of a time length of the dead time to an on-period length of the first or second switching element that was on immediately before the dead time. The power conversion device according to any one of claims 1 to 3.

5. The control circuit includes: a protection circuit for preventing a difference between the upper limit value and the lower limit value after the processing by the dead time compensating unit from becoming smaller than a predetermined limit value, The protection circuit modifies the upper limit value and the lower limit value used in the hysteresis comparator so that the limit value is secured when the difference is smaller than the limit value. The power conversion device according to any one of claims 1 to 4.

6. the power conversion circuit has a plurality of legs each formed of the first and second switching elements, and is configured to perform power conversion between a DC voltage source having a positive electrode and a negative electrode connected to the first and second electric wires, and an AC voltage source connected to each of the legs; The power conversion device is a reactor connected between a connection point of the first and second switching elements of each leg and the AC voltage source, The power conversion device according to any one of claims 1 to 5, wherein the detection value is a detection value of a current passing through the reactor.

7. At least one of a first neutral point of the DC voltage source and a second neutral point of the AC voltage source is not grounded, The control circuit includes: a current compensation unit for canceling a fluctuation component of the current detection value caused by a change in a neutral point voltage, which is a potential difference between the first and second neutral points; The power conversion device according to claim 6 , wherein the hysteresis comparator compares the upper limit value and the lower limit value after processing by the dead time compensation unit with the current detection value from which the fluctuation component has been removed by the current compensation unit.

8. A control method for a power conversion device, comprising: a power conversion circuit having first and second switching elements connected in series between first and second electric wires; and controlling on / off of the first and second switching elements so that a dead time is provided during which both the first and second switching elements are off when the first and second switching elements are switched on / off, a step of controlling on / off of the first and second switching elements by hysteresis control based on a comparison between a detection value of an amount of electricity handled in power conversion by the power conversion circuit and an upper limit value and a lower limit value of a hysteresis band including a command value of the amount of electricity, The controlling step includes: generating a hysteresis bandwidth in the hysteresis control according to target values ​​of switching frequencies of the first and second switching elements; setting the upper limit value and the lower limit value according to the hysteresis band width and the command value; a step of performing dead time compensation for adding a compensation amount to the set upper limit value and the set lower limit value in order to prevent the detection value from going outside the hysteresis band during the dead time; operating a hysteresis comparator to compare the upper limit value and the lower limit value after the dead time compensation with the detection value; generating on / off control signals for the first and second switching elements based on an output signal of the hysteresis comparator so that the dead time is provided; A control method for a power conversion device, wherein, in the dead time compensation, a compensation amount of a different polarity is added to one of the upper limit value and the lower limit value, which differs depending on whether the detected value is positive or negative.

9. The method further includes the step of preventing a difference between the upper limit value and the lower limit value after the dead time compensation from becoming smaller than a predetermined limit value, 9. The control method for a power conversion device according to claim 8, wherein in the preventing step, when the difference is smaller than the limit value, the upper limit value and the lower limit value used in the hysteresis comparator are modified so that the limit value is ensured.

10. the power conversion circuit has a plurality of legs each formed of the first and second switching elements, and is configured to perform power conversion between a DC voltage source having a positive electrode and a negative electrode connected to the first and second electric wires, and an AC voltage source connected to each of the legs; The power conversion device is a reactor connected between a connection point of the first and second switching elements of each leg and the AC voltage source, The method for controlling a power conversion device according to claim 8 or 9, wherein the detection value is a detection value of a current passing through the reactor.

11. At least one of a first neutral point of the DC voltage source and a second neutral point of the AC voltage source is not grounded, The controlling step includes: The method further includes a step of canceling a fluctuation component of the current detection value caused by a change in a neutral point voltage, which is a potential difference between the first and second neutral points; The method for controlling a power conversion device according to claim 10 , wherein the hysteresis comparator compares the upper limit value and the lower limit value after the dead time compensation with the current detection value from which the fluctuation component has been removed by the canceling step.

12. A power conversion device as described in any one of claims 1 to 7, wherein the compensation amount is calculated using a switching period which is the inverse of a target value of the switching frequency, a ratio of an off period length of the first or second switching element for controlling the electrical quantity immediately before the dead time to the switching period, and a predetermined period length of the dead time.

13. A control method for a power conversion device described in any one of claims 8 to 11, wherein the compensation amount is calculated using a switching period which is the inverse of a target value of the switching frequency, a duty ratio of the first or second switching element for controlling the electrical quantity just before the dead time, and a predetermined period length of the dead time.

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