Power Module

Abstract

To improve the heat transfer characteristics of a power module that enables a power conversion device with a power density of 150 kW / L, to reduce the power module losses by improving the switching speed, and to reduce the size of a cooler volume.SOLUTION: The module incorporates a self-inductance reduction design that cancels out magnetic fields resulting from current, prevents a value of potential of a gate drive signal from changing to an unexpected value due to inductance, by making a mutual inductance between current loops close to zero in principle by making current loop planes orthogonal to each other present in an inverter or converter, so as to enable high-speed switching. In addition, a module design with good heat transfer characteristics is employed. Thereby, it becomes possible to reduce losses and miniaturize a cooler and passive components.SELECTED DRAWING: None

Description

[Technical field]

[0001] The present invention relates to a power module, which is a power semiconductor device having terminals in a circuit formed using power switch elements having a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) or IGBT (Insulated Gate Bipolar Transistor) structure, exposed to the outside and assembled into a single package, and which has a surface for efficiently transferring heat generated from the power switch elements and a gate signal terminal and a gate signal reference potential terminal for operating the power switch elements, a driver circuit for operating the power module, a cooler for cooling the power module, a capacitor for suppressing fluctuations in input voltage, etc. [Background technology]

[0002] A circuit configuration in which one arm, with a power switch element and a diode connected in parallel, is connected in series and the desired power is extracted from the connection point of each arm, is called a half bridge, and a power module with two arms like this is called a 2-in-1 module. Similarly, a circuit configuration with two half bridges that uses the AC that appears between the connection points of each arm is called a full bridge. In particular, an inverter device that has three half bridges and can extract three-phase AC is called a three-phase inverter, and since it contains a total of six arms, it is called a 6-in-1 module.

[0003] The power density of power conversion devices using such modules has continued to improve with reference to a graph fitting the empirical rule of thumb for power density development in power conversion devices described in Non-Patent Document 1. Non-Patent Document 1 only goes up to 2020, but if this logarithmic graph is extended to 2025, it is expected that power conversion devices of around 60 kW / L in 2020 and 150 kW / L in 2025 will be commercialized.

[0004] In order to realize such a power conversion device with a high output density, which has long been desired, it is necessary to improve the heat transfer characteristics from the power switch elements to the outer surface of the module and to reduce loss in the power switch elements.

[0005] In recent years, power modules have been getting smaller and their chip areas have been reduced, and as a result, many products are being sold that allow for a reduced heat transfer area, which in turn deteriorates the heat transfer characteristics of the heat transferred from the elements inside the power module to the heat dissipation equipment.

[0006] In addition, while it is desirable to reduce the loss of power switching elements, there is a limit to how much the switching speed can be increased, which limits the reduction in loss and limits the miniaturization of coolers. In addition, there is a problem that the operating frequency cannot be increased due to the limit to how much the switching speed can be increased, and passive components that require values ​​inversely proportional to the operating frequency cannot be miniaturized. In particular, the volume of passive elements accounts for a large proportion of the volume of modern power conversion devices. Therefore, the difficulty of miniaturizing passive elements is a major obstacle to miniaturizing the entire power conversion device and improving power density.

[0007] In other words, the factors that prevent the improvement of switching speed are obstacles to miniaturization and high output density of power conversion devices.

[0008] Here, we will briefly touch upon the differences in switching speed and element losses resulting from element structure. Conventionally, in the power range of 1 kV or more withstand voltage and 100 A or more, IGBTs have been used because they can use both positive and negative carriers, unlike MOSFETs which only use a single carrier, and have relatively good V-I characteristics when on, even with an element structure that has an increased element thickness to obtain a high withstand voltage. However, this IGBT structure has a structural problem called tail current, in which the current cannot be immediately cut off, because some of the carriers that were flowing when the switch was turned off cannot be completely eliminated.

[0009] In other words, in the conventional power range with a withstand voltage of 1 kV or more and a current of 100 A or more, there was a limit to the switching speed due to factors derived from the element structure. Therefore, in the case of Si-IGBTs using Si (Silicon) semiconductor material, attempts have been made to improve the switching speed by manipulating the trade-off relationship between the VI characteristics per element area and the switching speed by adjusting the concentration of dopants that act as carriers. However, this method made it difficult to reduce both the conduction loss and switching loss per unit area in the IGBT. In addition, improving the switching speed is theoretically more difficult than with unipolar devices.

[0010] In recent years, by using SiC (Silicon Carbide) material instead of Si material, it is possible to reduce the element thickness while obtaining sufficient voltage resistance even with a MOSFET structure, so that the on-resistance can be reduced even when handling voltages of several kV or more, and because it is a unipolar device, there is no problem with tail current. SiC-MOSFETs, which can switch at high speed, have been put into practical use and are becoming more and more popular, mainly in trains, etc. SiC-MOSFETs can achieve both low conduction loss and low switching loss.

[0011] Thanks to the performance improvements in power switch elements as described above, high-speed switching in the order of several tens of nanoseconds has become possible on a power switch element chip in recent years, even when a voltage of 1 kV is applied and a current of 100 A is switched.

[0012] However, problems have emerged that make it difficult to achieve high-speed switching on the order of tens of nanoseconds, due to parasitic inductance that occurs in the wiring between the gate of the power switch chip and the gate driver circuit that is connected to the package or power module that contains the power switch chip, and mutual inductance coupling between the main current loop that turns the power switch on and off and the gate signal current loop.

[0013] In other words, in modern times, the switching speed of power switch elements is not limited by the element structure, but rather it is the parasitic inductance and mutual inductance outside the element chip that limit the improvement of the switching speed of the power switch elements, becoming a bottleneck.

[0014] In reality, there should be no need to supply a large amount of current to the gates of MOSFETs and IGBTs, which are voltage-operated devices. However, because MOSFETs and IGBTs contain junctions of different materials, a significant amount of parasitic capacitance is generated, and self-inductance and mutual inductance become obstacles when passing current to charge and discharge this capacitance.

[0015] In order to instantly operate the gate voltage, which determines the on / off state of a switching element in a MOSFET or IGBT structure, to the desired value, it is necessary to supply a sufficient drive current to charge and discharge the parasitic capacitance described above, and to draw the current out of the gate section fast enough. Unless the charge stored in the parasitic capacitance is transferred sufficiently, the potential difference across the parasitic capacitance of the gate section will not reach the desired value. In other words, unless the gate driver current is sufficient, the gate-source voltage in the case of a MOSFET, or the gate-emitter voltage in the case of an IGBT, cannot change to the designed gate-on voltage, for example, 15 V or 18 V, or the designed gate-off voltage, for example, 0 V or -2 V, within the specified time.

[0016] Below, we will explain the principle of the phenomenon in which high-speed switching becomes difficult due to parasitic inductance and mutual inductance, and the conventional techniques used to deal with this problem. Furthermore, we will explain how it is difficult to improve the output density of a power conversion device using designs using these conventional techniques.

[0017] When the gate driver circuit inputs an on / off signal to the power switch element, the parasitic inductance that exists in the path from the gate driver circuit to the gate pad of the MOSFET or IGBT prevents the rise of the current that flows to charge the gate parasitic capacitance.

[0018] However, since the gate current rises at high speed even though it is blocked by the parasitic inductance, an abnormal voltage is generated in the gate voltage due to the product of the time differential value of the current and the parasitic inductance.

[0019] Furthermore, due to mutual inductance coupling occurring between the gate signal current loop and the main current loop, the product of the on / off current change of the main current flowing through the power switch (for example, the current differential value of several hundred amperes) and the mutual inductance is fed back to the gate signal, disrupting the input gate signal. This disrupted gate voltage creates a vicious cycle that disrupts the operating characteristics of the power switch element.

[0020] Although mutual inductance is proportional to the cosine of the angle between the current loop planes, meaning that its effect varies from 0 to 1 depending on the angle, many power converters are seen that have a gate driver circuit parallel to the top surface of the circuit pattern on which the power switch elements are mounted. These can be said to be power converters designed so that, in principle, the effect on the gate driver of changes in the main current flowing through the power switch is maximized with respect to the angle between the loop planes.

[0021] The phenomenon of abnormal voltages caused by parasitic inductance and mutual inductance between current loops, and abnormal voltages fed back by the interaction between the gate signal and the main current, are actually observed as overshoots and ringing in the gate voltage, the MOSFET drain-source voltage, and the IGBT collector-emitter voltage. Such phenomena can cause the power switch element and the gate driver circuit to break down.

[0022] In order to reduce the adverse effects of parasitic inductance and mutual inductance on switching, a resistor is generally provided at the gate to reduce the amount of current flowing through the gate pin and intentionally slow down the switching speed. This reduces overshoot, undershoot, and ringing of the gate signal caused by parasitic inductance in the gate signal pin, source signal pin, and emitter signal pin, and also reduces abnormal gate voltage propagated by mutual inductance by increasing the rise and fall times of the current flowing between the drain and source of a MOSFET or between the collector and emitter of an IGBT.

[0023] However, if such a design is made to intentionally reduce the switching speed, the switching loss of the element increases due to the slow switching speed, and the increase in the loss increases the element temperature, so that it becomes necessary to enlarge the cooler. In this case, if the thermal resistance between the power switch element and the cooler is large, even if the cooler is at a low temperature, the element cannot be sufficiently cooled, and the element loss allowable in the power switch element further decreases. In this way, if the heat transfer characteristics or cooler are such that the element cannot be sufficiently cooled, an upper limit is placed on the operating frequency that determines the repeated switching loss per unit time. In addition, it becomes impossible to miniaturize passive elements that require a value inversely proportional to the operating frequency. In addition, in this case, a design method is required to improve the heat transfer characteristics by enlarging the element area and the module heat dissipation area, which leads to an increase in the element cost and an increase in the module area, making it even more difficult to miniaturize the power conversion device.

[0024] Due to these relationships, the heat transfer characteristics and parasitic inductance of the power module, the mutual inductance coupling between the current loops, and the conventional techniques for dealing with these problems are obstacles to improving the output density of the power conversion device.

[0025] Among the background art and problems in the power conversion device described above, patent documents related to improving the characteristics of the current loop are introduced below.

[0026] Patent Document 1 describes the angle of the wire bonding that connects from one surface of the power switch element to the wiring pattern, and includes the intention of designing a current flow loop.

[0027] Patent document 2 describes attempts to reduce the effective parasitic inductance by reducing the main current loop area through devising an electrode structure inside the power module, thereby reducing magnetic flux radiation, and by opposing the main current loop directions at the positive and negative electrodes, canceling out the magnetic fields originating from both the positive and negative directions, and to suppress the effects of control terminal noise from the main terminal by defining the gate emitter pin loop surface and preventing coupling between the gate pin current loop surface and other current loop surfaces.

[0028] Patent Document 3 describes a power module in which a conductor pattern is mounted on an insulator and a switch element is mounted on top of that, so that the main current passing through the switch element passes through a conductive pattern provided on the back side of the insulator when viewed from the switch element.Since the current loop of this module has a thickness equivalent to that of one sheet of insulator, it is expected that the magnetic flux generated from the surface of the main current loop will be reduced.

[0029] All of the cited patent documents include design intentions and claims for making the circuit pattern of the current loop more convenient. However, even if the technologies shown in these patent documents are used, it is not possible to achieve both a design that sufficiently suppresses the phenomenon in which fluctuations in main current, which occur when a power switch element in a power conversion device is switched at high speed, propagate to a gate signal pin or a gate driver circuit in a power module and disturb the gate signal, and a design that sufficiently transfers heat generated by the power switch element to the outside.

[0030] Patent Document 1 describes that one side of a power switch element is disposed on a first wiring pattern, and the other side of the disposed power switch is connected to another second wiring pattern by wire bonding, and the angle of the wire is approximately perpendicular to the second wiring pattern. As described above, Patent Document 1 includes the intention of designing a main current loop, and also includes a design example in which a gate external terminal and a gate reference potential external terminal are adjacent to each other. That is, a configuration is shown in which the gate pin loop area is reduced and the gate pin is perpendicular to the main current loop plane, thereby making the gate pin loop plane and the main current loop plane perpendicular to each other. However, the invention described in Patent Document 1 does not take into consideration the mutual inductance coupling between the gate driver circuit and the main current loop plane.

[0031] Patent Document 2 describes an attempt to prevent noise propagation from a current loop plane to a gate pin current loop plane by defining a gate emitter pin loop plane. One of the gate emitter pin loop planes described in the document is parallel to the main current plane on which the power switch element is mounted, and the magnetic flux generated by the one plane cancels out the magnetic flux generated from the AC output terminal, thereby reducing noise caused by inductance generated in the gate pin and emitter pin. However, when a gate driver circuit is provided at the position described in Patent Document 2, the current loop plane of the gate driver circuit and the main current loop plane of the above-mentioned power switch element mounting surface become parallel, so there is a risk of potential fluctuation on the gate driver circuit due to mutual inductance coupling.

[0032] In the power module described in Patent Document 3, the magnetic flux generated from the main current loop surface is reduced because the current loop passing through the power switch element has a thickness equivalent to that of one sheet of insulation, and the parasitic inductance is effectively reduced by the current passing through both sides in opposite directions. Since the main current loop surface is formed in the side direction of the insulating plate, even if the gate driver circuit is provided parallel to the power module plate surface direction described in Patent Document 3, the gate driver circuit current loop surface and the main current loop surface are configured to be perpendicular to each other, so there is little possibility that the gate signal or the operation of the power switch element will be disturbed due to mutual inductance coupling between the two current loop surfaces. However, the power module described in Patent Document 3 needs to have conductive patterns on both sides sandwiching the insulating substrate, and therefore the heat transfer characteristics from the power switch element to the external cooler are inferior to designs that do not require this.

[0033] Although not cited as a reference, the calculated value of the gate driver voltage that fluctuates due to mutual inductance when a gate driver circuit is installed on a general box-type 2-in-1 power module is shown below. The current loop area S1 flowing through the power module is 4.00×10 -3 m 2 The current flowing through this current loop surface is 200 A, and the output side loop area S2 after insulation of the gate driver circuit is 1.44 × 10 -4 m 2 , the loop center distance d is 3.40×10 -2 m 2 When the current change time when cutting off the current flowing through S1 is 40 ns, the mutual inductance is 1.47 nH, and the voltage generated on the loop area S1 due to mutual inductance coupling reaches 7.33 V. Typically, the gate voltage of Si-MOSFETs and Si-IGBTs is designed to be approximately 15 V, and that of SiC-MOSFETs is approximately 18 V. Furthermore, the gate withstand voltage of each element is an upper limit of 20 to 25 V, and a lower limit of approximately -5 V. Overshoot or undershoot exceeding 7 V can cause destruction of the gate of MOSFETs or IGBTs.

[0034] Therefore, as mentioned above, it is necessary to design the switching speed to be intentionally slowed down. For example, in the case of this power module and gate driver circuit pattern layout, the voltage generated in the gate current loop S2 can be reduced to about 0.98 V by slowing the switching speed from 40 ns to about 300 ns.

[0035] However, as mentioned above, slowing down the switching speed increases the switching loss, which is the loss that occurs during the time when current and voltage are applied simultaneously, and the cooler required to cool this loss becomes larger. Also, when the operating frequency is increased, the switching loss per unit time increases more than in devices capable of high-speed switching, so the operating frequency, which is the repetition frequency of the switching loss, cannot be increased, making it difficult to miniaturize passive elements.

[0036] As described above, the means described in the background art cannot switch power switch elements at a sufficient speed. Although the switching speed of a single power switch element is on the order of several tens of nanoseconds, the parasitic inductance of the power module and gate driver circuit and the mutual inductance between each current loop are bottlenecks in the switching speed of the power switch element. [Prior art documents] [Patent documents]

[0037] [Patent Document 1] JP2002-153079A [Patent Document 2] Patent Publication No. 2016-119430 [Patent Document 3] International Publication No. WO 2019 / 221242 [Non-patent literature]

[0038] [Non-Patent Document 1] Hiromichi Ohashi, "Trends in the Latest Power Devices," Journal of the Institute of Electrical Engineers of Japan, (2002) Summary of the Invention [Problem to be solved by the invention]

[0039] It has been expected for a long time that the output density of a power converter will be improved in accordance with the power converter development empirical rule described in Non-Patent Document 1. In order to achieve this, it is desirable to improve the heat transfer characteristics of the power module, reduce the loss of the power module by improving the switching speed, and reduce the volume of the cooler. Furthermore, by making it possible to improve the operating frequency by reducing the loss, it is desirable to also reduce the size of passive elements that require values ​​inversely proportional to the operating frequency. In particular, since passive elements occupy a relatively large proportion of the total volume of the power converter compared to other components, miniaturizing the passive elements effectively works to reduce the volume of the entire power converter. In order to improve the switching speed, it is necessary to reduce the parasitic inductance and mutual inductance, thereby reducing the adverse effect of these inductances on switching. These issues of heat transfer characteristics and issues of switching characteristics caused by inductance are the issues that the present invention aims to solve. [Means for solving the problem]

[0040] The DC positive bus plate and the DC negative bus plate on which the power switch elements in the power module are mounted are arranged in parallel without overlapping, and the phase output bus plate connecting the power switch elements mounted on each bus plate is provided on a plane different from the plane of the DC positive bus plate and the DC negative bus plate. The insulating surface provided in the path for transferring heat from these bus plates to the cooler does not have any foreign matter on the surface opposite to the bus plate surface as a power module. Furthermore, a gate signal pin is provided in a direction perpendicular to the direction of direct current flowing through the DC positive bus plate and the DC negative bus plate, a gate signal reference potential pin is provided in a position parallel to the gate signal pin, and the distance between the gate signal pin and the gate signal reference potential pin is made closer to a distance that allows insulation. In addition, the power module internal configuration and the gate driver circuit, and their respective mounting arrangements, are provided such that the main current loop plane including the DC positive bus plate plane and the DC negative bus plate plane, the gate signal current loop plane, and the gate driver circuit current loop plane are orthogonal to each other or have a gate driver circuit within a range of 90 ±10 deg. Effect of the Invention

[0041] Since the heat of the power switch element mounted in the power module can be transferred to the outside from both sides of the power switch element, the heat dissipation is higher than that of a power switch element that dissipates heat from one side. In addition, since there is no conductive pattern, fixing metal fittings, or other insulators on the back of the insulating surface, the thermal resistance is smaller than that of a power switch element that does have these. Furthermore, since the distance between the gate signal pin and the gate signal reference potential pin is short and they are in the opposite direction, the magnetic fields generated by the currents flowing through them cancel each other out, reducing the parasitic inductance of the pin. In addition, the gate signal pin current loop area is reduced. Furthermore, since the main current loop plane, the gate signal pin current loop plane, and the gate driver circuit current loop plane are perpendicular to each other, the mutual inductance between each loop plane is almost 0. When the angle θ between each plane is not 90 deg. but is within the range of θ = 90 ± 10 deg., this mutual inductance value is proportional to Cosθ. These effects of reducing the self-inductance and mutual inductance eliminate the need to reduce the current value of the gate drive signal and the design to reduce the switching speed due to this, and high-speed switching of the power switch element is realized. Since the power switch element can be stably switched within a time of about 10 to 40 ns, the repetition frequency can be increased sufficiently even in power conversion devices that handle large amounts of power, such as 80 kW to 150 kW. For example, this repetition frequency exceeds 100 kHz. This high-frequency operation allows passive elements to be made smaller, and high-speed switching reduces losses, allowing coolers to be made smaller, greatly improving the output density of power conversion circuits, especially those with input voltages of 600 V or more. [Brief description of the drawings]

[0042] [Figure 1] 6 in 1 module diagram [Diagram 2] 6 in 1 module circuit diagram [Diagram 3] Schematic diagram showing a simplified variant of the 6 in 1 module [Figure 4a] 6 in 1 module mounting diagram a [Figure 4b] 6 in 1 module mounting diagram b [Diagram 5] 6 in 1 module mounting front view [Figure 6] Example of a three-phase inverter system [Figure 7] Exploded view of 3-phase inverter system [Figure 8] Schematic diagram of a three-phase inverter circuit [Figure 9] Orthogonal diagram of current loops in a three-phase inverter DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0043] The present invention is characterized in that the main current loop plane in the power module, the gate signal pin current loop plane, and the output section current loop plane of the gate driver circuit are perpendicular to each other.

[0044] Power switch elements and power diode elements are mounted on the DC positive bus plate and DC negative bus plate in the power module. There are no restrictions on the area of ​​these elements or the number of parallel mounting, but it is preferable that the total area of ​​the power switch elements and power diode elements is as close as possible to the required power module bottom surface area, which improves the rigidity and heat transfer characteristics of the entire power module, as well as the power handling capacity and heat transfer efficiency per module volume.

[0045] The power switch element mounted on the DC positive bus plate in the power module may have an IGBT structure, a MOSFET structure, a DMOSFET (Double Diffused MOSFET), an IE-IGBT (Injection Enhanced-IGBT), an SJ-MOSFET (Super Junction MOSFET), a UMOSFET (U-shaped trench gate MOSFET), an SJ-UMOSFET, or other structures. The material used for the power switch element may be Si or SiC.

[0046] It is more preferable that the gate terminal pad formed on the outer surface of the power switch element is formed on the outer edge of the element, not in the center of the power switch element. The power diode element having a function as an FWD (Free Wheeling Diode) provided in inverse parallel to the power switch element may be of a PIN (a structure in which a P-type semiconductor, an I-type semiconductor, and an N-type semiconductor are stacked) diode structure or an SBD (Schottky Barrier Diode) structure, but in consideration of the problem and means to be solved by the present invention, a diode that can be switched at high speed is more preferable.

[0047] The number of phase output bus plates that connect the power switch elements is equal to the number of phases in the power module. The current flowing through the DC positive bus plate and DC negative bus plate is combined with the current flowing through the phase output bus plate to form a main current loop surface.

[0048] At this time, the current flowing through the power switch elements and power diode elements is combined with the current flowing through the phase output bus plate to form a U-shaped current loop surface in the thickness direction of the power module. Although the area of ​​this loop surface is very small, it is desirable for this loop surface to be in an orthogonal relationship with the three loop surfaces mentioned above.

[0049] The input / output terminals of the phase output bus plate are arranged perpendicular to the current flow direction of the DC positive bus plate of the power module, and it is desirable that the direction of current flowing to the phase current measuring device connected to this be perpendicular to the current loop plane passing through the gate driver circuit output section.

[0050] The phase input / output terminals, DC input / output terminals, gate signal pins, and gate signal reference potential pins may have a curved shape due to the points where they protrude from the DC positive bus plate, DC negative bus plate, and phase output bus plate, respectively. It is desirable to ensure that the insulation distances of the four types of pins described above are adequate, and that the distance between the pin tips is adequate so that the female terminals that receive the pins can be properly laid out.

[0051] Furthermore, since the entire power module generates heat due to losses in the power switch elements and buses, it is expected that each bus plate and the four types of pins will expand and extend. It is desirable to provide the four types of pins with slopes that can mitigate the effects of such expansion and extension. Furthermore, a design in which the above four types of pins are connected by female terminals that have a spatial margin that does not hinder the expansion and extension of such pins is more suitable for a high-output density power conversion device.

[0052] It is more preferable that the insulator inserted between the gate signal pin and the gate signal reference potential pin, which are provided at a position where the two pins are close to each other, is low dielectric. In light of the purpose of the present invention, it is desirable that the parasitic capacitance generated between the gate signal pin and the gate signal reference potential pin is as small as possible. The gate signal pin parasitic capacitance causes a decrease in the rise and fall speed of the gate signal.

[0053] The gate signal pin and the power switch element may be connected by wire bonding, by a metal film with some deformation, or by directly soldering the gate signal pin that has sufficient rigidity. These connection methods may be applied to any of the switches arranged in the upper and lower arms and in multiple phases.

[0054] When wire bonding or metal film is used, even if the distance between the gate signal pin to be connected and the power switch element changes due to the DC positive bus plate, DC negative bus plate, or phase output bus plate being deformed by heat, the amount of change can be absorbed by the deformation of the wire or film.

[0055] When a metallic gate signal pin is soldered directly to the gate terminal of the power switch element, in order to reduce the possibility of each part being damaged due to differences in the thermal expansion coefficients of the metal plate, each bus plate, and the power semiconductor element, each part is filled with resin having a thermal expansion coefficient close to that of the other parts, and the gate signal pin soldered directly to the power switch element is not supported only by the power switch element, but is fixed so that it is sandwiched between a heat transfer part provided in the direction of the power module surface and a support structure that supports the gate signal pin.

[0056] It is more preferable that the cooler has the strength to resist deformation of the power module caused by the expansion and extension of the DC positive bus plate, DC negative bus plate, and phase output bus plate. In addition, it is preferable that the cooler is designed to apply uniform stress in the direction of the surface of the power module. In this case, by designing the power module with consideration of how the components inside the power module, especially the bus plates and input / output pins, are deformed in the longitudinal direction due to the pressure applied to the power module by the cooler, it is possible to configure a power module and gate driver circuit that are less likely to be destroyed by loss, heat generation, or deformation.

[0057] It is more preferable for the gate driver circuit board, which is arranged on a plane perpendicular to the power module main current loop plane and the gate signal pin current loop plane, to have a pattern design in which the path from the portion connected to the gate signal pin or gate signal reference potential pin to the gate driver IC output pin is short and the spacing between the patterns connected to both pins is narrow.

[0058] In addition, the gate driver circuit is configured so that the insulating part of the gate driver IC and the insulating part of the power supply for the output side of the gate driver IC overlap on the same straight line, or the gate driver IC and the power supply for the output side of the gate driver IC are arranged separately on both sides of the gate driver circuit board, and the insulating parts between the IC and the power supply respectively overlap on a straight line on both sides of the board.

[0059] The length of the gate driver circuit board in the thickness direction of the cooler is referred to as the gate driver circuit board longitudinal direction. If the dimensions of the gate driver circuit board and the cooler are designed so that the end point of the gate driver circuit board longitudinal direction, which faces the gate signal pin, is closer to the power module side than the end point of the cooler in the thickness direction, the protrusions of the entire power conversion system are reduced, resulting in a design with good volumetric efficiency that is advantageous for making the power conversion system more compact.

[0060] The inside of the power module is filled with a resin material that has a thermal expansion coefficient similar to that of the DC positive bus plate, DC negative bus plate, and phase output bus plate. This reduces the possibility of each part inside the power module breaking due to the difference in deformation of the joint surface caused by the difference in the amount of expansion of the contact surface due to the difference in the thermal expansion coefficient when the power module generates heat and expands.

[0061] When mounting the DC positive bus plate and the DC negative bus plate on the insulating material, metal brazing may be used, or the connection may be made with solder that has a thermal expansion coefficient close to that of the insulating material and the bus plate. In addition, other thermally conductive materials with high creep properties may also be used. The same applies to the connection between the phase output terminals and the insulating material on the other side of the power switch elements and power diode elements.

[0062] In this case, by using an insulating material with a thermal expansion coefficient similar to that of the bus plate and resin filling material, the possibility of the power module being destroyed when it is heated or cooled can be reduced. In recent years, research has been progressing on using Si3N4 material, which has a thermal expansion coefficient close to that of the semiconductor material, as an insulating material, and by using this, the possibility of the material being destroyed due to the difference in expansion area between the insulating material and the semiconductor can be reduced.

[0063] When filling the power module with resin material, pressure is applied between the outermost surfaces inward while maintaining a certain degree of accuracy so that the two insulating materials on the outermost surfaces are parallel to each other. During this process, the temperature of each part of the power module during manufacture is preheated to a certain temperature, and after filling with resin, the temperature of the entire power module is cooled to the storage temperature.

[0064] Example 1 1 shows a view of the 6-in-1 module in Example 1 and Example 2 with one insulating surface peeled off. In the 6-in-1 module, DC positive terminal 111 and DC positive bus plate 110, DC negative terminal 121 and DC negative bus plate 120, and DC side insulating plate 102 are mounted on the DC side insulating plate via solder, heat conductive material, or brazing material. It is even better if the mounting solder contains the same material as DC positive bus plate 110 and DC negative bus plate 120.

[0065] Phase output terminals are provided in a direction perpendicular to the DC positive terminal 111 and the DC negative terminal 121, and are respectively a U-phase output terminal 131, a V-phase output terminal 141, and a W-phase output terminal 151. A capacitor is provided between the DC positive bus plate 110 and the DC negative bus plate 120 via a P-type terminal shown as 161c in Fig. 5. The U-phase is provided with capacitors 161a and 161b, the V-phase is provided with capacitors 171a and 171b, and the W-phase is provided with capacitors 181a and 181b.

[0066] Figure 2 shows a schematic circuit diagram of the 6-in-1 module in Example 1 and Example 2. The reference symbols in the figure are the same as those in Figures 1, 3, 4a, and 4b. In the schematic circuit diagram, capacitors are depicted in positions according to the layout. For example, in the case of the U phase, capacitors 161a and 161b are written next to the MOSFET and FWD.

[0067] Since there are two MOSFETs and two FWDs in the first embodiment, the number of elements is also written in Fig. 2. Fig. 3 shows a circuit diagram with a different number of elements from that in Fig. 1. As shown in Fig. 3, which is a simplified circuit, the present invention may be applied to a modified example in which one MOSFET and one FWD are used for one arm and no capacitor is provided for each phase. Also, more than three elements may be introduced in parallel in one arm.

[0068] 4a and 4b show mounting diagrams of the 6-in-1 modules in the first and second embodiments. Two high-side MOSFETs for each phase are mounted on the DC positive bus plate 110 mounted on the DC side insulating plate 101 so that their drain surfaces are in contact with each other. Similarly, two low-side MOSFETs for each phase are mounted on the U-phase output bus plate 130, the V-phase output bus plate 140, and the W-phase output bus plate 150 so that their drain surfaces are in contact with each other. The MOSFETs may have an IGBT structure as long as they are switching elements, and any element structure such as UMOSFET, SJ-MOSFET, or IE-IGBT may be used. Also, either Si or SiC may be used as the semiconductor material.

[0069] According to the study, the high-side switch elements 133a, 133b, 143a, 143b, 153a, and 153b and the low-side switch elements 135a, 135b, 145a, 145b, 155a, and 155b have an element area of ​​0.42 cm. 2 By using these SiC-MOSFETs, a three-phase inverter with an output voltage of 650 V, an output of 150 kW, and a power density of 150 kW / L can be realized. Two FWDs are mounted on each arm of each phase near each MOSFET, and on the U-phase high side, these correspond to 132a and 132b. These FWDs can be of either a PIN structure or an SBD structure.

[0070] To prevent electrolytic corrosion and rust, plating is applied to the DC positive bus plate 110, the DC negative bus plate 120, the phase output bus plates 130, 140, 150, the gate signal pins 136, 139, 146, 149, 156, 159, the source signal pins 137, 138, 147, 148, 157, 158, the DC positive terminal 111, and the DC negative terminal 121. Grooves are provided only at positions where MOSFETs are mounted among the DC positive bus plate 110, the DC negative bus plate 120, and the phase output bus plates 130, 140, 150, and plating is applied with gold flash or the like to enhance solder wettability and prevent solder from leaking to unexpected positions.

[0071] The gate terminals of the high-side MOSFETs are directly soldered to the U-phase high-side gate signal pin 136, the V-phase high-side gate signal pin 146, and the W-phase high-side gate signal pin 156, respectively, and each high-side gate signal pin is soldered to the DC positive bus plate 136 via an insulating material. This insulating material may be, for example, Al2O3 or Si3N4. By using an insulating material with a thermal expansion coefficient close to that of a Si power switch element or a SiC power switch element, the possibility of the power switch element being destroyed by stress generated at the gate signal pin or the joint surface between the solder and the power switch element due to the difference in thermal expansion coefficient between the insulator and the power switch element when heat is generated is reduced.

[0072] The gate signal pins of the low-side MOSFETs are provided with an insulating distance so as to be parallel to the phase output plates 130, 140, 150 mounted on the phase output side insulating plate 101. The U-phase low-side gate signal pin 139 is connected to the U-phase MOSFETs 135a, 135b using metal films 162a, 162b, respectively. Similarly, the V-phase low-side gate signal pin 149 is connected to the V-phase MOSFETs 145a, 145b using metal films 172a, 172b, respectively, and the W-phase low-side gate signal pin 159 is connected to the W-phase MOSFETs 155a, 155b using metal films 182a, 182b, respectively.

[0073] At this time, in order to prevent the gate terminal from shorting out with the DC negative bus plate, recesses 163, 173, and 183 are provided in the DC negative bus plate, and the metal film connects between the gate pad and the gate terminal of the power switch element via each recess.

[0074] A 0.2 mm thick insulator is sandwiched between the 0.3 mm thick high side gate signal pin and the 0.3 mm thick high side source signal pin by soldering with a thickness of 0.1 mm on one side, and the insulator between the high side gate signal pin and the DC positive electrode bus plate 110 is 0.1 mm thick and fixed by soldering with a thickness of 0.1 mm on one side. This insulator may be made of Si3N4 with a withstand voltage of 31 kV / mm, or other materials may be used as long as the insulator maintains a withstand voltage of 2 kV or more.

[0075] Solder is applied to the switch element and FWD so that the phase output side insulating plate 101 shown in FIG. 4a and the DC side insulating plate 102 shown in FIG. 4b on which the various components are mounted are parallel to each other, and they are joined by pressure welding and then reflow.

[0076] Each low-side source signal pin 138, 148, 158 has a shape extending from the DC negative bus plate 120 and protrudes in a direction perpendicular to the current flow direction of the DC negative bus plate 120. An appropriate distance is provided between the end of the low-side gate signal pin 139, 149, 159 and the end of the low-side source signal pin 138, 148, 158 to provide a female terminal, and in the embodiment shown in the figure, the distance is 1.7 mm.

[0077] Each high-side source signal pin 137, 147, 157 is connected to the side of each phase output bus plate 130, 140, 150, and may be integrally formed when forming each phase output bus plate. Each high-side gate signal pin 136, 146, 156 is deformed from the point where it passes through the side of the positive bus plate 110, and an appropriate gap is provided between the end of each high-side source signal pin 137, 147, 157 and the end of the corresponding high-side gate signal pin 136, 146, 156 to provide a female terminal. In the embodiment shown in the figure, the gap is 1.7 mm.

[0078] The low-side gate signal pin and low-side source signal pin in each phase, and the high-side gate signal pin and high-side source signal pin in each phase are parallel to each other, and it is desirable that the current plane generated by the current flowing through the center of the low-side gate signal pin in a certain phase and the current flowing through the center of the low-side source signal pin in that phase is perpendicular to the plane of the DC negative bus plate 120, or within a range of 90 ±10 deg. Similarly, it is desirable that the current flowing through the center of the high-side gate signal pin in a certain phase and the current plane flowing through the center of the high-side source signal pin in that phase are perpendicular to the plane of the DC positive bus plate 110, or within a range of 90 ±10 deg. This is because the mutual inductance between the current loops is proportional to Cosθ when the inter-plane angle is θ.

[0079] 1 and 2 of the first embodiment, if the inter-plane angle between the current loop plane of V-phase high-side gate signal pin 146 and V-phase high-side source signal pin 147 and the main current loop plane through which a current of 200 A flows through the V-phase output bus plate is in a parallel relationship of 0 deg., the voltage resulting from mutual inductance coupling generated in the high-side gate voltage reaches 3.79 V. Similarly, in the W-phase, it becomes 4.07 V. If this inter-plane angle is 90 deg., the voltage generated in the V-phase high-side gate signal is 0 V, and similarly, the voltage generated in the W-phase gate signal is also 0 V.

[0080] In this case, if the inter-plane angle has a tilt of ±10 deg. with respect to the perpendicular direction, the voltage resulting from mutual inductance coupling generated in the V-phase high-side gate voltage corresponding to the sign of the tilt will be approximately ±0.14 V, and similarly the voltage resulting from mutual inductance coupling generated in the W-phase will be ±0.13 V. The 6-in-1 module 100 shown in Figures 1 and 2 of the first embodiment is characterized in that the change over time of the current flowing through the main current loop plane does not affect the gate signal, or the amount of change in potential exerted on the gate signal is within a range that does not pose a problem in terms of the quality of the gate drive signal.

[0081] The output terminals 131, 141, 151 for each phase are deformed to one side to prevent interference with the gate driver circuits 400, 500 and the current detection devices 630, 640, 650. This deformed portion has the effect of reducing the stress applied to the male terminals and female terminals on the module side and the contact points due to expansion when the power module generates heat, and reduces the possibility of damage to the power module and surrounding components.

[0082] In the 6-in-1 power module shown in Fig. 1, parasitic inductance exists between the DC input terminal 111 and each switch. When the current value flowing through this parasitic inductance changes suddenly, a voltage corresponding to the parasitic inductance is generated. In order to suppress this potential change, a capacitor connected by a P-type terminal is provided inside the power module.

[0083] When the current passing through is 200 A, the potential fluctuation due to this parasitic inductance is predicted to be about 20 mV depending on the inductance of the DC positive terminal for one phase, and about 100 mV depending on the inductance of the phase output terminal. This type of potential fluctuation is not a monotonous overshoot or undershoot observed once per switching, but rather oscillations occur due to the LCR circuit formed by the parasitic elements, resulting in ringing during switching. This ringing causes losses in the switching element and reduces the quality of the output power, so it is desirable to reduce it as much as possible.

[0084] Such potential fluctuations can be suppressed by the P-type terminal capacitors 161a, 161b, 171a, 171b, 181a, and 181b shown in the figure, which can also suppress uncontrolled potential fluctuations due to other factors.

[0085] 1, the distance from the DC positive terminal 111 to the W phase is greater than the distance from the DC negative terminal 121 to the U phase, and the distance from the DC negative terminal 121 to the W phase is greater than the distance from the DC positive terminal 111 to the U phase. This difference in distance also changes the influence of parasitic inductance, parasitic capacitance, and parasitic resistance on the current supplied to each phase switch when each phase is switched.

[0086] The influence of these parasitic inductances and parasitic resistances cannot be reduced by DC link capacitors (not shown) provided outside the DC positive terminal 111 and the DC negative terminal 121. The influence of the interphase parasitic elements described above can be reduced by the capacitors 161a, 161b, 171a, 171b, 181a, and 181b provided in each phase shown in Fig. 1, thereby reducing the charge shortage immediately after switching and reducing unexpected potential fluctuations.

[0087] Example 2 6 shows an inverter system using the 6-in-1 module 100 shown in FIG. 1. In the inverter system, both sides of the 6-in-1 module 100 are sandwiched between coolers 210 and 220, and a DC input capacitor 300 is connected to the 6-in-1 module 100.

[0088] When heat generation inside the 6-in-1 module causes DC positive bus plate 110 or DC negative bus plate 120 to generate stress that deforms DC side insulating plate 102, cooler 220 is designed to apply a force to DC side insulating plate 102 to offset the stress. Similarly, when each phase output plate 130, 140, 150 generates stress that deforms phase output side insulating surface 101, cooler 210 is designed to apply a force to phase output side insulating surface 101 to offset the stress.

[0089] The three-phase low-side gate driver assembly 400 and the three-phase high-side gate driver assembly 500 are removed and attached by the gate driver fixtures 410 and 510 in the same axial direction as the protruding direction of the gate signal pins of the 6-in-1 module.

[0090] The phase output current sensors 630, 640, 650 are attached and detached coaxially with the protruding direction of the phase output terminals corresponding to the phase output terminals 131, 141, 151. The phase output current sensors 630, 640, 650 each have a metal part bonded to a circuit board, and are cooled by bringing the metal part into contact with the side surface of the cooler 220.

[0091] Fig. 7 shows an exploded view of the inverter system shown in Fig. 6. The DC positive input terminal 312 and the DC positive output terminal 311 of the DC input capacitor 300 are connected by the same bus plate, and similarly, the DC negative input terminal 322 and the DC negative output terminal 321 are connected by the same bus plate. The respective electrodes are configured to be separated into left and right when the capacitor 300 is viewed from above in the figure.

[0092] The U-phase low-side gate driver circuit 430, the V-phase low-side gate driver circuit 440, and the W-phase low-side gate driver circuit 450 are each insulated and fixed to the low-side gate driver circuit fixture 410. Similarly, the U-phase high-side gate driver circuit 530, the V-phase high-side gate driver circuit 540, and the W-phase high-side gate driver circuit 550 are also each insulated and fixed to the high-side gate driver circuit fixture 510.

[0093] The volumetric efficiency increases as the cooler thickness direction length of these three-phase low-side gate driver assembly 400 and three-phase high-side gate driver assembly 500 approaches the total value of the thickness of the power module 100 and the thickness of the cooler 210. Also, if the elements mounted inside the 6-in-1 power module 100 and the gate driver circuit have a width close to the width of one phase occupying the DC positive bus plate, the volumetric efficiency similarly increases, and an inverter with higher power density can be designed.

[0094] Since there is a limit to how small the floating power supplies used in these gate driver circuits can be, the limit values ​​for the gate driver circuit area and volume are naturally determined according to the characteristics of the power switch element it drives, such as the parasitic capacitance, and the specifications of the power conversion device system. On the other hand, the fin spacing and flow rate at which the cooler functions efficiently are limited by the refrigerant, fin length, fin height, etc.

[0095] In other words, there are not many options for various design values ​​that will approximate the fin height and the length in the fin height direction in the gate driver circuit area described above when designing a cooler that can sufficiently cool and function efficiently with the loss that occurs in the 6-in-1 module 100 as shown in Fig. 6 and the area to transfer heat. The design example of the inverter system shown in Fig. 6 takes the above relationship into consideration compared to other designs, and is a design that can achieve a power density of 150 kW / L.

[0096] The inverter system circuit diagram shown in FIG. 6 is shown in FIG. 8. The circuit diagram shows high-side gate driver and low-side gate driver blocks for each phase. It also shows how current sensors are connected to phase output terminals 131, 141, and 151. The current sensors may be magnetic or shunt resistor type.

[0097] 9 shows the orthogonal relationship of current loops flowing through the inverter system in the second embodiment. When the W-phase high-side MOSFETs 153a and 153b are turned on, the current that has flowed through the DC positive bus plate 110 passes through the W-phase output bus plate 150 (not shown in the figure) and is output from the W-phase output terminal 151. Similarly, when the V-phase low-side MOSFETs 145a and 145b are turned on, the current that has been fed back from the V-phase output terminal flows through the DC negative bus plate 120, and the current is fed back to the DC input capacitor 300.

[0098] Since the flow of electrons is opposite to that of the current, the electrons that should be moving flow in the opposite direction to the above-mentioned flow process. During this time, the current loop surface is formed by the current flowing through the DC input capacitor 300, the DC positive bus plate 110, the V-phase output bus plate 140, and the DC negative bus plate 120, and the magnetic flux is generated radially from the center of this loop surface, passes through the outer periphery of each bus plate, and then forms a closed circuit with a path that returns to the back side of the loop surface.

[0099] However, in this embodiment, since coolers 210 and 220 are provided on both sides of 6-in-1 module 100, some of the above-mentioned magnetic flux is converted into current in the metal parts on the bottom surface of each cooler. This proximity effect is observed from each bus plate in the 6-in-1 module as AC resistance to the current flowing through each bus plate.

[0100] FIG. 9 shows that current loop planes 931, 941, 951 of the main current flowing through such a 6-in-1 module, a gate signal pin current loop plane 932 flowing through the U-phase high side gate signal pin 136 and the U-phase high side source signal pin 137, and a loop plane 933 of the drive current flowing through the U-phase high side gate driver circuit 530 are all orthogonal to each other.

[0101] In the figure, only the relationship between a current loop plane 933 passing through the U-phase high-side gate driver circuit and a current loop plane 932 passing through the U-phase gate driver signal pin is shown with respect to the current loop plane passing through the 6-in-1 module, but the above-mentioned loop plane orthogonal relationship holds between all current loop planes passing through the gate driver circuits shown in FIG. 7 and the gate signal pins and source signal pins shown in FIGS. 4a and 4b.

[0102] The orthogonal relationship between these current loop planes is shown in the three-axis diagram at the bottom center of Figure 9, where the main current loop plane inside the 6-in-1 module is shown by a dashed line, the gate signal pin current loop plane, which is the current loop between the gate signal pin and the source signal pin, is shown by a dashed line, and the current loop plane in the gate driver is shown by a dotted line.

[0103] As shown in the three-axis diagram in Fig. 9, the present invention is characterized in that the inverter main current loop plane, the gate signal pin current loop plane, and the current loop plane in the gate driver circuit board in such an inverter system are all perpendicular to each other. This characteristic is not limited to the three-phase inverter configuration as in the embodiment shown in Fig. 9, but also applies to a half-bridge configuration, a full-bridge configuration, and a four-phase configuration of a three-phase inverter + half-bridge.

[0104] This half-bridge or full-bridge configuration may be used to configure a booster, a step-down converter, or a bidirectional chopper circuit. Due to the features of the present invention, these circuits can switch faster than conventional circuits, enabling high-frequency operation, and the circuit constants of passive components such as choke coils and output smoothing capacitors can be made smaller than conventional ones, allowing the overall circuit to be made smaller.

[0105] The power modules shown in the first and second embodiments may operate as inverters or PFCs. They may function as inverters for operating traction motors for EVs and HVs, and may also operate as rectifiers or PFCs when recovering the back electromotive force obtained from the traction motors to storage batteries or the like.

[0106] Up until now, improvements in the power density of power conversion devices have been limited by the following two points. The first point is that the loss in the power switching elements is high, and coupled with the problem of thermal resistance per area when heat is transferred within the module, there is a limit to how small the cooler can be. The second point is that increasing the operating frequency also increases the loss, which places an upper limit on the operating frequency and limits how small the passive components can be.

[0107] According to the present invention, the parasitic inductance of each part is reduced. In addition, the mutual inductance between the gate driver circuit current loop surface, the gate signal pin current loop surface, and the main current loop surface is almost zero. This reduction in inductance allows the power switch element to switch at high speed, and the power modules described in the first and second embodiments have low loss. Furthermore, the power modules described in the first and second embodiments can be cooled from both sides, and the ratio of the surface area of ​​the mounted elements to the cooling surface area of ​​the module is close, and there is little waste in terms of surface area and volume, so the volume of the power module can be reduced. As described above, the power conversion device to which the present invention is applied has low loss and good heat transfer characteristics compared to conventional ones, and the cooler can be made smaller, and the operating frequency can be increased, so that the passive components can be made smaller. By combining these characteristics, it is possible to significantly increase the output density of the power conversion device.

[0108] While the maximum output density of current power conversion devices is around 60 kW / L, the inverter system shown in Example 2 to which the present invention is applied can achieve an output density that far exceeds 60 kW / L according to investigations, making it possible to achieve the output density that has long been hoped for. [Explanation of symbols]

[0109] 100: 6 in 1 module 101: Phase output side insulation surface 102: DC side insulation surface 110: DC positive bus plate 111: DC positive terminal 120: DC negative bus plate 121: DC negative terminal 130: U-phase output bus plate 131: U phase output terminal 132a: U phase high side FWD1 132b: U phase high side FWD2 133a: U-phase high-side MOSFET1 133b: U-phase high-side MOSFET2 134a: U phase low side FWD1 134b: U phase low side FWD2 135a: U-phase low-side MOSFET1 135b: U-phase low-side MOSFET2 136: U-phase high-side gate signal pin 137: U-phase high-side source signal pin 138: U-phase low-side source signal pin 139: U-phase low-side gate signal pin 140: V-phase output bus plate 141: V phase output terminal 142a: V-phase high side FWD1 142b: V-phase high side FWD2 143a: V-phase high-side MOSFET 1 143b: V-phase high-side MOSFET2 144a: V-phase low side FWD1 144b: V-phase low side FWD2 145a: V-phase low-side MOSFET1 145b: V-phase low-side MOSFET2 146: V-phase high-side gate signal pin 147: V-phase high-side source signal pin 148: V-phase low-side source signal pin 149: V-phase low-side gate signal pin 150: W-phase output bus plate 151: W phase output terminal 152a: W phase high side FWD1 152b: W-phase high side FWD2 153a: W-phase high-side MOSFET1 153b: W-phase high-side MOSFET2 154a: W-phase low side FWD1 154b: W-phase low side FWD2 155a: W-phase low-side MOSFET1 155b: W-phase low-side MOSFET2 156: W-phase high-side gate signal pin 157: W-phase high-side source signal pin 158: W-phase low-side source signal pin 159: W-phase low-side gate signal pin 161a: U phase capacitor a 161b: U phase capacitor b 161c: P-type terminal of U-phase capacitor a 162a: U-phase gate film a 162b: U-phase gate film b 163: U-phase low side recess 171a: V phase capacitor a 171b: V-phase capacitor b 172a: V-phase gate film a 172b: V-phase gate film b 173: V-phase low side recess 181a: W phase capacitor a 181b: W phase capacitor b 182a: W-phase gate film a 182b: W-phase gate film b 183: W-phase low side recess 210: Cooler 1 220: Cooler 2 300: DC input capacitor 311: DC positive output terminal 312: DC positive input terminal 321: DC negative output terminal 322: DC negative input terminal 400: 3-phase low-side gate driver assembly 410: Low side gate driver fixture 430: U-phase low-side gate driver circuit 440: V-phase low-side gate driver circuit 450: W-phase low-side gate driver circuit 500: 3-phase high-side gate driver assembly 510: High side gate driver fixture 530: U-phase high-side gate driver circuit 540: V-phase high-side gate driver circuit 550: W-phase high-side gate driver circuit 630: U phase output current sensor 640: V-phase output current sensor 650: W phase output current sensor 931: U-phase main current loop surface 932: U-phase gate signal pin current loop surface 933: Drive current loop surface in U-phase driver circuit 941: V-phase main current loop surface 951: W-phase main current loop surface

Claims

1. a DC positive bus plate on which one or more positive power switch elements and one or more positive power diode elements are mounted, and a DC negative bus plate on which one or more negative power switch elements and one or more negative power diode elements are mounted, a phase output bus plate connecting the one or more positive side power switch elements, the one or more positive side power switch elements, the one or more negative side power switch elements, and the one or more negative side power switch elements, and a phase output terminal is provided on the phase output bus plate, The DC positive bus plate and the DC negative bus plate have planes on which the respective elements are mounted and extend in parallel to each other, a high side gate signal transmission pin to which a high side gate signal is input in a direction perpendicular to the extension direction of the DC positive bus plate, and a low side gate signal transmission pin to which a low side gate signal is input in a direction perpendicular to the extension direction of the DC negative bus plate, a high-side reference potential signal transmission pin to which a reference potential of the high-side gate signal is connected, the high-side reference potential signal transmission pin being parallel to an extending direction of the high-side gate signal transmission pin; A power module including a low-side reference potential signal transmission pin to which a reference potential of the low-side gate signal is connected, the low-side reference potential signal transmission pin being parallel to an extension direction of the low-side gate signal transmission pin, a high-side gate driver circuit on a plane that is perpendicular to the central axis of the protruding portion of the high-side gate signal transmission pin protruding from the outer edge of the power module and perpendicular to both the DC positive bus plate surface and the DC negative bus plate surface direction, and a low-side gate driver circuit on a plane that is parallel to a side surface of the DC negative bus plate, perpendicular to the central axis of the protruding portion of the low-side gate signal transmission pin protruding from the outer edge of the power module and perpendicular to both the DC positive bus plate and the DC negative bus plate surface direction.

2. 2. The power module according to claim 1, wherein the DC positive bus plate and the DC negative bus plate, which are part of the half-bridge configuration, are extended, and the one or more positive side power switch elements, the one or more positive side power diode elements, the one or more negative side power switch elements, the one or more negative side power diode elements, the high side gate signal transmission pin, the high side reference potential signal transmission pin, the low side gate signal transmission pin, the low side reference potential signal transmission pin, and the phase output bus plate are duplicated for the number of phases to form a full bridge configuration.

3. 2. The power module according to claim 1, wherein the DC positive bus plate and the DC negative bus plate, which are part of the half-bridge configuration, are extended, and the one or more positive side power switch elements, the one or more positive side power diode elements, the one or more negative side power switch elements, the one or more negative side power diode elements, the high side gate signal transmission pin, the high side reference potential signal transmission pin, the low side gate signal transmission pin, the low side reference potential signal transmission pin, and the phase output bus plate are duplicated for the number of phases, to form a three-phase inverter configuration.

4. 2. The power module according to claim 1, wherein the DC positive bus plate and the DC negative bus plate which are part of the half-bridge configuration are extended, and the one or more positive side power switch elements, the one or more positive side power diode elements, the one or more negative side power switch elements, the one or more negative side power diode elements, the high side gate signal transmission pin, the high side reference potential signal transmission pin, the low side gate signal transmission pin, the low side reference potential signal transmission pin, and the phase output bus plate are duplicated for the number of phases to form a four-phase inverter configuration.

5. The DC positive bus plate and the DC negative bus plate are connected by the one or more positive side power switch elements, the one or more positive side power diode elements, the one or more negative side power switch elements, and the one or more negative side power diode elements through the respective phase output bus plates duplicated by the number of phases, with respect to each phase main current loop surface, an angle between the high-side gate signal current loop surfaces of each phase generated between the high-side gate signal transmission pin and the high-side reference potential signal transmission pin, which are duplicated for each phase, is between 80 deg. and 100 deg., and an angle between the low-side gate signal current loop surfaces of each phase generated between the low-side gate signal transmission pin and the low-side reference potential signal transmission pin, which are duplicated for each phase, is between 80 deg. and 100 deg. with respect to the main current loop surface of each phase; The power module according to any one of claims 2 to 4.

6. a high-side gate driver substrate total width, which is a value obtained by further adding up the sum of the interphase insulation distance of the high-side gate driver circuit and the substrate width for one phase of the high-side gate driver circuit by the number of phases; or a total width of a low-side gate driver substrate, which is a value obtained by further summing the sum of the interphase insulation distance of the low-side gate driver circuit and the substrate width of one phase of the low-side gate driver circuit for the number of phases, The power module according to claim 1 , wherein the width of the half-bridge configuration in the positive and negative current flow direction coincides with the total value of the number of phases within ±10 mm.

7. 7. The power module according to claim 1, wherein a width of a high-side gate driver circuit assembly in which the high-side gate driver circuits are laid out for each phase for the number of phases of the power module with an insulation distance therebetween, and a width of a low-side gate driver circuit assembly in which the low-side gate driver circuits are laid out for each phase for the number of phases of the power module with an insulation distance therebetween, match within a range of ±30 mm a width of the DC positive bus plate or a width of the DC negative bus plate in a positive current / negative current flow direction of the power module not including a DC input / output terminal unit.

8. 7. The power module according to claim 1, wherein a width in a thickness direction of the power module of the high side gate driver circuit of each phase, or a sum of a width in a thickness direction of the power module of the low side gate driver circuit of each phase, a width in a thickness direction of a cooler that cools the power module, and a width in a thickness direction of the power module coincide within a range of ±30 mm.

9. a main current loop surface generated by connecting the DC positive bus plate and the DC negative bus plate through the one or more positive side power switch elements, the one or more positive side power diode elements, the one or more negative side power switch elements, and the one or more negative side power diode elements by the phase output bus plate; a high side current loop plane angle between the high side gate signal current loop plane generated between the high side gate signal transmission pin and the high side reference potential signal transmission pin; the angles between the three types of high-side current loop planes generated between the high-side gate driver circuit and a current loop plane in the high-side gate driver circuit passing through a connection portion between the high-side gate signal transmission pin and the high-side reference potential signal transmission pin are within a range of 80 degrees to 100 degrees, the main current loop surface; a low-side current loop plane angle between the low-side gate signal current loop plane generated between the low-side gate signal transmission pin and the low-side reference potential signal transmission pin; the angles between the three types of low-side current loop planes generated between the low-side gate driver circuit and a current loop plane in the low-side gate driver circuit passing through a connection part between the low-side gate signal transmission pin and the low-side reference potential signal transmission pin are within a range of 80 degrees to 100 degrees, The power module according to any one of claims 1 to 8.

Images