Apparatus, method and system for matrix operation accelerator instructions - Patents.com

Abstract

To execute matrix calculation using a matrix calculation accelerator.SOLUTION: A processor includes a two-dimensional grid of a matrix calculation accelerator circuit switchable from a first mode to a second mode. In the first mode, when an output of a first subset of a fused product sum circuit of a two-dimensional grid is transmitted to a second subset input of the fused product sum circuit of a downstream two-dimensional grid, an output value is formed from at least one first input two-dimensional matrix and at least one second input two-dimensional matrix. In the second mode, an output of the first subset of a two-dimensional grid fused product sum circuit forms a first output value from a first subset of at least one first input two-dimensional matrix and at least one second input two-dimensional matrix to store it in a storage, and an output of a second subset of the two-dimensional grid fused product sum circuit forms a second output value from a second subset of at least one first input two-dimensional matrix and at least one second input two-dimensional matrix to store it in the storage.SELECTED DRAWING: Figure 3

Description

[Technical field]

[0001] The present disclosure relates generally to computer processor architectures, and more particularly to apparatus, systems and methods for executing instructions to perform matrix operations using matrix operation accelerator circuitry. [Background technology]

[0002] A processor or set of processors executes instructions from an instruction set, such as an Instruction Set Architecture (ISA). An instruction set is a part of a computer architecture that is related to programming and generally includes native data types, instructions, register architecture, addressing modes, memory architecture, interrupt and exception handling, and external input / output (I / O). Note that the term instructions here may refer to macroinstructions, e.g., instructions provided for a processor to execute, or microinstructions, e.g., instructions resulting from a decoder of the processor decoding a macroinstruction. [Brief description of the drawings]

[0003] The present disclosure is illustrated by way of example and not limitation in the several figures of the accompanying drawings, in which like reference symbols indicate similar elements and in which:

[0004] [Figure 1A] 1 illustrates an embodiment of a configured tile according to multiple embodiments of the present disclosure.

[0005] [Figure 1B] 1 illustrates an embodiment of a configured tile according to multiple embodiments of the present disclosure.

[0006] [Diagram 2] 1 illustrates several examples of matrix storage devices according to embodiments of the present disclosure.

[0007] [Diagram 3]1 illustrates an embodiment of a system using a matrix (tile) operation accelerator according to embodiments of the present disclosure.

[0008] [Figure 4] 1 illustrates different embodiments of how memory is shared using a matrix operation accelerator. [Diagram 5] 1 illustrates different embodiments of how memory is shared using a matrix operation accelerator.

[0009] [Figure 6] 1 illustrates an embodiment of a matrix multiply-add operation using tiles (TMMA).

[0010] [Figure 7] 1 illustrates an embodiment of a subset of iterative execution of a chain fused multiply-accumulate instruction.

[0011] [Figure 8] 1 illustrates an embodiment of a subset of iterative execution of a chain fused multiply-accumulate instruction.

[0012] [Figure 9] 1 illustrates an embodiment of a subset of iterative execution of a chain fused multiply-accumulate instruction.

[0013] [Figure 10] 1 illustrates an embodiment of a subset of iterative execution of a chain fused multiply-accumulate instruction.

[0014] [Figure 11] A power-of-two sized SIMD implementation is shown, where the accumulator uses a larger input size than the input to the multiplier in this embodiment.

[0015] [Figure 12] 1 shows an embodiment of a system using a matrix operation circuit.

[0016] [Figure 13]1 illustrates an embodiment of a processor core pipeline that supports matrix operations using tiles.

[0017] [Figure 14] 1 illustrates an embodiment of a processor core pipeline that supports matrix operations using tiles.

[0018] [Figure 15] 1 shows an example of a matrix represented in row-major and column-major formats.

[0019] [Figure 16] Here is an example of how to use multiple matrices (tiles):

[0020] [Figure 17] 1 illustrates an embodiment of a method for the use of multiple matrices (tiles).

[0021] [Figure 18] 1 illustrates support for setting tile usage according to one embodiment.

[0022] [Figure 19] 1 illustrates an embodiment for describing multiple matrices (tiles) that are supported.

[0023] [Figure 20A] An example of a register is shown below. [Figure 20B] An example of a register is shown below. [Figure 20C] An example of a register is shown below. [Figure 20D] An example of a register is shown below.

[0024] [Figure 21] 1 illustrates an embodiment of a matrix operation accelerator circuit comprising a two-dimensional grid of processing element circuits.

[0025] [Figure 22]FIG. 1 is a block diagram illustrating the use of a TILEPARTIALDOTPRODUCT instruction to accelerate matrix operations in accordance with some embodiments.

[0026] [Figure 23] 2 illustrates a method 2300 for processing a TILE PARTIAL DOT PRODUCT instruction according to embodiments of the present disclosure.

[0027] [Figure 24] 1 illustrates an embodiment of a matrix operations accelerator circuit comprising a two-dimensional grid of processing element circuits including rows of configuration switches for switching between a first mode and a second mode.

[0028] [Diagram 25] 1 illustrates an embodiment of a configuration switch.

[0029] [Figure 26] 1 illustrates an embodiment of a matrix math accelerator circuit comprising a two-dimensional grid of processing element circuits including multiple rows of configuration switches for switching between multiple modes.

[0030] [Figure 27A] FIG. 1 is a block diagram illustrating a generic vector friendly instruction format and its class A instruction templates according to embodiments of the present disclosure.

[0031] [Figure 27B] FIG. 1 is a block diagram illustrating a generic vector friendly instruction format and its Class B instruction templates according to embodiments of the present disclosure.

[0032] [Figure 28A] FIG. 27C is a block diagram illustrating fields for the generic vector friendly instruction format in FIGS. 27A and 27B according to embodiments of the present disclosure.

[0033] [Figure 28B]FIG. 28B is a block diagram illustrating the fields of the vector specific instruction format in FIG. 28A that form a full opcode field in accordance with one embodiment of the present disclosure.

[0034] [Figure 28C] FIG. 28B is a block diagram illustrating the fields of the vector specific instruction format from FIG. 28A that form a register index field in accordance with one embodiment of the present disclosure.

[0035] [Figure 28D] FIG. 27B is a block diagram illustrating the fields of the vector specific instruction format in FIG. 28A that form an extended operation field 2750 in accordance with one embodiment of the present disclosure.

[0036] [Figure 29] FIG. 2 is a block diagram of a register architecture according to one embodiment of the present disclosure.

[0037] [Figure 30A] 1 is a block diagram illustrating both an example in-order pipeline and an example register renaming and out-of-order issue / execution pipeline, according to an embodiment of the present disclosure.

[0038] [Figure 30B] 1 is a block diagram illustrating both an example embodiment of an in-order architecture core and an example register renaming, out-of-order issue / execution architecture core to be included in a processor according to multiple embodiments of the present disclosure.

[0039] [Figure 31A] 1 illustrates a block diagram of a single processor core according to embodiments of the present disclosure, along with its connection to an on-die interconnect network and its local subset of a level 2 (L2) cache.

[0040] [Figure 31B]FIG. 31B is an expanded view of a portion of the processor core of FIG. 31A in accordance with multiple embodiments of the present disclosure.

[0041] [Diagram 32] FIG. 2 is a block diagram of a processor according to embodiments of the present disclosure, which may have more than one core, may have an integrated memory controller, and may have integrated graphics.

[0042] [Diagram 33] FIG. 1 is a block diagram of a system according to an embodiment of the present disclosure.

[0043] [Diagram 34] FIG. 2 is a block diagram of a more specific exemplary system according to an embodiment of the present disclosure.

[0044] [Diagram 35] Shown is a block diagram of a second more specific exemplary system according to an embodiment of the present disclosure.

[0045] [Diagram 36] Shown is a block diagram of a system on chip (SoC) according to an embodiment of the present disclosure.

[0046] [Figure 37] 1 is a block diagram contrasting the use of a software instruction converter to convert binary instructions in a source instruction set to binary instructions in a target instruction set according to embodiments of the present disclosure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0047] In the following description, numerous specific details are set forth. However, it is understood that embodiments may be practiced without these specific details. In other instances, well-known circuits, structures and techniques are not shown in detail in order not to obscure the understanding of the present description.

[0048] References herein to "one embodiment," "an embodiment," "an exemplary embodiment," and the like indicate that the embodiment being described may include a particular feature, structure, or characteristic, but not all embodiments necessarily include the particular feature, structure, or characteristic. Moreover, these phrases do not necessarily refer to the same embodiment. Moreover, when a particular feature, structure, or characteristic is described in connection with one embodiment, it is believed that one of ordinary skill in the art would be inclined to use such feature, structure, or characteristic in connection with other embodiments, whether or not expressly described.

[0049] Matrices may become increasingly important in many computing tasks, such as machine learning and other bulk data processing. Deep learning is a class of machine learning algorithms. Deep learning architectures, such as deep neural networks, may be applied to fields including computer vision, speech recognition, natural language processing, audio recognition, social network filtering, machine translation, bioinformatics, and drug design.

[0050] Inference and training, two tools used for deep learning, may use low precision arithmetic. Maximizing the throughput of deep learning algorithms and computations can help meet the needs of deep learning processors, such as those running them in data centers.

[0051] Matrix-matrix multiplication (also known as GEMM or generalized matrix multiplication) is a computationally intensive operation on certain processors. Specialized hardware for matrix multiplication (e.g., GEMM) is a good option to improve the peak computation (and energy efficiency) of certain applications, such as deep learning. Some of these applications, including deep learning, can operate on input data elements with relatively few bits without losing accuracy, as long as the output elements have enough bits (e.g., more than the inputs).

[0052] Matrix operations are instruction difficult and / or intensive tasks on certain processors. For example, rows of a matrix may be placed into multiple packed data (e.g., SIMD or vector) registers and then operated on individually. For example, adding two 8×2 matrices (e.g., rows and columns) may require loading or gathering into four packed data registers depending on the data size. A first addition is then performed on the packed data registers corresponding to the first row of each matrix, and a second addition is performed on the packed data registers corresponding to the second row of each matrix. The resulting packed data registers are then scattered back to memory. While this scenario is acceptable for small matrices, it is often unacceptable for larger matrices. explanation

[0053] Described herein are mechanisms for supporting matrix operations on computer hardware such as central processing units (CPUs), graphic processing units (GPUs) and accelerators. Matrix operations use two-dimensional (2-D) data structures that represent one or more packed regions of memory, such as registers. Throughout this description, these 2-D data structures are referred to as tiles. Note that a matrix may be smaller than a tile (using less than all of a tile) or may use multiple tiles (a matrix larger than the size of any one tile). Throughout this description, the term matrix (tile) is used to indicate that an operation is performed using multiple tiles that affect a matrix, and whether the matrix is ​​larger than any one tile is typically not relevant.

[0054] Each tile may be operated on by different operations, as detailed herein, which may include, but are not limited to, matrix (tile) multiplication, tile addition, tile subtraction, tile diagonal, tile zero, tile transform, tile dot product, tile broadcast, tile row broadcast, tile column broadcast, tile multiply, tile multiply sum, tile move, etc. Additionally, support for operators such as the use of scale and / or bias may be used in conjunction with these operations, or with support for future non-numeric applications, such as OpenCL "local memory", data compression / decompression, etc. Also described herein are instructions for performing matrix operations (e.g., TILE PARTIAL DOT PRODUCT) instructions.

[0055] Portions of storage (e.g., memory (non-volatile / volatile), registers, cache, etc.) are arranged into tiles of different horizontal and vertical dimensions. For example, a tile may have a horizontal dimension of 4 (e.g., 4 rows of a matrix) and a vertical dimension of 8 (e.g., 8 columns of a matrix). Typically, the horizontal dimension is related to the element size (e.g., 2-, 4-, 8-, 16-, 32-, 64-, 128-bit, etc.). Multiple data types (single precision floating point, double precision floating point, integer, etc.) may be supported. Example of using configured tiles

[0056] In some embodiments, tile parameters may be configured. For example, a given tile may be configured to provide multiple tile options. Exemplary tile options include, but are not limited to, the number of rows in the tile, the number of columns in the tile, whether the tile is enabled, and whether the tile consists of a pair of equal-sized tiles.

[0057] FIG. 1A illustrates an embodiment of an organized tile. As shown, 4kB of application memory 102 stores four 1kB titles: tile t0 104, tile t1 106, tile t2 108, and tile t3 110. In this example, the four tiles are not paired, and each has elements arranged in rows and columns. Tiles t0 104 and tile t1 106 have K rows and N columns of 4-byte elements (e.g., single precision data), where K equals 8 and N=32. Tiles t2 108 and tile t3 110 have K rows and N / 2 columns of 8-byte elements (e.g., double precision data). Because double precision operands are twice as wide as single precision, this organization provides at least 4KB of total storage for at least four names, consistent with the palette used to provide the tile options. During operation, tiles are loaded from and stored to memory using load and store operations. Depending on the instruction encoding scheme used, the size, number and organization of available tiles, as well as the amount of available application memory, vary.

[0058] 1B illustrates an embodiment of configured tiles. As shown, 4kB of application memory 122 stores two pairs of 1kB tiles, a first pair of tiles t4L 124 and t4R 126, and a second pair of tiles t5L 128 and t5R 130. As shown, the pair of tiles is divided into a left tile and a right tile. In other embodiments, the pair of tiles is divided into an even tile and an odd tile. In this example, each of the four tiles has elements arranged in rows and columns. Tiles t4L 124 and t4R 126 have K rows · N columns of 4-byte elements (e.g., single-precision floating-point data), where K is equal to 8 and N is equal to 32. Tiles t5L 128 and t5R 130 have K rows · N / 2 columns of 8-byte elements (e.g., double-precision floating-point data). Because double precision operands are twice as wide as single precision, this configuration aligns with the palette used to provide the tile options and provides at least 4KB of total storage for at least two names. The four tiles of FIG. 1A use four names, each a 1kB tile, while the pair of two tiles of FIG. 1B can use two names to specify the pair tile. In some embodiments, the tile instructions accept the name of the pair tile as an operand. During operation, tiles are loaded from and stored to memory using load-store operations. Depending on the instruction encoding scheme used, the size, number, and configuration of the available tiles vary, as well as the amount of available application memory.

[0059] In some embodiments, tile parameters can be defined. For example, a "palette" can be used to provide tile options. Exemplary options include, but are not limited to, the number of tile names, the number of bytes in a row of storage, the number of rows and columns in a tile, etc. For example, the maximum "height" of a tile (number of rows) may be defined as follows:

[0060] Maximum tile rows = Design storage / (number of palette names x number of bytes per row)

[0061] In this way, it is possible to write applications such that a fixed usage of names can take advantage of different storage sizes across implementations.

[0062] Tile configuration is performed using the tile configuration (TILECONFIG) command, where a particular tile specification is defined with a selected palette. This declaration includes the number of tile names to be used, the desired number of rows and columns per name (tile), and in some embodiments the desired data type for each tile. In some embodiments, a consistency check is performed during execution of the TILECONFIG command to determine whether the constraints of the palette entries are met. Example Tile Storage Types

[0063] Figure 2 shows some examples of matrix storage. At (A) one tile is stored in memory. As shown, each row consists of four packed data elements. A stride value is used to get the next "row". Note that multiple rows may be stored contiguously in memory. Strided memory access allows access from one row to the next if the tile storage does not map the row width of the underlying memory array.

[0064] Tiles loaded from and stored to memory are typically stride accessed packed data rows from application memory. The exemplary TILELOAD and TILESTORE instructions, or other instructions that reference application memory as tile operands in load-op instructions, are restartable in some embodiments to handle (up to) 2× rows of page faults, unmasked floating-point exceptions, and / or per-instruction interrupts.

[0065] In (B), the matrix is ​​stored in a tile consisting of multiple registers, such as packed data registers (single instruction, multiple data (SIMD) or vector registers). In this example, the tile is overlaid onto three physical registers. Typically, contiguous registers are used, however, this is not necessary in this case.

[0066] In (C), the matrices are stored in the tiles in non-register storage accessible to a fused multiply-accumulate (FMA) circuit used in the tiled operations. This storage may be within or adjacent to the FMA. Additionally, in some embodiments described below, the storage may be for data elements and not for entire rows or tiles.

[0067] The parameters supported by the TMAA architecture are reported via CPUID. In some embodiments, the list of information includes the maximum height and maximum SIMD dimensions. Configuration of the TMAA architecture requires specifying the dimensions of each tile, the element size of each tile, and the palette identifier. This configuration is performed by executing the TILECONFIG instruction.

[0068] Successful execution of the TILECONFIG instruction allows subsequent tile operations. The TILERELEASEALL instruction clears the tile configuration and disables tile operations (until the next TILECONFIG instruction executes). In some embodiments, XSAVE, XSTORE, etc. are used for context switching with tiles. In some embodiments, two XCR0 bits are used in XSAVE: one for TILECONFIG metadata and one bit for the actual tile payload data.

[0069] TILECONFIG not only configures tile usage, but also sets state variables that indicate that the program is in a code region with a configured tile. Some implementations may list constraints on other instructions that can be used with a tile region, such as not using existing register sets, etc.

[0070] Exiting a tile region is typically done with the TILERELEASEALL command, which takes no parameters and immediately invalidates all tiles (indicating that no saving or restoring of any data is anymore necessary) and clears any internal state associated with being in the tile region.

[0071] In some embodiments, the tile operation zeros out any rows and any columns beyond the dimension specified by the tile configuration. For example, the tile operation zeros out data beyond the number of configured columns (taking into account the element size) as each row is written. For example, for a tile consisting of 64 byte rows and 10 rows and 12 columns, an operation writing an FP32 element would write 12*4 bytes with output / result data to each of the first 10 rows and zero out the remaining 4*4 bytes in each row. The tile operation also completely zeros all rows after the first 10 configured rows. If using a 1K tile with 64 byte rows, there would be 16 rows, so in this example, the last 6 rows would also be zeroed out.

[0072] In some embodiments, when reading data, a context restore command (e.g., XRSTOR) forces data beyond the configured rows for the tile to be maintained as zero. If there is no valid configuration, all rows are zeroed out. XRSTOR for tile data can load unwanted data in columns beyond their configuration. Since there is no element width associated with a tile configuration, XRSTOR should not be able to clear beyond the configured number of columns.

[0073] When writing to memory, a context save (e.g., XSAVE) will point to the entire tile storage area. If XRSTOR reads garbage data into the right edge of a tile, that data will be saved by XSAVE. XSAVE will write zeros to rows beyond the number specified for each tile.

[0074] In some embodiments, tile instructions are restartable: for operations that access memory, they allow restart after a page fault; for computational instructions that deal with floating point arithmetic, unmasked floating point exceptions are also possible, with masking of exceptions controlled by control and / or status registers.

[0075] To support restart commands after these events, the command stores information in a start register, which is described in more detail below. Matrix (tile) calculation system Exemplary Hardware Support

[0076] FIG. 3 illustrates an embodiment of a system using a matrix (tile) operations accelerator. In this example, a host processor / processing system 301 communicates commands 311 (e.g., matrix operations such as arithmetic or matrix operations and load-store operations) to a matrix operations accelerator 307. However, this aspect is shown for illustrative purposes only. As will be described in more detail below, this accelerator 307 may be part of a processing core. Typically, commands 311 that are tile operation operator instructions will reference tiles in register-register (reg-reg) or register-memory (reg-mem) format. Other commands, such as, for example, TILESTORE, TILELOAD, TILECONFIG, etc., do not perform data operations on tiles. The commands may be decoded instructions (e.g., micro-ops) or macro-instructions for the accelerator 307 to process.

[0077] In this example, a coherent memory interface 303 is coupled to the host processor / processing system 301 and the matrix operation accelerator 307, thereby sharing memory. Figures 4 and 5 show different embodiments of how memory is shared using the matrix operation accelerator. As shown in Figure 4, the host processor 401 and the matrix operation accelerator circuit 405 share the same memory 403. Figure 5 shows an embodiment in which the host processor 501 and the matrix operation accelerator 505 do not share memory, but can each access the other's memory. For example, the processor 501 can access the tile memory 507 and use its host memory 503 as usual. Similarly, the matrix operation accelerator 505 can access the host memory 503, and more typically uses its own memory 507. Note that these memories can be different types of memories.

[0078] In some embodiments, tiles are supported using an overlay on physical registers. For example, a tile may utilize sixteen 1024-bit registers, thirty-two 512-bit registers, etc., depending on the implementation. In some embodiments, matrix operations use data structures in two dimensions (2-D) that represent one or more packed regions of memory, such as registers. Throughout this description, these 2-D data structures are referred to as tiles or tile registers.

[0079] In some embodiments, the matrix operations accelerator 307 includes multiple FMAs 309 coupled to a data buffer 305 (in some implementations, one or more of these multiple buffers 305 are stored in a grid of FMAs as shown). The data buffer 305 buffers tiles read from memory and / or tiles to be stored in memory (e.g., using a tileload or tilestore instruction). The data buffer may be, for example, multiple registers. Typically, these FMAs are arranged as a grid of chained FMAs 309, allowing reads and writes to the tiles. In this example, the matrix operations accelerator 307 performs a matrix multiplication operation using tiles T0, T1, and T2. At least one tile is stored in the FMA grid 309. In some embodiments, all tiles in the operation are stored in the FMA grid 309. In other embodiments, only a subset is stored in the FMA grid 309. As shown, T1 is stored, while T0 and T2 are not. Note that A, B, and C refer to the rows and columns of these tiles, which may or may not occupy the entire space of the tiles.

[0080] FIG. 6 shows an embodiment of a matrix multiply-add operation using tiles (TMMA).

[0081] The number of rows in the matrix (tile A 601) corresponds to the number of serial (chain) FMAs with the computational latency in a particular embodiment. An implementation is free to recycle on a grid of smaller heights, but the computation remains the same.

[0082] The source / destination vectors come from an N-row tile (Tile C 605) and the FMA 611 grid performs the N-vector matrix operations, resulting in a complete instruction to perform the tile matrix multiplication. Tile B 603 is the other vector source and provides a "broadcast" period for the FMAs of each stage.

[0083] In some embodiments, during operation, the elements of matrix B (stored in tile B 603) are distributed across a rectangular grid of FMAs. Matrix B (stored in tile A 601) has some of its elements transformed into row elements to fit the column dimension of the rectangular grid of the FMAs. At each FMA in the grid, the elements of A and B are multiplied and added to the incoming summand (from the top of the figure), and the outgoing sum is passed to the next row (or final output) of the FMA.

[0084] The latency of a single stage is proportional to K (the row height of matrix B), and the dependent TMMA typically has enough source-destination rows to hide the latency (either in a single tile or across tiles). An implementation may also divide the SIMD (packed data element) dimension M (the row height of matrix A) across time stages, but this simply changes the constant by which K is multiplied. If a program specifies K smaller than the maximum enumerated by the TMMA, the implementation is free to implement this with "masking" or "early out".

[0085] The overall latency of TMMA is proportional to N*K. The repeat rate is proportional to N. The number of MACs per TMMA instruction is N*K*M.

[0086] 7 illustrates an embodiment of a subset of iterative execution of a chain-fused multiply-accumulate instruction. In particular, the execution circuitry is shown for iteration of one packed data element location for the destination. In this embodiment, the chain-fused multiply-accumulate operates on a signed source and the accumulator is 2× the input data size.

[0087] The first signed source (Source 1 701) and the second signed source (Source 2 703) each have four packed data elements. Each of these packed data elements stores signed data, such as floating point data. The third signed source (Source 3 709) has two packed data elements, each of which stores signed data. The first signed source 701 and the second signed source 703 are half the size of the third signed source 709 (initial value or previous result). For example, the first signed source 701 and the second signed source 703 may have 32-bit packed data elements (e.g., single precision floating point), while the third signed source 709 may have 64-bit packed data elements (e.g., double precision floating point).

[0088] In this example, only the two most significant packed data element positions of the first signed source 701 and the second signed source 703 and the most significant packed data element position of the third signed source 709 are shown. Of course, other packed data element positions may also be processed.

[0089] As shown, packed data elements are processed in pairs. For example, data from the most significant packed data element positions of the first signed source 701 and the second signed source 703 are multiplied using multiplier circuit 705, and data from the second most significant packed data element positions of the first signed source 701 and the second signed source 703 are multiplied using multiplier circuit 707. In some embodiments, these multiplier circuits 705 and 707 are reused for other packed data element positions. In other embodiments, additional multiplier circuits are used, thereby processing packed data elements in parallel. In some contexts, the parallel execution is performed using lanes that are the size of the third signed source 709. The results of each of the multiple multiplications are added using adder circuit 711.

[0090] The result of adding the multiplication results is added to the data from the most significant packed data element position of Signed Source 3 709 (using a different adder 713 or the same adder 711).

[0091] Finally, the result of the second addition is either stored from the third signed source 709 to the signed destination 715 at the packed data element location corresponding to the packed data element location used or passed to the next iteration, if any. In some embodiments, a writemask is applied to this storage, such that a store occurs if the corresponding writemask (bit) is set, and no store occurs if it is unset.

[0092] 8 illustrates an embodiment of a subset of iterative execution of the chain-fused multiply-accumulate instruction. In particular, it illustrates the execution circuitry for iteration of one packed data element location for the destination. In this embodiment, the chain-fused multiply-accumulate operates on a signed source and the accumulator is 2× the input data size.

[0093] The first signed source (Source 1 801) and the second signed source (Source 2 803) each have four packed data elements. Each of these packed data elements stores signed data, such as integer data. The third signed source (Source 3 809) has two packed data elements, each of which stores signed data. The first signed source 801 and the second signed source 803 are half the size of the third signed source 809. For example, the first signed source 801 and the second signed source 803 may have 32-bit packed data elements (e.g., single precision floating point) and the third signed source 809 may have 64-bit packed data elements (e.g., double precision floating point).

[0094] In this example, only the two most significant packed data element positions of the first signed source 801 and the second signed source 803 and the most significant packed data element position of the third signed source 809 are shown. Of course, other packed data element positions may also be processed.

[0095] As shown, packed data elements are processed in pairs. For example, data from the most significant packed data element positions of the first signed source 801 and the second signed source 803 are multiplied using multiplier circuit 805, and data from the second most significant packed data element positions of the first signed source 801 and the second signed source 803 are multiplied using multiplier circuit 807. In some embodiments, these multiplier circuits 805 and 807 are reused for other packed data element positions. In other embodiments, additional multiplier circuits are used, thereby processing the packed data elements in parallel. In some contexts, the parallel execution is performed using lanes that are the size of the third signed source 809 (either the initial value or the result of a previous iteration). The results of each of the multiple multiplications are added to the third signed source 809 using add / saturate circuit 813.

[0096] The Addition / Saturation (Accumulator) Circuit 813 preserves the signs of the operands if the sum result is too large in value. In particular, saturation evaluation occurs on infinite precision results between the multiway addition and the write to the destination or next iteration. If the Accumulator 813 is floating point and the input terms are integers, the sum of the products and the floating point accumulator input value are converted to an infinite precision value (a few hundred bits of fixed point), an addition of the multiplication result with the third input is performed, and a single round to the actual accumulator type is performed.

[0097] Unsigned saturation means that the output value is limited to the largest unsigned number for the element width (all ones). Signed saturation means that the value is limited to be in the range between the most negative and most positive number for the element width (e.g., in bytes, the range is -128 (=-2^7) to 127 (2^7-1)).

[0098] The result of the addition and saturation check is stored to signed result 815 in the packed data element location corresponding to the packed data element location used from third signed source 809 or passed to the next iteration, if any. In some embodiments, a writemask is applied to this storage so that a store occurs if the corresponding writemask (bit) is set and no store occurs if it is unset.

[0099] 9 illustrates an embodiment of a subset of iterative execution of a chain-fused multiply-accumulate instruction. In particular, the execution circuitry is shown for iteration of one packed data element location for the destination. In this embodiment, the chain-fused multiply-accumulate operates on signed and unsigned sources, and the accumulator is 4× the input data size.

[0100] A first signed source (Source 1 901) and a second unsigned source (Source 2 903) each have four packed data elements. Each of these packed data elements has signed data, such as floating point data or integer data. A third signed source (initial value or result 915) has packed data elements that store the signed data. The first source 901 and the second source 903 are one-quarter the size of the third signed source 915. For example, the first source 901 and the second source 903 may have 16-bit packed data elements (e.g., words) and the third signed source 915 may have 64-bit packed data elements (e.g., double precision floating point or 64-bit integer).

[0101] In this example, the four most significant packed data element positions of the first source 901 and the second source 903 and the most significant packed data element position of the third signed source 915 are shown. Of course, other packed data element positions, if any, would also be processed.

[0102] As shown, the packed data elements are processed in quadruplets. For example, data in the most significant packed data element positions of the first source 901 and the second source 903 are multiplied using multiplier circuit 905, data from the second most significant packed data element positions of the first source 901 and the second source 903 are multiplied using multiplier circuit 907, data from the third most significant packed data element positions of the first source 901 and the second source 903 are multiplied using multiplier circuit 909, and data from the least significant packed data element positions of the first source 901 and the second source 903 are multiplied using multiplier circuit 911. In some embodiments, the signed packed data elements of the first source 901 are sign extended and the unsigned packed data elements of the second source 903 are zero extended before multiplication.

[0103] In some embodiments, these multiplier circuits 905-911 are reused for other packed data element positions. In other embodiments, additional multiplier circuits are used to process the packed data elements in parallel. In some contexts, the parallel execution is performed using lanes that are the size of the third signed source 915. The results of each of the multiple multiplications are added together using adder circuit 913.

[0104] The result of adding the multiplication results is added to the data from the most significant packed data element position of Signed Source 3 915 (using a different adder 917 or the same adder 913).

[0105] Finally, the result 919 of the second addition is either stored to a signed destination at a packed data element location corresponding to the packed data element location used from the third signed source 915 or passed to the next iteration. In some embodiments, a writemask is applied to this storage so that a store occurs if the corresponding writemask (bit) is set and no store occurs if it is unset.

[0106] 10 illustrates an embodiment of a subset of iterative execution of a chain-fused multiply-accumulate instruction. In particular, the execution circuitry is shown for iteration of one packed data element location for the destination. In this embodiment, the chain-fused multiply-accumulate operates on signed and unsigned sources, and the accumulator is 4× the input data size.

[0107] The first signed source 1001 and the second unsigned source 1003 each have four packed data elements. Each of these packed data elements stores data such as floating point data or integer data. The third signed source 1015 (initial or previous result) has packed data elements that store signed data. The size of the first and second sources is one-quarter of the size of the third signed source 1015 (initial or previous result). For example, the first and second sources may have 16-bit packed data elements (e.g., words) and the third signed source 1015 (initial or previous result) may have 64-bit packed data elements (e.g., double precision floating point or 64-bit integer).

[0108] In this example, the four most significant packed data element positions of a first signed source 1001 and a second unsigned source 1003 are shown, as well as the most significant packed data element position of a third signed source 1015. Of course, other packed data element positions, if any, would also be processed.

[0109] As shown, the packed data elements are processed in quadruplets. For example, data in the most significant packed data element positions of the first signed source 1001 and the second unsigned source 1003 are multiplied using multiplier circuitry 1005, data from the second most significant packed data element positions of the first signed source 1001 and the second unsigned source 1003 are multiplied using multiplier circuitry 1007, data from the third most significant packed data element positions of the first signed source 1001 and the second unsigned source 1003 are multiplied using multiplier circuitry 1009, and data from the least significant packed data element positions of the first signed source 1001 and the second unsigned source 1003 are multiplied using multiplier circuitry 1011. In some embodiments, the signed packed data elements of the first signed source 1001 are sign extended and the unsigned packed data elements of the second unsigned source 1003 are zero extended before multiplication.

[0110] In some embodiments, these multiplier circuits 1005-1011 are reused for other packed data element positions. In other embodiments, additional multiplier circuits are used, thereby processing the packed data elements in parallel. In some contexts, the parallel execution is performed using lanes that are the size of the third signed source 1015 (initial or previous result). The result of adding the multiplication results is added to the data from the most significant packed data element position of the third signed source 1015 (initial or previous result) using add / saturate circuitry 1013.

[0111] The add / saturate (accumulator) circuit 1013 preserves the signs of the operands when the addition result is too large or too small in value for signed saturation. In particular, saturation evaluation occurs on infinite precision results between the multiway addition and the write to the destination. If the accumulator 1013 is floating point and the input terms are integers, the sum of the products and the floating point accumulator input value are converted to an infinite precision value (a few hundred bits of fixed point), an addition of the multiplication result with the third input is performed, and a single round to the actual accumulator type is performed.

[0112] The result 1019 of the addition and saturation check is stored to a signed destination at a packed data element location corresponding to the packed data element location used from the third signed source 1015 (initial or previous result) or passed to the next iteration. In some embodiments, a writemask is applied to this storage so that a store occurs if the corresponding writemask (bit) is set and no store occurs if it is unset.

[0113] FIG. 11 shows a power-of-two sized SIMD implementation where the accumulator uses a larger input size than the input to the multiplier in this embodiment. Note that the source (to the multiplier) and the accumulator value can be signed or unsigned values. For an accumulator with 2× input size (in other words, the accumulator input value is twice the packed data element size at the source), table 1101 shows different configurations. For a byte sized source, the accumulator uses word or 16-bit sized half-precision floating-point (HPFP) values. For a word sized source, the accumulator uses 32-bit integer or 32-bit sized single-precision floating-point (SPFP) values. For a SPFP or 32-bit integer sized source, the accumulator uses 64-bit integer or 64-bit sized double-precision floating-point (DPFP) values.

[0114] For an accumulator with 4x input size (in other words, the accumulator input value is four times the packed data element size at the source), table 1103 shows different configurations: For byte-sized sources, the accumulator uses 32-bit integers or 32-bit sized single-precision floating-point (SPFP) values. In some embodiments, for word-sized sources, the accumulator uses 64-bit integers or 64-bit sized double-precision floating-point (DPFP) values.

[0115] For an accumulator with 8x input size (in other words, the accumulator input value is 8 times the packed data element size in the source), table 1105 shows one configuration: For a byte-sized source, the accumulator uses 64-bit integers.

[0116] As alluded to earlier, the matrix operation circuitry may be included in the core or as an external accelerator. Figure 12 shows an embodiment of a system using the matrix operation circuitry. In this example, multiple entities are coupled to a ring interconnect 1245.

[0117] Multiple cores, core 0 1201, core 1 1203, core 2 1205 and core N 1207, provide support for non-tile-based instructions. In some embodiments, matrix operation circuitry 1251 is provided in core 1203, while in other embodiments, matrix operation circuitry 1211 and 1213 are accessible over ring interconnect 1245.

[0118] Additionally, one or more memory controllers 1223-1225 are provided to communicate with memories 1233 and 1231 for the multiple cores and / or matrix processing circuits.

[0119] FIG. 13 illustrates an embodiment of a processor core pipeline that supports matrix operations using tiles. A branch prediction and decode circuit 1303 performs branch prediction, instruction decoding, and / or both of instructions from instructions stored in an instruction storage 1301. For example, instructions detailed herein may be stored in the instruction storage. In some implementations, a separate circuit is used for branch prediction, and in some embodiments, at least some instructions are decoded into one or more micro-operations, microcode entry points, microinstructions, other instructions, or other control signals using microcode 1305. The branch prediction and decode circuit 1303 may be implemented using a variety of different mechanisms. Examples of suitable mechanisms include, but are not limited to, look-up tables, hardware implementations, programmable logic arrays (PLAs), microcode read-only memories (ROMs), and the like.

[0120] The branch prediction decode circuit 1303 is coupled to an allocate / rename 1307 circuit, which in some embodiments is coupled to a scheduler circuit 1309. In some embodiments, these circuits provide register renaming, register allocation, and / or scheduling functionality by performing one or more of: 1) renaming logical operand values ​​to physical operand values ​​(e.g., register alias tables in some embodiments), 2) assigning state bits and flags to decoded instructions, and 3) scheduling decoded instructions from an instruction pool for execution by an execution circuit (e.g., using reservation stations in some embodiments).

[0121] Scheduler circuitry 1309 may represent any number of different schedulers including reservation stations, central instruction window, etc. Scheduler circuitry 1309 is coupled to or includes physical register files 1315. Each of physical register files 1315 represents one or more physical register files, with the different files storing one or more different data types, such as, for example, scalar integer, scalar floating point, packed integer, packed floating point, vector integer, vector floating point, status (e.g., an instruction pointer that is the address of the next instruction to be executed), tiles, etc. In one embodiment, physical register file 1315 comprises vector register circuitry, writemask register circuitry, and scalar register circuitry. These register circuits may provide architectural vector registers, vector mask registers, and general purpose registers. The physical register file 1315 is overlaid with a retirement circuit 1317 to illustrate the various ways in which register renaming and out-of-order execution may be implemented (e.g., using a reorder buffer and a retirement register file, using a future file, a history buffer and a retirement register file, using a register map and register pools, etc.). The retirement circuit 1317 and the physical register file 1315 are coupled to the execution circuit 1311.

[0122] Although register renaming is described in the context of out-of-order execution, it should be understood that register renaming may be used in an in-order architecture. While the illustrated processor embodiment may include separate instruction and data cache units and a shared L2 cache unit, alternative embodiments may have one internal cache for both instructions and data, such as a first level (L1) internal cache, or a multi-level internal cache. In some embodiments, the system may include a combination of an internal cache and an external cache that is external to the core and / or processor. Alternatively, all of the cache may be external to the core and / or processor.

[0123] Execution circuitry 1311 is a set of one or more execution circuits including scalar circuitry 1321, vector / SIMD circuitry 1323, and matrix operation circuitry 1327, as well as memory access circuitry 1325 that accesses cache 1313. The execution circuits perform various operations (e.g., shift, add, subtract, multiply) and may operate on various data types (e.g., scalar floating point, packed integer, packed floating point, vector integer, vector floating point). Some embodiments may include multiple execution units dedicated to a particular function or set of functions, while other embodiments may include only one execution unit or multiple execution units that all perform all functions. Scalar circuitry 1321 performs scalar operations, vector / SIMD circuitry 1323 performs vector / SIMD operations, and matrix operation circuitry 1327 performs matrix (tiled) operations as detailed herein.

[0124] As an example, an exemplary register renaming out-of-order issue / execution core architecture may implement a pipeline as follows: 1) The instruction fetch circuitry performs a fetch and length decode stage. 2) The branch decode circuit 1303 executes the decode stage. 3) The Allocate / Rename 1307 circuit performs the allocation and renaming stages. 4) The scheduler circuit 1309 executes the schedule stage. 5) The physical register file(s) (coupled to or contained in the scheduler circuit 1309, the allocate / rename 1307 circuit and the memory unit) perform the register read / memory read stages and the execute circuit 1311 performs the execute stage. 6) The memory unit and physical register file unit(s) perform the writeback / memory write stage. 7) Various units may be involved in the exception handling stage. 8) The retirement unit and physical register file unit(s) perform the commit stage.

[0125] The core may support one or more instruction sets (e.g., the x86 instruction set (with some extensions added in newer versions), the MIPS instruction set from MIPS Technologies of Sunnyvale, Calif., the ARM instruction set from ARM Holdings, Inc. of Sunnyvale, Calif. (with optional additional extensions such as NEON)), including the instruction(s) described herein. In one embodiment, core 1390 includes logic to support packed data instruction set extensions (e.g., AVX1, AVX2), allowing operations used by many multimedia applications to be performed using packed data.

[0126] It will be appreciated that a core may support multithreading (performing two or more parallel sets of operations or threads) and may do so in a variety of ways, including time-shared multithreading, simultaneous multithreading (where one physical core provides a logical core for each thread on which the physical core performs simultaneous multithreading), or a combination thereof (e.g., time-shared fetch-and-decode and then simultaneous multithreading, such as Intel Hyper-Threading Technology).

[0127] FIG. 14 illustrates an embodiment of a processor core pipeline that supports matrix operations using tiles. A branch prediction and decode circuit 1403 performs branch prediction, instruction decoding, and / or both of instructions from instructions stored in an instruction storage 1401. For example, instructions detailed herein may be stored in the instruction storage. In some implementations, a separate circuit is used for branch prediction, and in some embodiments, at least some instructions are decoded into one or more micro-operations, microcode entry points, microinstructions, other instructions, or other control signals using microcode 1405. The branch prediction and decode circuit 1403 may be implemented using a variety of different mechanisms. Examples of suitable mechanisms include, but are not limited to, look-up tables, hardware implementations, programmable logic arrays (PLAs), microcode read-only memories (ROMs), and the like.

[0128] The branch prediction decode circuit 1403 is coupled to an allocate / rename 1407 circuit, which in some embodiments is coupled to a scheduler circuit 1409. In some embodiments, these circuits provide register renaming, register allocation, and / or scheduling functionality by performing one or more of: 1) renaming logical operand values ​​to physical operand values ​​(e.g., register alias tables in some embodiments), 2) assigning state bits and flags to decoded instructions, and 3) scheduling decoded instructions from an instruction pool for execution by the execution circuitry (e.g., using reservation stations in some embodiments).

[0129] Scheduler circuit 1409 may represent any number of different schedulers, including reservation stations, central instruction window, etc. Scheduler unit(s), scheduler circuit 1409 is coupled to or includes physical register file 1415. Each of physical register files 1415 represents one or more physical register files, the different files storing one or more different data types, such as, for example, scalar integer, scalar floating point, packed integer, packed floating point, vector integer, vector floating point, status (e.g., instruction pointer, which is the address of the next instruction to be executed), tiles, etc. In one embodiment, physical register file 1415 comprises vector register circuitry, writemask register circuitry, and scalar register circuitry. These register circuits may provide architectural vector registers, vector mask registers, and general purpose registers. The physical register file 1415 is overlaid by a retirement circuit 1417 and illustrates various ways in which register renaming and out-of-order execution may be implemented (e.g., using a reorder buffer and a retirement register file, using a future file, a history buffer and a retirement register file, using a register map and register pools, etc.). The retirement circuit 1417 and the physical register file 1415 are coupled to the execution circuit 1411.

[0130] Although register renaming is described in the context of out-of-order execution, it should be understood that register renaming may be used in an in-order architecture. The illustrated processor embodiment may include separate instruction and data cache units and a shared L2 cache unit, and alternative embodiments may have one internal cache for both instructions and data, such as a first level (L1) internal cache, or a multi-level internal cache. In some embodiments, the system may include a combination of an internal cache and an external cache that is external to the core and / or processor. Alternatively, all of the cache may be external to the core and / or processor.

[0131] The execution circuitry 1411 includes a set of one or more execution circuits 1427 and a set of one or more memory access circuits 1425 that access the cache 1413. The execution circuitry 1427 performs the matrix (tile) operations detailed herein.

[0132] As an example, an exemplary register renaming out-of-order issue / execution core architecture may implement a pipeline as follows: 1) The instruction fetch circuitry performs a fetch and length decode stage. 2) The branch decode circuit 1403 executes the decode stage. 3) The Allocate / Rename 1407 circuit performs the allocation and renaming stages. 4) The scheduler circuit 1409 executes the schedule stage. 5) The physical register file(s) (coupled to or contained in the scheduler circuit 1409, the allocate / rename 1407 circuit and the memory unit) perform the register read / memory read stages and the execute circuit 1411 performs the execute stage. 6) The memory unit and physical register file unit(s) perform the writeback / memory write stage. 7) Various units may be involved in the exception handling stage. 8) The retirement unit and physical register file unit(s) perform the commit stage.

[0133] The core may support one or more instruction sets (e.g., the x86 instruction set (with some extensions added in newer versions), the MIPS instruction set from MIPS Technologies of Sunnyvale, Calif., the ARM instruction set from ARM Holdings, Inc. of Sunnyvale, Calif. (with optional additional extensions such as NEON)), including the instruction(s) described herein. In one embodiment, core 1490 includes logic to support packed data instruction set extensions (e.g., AVX1, AVX2), allowing operations used by many multimedia applications to be performed using packed data.

[0134] It will be appreciated that a core may support multithreading (performing two or more parallel sets of operations or threads) and may do so in a variety of ways, including time-shared multithreading, simultaneous multithreading (where one physical core provides a logical core for each thread on which the physical core performs simultaneous multithreading), or a combination thereof (e.g., time-shared fetch and decode, and then simultaneous multithreading, such as Intel Hyper-Threading Technology). Layout

[0135] Throughout this description, data is represented using a row-major data layout. Column-major users should convert terms according to these directions. Figure 15 shows an example of a matrix represented in row-major and column-major formats. As shown, matrix A is a 2x3 matrix. When this matrix is ​​stored in row-major format, multiple data elements in a row are contiguous. When this matrix is ​​stored in column-major format, multiple data elements in a column are contiguous. A property of a matrix is ​​that AT *B T =(BA) T is well known, where the superscript T denotes a transformation. If you read the column-major data as row-major data, the resulting matrix is ​​similar to the transformation matrix.

[0136] In some embodiments, row-major semantics is used in the hardware and the column-major data swaps operand order with the matrix transformed result, but for a subsequent column-major read from memory, it is the exact untransformed matrix.

[0137] For example, multiplication of two column-major matrices is: ab gik ag+bh ai+bj ak+bl cd*hjl=cg+dh ci+dj ck+dl ef eg+fh ei+fj ek+fl (3x2) (2x3) (3x3)

[0138] The input matrix is ​​stored in linear memory (column-major order) as follows: acebdf and ghijkl will be stored as

[0139] Reading these matrices row-major with dimensions 2x3 and 3x2 would result in: ace and gh bdf ij kl

[0140] Swap the order and do matrix multiplication: gh ace ag+bh cg+dh eg+fh ij * bdf = ai + bj ci + dj ei + fj kl ak+bl ck+dl ek+fl

[0141] The transformation matrix is ​​output and then stored in row-major order. ag+bh cg+dh eg+fh ai+bj ci+dj ei+fj ak+bl ck+dl ek+fl

[0142] It is then used in subsequent column-major calculations to yield the exact untransformed matrix. ag+bh ai+bj ak+bl cg+dh ci+dj ck+dl eg+fh ei+fj ek+fl Usage example

[0143] FIG. 16 shows an example of the usage of multiple matrices (tiles). In this example, matrix C 1601 contains two tiles, matrix A 1603 contains one tile, and matrix B 1605 contains two tiles. This figure shows an example of an inner loop of an algorithm for computing matrix multiplication. In this example, two result tiles of matrix C 1601, tmm0 and tmmm1, are used for accumulating intermediate results. One tile (tmm2) of matrix A 1603 is reused twice, since it is multiplied with two tiles of matrix B 1605. Pointers load a new A matrix (tile) and two new B matrices (tiles) from the direction indicated by the arrows. An outer loop, not shown, adjusts the pointers to the C tiles.

[0144] The example code shown includes the use of tile setting instructions, which are executed to configure tile usage, load multiple tiles, loop through the tiles, store the tiles in memory, and free the tile usage.

[0145] 17 illustrates an embodiment of a method for multiple matrix (tile) usage. At 1701, tile usage is set. For example, a TILECONFIG instruction is executed to configure tile usage, including setting the number of rows and columns per tile. At 1703, at least one matrix (tile) is typically read from memory. At 1705, an operation of the at least one matrix (tile) is performed using the multiple matrices (tiles). At 1707, the at least one matrix (tile) is flushed to memory and a context switch can be performed at 1709. Exemplary Configurations Tiling Hardware Support

[0146] As described above, tile usage typically needs to be configured before use. For example, it may not be necessary for all rows and columns to be fully used. In some embodiments, the configuration may be used to determine whether an operation will generate an error, as well as not configuring these rows and columns to save power. For example, a matrix multiplication of the form (N×M)*(L×N) will typically not work unless M and L are the same.

[0147] Before using tiled matrices, in some embodiments, the tile support must be configured, e.g., how many rows and columns there are per tile, how many tiles there are to be used, etc. The TILECONFIG instruction is an improvement to the computer itself, as it provides support for configuring the computer to use a matrix accelerator (either as part of the processor core or as an external device). In particular, executing the TILECONFIG instruction retrieves configuration from memory and applies it to the configuration of matrices (tiles) within the matrix accelerator. Tile Usage Settings

[0148] Figure 18 illustrates support for setting tile usage according to one embodiment. Memory 1801 contains tile descriptions 1803 of supported matrices (tiles).

[0149] The instruction execution resources 1811 of the processor / core 1805 store aspects of the tile description 1803 in a tile configuration 1817. The tile configuration 1817 includes a palette table 1813 that details which tiles are set in the palette (the number of rows and columns for each tile) and marks where matrix support is used. In particular, the instruction execution resources 1811 are configured to use tiles as specified by the tile configuration 1817. The instruction execution resources 1811 may include machine specific registers and configuration registers that indicate tile usage. Additional values ​​such as in use and start values ​​are also set. The tile configuration 1817 uses register(s) 1819 to store tile usage and configuration information.

[0150] Figure 19 shows an embodiment of a description of supported matrices (tiles). This is the description to be stored upon execution of the STTILECFG instruction. In this example, each field is a byte. In byte[0], the palette ID 1901 is stored. The palette ID is used to index into a palette table 1813, which stores, for each palette ID, the number of bytes in the tile and the bytes per row of the tile associated with this ID as defined by the settings above.

[0151] Byte 1 stores the value to be stored in the "startRow" register 1903, and byte 2 stores the value to be stored in the register startP 1905. The instructions store information in these registers to support restart commands after these events. The instructions store information in these registers to support restart commands after break events as detailed above. The startRow value indicates which row should be used for restart. The startP value indicates the location within the row of the store operation when a pair is used, and in some embodiments indicates the lower half of the row (lower tile of the pair) or the upper half of the row (upper tile of the pair). Generally, the row (column) location is not required.

[0152] With the exception of TILECONFIG and STTILECFG, successful execution of a matrix (tile) instruction will result in setting both startRow and startP to zero.

[0153] Whenever an interrupted matrix (tile) instruction does not restart, it is the software's responsibility to zero the startRow and startP values. For example, an unmasked floating-point exception handler may decide to end operations in software and change the program counter value to another instruction, usually the next instruction. In this case, the software exception handler must zero the startRow and startP values ​​of the exception raised by the operating system before resuming the program. The operating system will then use the restore instruction to successfully reload those values.

[0154] Byte 3 stores the index of the pair of tiles 1907 (1B per tile).

[0155] Bytes 16-17 store the number of rows 1913 and columns 1915 of tile 0, bytes 18-19 store the number of rows and columns of tile 1, etc. In other words, each two-byte group specifies the number of rows and columns of one tile. If two-byte groups are not used to specify tile parameters, they should have zero values. Specifying tile parameters for more tiles than the implementation or palette limits results in an error. Unconfigured tiles are set to an initial state of 0 row and 0 column.

[0156] Eventually, the structure in memory will typically end up with an ending delineation, such as several consecutive bytes that are all zero. Exemplary Tile and Tile Configuration Storage

[0157] 20A-20D show example registers 1819. FIG. 20A shows multiple registers 1819. As shown, each tile (TMM0 2001...TMMN 2003) has a separate register, with each register storing the row and column size for that particular tile. StartP 2011 and StartRow 2013 are stored in separate registers. One or more status registers 2015 are set to indicate that the tiles are configured to be used (e.g., TILES_CONFIGURED=1).

[0158] 20B shows a number of registers 1819. As shown, each tile has separate registers for its rows and columns. For example, TMM0 Row Configuration 2021, TMM0 Column Configuration 2023, StartP 2011 and StartRow 2013 are stored in separate registers. One or more status registers 2015 are set to indicate that the tiles are configured to be used (e.g., TILES_CONFIGURED=1).

[0159] 20C shows a single register 1819. As shown, this register stores the tile configuration (rows and columns per tile) 2031, with StartP 2011 and StartRow 2013 stored in a single register as a packed data register. One or more status registers 2015 are set to indicate that tiles are configured to be used (e.g., TILES_CONFIGURED=1).

[0160] Figure 20D shows a number of registers 1819. As shown, a single register stores the tile configuration (rows and columns per tile) 2031. StartP and StartRow are stored in separate registers 2011 and 2013. One or more status registers 2015 are set to indicate that the tiles are configured to be used (e.g., TILES_CONFIGURED=1).

[0161] Other combinations are contemplated, such as combining the start registers into a single register and displaying them separately. Configurable Systolic Array

[0162] As mentioned above, hardware for general matrix multiplication (aka GEMM) is a good option to improve peak computation (and energy efficiency) for certain applications such as deep learning. The huge computational demands for applications based on deep neural networks (DNNs) may result in the use of hardware (e.g., accelerators) that use a large number (e.g., hundreds) of processing elements, e.g., fused multiply-add (FMA) circuits. However, accelerators (e.g., DNNs) may be optimized for the highly regular data flow patterns in dense matrix multiplication. In a particular embodiment, the accelerator uses a systolic array implementation to maximize performance and area / power efficiency. The systolic array may include a dense two-dimensional array optimized for highly regular data flow.

[0163] However, because some parts of the execution do not map perfectly to regular data flows, operations (e.g., problems) that do not map perfectly to those data flows, and therefore hardware optimized for those data flows, can lead to significantly underutilization of processing elements (e.g., arithmetic logic unit (ALU) circuits), for example, in a systolic array. In one embodiment, certain matrix multiplications do not fully utilize the hardware array, for example, multiplications that occur due to small problem sizes, or that occur around matrix boundaries that are not multiples of the array size.

[0164] In certain embodiments, accelerators optimized for fixed matrix sizes suffer from low utilization. For example, consider a workload where the matrix width is 36 and the systolic array width is 32 (e.g., a matrix operation accelerator circuit). If the array is padded with zeros (or the entire tile is reconfigured), the hardware processes a full-width tile that is 32 elements wide in the first pass, and then processes tiles that are only 4 elements wide in the next pass. Thus, the overall efficiency is 56.25% (average 32 / 32=100%, 4 / 32=12.5%). In certain embodiments, moving values ​​to a vector accelerator (e.g., a vector stack separate from the matrix operation accelerator circuit) is expensive and the peak computation is much smaller than for a systolic array (e.g., a matrix operation accelerator circuit).

[0165] A particular embodiment of this specification is a configurable systolic array (e.g., a matrix math accelerator circuit) that supports multiple simultaneous smaller matrix multiplications and a new instruction that drives the hardware. In the particular hardware, decoding and executing the instruction causes the configurable systolic array hardware (e.g., a matrix math accelerator circuit) to compute C=A*B+C, where A, B, and C are each two-dimensional matrices, and for each element of C, the hardware computes the dot product of one row of the input matrix A with one column of the matrix B. A particular embodiment of this specification is a new instruction (and hardware support in the systolic array) that takes A and B (e.g., and C) inputs, each of which is composed of multiple matrices "glued" together, to generate multiple output matrices.

[0166] The advantage of this solution is that it allows the hardware to be more flexible, and therefore obtain maximum utilization under more conditions than other solutions. For example, if the number of processing elements (e.g., ALU circuits) in an array is 32x32 in size, and the A matrix is ​​16 wide and 32 high, the hardware will allow the user to effectively "glue" two such A matrices together to obtain a 32x32 A', thereby fully utilizing the array.

[0167] For deep learning and other applications, embodiments herein enable execution of a single instruction to operate simultaneously on multiple small matrices in a systolic array, thereby increasing utilization of processing elements (e.g., ALU circuits). Moreover, embodiments herein provide this capability without paying the high-performance / area / power tax for large matrix operations.

[0168] Designing an accelerator for each different size of matrix is ​​impractical in certain embodiments. A systolic array implementation may use a dense two-dimensional grid of processing elements (e.g., FMA circuits) for fixed size input and / or output matrices. Thus, in contrast to the case of smaller than fixed size matrix sizes provided by either reconfiguring registers (e.g., improving efficiency only by a certain amount in one dimension) or padding matrices with zeros to make them fit the size of the array, embodiments herein use hardware (and one or more instructions) that operate simultaneously (e.g., processed together) on multiple small matrices. Certain embodiments herein provide a matrix operation accelerator circuit that does not use zero padding of data values ​​(e.g., inputs) that are moved to / from a vector stack (e.g., an Intel AVX stack via a data cache unit DCU) and / or data values ​​(e.g., inputs).

[0169] In a particular embodiment, the matrix operations accelerator circuit receives as input a plurality (e.g., two or three) (e.g., each two-dimensional) matrix A (M×K dimensional, where M and K are integers), matrix B (K×N dimensional, where K and N are integers), and matrix C (M×N dimensional, where M and N are integers), and then performs an operation on each element (e.g., fused multiplication addition) to generate a result that is stored as a matrix (e.g., returned to matrix C of M×N dimensional, where M and N are integers). In one embodiment, M, K, and N are less than or equal to 16. In a particular embodiment, the matrix operations accelerator circuit performs the following operations:

[0170]

number

[0171] FIG. 21 illustrates an embodiment of a matrix operation accelerator circuit 2100 comprising a two-dimensional grid of processing element circuits 2106-1 to 2106-4. In a particular embodiment, a data storage 2102 (e.g., a register file) has a plurality of registers, e.g., including respective sets of registers representing a first input two-dimensional matrix (A), a second input two-dimensional matrix (B), and a third input two-dimensional matrix (C) (and, e.g., a result storage). In one embodiment, the results of the output two-dimensional matrix are stored in registers forming the third input two-dimensional matrix (C), e.g., overwriting the values ​​of the input two-dimensional matrix (C) after they have been used by the matrix operation accelerator circuit 2100. The illustrated matrix operation accelerator circuit 2100 includes a plurality of routing circuits 2104-1 to 2104-4 to route input values ​​(e.g., from matrix A and matrix B) to processing elements according to the operation to be performed.

[0172] It should be noted that the figures herein may not show all data communication couplings (e.g., connections). Those skilled in the art will appreciate that this is to avoid obscuring certain details in the figures. It should be noted that bidirectional arrows in the figures may not require bidirectional communication, and may, for example, indicate one-way communication (e.g., to / from that component or device). Any or all combinations of communication paths may be used in certain embodiments herein. A single line may include multiple paths therein, e.g., multiple channels. For example, line 2110 may include multiple paths (e.g., X paths, where X is any positive integer), e.g., one path for values ​​from matrix A and one path for values ​​from matrix B.

[0173] Upon a request to perform an operation (e.g., by decoding and executing an instruction to cause that operation), in a particular embodiment, the matrix operation accelerator circuit 2100 transmits values ​​from matrix A and matrix B to each routing circuit. For example, the operation may be to multiply matrix A by matrix B and then add a corresponding value from matrix C to each result. In one embodiment, the first routing circuit 2104-1 receives a first value A[0][0] from matrix A[row][column] (value from row index 0 and column index 0), broadcasts that value to each processing element 2106-1, a row to each first input of the processing element 2106-1 and a set of values ​​from the first row of matrix B, and transmits these values ​​to each second input of the processing element 2106-1 (e.g., such that processing element 2112 receives a value from B[0][0], processing element 2114 receives a value from B[0][1], etc.). In one embodiment, processing element 2112 provides the result of the multiplication of A[0][0]*B[0][0] at its output 2116, and processing element 2114 provides the result of the multiplication of A[0][0]*B[0][1] at its output 2118. Multiple outputs (e.g., outputs 2116 and 2118) are sent to routing circuit 2 2104-2.

[0174] In one embodiment, the second routing circuit 2104-2 receives a second value A[0][1] from matrix A[row][column] (the value from row index 0 and column index 1), broadcasts the value to each processing element 2106-2, to each first input of the processing element 2106-2 and to a row to a set of multiple values ​​from the second row of matrix B, and sends these multiple values ​​to each second input of the processing element 2106-1 (e.g., whereby processing element 2122 receives a value from B[1][0], processing element 2124 receives a value from B[1][1], etc.) and to each output from the multiple outputs of the row of the processing element 2106-1. In one embodiment, processing element 2122 provides at its output 2126 the result of the multiplication of A[0][1]*B[1][0] added to output 2116 (A[0][0]*B[0][0]), and processing element 2124 provides at its output 2128 the result of the multiplication of A[0][1]*B[1][1] added to output 2118 (A[0][0]*B[0][1]). In a particular embodiment, this fused multiply-add operation continues through each row of processing elements 2106-3 through 2106-4 to generate output 2130 and output 2132 from processing element 2106-4. Note that 4 is an exemplary number of rows of processing elements (and thus rows and columns of each matrix A, B, and C, for example), and could be any multiple of rows. Upon reaching the end of a row of processing elements for the matrix operations accelerator circuit 2100, the bias adder circuit 2108 adds each element (e.g., each element from the first row of matrix C) from the input 2134 (e.g., a parallel input port) and stores the result in each element of matrix C (e.g., each element position of the first row of matrix C) via the output 2136 (e.g., a set of parallel output ports). For example, the first element from the first row of matrix C is added to the result from the output 2130 and the result is stored back in the first element position of the first row of matrix C, and the second element from the first row of matrix C is added to the result from the output 2132 and the result is stored back in the second element position of the first row of matrix C. This is repeated for each row of matrix A, generating an overall multiplication of matrix A*matrix B (and, for example, adding a bias from matrix C to each result).

[0175] Thus, particular embodiments of the circuit use a two-dimensional (2D) array of processing elements (PEs) (e.g., FMA units), together with, for example, a number of input and output buffers and local control logic. In one embodiment, each PE gets some of its inputs from a data store such as a register file, other inputs from other PEs, and the last row of PEs sends its output back to the data store. Thus, the PEs form a pipeline in these embodiments. A user may generally intend to perform a series of operations on a large set of data elements (e.g., more data elements than there are PEs). Thus, elements may be input to the top of the array to start the pipeline, and data may flow downwards through the pipeline (with additional inputs provided at various stages of the pipeline, if appropriate).

[0176] In one embodiment, each instance of a processing element is a fused multiply-accumulate (FMA) circuit and includes a multiplier circuit (e.g., receiving a first input a, a second input b, and generating a result output) and an adder circuit (e.g., adding the result output from the multiplier circuit as a first input with a third input c to generate a result).

[0177] A particular embodiment herein is a new instruction (and hardware support in a systolic array) that accepts A and B (e.g., and C) inputs, each of which is composed of multiple matrices "glued" together to produce multiple output matrices, instead of operating only on a single matrix A, a single matrix B, and a single matrix C. To simplify the control used for data flow within the two dimensions of the FMA circuit, a particular embodiment herein provides control of a multiple matrix dot-product operation without modifying the control of a fused multiply-add operation.

[0178] 22 is a block diagram illustrating the use of a TILE PARTIAL DOT PRODUCT instruction 2201 to accelerate matrix operations according to some embodiments. The instruction 2201 causes an operation of (matrix A * matrix B) + matrix C to be performed by a matrix operation accelerator circuit 2220. The matrix operation accelerator circuit 2220 may be an instance of the matrix operation accelerator circuit 2400 of FIG. 24 or the matrix operation accelerator circuit 2600 of FIG. 26.

[0179] Instead of operating only on a single matrix A, a single matrix B, and a single matrix C, the instruction 2201 (and the matrix operation accelerator circuit 2400 of FIG. 24 and the matrix operation accelerator circuit 2600 of FIG. 26) can operate on multiple input matrices simultaneously. For example, embodiments herein may fetch an A tile side-by-side with multiple matrices A (e.g., by rearranging data) (e.g., matrix A2222 includes a first row A1 of data and a second row A2 of data from the same A matrix, while A1′ and A2′ are the first row of data and the second row of data, respectively, from another A matrix). Depending on the application, embodiments herein can form a B tile by either replicating the same B matrix or by splicing together multiple B matrices (e.g., with a first row B1 data and a first row B′ data from different B matrices, as shown in FIG. 22). In other embodiments, the B matrix may be replicated, so that, for example, B1′=B1. In a particular embodiment, the hardware supports access to multiple C matrices (e.g., as shown in Figure 22). In one embodiment, separate instructions (e.g., as shown in the software) generate tile A from different matrices, generate B tiles from either different B matrices or a replicated B matrix, and form C tiles from either different C matrices or a replicated C matrix (e.g., C1'=C1, C2'=C2, and / or C1=C2).

[0180] Thus, certain embodiments of instruction 2201, when decoded and executed, operate precisely on A & B inputs each made up of multiple matrices "glued" together, producing multiple output matrices after adding each C value.

[0181] Thus, in one operation mode, the matrix operation accelerator circuit generates an updated C1=(A1*B1+A1′*B2′+···)+C1. However, in certain embodiments, this is not the desired operation when A and A′ are different matrices that are both input. Instead, in another operation mode, the matrix operation accelerator circuit performs fewer operations per output element, for example, updated C1=A1*B1+C1. This means that there are more output elements in the second mode than in the first mode. The resulting updated C matrix may be packed into multiple output matrices glued together (e.g., as shown in updated matrix C2226 of FIG. 22) or may have multiple independent destinations.

[0182] An example instruction format has the mnemonic TILEPARTIALDOT PRODUCT (or TPNDP for "tile partial 'N' dot product"), where N is the number of different matrices to be logically glued together. For example, if two A matrices are input to an A tile (and also, for example, two B matrices are input to a B tile), the instruction may be referred to as TP2DP. The instruction may have the format TPNDPtsrcdest, tsrc1, tsrc2, where a first field "tsrcdest" identifies the tile source / destination (e.g., tile 2226), a second field "tsrc1" identifies the second tile source (e.g., tile 2222), and a third field "tsrc2" identifies the third tile source (e.g., tile 2224). In one embodiment (e.g., with large output tiles), the size of the output tiles is implicit. In an embodiment with multiple output tiles, the number of output tiles is N (N is any positive integer). The specific tile registers may be consecutive, starting from tsrcdest (e.g., tmm0 and tmmm1, where tmm0 is specific and N=2), or other designations may be used to select groups of multiple registers. In a particular embodiment, new instructions are used to process matrices of given different sizes glued together. For example, a matrix operation accelerator circuit can process four matrices glued together, but if only two matrix inputs glued together (one of them is three times larger than the other) are provided, one-quarter of the elements will come from one matrix and three-quarters from the other, which may be specified in the opcode (e.g., T1AND3DP) or via an immediate value passed to the instruction (e.g., TPDP tsrcdest, tsrc1, tsrc2, imm8). Possible encodings of the immediate value are described below.

[0183] FIG. 22 is a block diagram illustrating the use of a TILE PARTIAL DOT PRODUCT instruction 2201 to accelerate a matrix dot product operation, according to some embodiments. As shown, the instruction 2201 includes an opcode 2202 (e.g., TILE TRANSFORM), which indicates a processor performing a dot product on a matrix in accordance with the present disclosure. In particular, in a particular embodiment, in response to the opcode, the processor performs each operation on each of multiple matrices stored in a single input tile. For example, source location 1 2206 stores one or more A matrices, source location 2 2208 stores one or more B matrices, and source location 3 2204 stores one or more C matrices. Optionally, the instruction may include fields (e.g., operands or opcodes) that indicate the M 2210 (e.g., number of rows) and K 2212 (e.g., number of columns) of one or more of the input or output matrices. The size and / or number of matrices "glued" together may be specified in one or more of several ways, including as operands of the TILEPARTIALDOTPRODUCT instruction, as a suffix or prefix of a specified opcode, as part of an immediate value 2214 provided with the instruction, as part of a control register programmed in software prior to issuing the instruction (e.g., TILECONFIG), or even as architectural default values. In particular embodiments, M and K may each be selected from an unlimited range of integer values.

[0184] The instruction 2201 further specifies a destination matrix (e.g., tile) location 2204. Each specified matrix location may be in either a memory location, a set of vector registers, or a set of tile registers, where the specified source 2206, 2208, 2210 and destination matrix 2216 each include multiple elements. In one embodiment, the elements are 64-bit or 32-bit.

[0185] Also shown is a system 2200 for executing the TILE PARTIAL DOT PRODUCT instruction 2201. The system includes source location 1 2222 for storing one or more A matrices, source location 2224 for storing one or more B matrices, source location 3 2226 for storing one or more C matrices, a matrix operations accelerator circuit 2220, and a designated destination matrix (tile) 2226.

[0186] There may be alternative, lesser approaches to perform these matrix operations, but they do not provide the power and performance gains of the disclosed embodiment that implements the TILE PARTIAL DOT PRODUCT instruction. In some other approaches, software loads the data into vector / SIMD registers, performs the transformation using vector instructions, writes the reformatted data to memory, and then loads the reformatted data into the 2D / vector / tile registers. However, performing the format transition with vector instructions can be slow, require complex software tuning, and may require more space in the cache.

[0187] 23 illustrates a method 2300 for processing a TILE PARTIAL DOT PRODUCT instruction according to embodiments of the present disclosure. The method 2300 includes fetching, using a fetch circuitry, an instruction having a format having fields specifying an opcode, a location of a source tile, and a destination tile, where the opcode indicates that the processor is to perform a dot product operation on an appropriate subset of data of each matrix in a plurality of matrices in a single source tile, and further comprising decoding the fetched instruction 2303 using a decode circuitry, scheduling execution of the decoded matrix instruction 2305, responding to the decoded instruction using an execution circuitry by performing the dot product operation on the appropriate subset of data and storing the result in the destination tile 2307, and committing the result of the executed instruction 2309. In one embodiment, the instruction switches the matrix operations accelerator circuitry between a first mode (e.g., having only a single matrix in each input tile / each set of registers) and a second mode (e.g., having multiple matrices in at least one of the input tiles / each set of registers).

[0188] In a particular embodiment, the operation starts similarly to the matrix operation accelerator circuit 2100 of FIG. 21, where a data value is input to the top of the array to start the pipeline, and successive results are transferred bit by bit through the pipeline (e.g., additional inputs are provided at various stages of the pipeline, if appropriate). For example, data flows downward from one PE to the next PE through a routing channel. To provide configurability to the matrix operation accelerator circuit, in a particular embodiment herein, a configuration switch is added to the matrix operation accelerator circuit at regular intervals (e.g., configuration switch 2438 after the fourth row of PEs in FIG. 23). In a particular embodiment, the configuration switch is a pair of multiple demultiplexers and multiple multiplexers. In one embodiment, when the configuration switch is turned on, the demultiplexer adds an initial value C to the result output from the previous PE before writing it to the C buffer, and the multiplexer for the next PE transfers zero instead of transferring the output of the previous PE. Thus, a particular embodiment herein interrupts the chain of dot products and starts a new chain. In one embodiment, when a configuration switch is turned off, the complete matrix math accelerator circuit behaves like a single pipeline with one output stage to C. This means that, for example, if an input data value is inserted at the beginning of the pipeline (e.g., processing element 2406-1), the results will flow (e.g., downwards in the direction shown) until they reach an enabled configuration switch. At this stage, the pipeline, in a particular embodiment, breaks off after adding the value to the corresponding C element, writes the value to a buffer, and the next stage in the pipeline, for example, is read as if the output value of the previous PE was zero. This can therefore be thought of as the beginning of a new pipeline.

[0189] In a particular embodiment, the configuration switches are controlled by one or more instructions. For example, a first instruction turns off all the configuration switches (e.g., a single matrix in each tile multiplication), and a second instruction turns on one or more rows of multiple configuration switches (e.g., multiple matrices in each tile). For example, an instruction for processing two evenly sized matrices logically glued together (e.g., TP2DP as described above) (e.g., two evenly sized matrices in each of tiles A, B, and C) turns on a row of configuration switches in the center of the PE array to perform A*B+C for a first set of matrices stored in tiles A, B, and C, and A'*B'+C' for a second set of matrices stored in tiles A, B, and C.

[0190] 24 illustrates an embodiment of a matrix operations accelerator circuit 2400 comprising a two-dimensional grid of processing element circuits 2406-1 through 2406-5 including rows of configuration switches (e.g., routing circuits and configuration switches) that switch between a first mode and a second mode. In one embodiment, a decode and execute instruction switches the matrix operations accelerator circuit 2400 from the first mode (e.g., having only a single matrix in each input tile / each set of registers) to the second mode (e.g., having multiple matrices in at least one of the input tiles / each set of registers) or from the second mode to the first mode.

[0191] In a particular embodiment, the data storage 2402 (e.g., a register file) has a plurality of registers, e.g., including respective sets of registers representing at least one (e.g., multiple) first input two-dimensional matrix (A), at least one (e.g., multiple) second input two-dimensional matrix (B), and at least one (e.g., multiple) third input two-dimensional matrix (C) (and, e.g., result storage). In one embodiment, the results of the output two-dimensional matrix are stored in registers forming the at least one third input two-dimensional matrix (C), e.g., overwriting the values ​​of the input two-dimensional matrix (C) after they have been used by the matrix operation accelerator circuit 2400.

[0192] In one embodiment, in the first mode, the values ​​stored in the first plurality of registers represent a single input two-dimensional matrix A and the values ​​stored in the second plurality of registers represent a single input two-dimensional matrix B (and, e.g., the values ​​stored in the third plurality of registers represent a single input two-dimensional matrix C), and in the second mode, the values ​​stored in the first plurality of registers represent multiple input two-dimensional matrices A and A' and the values ​​stored in the second plurality of registers represent multiple input two-dimensional matrices B and B' (and, e.g., the values ​​stored in the third plurality of registers represent multiple input two-dimensional matrices C and C').

[0193] The illustrated matrix operation accelerator circuit 2400 includes multiple routing circuits 2402-1 to 2402-4 that route input values ​​(eg, from matrices A and A' and matrices B and B') to processing elements according to the operation to be performed.

[0194] It should be noted that the figures herein may not show all data communication couplings (e.g., connections). Those skilled in the art will appreciate that this is to avoid obscuring certain details in the figures. It should be noted that bidirectional arrows in the figures may not require bidirectional communication, and may, for example, indicate one-way communication (e.g., to / from that component or device). Any or all combinations of communication paths may be used in certain embodiments herein. A single line may include multiple paths therein, e.g., multiple channels. For example, line 2410 may include multiple paths (e.g., X paths, where X is any positive integer), e.g., one path for values ​​from matrix A and one path for values ​​from matrix B.

[0195] Upon a request to perform an operation (e.g., by decoding and executing an instruction to cause that operation), in a particular embodiment, matrix operation accelerator circuit 2400 sends values ​​from tile A and tile B to each routing circuit. For example, the operation may be, for a first mode, multiplying matrix A from tile A with matrix B from tile B and then adding each result to a value corresponding to matrix C from tile C, and for a second mode, multiplying matrix A from tile A with matrix B from tile B and then adding each result to a value corresponding to matrix C from tile C, and multiplying matrix A' from tile A with matrix B' from tile B and then adding each result to a value corresponding to matrix C' from tile C.

[0196] In one embodiment, the first routing circuit 2404-1 receives a first value A[0][0] from matrix A[row][column] (the value from row index 0 and column index 0), broadcasts the value to each of the processing elements 2406-1, a row to a first input of each of the processing elements 2406-1 and a set of values ​​from the first row of matrix B, and transmits the values ​​to a respective second input of each of the processing elements 2406-1 (e.g., whereby processing element 2412 receives a value from B[0][0], processing element 2414 receives a value from B[0][1], etc.). In one embodiment, processing element 2412 provides at its output 2416 the result of the multiplication of A[0][0]*B[0][0], and processing element 2414 provides at its output 2418 the result of the multiplication of A[0][0]*B[0][1]. Multiple outputs (eg, outputs 2416 and 2418) are sent to routing circuit 2 2404-2.

[0197] In one embodiment, the second routing circuit 2404-2 receives a second value A[0][1] from matrix A[row][column] (the value from row index 0 and column index 1), broadcasts the value to each processing element 2406-2, to each first input of the processing element 2406-2 and to a row to a set of values ​​from the second row of matrix B, and sends those values ​​to each second input of the processing element 2406-1 (e.g., whereby processing element 2422 receives a value from B[1][0], processing element 2424 receives a value from B[1][1], etc.) and to each output from the multiple outputs of the row of the processing element 2406-1. In one embodiment, the processing element 2422 provides at its output 2426 the result of the multiplication of A[0][1]*B[1][0] added to the output 2416 (A[0][0]*B[0][0]), and the processing element 2424 provides at its output 2428 the result of the multiplication of A[0][1]*B[1][1] added to the output 2418 (A[0][0]*B[0][1]). In a particular embodiment, this fused multiply-add operation continues through each row of processing elements 2406-3 through 2406-4 to generate outputs 2430 and 2432 from the processing elements 2406-4. Compared to the matrix operation accelerator circuit 2100 of FIG. 21, the matrix operation accelerator circuit 2400 of FIG. 24 includes a routing circuit 2438 having a configuration switch. The configuration switch 2438 may be multiple instances (e.g., in parallel) of the configuration switch 2500 of FIG. 25.

[0198] In particular embodiments, in the first mode, the setting switch 2438 passes the results from the fourth row of processing elements 2406-4 (e.g., output 2430 and output 2432) to the next row of processing elements 2406-5 to be added to the results of the fifth row of processing elements 2406-5 (e.g., output 2430 as an input to PE 2454 and output 2432 as an input to PE 2456). For the five rows shown for processing element 2406-5, routing circuit 2438 with setting switch, in a first mode, receives value A[0][4] for input 2442 from matrix A[row][column] (value from row index 0 and column index 4), broadcasts that value to each processing element 2406-5, to the row to each first input of processing element 2406-5 and to the set of multiple values ​​for input 2444 from the fourth row of matrix B, and sends those multiple values ​​to each second input of processing element 2406-5 (e.g., whereby input 2450 of processing element 2454 receives a value from B[4][0], input 2452 of processing element 2456 receives a value from B[4][1], etc.). In one embodiment of the first mode, processing element 2454 provides at its output 2458 the result of the multiplication A[0][0]*B[0][0]+A[0][1]*B[1][0]+A[0][2]*B[2][0]+A[0][3]*B[3][0]+A[0][4]*B[4][0], and processing element 2456 provides at its output 2460 the result of the multiplication A[0][0]*B[0][1]+A[0][1]*B[1][1]+A[0][2]*B[2][1]+A[0][3]*B[3][1]+A[0][4]*B[4][1]. Upon reaching the end of a row of processing elements for the matrix operation accelerator circuit 2400, the biased summation circuit 2462 sums each element (e.g., each element from the first row of matrix C) from the inputs 2434 (e.g., parallel input ports) and stores the results in each element of matrix C (e.g., each element position in the first row of matrix C) via the outputs 2436 (e.g., a set of parallel output ports).For example, the first element from the first row of matrix C is added to the result from output 2458 and the result is stored back into the first element position of the first row of matrix C, and the second element from the first row of matrix C is added to the result from output 2460 and the result is stored back into the second element position of the first row of matrix C. This is repeated for each row of matrix A to produce an overall multiplication of matrix A*matrix B (and, for example, adding a bias from matrix C to each result). Thus, in certain embodiments of the first mode, when operating on a single matrix within each tile (e.g., with the tile being a proper subset of the registers of the matrix operations accelerator circuit), the bias adder circuit 2440 is not used.

[0199] In a particular embodiment in the second mode (e.g., tile A includes matrix A and matrix A', tile B includes matrix B and matrix B', and tile C includes matrix C and matrix C'), configuration switch 2438 does not pass the results from the fourth row of processing elements 2406-4 (e.g., outputs 2430 and 2432) to the next row of processing elements 2406-5 to be added to the results of the fifth row of processing elements 2406-5 (e.g., output 2430 is not an input to PE 2454, and output 2432 is not an input to PE 2456). In the second mode (e.g., in an example where matrix A is four columns wide), routing circuitry 2438 with configuration switch sends the result values ​​from the fourth row of processing elements 2406-4 (e.g., outputs 2430 and 2432) to biased adder circuitry 2440.

[0200] In a particular embodiment of the second mode, a first processing element from the fourth row 2406-4 provides at its output 2430 the result of the multiplication A[0][0]*B[0][0]+A[0][1]*B[1][0]+A[0][2]*B[2][0]+A[0][3]*B[3][0], and a second processing element 2456 from the fourth row 2406-4 provides at its output 2432 the result of the multiplication A[0][0]*B[0][1]+A[0][1]*B[1][1]+A[0][2]*B[2][1]+A[0][3]*B[3][1]. Upon reaching the end of a row of a first subset of multiple matrices (e.g., matrices A, B, and C), biased adder circuit 2440 adds each element (e.g., each element from the first row of matrix C) from input 2446 (e.g., a parallel input port) and stores the result in each element of matrix C (e.g., in each element position of the first row of matrix C) via output 2448 (e.g., a set of parallel output ports). For example, the first element from the first row of matrix C is added to the result from output 2430 and the result is stored back in the first element position of the first row of matrix C, and the second element from the first row of matrix C is added to the result from output 2432 and the result is stored back in the second element position of the first row of matrix C.

[0201] In a particular embodiment of the second mode, the routing circuit 2438 with configuration switch receives the value A′[0][0] from matrix A′ (and does not receive A[0][4] from matrix A) at input 2442 from matrix A′[row][column] (where the value of the second matrix A′ is row index 0 and column index 0) and routes that value to each of the processing elements 2406-5, the first input of each of the processing elements 2406-5 and the first row of matrix B′ (matrix 24. The PE 2406-5 broadcasts these values ​​to a row in the input 2444 from B'[0][0] (not the fourth row of B) and sends these values ​​to each of the second inputs of processing element 2406-5 (e.g., so that input 2450 of processing element 2454 receives a value from B'[0][0], input 2452 of processing element 2456 receives a value from B'[0][1], etc.), but output 2430 is not an input to PE 2454 and output 2432 is not an input to PE 2456.

[0202] In a particular embodiment of the second mode, processing element 2454 provides at its output 2458, the result of the multiplication of A'[0][0]*B'[0][0], and processing element 2456 provides at its output 2460, the result of the multiplication of A'[0][0]*B'[0][1]. Upon reaching the end of a row of processing elements for matrix operation accelerator circuit 2400, biased adder circuit 2462 adds each element (e.g., each element from the first row of matrix C) from matrix C' (not matrix C) at input 2434 (e.g., a parallel input port) and stores the result in each element of matrix C' (e.g., each element position in the first row of matrix C') via output 2436 (e.g., a set of parallel output ports). For example, the first element from the first row of matrix C' is added to the result from output 2458 and the result is stored back into the first element position of the first row of matrix C', and the second element from the first row of matrix C' is added to the result from output 2460 and the result is stored back into the second element position of the first row of matrix C. This is then (i) repeated for each row of matrix A to generate a total multiplication of matrix A*matrix B (and, e.g., adding a bias from matrix C to each result), and (ii) repeated for each row of matrix A' to generate a total multiplication of matrix A'*matrix B' (and, e.g., adding a bias from matrix C' to each result). In certain embodiments of the second mode, when operating on multiple matrices within each tile (e.g., with the tiles being a suitable subset of the registers of the matrix operation accelerator circuit), a bias adder circuit 2440 is used. Note that 5 is an example number of rows of processing elements (and thus the maximum number of rows and columns of each of matrices A, B, and C to be processed, for example), and could be any number of rows.

[0203] 25 illustrates an embodiment of a setting switch 2500. The illustrated circuit 2502 includes a setting switch 2500 and a bias summing circuit 2504. The illustrated setting switch 2500 is coupled between a first processing element 2506 (e.g., upstream) and a second processing element 2508 (e.g., downstream). For example, the first processing element 2506 may be the processing element 2430 of FIG. 24 and the second processing element may be the processing element 2454 of FIG. 24.

[0204] In the illustrated embodiment, the first processing element 2506 includes a first input 2516 that provides data (e.g., result) from a previous PE (e.g., a PE in a previous row), a second input 2510 that provides data from Tile A (e.g., internally stored matrix A and / or matrix A'), and a third input 2512 that provides data from Tile B (e.g., internally stored matrix B and / or matrix B'). In one embodiment, the first processing element 2506 multiplies elements from Tile A provided from the second input 2510 with elements from Tile B provided from the third input 2512 to generate an intermediate result, and then adds the intermediate result to a data element from the first input 2516 to generate a result. In one embodiment, the result is then passed to an input port of the configuration switch 2500, e.g., a demultiplexer 2520.

[0205] In a particular embodiment, when a first control value (e.g., 0) is sent to the setting switch input 2526, (i) the result from the first processing element 2506 is routed from an input port of the demultiplexer 2520 to an output port coupled to path 2528 and to a first input port of the multiplexer 2522, and (ii) the result is sent from the output port of the multiplexer 2522 to a first input port 2532 of the second processing element 2508. In the embodiment shown, the second processing element includes a first input 2532 that provides data (e.g., result) from the previous PE 2506 (e.g., in a first mode) or 0 (e.g., in a second mode) from the source 2524, a second input 2510 that provides data from Tile A (e.g., matrix A and / or matrix A' stored internally), and a third input data 2512 that provides data from Tile B (e.g., matrix B and / or matrix B' stored internally). In one embodiment, the second processing element 2508 multiplies an element from Tile A provided at its second input 2510 with an element from Tile B provided at its third input 2512 to generate an intermediate result, and then adds the intermediate result to the result from the PE 2506 provided at its first input 2532 to generate a result. In one embodiment, the result is then passed downstream via output 2518, for example to an input port of another processing element.

[0206] In a particular embodiment, when a second control value (e.g., 1) is sent to the setting switch input 2526, (i) the result from the first processing element 2506 is routed from an input port of the demultiplexer 2520 to an output port coupled to path 2530 and to the bias summing circuit 2504, and (ii) a 0 from the source 2524 is sent from an output port of the multiplexer 2522 to a first input port 2532 of the second processing element 2508. In the embodiment shown, the second processing element includes a first input 2532 that provides data (e.g., a result) from the previous PE 2506 (e.g., in a first mode) or a 0 from the source 2524 (e.g., in a second mode), a second input 2510 that provides data from Tile A (e.g., matrix A and / or matrix A' stored internally), and a third input data 2512 that provides data from Tile B (e.g., matrix B and / or matrix B' stored internally). In one embodiment, the second processing element 2508 multiplies elements from Tile A provided from the second input 2510 with elements from Tile B provided from the third input 2512 to generate an intermediate result, and then adds the intermediate result to zeros from source 2524 provided from the first input 2532 to generate a result (e.g., the dot product chain is broken to a new matrix A' instead of matrix A). In one embodiment, the result is then passed downstream via output 2518, e.g., to an input port of another processing element. In one embodiment, the biased summation circuit 2504 provides each element from port 2514 to Tile C, adds each element to the result from path 2530, and stores the updated result back in each element position of Tile C via port 2514. In a particular embodiment, a respective instance of the circuit 2502 is provided between each pair of upstream and downstream PEs supporting multiple modes as described herein.

[0207] 26 illustrates an embodiment of a matrix operation accelerator circuit 2602 comprising a two-dimensional grid of processing elements including multiple rows of configuration switches 2606-1 through 2606-7 that switch between multiple modes. In a particular embodiment, each circuit block 2604-1 through 2604-8 is an instance of circuit block 2470 of FIG. 25. In the illustrated embodiment, circuit blocks 2604-1 through 2604-7 are coupled to respective instances of routing circuits 2606-1 through 2606-7 (e.g., as described with reference to FIG. 24) having configuration switches, which in turn are coupled to respective instances of bias summation circuits (e.g., as described with reference to FIG. 24), and circuit block 2604-8 is coupled to bias summation circuit 2608-8. FIG. 26 illustrates that multiple suitable subsets (e.g., rows) of configuration switches may be included to control, in a first mode, the result data continues pipeline processing through the matrix operation accelerator circuit 2602, and in a different mode, the result data is routed from the processing element to stop the pipeline processing of the data, for example, by routing the result data to respective instances of the bias adder circuitry and updating respective values ​​in Tile C with the result data.

[0208] The mode selection control value(s) may be provided by a decode and execute instruction (e.g., the partial equal dot product instruction described herein). In one embodiment, the instruction includes an immediate value to explicitly encode the control for the configuration switches. The immediate value (e.g., configuration parameter) is an encoded value, and the following table may show how it is decoded and programmed to be on or off for each set (e.g., row) of configuration switches, e.g., an array having seven rows of configuration switches. If an application wants to turn on multiple configuration switches for the same array, a different encoding may be used. The instruction may carry the number of output tiles or the size of the output tiles, or the hardware may infer this from the number of configuration switches turned on. Table: Example of settings (Table 1-2 is a continuation of Table 1-1) [Table 1-1] [Table 1-2]

[0209] Exemplary architectures, systems, etc. that may be used above are detailed below.

[0210] At least some embodiments of the disclosed technology will be described in view of the following examples. Example 1: A matrix operation accelerator circuit having a two-dimensional grid of fused multiply-add circuits; a first plurality of registers representing at least one first input two-dimensional matrix coupled to the matrix operation accelerator circuit; a second plurality of registers representing at least one second input two-dimensional matrix coupled to the matrix operation accelerator circuit; a decoder of a core coupled to the matrix operation accelerator circuit, the decoder decoding a single instruction into a decoded single instruction and having a field identifying a storage resulting from the single instruction; execution circuitry of said core for executing said single decoded instruction; Equipped with and an execution circuit of the core causes the matrix operation accelerator circuit to transition from a first mode to a second mode in which each output of each of a first suitable subset of fused multiply-add circuits of the two-dimensional grid is transmitted to a respective input of each of a second suitable subset of fused multiply-add circuits of the two-dimensional grid downstream to form output values ​​from the at least one first input two-dimensional matrix and the at least one second input two-dimensional matrix and store the output values ​​in the resulting storage. and switching to a second mode in which each output for each of the second suitable subset of fused product-accumulator circuits of the two-dimensional grid forms a second output value from a second subset of the at least one first input two-dimensional matrix and the at least one second input two-dimensional matrix and stores the first output value in the resulting storage. 2. The apparatus of Example 1, wherein the single instruction has a second field indicating that the matrix operation accelerator circuit executes in the first mode if the second field is a first value, and executes in the second mode if the second field is a second value. 3. The apparatus of example 2, wherein the second field is an immediate value of the single instruction. 4. The apparatus of example 1, wherein the resulting storage is a third plurality of registers representing at least one output two-dimensional matrix formed by executing the single decoded instruction. 5. Executing the single decoded instruction, in said first mode, adding values ​​from said third plurality of registers representing at least one third input two-dimensional matrix initially stored in said third plurality of registers to said output value to form an updated output value, and storing said updated output value in said resulting storage in place of said output value; 5. The apparatus of example 4, wherein in the second mode, adding values ​​from the at least one third input two-dimensional matrix initially stored in the third plurality of registers to the first output values ​​and the second output values ​​to form updated first output values ​​and updated second output values, and storing the updated first output values ​​and the updated second output values ​​in the resulting storage in place of the first output values ​​and the second output values. 6. Executing the single decoded instruction, in said first mode, adding to said output value a value from at least one third input two-dimensional matrix initially stored in a third plurality of registers to form an updated output value, and storing said updated output value in said resulting storage in place of said output value; and, in the second mode, adding values ​​from the at least one third input two-dimensional matrix initially stored in the third plurality of registers to the first output values ​​and the second output values ​​to form updated first output values ​​and updated second output values, and storing the updated first output values ​​and the updated second output values ​​in the resulting storage in place of the first output values ​​and the second output values. 7. The apparatus of example 1, wherein the resulting storage is a third plurality of registers representing a plurality of output two-dimensional matrices formed by executing the single decoded instruction. 8. The first suitable subset of the fused sum-of-products circuits is one of the rows or columns in the two-dimensional grid of the fused sum-of-products circuits; 2. The apparatus of example 1, wherein the second suitable subset of the fused product-sum circuits is the other one of the rows or columns in the two-dimensional grid of fused product-sum circuits. Example 9: Decoding a single instruction at a decoder of a processor core into a decoded single instruction, the processor core being coupled to a matrix operation accelerator circuit having a two-dimensional grid of fused multiply-add circuits, the matrix operation accelerator circuit being coupled to a first plurality of registers representing at least one first input two-dimensional matrix and a second plurality of registers representing at least one second input two-dimensional matrix, the single instruction having a field identifying a resulting storage; executing said decoded single instruction in execution circuitry of said processor core; Equipped with The executing step causes the matrix operation accelerator circuit to transition from a first mode to a second mode in which each output of each of the first suitable subset of fused product-accumulator circuits of the two-dimensional grid is transmitted to a respective input of each of a second suitable subset of fused product-accumulator circuits of the two-dimensional grid downstream to form output values ​​from the at least one first input two-dimensional matrix and the at least one second input two-dimensional matrix and store the output values ​​in the resulting storage. and switching to a second mode in which each output for each of the second suitable subset of fused product-accumulator circuits of the two-dimensional grid forms a second output value from a second subset of the at least one first input two-dimensional matrix and the at least one second input two-dimensional matrix and stores the first output value in the resulting storage. 10. The method of example 9, wherein the single instruction has a second field indicating that the matrix operation accelerator circuit executes in the first mode if the second field is a first value, and executes in the second mode if the second field is a second value. 11. The method of example 10, wherein the second field is an immediate value of the single instruction. 12. The method of example 9, wherein the resulting storage is a third plurality of registers representing at least one output two-dimensional matrix formed by executing the single decoded instruction. 13. The step of executing the single decoded instruction comprises: in said first mode, adding values ​​from said third plurality of registers representing at least one third input two-dimensional matrix initially stored in said third plurality of registers to said output value to form an updated output value, and storing said updated output value in said resulting storage in place of said output value; 13. The method of claim 12, wherein in the second mode, adding values ​​from the at least one third input two-dimensional matrix initially stored in the third plurality of registers to the first output values ​​and the second output values ​​to form updated first output values ​​and updated second output values, and storing the updated first output values ​​and the updated second output values ​​in the resulting storage in place of the first output values ​​and the second output values. 14. The step of executing the single decoded instruction, in said first mode, adding to said output value a value from at least one third input two-dimensional matrix initially stored in a third plurality of registers to form an updated output value, and storing said updated output value in said resulting storage in place of said output value; 10. The method of claim 9, wherein in the second mode, adding values ​​from the at least one third input two-dimensional matrix initially stored in the third plurality of registers to the first output values ​​and the second output values ​​to form updated first output values ​​and updated second output values, and storing the updated first output values ​​and the updated second output values ​​in the resulting storage in place of the first output values ​​and the second output values. 15. The method of example 9, wherein the resulting storage is a third plurality of registers representing a plurality of output two-dimensional matrices formed by executing the single decoded instruction. 16. The first suitable subset of the fused sum-of-products circuits is one of the rows or columns in a two-dimensional grid of the fused sum-of-products circuits; 10. The method of example 9, wherein the second suitable subset of fused multiply-add circuits is the other one of the rows or the columns in the two-dimensional grid of fused multiply-add circuits. Example 17. A non-transitory machine-readable medium storing code that, when executed by a machine, causes the machine to perform a method, the method comprising: decoding a single instruction at a decoder of a processor core into a decoded single instruction, the processor core being coupled to a matrix operation accelerator circuit having a two-dimensional grid of fused multiply-add circuits, the matrix operation accelerator circuit being coupled to a first plurality of registers representing at least one first input two-dimensional matrix and a second plurality of registers representing at least one second input two-dimensional matrix, the single instruction having a field identifying a resulting storage; executing said decoded single instruction in execution circuitry of said processor core; Equipped with The executing step causes the matrix operation accelerator circuit to switch from a first mode to a second mode in which each output of a first suitable subset of fused multiply-add circuits of the two-dimensional grid is transmitted to a respective input of a second suitable subset of fused multiply-add circuits of the two-dimensional grid downstream to form output values ​​from the at least one first input two-dimensional matrix and the at least one second input two-dimensional matrix, and store the output values ​​in the resulting storage, such that each output of each of the first suitable subset of fused multiply-add circuits of the two-dimensional grid downstream to form output values ​​from the at least one first input two-dimensional matrix and the at least one second input two-dimensional matrix, forming first output values ​​from at least one first input two-dimensional matrix and a first subset of the at least one second input two-dimensional matrix and storing the first output values ​​in the resulting storage, and switching to a second mode in which each output for each of the second suitable subset of the two-dimensional grid fused sum-of-products circuits forms second output values ​​from a second subset of the at least one first input two-dimensional matrix and the at least one second input two-dimensional matrix and storing the second output values ​​in the resulting storage. 18. The non-transitory machine-readable medium of Example 17, wherein the single instruction has a second field indicating that the matrix operation accelerator circuit executes in the first mode if the second field is a first value, and executes in the second mode if the second field is a second value. 19. The non-transitory machine-readable medium of example 18, wherein the second field is an immediate value of the single instruction. 20. The non-transitory machine-readable medium of Example 17, wherein the resultant storage is a third plurality of registers representing at least one output two-dimensional matrix formed by executing the decoded single instruction. 21. The step of executing the single decoded instruction comprises: in said first mode, adding values ​​from said third plurality of registers representing at least one third input two-dimensional matrix initially stored in said third plurality of registers to said output value to form an updated output value, and storing said updated output value in said resulting storage in place of said output value; 21. The non-transitory machine-readable medium of Example 20, wherein in the second mode, values ​​from the at least one third input two-dimensional matrix initially stored in the third plurality of registers are added to the first output value and the second output value to form updated first output value and updated second output value, and the updated first output value and the updated second output value are stored in the resulting storage in place of the first output value and the second output value. 22. The step of executing the single decoded instruction comprises: in said first mode, adding to said output value a value from at least one third input two-dimensional matrix initially stored in a third plurality of registers to form an updated output value, and storing said updated output value in said resulting storage in place of said output value; 18. The non-transitory machine-readable medium of Example 17, wherein in the second mode, adding values ​​from the at least one third input two-dimensional matrix initially stored in the third plurality of registers to the first output value and the second output value to form updated first output value and updated second output value, and storing the updated first output value and the updated second output value in the resulting storage in place of the first output value and the second output value. 23. The non-transitory machine-readable medium of Example 17, wherein the resulting storage is a third plurality of registers representing a plurality of output two-dimensional matrices formed by executing the single decoded instruction. 24. The first suitable subset of the fused sum-of-products circuits is one of the rows or columns in the two-dimensional grid of the fused sum-of-products circuits; 20. The non-transitory machine-readable medium of Example 17, wherein the second suitable subset of the fused sum-of-products circuits is the other one of the rows or columns in the two-dimensional grid of the fused sum-of-products circuits.

[0211] In yet another embodiment, the apparatus comprises a data storage device storing code that, when executed by a hardware processor, causes the hardware processor to perform any method disclosed herein. The apparatus may be as described in the detailed description. The method may be as described in the detailed description. Detailed Exemplary Systems, Processors and Emulation

[0212] Examples of hardware, software, etc. for executing the above-mentioned instructions are detailed herein. For example, described below are details as to aspects of instruction execution including various pipeline stages such as, for example, fetching, decoding, scheduling, executing, retiring, etc. Instruction Set

[0213] An instruction set may include one or more instruction formats. A given instruction format may define various fields (e.g., number of bits, bit positions) that specify, among other things, the operation to be performed (e.g., opcode) and the operands on which the operation is to be performed, and / or other data fields (e.g., masks). Some instruction formats are further subdivided by the definition of instruction templates (or sub-formats). For example, the instruction templates of a given instruction format may be defined as having various subsets of the fields of the instruction format (where the included fields are typically in the same order, but at least some have different bit positions due to a smaller number of included fields) and / or as having certain fields that are interpreted differently. Thus, each instruction of the ISA is expressed using a given instruction format (and in one of the instruction templates of the instruction format, if defined) and includes fields for specifying the operation and the operands. For example, an exemplary ADD instruction has a particular opcode and an instruction format that includes an opcode field for specifying the opcode and operand fields for selecting the operands (source1 / destination and source2). Occurrences of this ADD instruction in the instruction stream will have particular contents in the operand field that select a particular operand. A set of SIMD extensions called Next Generation Vector Extensions (AVX) (AVX1 and AVX2) and using the Vector Extensions (VEX) encoding scheme have been released and / or published (see, e.g., Intel® 64 and IA-32 Architectures Software Developer's Manual, November 2018 and Intel® Architecture Instruction Set Extensions Programming Reference, October 2018). Example instruction formats

[0214] Embodiments of the instructions described herein may be embodied in different forms. In addition, example systems, architectures, and pipelines are detailed below. Embodiments of the instructions may be executed on such systems, architectures, and pipelines, but are not limited to those detailed. Generic Vector Instruction Format

[0215] The vector friendly instruction format is an instruction format that is suitable for vector instructions (e.g., has certain fields that are specific to vector operations). Although embodiments are described in which both vector and scalar operations are supported through the vector friendly instruction format, alternative embodiments use only vector operations supported through the vector friendly instruction format.

[0216] 27A-27B are block diagrams illustrating a generic vector friendly instruction format and its instruction templates according to embodiments of the present disclosure. FIG. 27A is a block diagram illustrating a generic vector friendly instruction format and its class A instruction templates according to embodiments of the present disclosure, and FIG. 27B is a block diagram illustrating a generic vector friendly instruction format and its class B instruction templates according to embodiments of the present disclosure. Specifically, a generic vector friendly instruction format 2700 is defined for class A and class B instruction templates, both of which include a no memory access 2705 instruction template and a memory access 2720 instruction template. The term generic in the context of vector friendly instruction formats refers to instruction formats that are not tied to a specific instruction set.

[0217] In an embodiment of the present disclosure, the vector friendly instruction format supports 64 byte vector operand lengths (or sizes) having 32-bit (4 byte) or 64-bit (8 byte) data element widths (or sizes) (so a 64 byte vector is made up of either 16 doubleword sized elements or alternatively 8 quadword sized elements), 64 byte vector operand lengths (or sizes) having 16-bit (2 byte) or 8-bit (1 byte) data element widths (or sizes), 32-bit (4 byte), 64-bit (8 byte), 16-bit (2 byte) or 8-bit (1 byte) data element widths (or sizes), While described as supporting vector operand lengths (or sizes) of 32 bytes having a raw width (or size), and vector operand lengths (or sizes) of 16 bytes having 32-bit (4-byte), 64-bit (8-byte), 16-bit (2-byte) or 8-bit (1-byte) data element widths (or sizes), alternative embodiments may support more, fewer and / or different vector operand sizes (e.g., 256-byte vector operands) having more, fewer or different data element widths (e.g., 128-bit (16-byte) data element widths).

[0218] The class A instruction templates of Figure 27A include: 1) a no memory access 2705 instruction template shows a no memory access, full round control type operation 2710 instruction template and a no memory access, data transform type operation 2715 instruction template; and 2) within the memory access 2720 instruction template, a memory access, temporal 2725 instruction template and a memory access, non-temporal 2730 instruction template are shown. The class B instruction templates of Figure 27B include: 1) within the no memory access 2705 instruction template, a no memory access, write mask control, partial round control type operation 2712 instruction template and a no memory access, write mask control, vsize type operation 2717 instruction template are shown; and 2) within the memory access 2720 instruction template, a memory access, write mask control 2727 instruction template is shown.

[0219] The generic vector friendly instruction format 2700 includes the following fields, listed below in the order shown in Figures 27A-27B:

[0220] Format field 2740 - a particular value in this field (the value of the instruction format identifier) ​​uniquely identifies the vector friendly instruction format and thus the occurrence of an instruction in the vector friendly instruction format in an instruction stream. As such, this field is optional in the sense that it is not required for an instruction set that has only the generic vector friendly instruction format.

[0221] Basic operation field 2742: its contents distinguish between different basic operations.

[0222] Register index field 2744 - its contents specify, either directly or through address generation, the location of the source and destination operands, whether they are in registers or in memory. These contain a number of bits sufficient to select N registers from a PxQ (e.g., 32x512, 16x128, 32x1024, 64x1024) register file. In one embodiment, N can be up to three source and one destination register, although alternative embodiments may support more or fewer source and destination registers (e.g., supporting up to two sources, one of which may also act as a destination, supporting up to three sources, one of which may also act as a destination, supporting up to two sources and one destination).

[0223] A qualifier field 2746 - its content distinguishes between occurrences of instructions of the generic vector instruction format that specify memory access from instructions that do not, i.e., distinguishes between no-memory access 2705 instruction templates and memory access 2720 instruction templates. Memory access operations read and / or write to the memory hierarchy (in some cases using values ​​in registers to specify source and / or destination addresses), while non-memory access operations do not (e.g., the source and destination are registers). In one embodiment, this field also selects among three different ways of performing memory address calculations, although alternative embodiments may support more, fewer, or different ways of performing memory address calculations.

[0224] Extended operation field 2750 - its contents distinguish which of a variety of different operations should be performed in addition to the basic operations. This field is context specific. In one embodiment of the present disclosure, this field is split into a class field 2768, an alpha field 2752, and a beta field 2754. The extended operation field 2750 allows a common group of operations to be performed in a single instruction, rather than two, three, or four instructions.

[0225] Scale field 2760 - its contents allow for scaling of the contents of the index field for memory address generation (e.g., 2 [スケール] *For address generation using [index]+[base]).

[0226] Displacement field 2762A - its contents are used as part of memory address generation (e.g., 2 [スケール] *Used for address generation using [index]+[base]+[displacement].

[0227] Displacement factor field 2762B (note that the juxtaposition of displacement field 2762A directly above displacement factor field 2762B indicates that one or the other is used) - its contents are used as part of address generation, it specifies the displacement factor to be scaled by the size of the memory access (N) - N may be (e.g., 2 [スケール]*[index]+[base]+[scaled displacement] is the number of bytes in a memory access (for address generation using [index]+[base]+[scaled displacement]). Redundant low-order bits are ignored, so the contents of the displacement factor field are multiplied by the total size of the memory operands (N) to generate the final displacement to be used in calculating the effective address. The value of N is determined by the processor hardware at run-time based on the full opcode field 2774 and the data manipulation field 2754C (described later in this specification). The displacement field 2762A and the displacement factor field 2762B are optional in the sense that they are not used for the non-memory access 2705 instruction templates and / or different embodiments may implement only one or neither of the two.

[0228] Data element width field 2764 - its contents distinguish which of multiple data element widths should be used (in some embodiments for all instructions, in other embodiments for only some instructions). This field is optional in the sense that it is not needed if only one data element width is supported and / or if data element widths are supported using some aspect of the opcode.

[0229] A write mask field 2770 - its contents control, for each data element position, whether that data element position in the destination vector operand reflects the results of the basic and extended operations. Class A instruction templates support merging-write masking, while class B instruction templates support both merging-write masking and zero write masking. When merging, the vector mask allows any set of elements in the destination to be protected from updates during the execution of any operation (specified by the basic and extended operations), but in one embodiment, retains the old value of each element in the destination if the corresponding mask bit has a zero value. In contrast, when writing zero, the vector mask allows any set of elements in the destination to be zero-written during the execution of any operation (specified by the basic and extended operations), but in one embodiment, an element in the destination is set to zero if the corresponding mask bit has a zero value. A subset of this functionality is the ability to control the vector length of the operation being performed (i.e., the range of elements being modified, from the first element to the last element), but the modified elements do not need to be contiguous. Thus, the write mask field 2770 allows for partial vector operations including loads, stores, arithmetic, logical, etc. While several embodiments of the present disclosure are described in which the contents of the write mask field 2770 select one of a number of write mask registers containing the write mask to be used (and thus the contents of the write mask field 2770 indirectly identify that masking to be performed), alternative embodiments allow the contents of the mask write field 2770 to instead or additionally directly specify the masking to be performed.

[0230] Immediate Field 2772 - its contents allow for the specification of an immediate value. This field is optional in the sense that it is not present in implementations of the generic vector friendly format that do not support immediate values, and that it is not present in instructions that do not use immediate values.

[0231] Class field 2768 - its contents distinguish between different classes of instructions. With reference to Figures 27A-27B, the contents of this field select between class A and class B instructions. In Figures 27A-27B, a rounded rectangle is used to indicate that a particular value is present in a field (e.g., class A 2768A and class B 2768B, respectively, of class field 2768 in Figures 27A-27B). Instruction Template Class A

[0232] For class A no memory access 2705 instruction templates, the alpha field 2752 is interpreted as an RS field 2752A whose contents distinguish which of the different augmented operation types are to be performed (e.g., round 2752A.1 and data transform 2752A.2 are specified for the no memory access, round type operation 2710 and no memory access, data transform type operation 2715 instruction templates, respectively), while the beta field 2754 distinguishes which of the specified types of operations are to be performed. The scale field 2760, displacement field 2762A, and displacement scale field 2762B are not present in the no memory access 2705 instruction templates. Non-memory access instruction template - full round control type operation

[0233] In a no memory access, full round control type operation 2710 instruction template, the beta field 2754 is interpreted as a round control field 2754A, whose contents provide static rounding. In described embodiments of the disclosure, the round control field 2754A includes a suppress all floating-point exceptions (SAE) field 2756 and a round operation control field 2758, although alternative embodiments may support encoding both of these concepts in the same field or may only have one or the other of these concepts / fields (e.g., may only have the round operation control field 2758).

[0234] SAE field 2756 - its contents distinguish whether exception event reporting should be disabled or not. If the contents of SAE field 2756 indicate that suppression is enabled, then the given instruction will not report any floating-point exception flags of any kind and will not raise any floating-point exception handlers.

[0235] A round operation control field 2758 - its contents distinguish which rounding operation from a group of rounding operations (e.g., round up, round down, round towards zero, and round to nearest) to perform. Thus, the round operation control field 2758 allows changing the rounding mode on an instruction-by-instruction basis. In one embodiment of the present disclosure in which the processor includes a control register for specifying multiple rounding modes, the contents of the round operation control field 2750 override the register value. Memory Access Instruction Templates - Data Transformation Type Operations

[0236] In a non-memory access data transform type operation 2715 instruction template, the beta field 2754 is interpreted as a data transform field 2754B, whose contents distinguish which of a number of data transforms should be performed (e.g., no data transform, swizzle, broadcast).

[0237] For memory access 2720 instruction templates of class A, the alpha field 2752 is interpreted as an eviction hint field 2752B, whose content distinguishes which of the eviction hints should be used (in FIG. 27A , temporal 2752B.1 and non-temporal 2752B.2 are specified for the memory access, temporal 2725 instruction template and the memory access, non-temporal 2730 instruction template, respectively), while the beta field 2754 is interpreted as a data manipulation field 2754C, whose content distinguishes which of a number of data manipulation operations (also known as primitives) should be performed (e.g., no operation, broadcast, up-conversion of source, and down-conversion of destination). The memory access 2720 instruction templates include a scale field 2760, and possibly a displacement field 2762A or a displacement scale field 2762B.

[0238] Vector memory instructions perform vector loads from memory and vector stores to memory with conversion support. Like regular vector instructions, vector memory instructions transfer data to and from memory on a data element by data element basis, with the elements actually transferred being dictated by the contents of a vector mask selected as the write mask. Memory Access Instruction Templates - Temporal

[0239] Transient data is data that is likely to be reused quickly enough to benefit from caching, however this is a suggestion and different processors may implement it in different ways, including ignoring this suggestion entirely. Memory Access Instruction Templates - Non-temporal

[0240] Non-transient data is data that is unlikely to be reused quickly enough to benefit from caching in the first level cache and should be given priority for eviction, however this is a suggestion and different processors may implement it in different ways, including ignoring this suggestion entirely. Class B instruction template

[0241] For class B instruction templates, the alpha field 2752 should be interpreted as a write mask control (Z) field 2752C, whose content distinguishes whether the write masking controlled by the write mask field 2770 should be merging or zero writing.

[0242] For class B no memory access 2705 instruction templates, a portion of the beta field 2754 should be interpreted as an RL field 2757A, whose contents distinguish which of the different extended operation types should be performed (e.g., round 2757A.1 and vector length (VSIZE) 2757A.2 are specified for the no memory access, write mask control, partial round control type operation 2712 instruction template and the no memory access, write mask control, VSIZE type operation 2717 instruction template, respectively), while the remainder of the beta field 2754 distinguishes which of the specified types of operations should be performed. The scale field 2760, displacement field 2762A, and displacement scale field 2762B are not present in the no memory access 2705 instruction templates.

[0243] For the no memory access, write mask control, partial round control type operation 2710 instruction template, the remainder of the beta field 2754 is interpreted as the round operation field 2759A and exception event reporting is disabled (the given instruction will not report any floating-point exception flags of any kind and will not raise any floating-point exception handlers).

[0244] Round operation control field 2759A - similar to round operation control field 2758, its content distinguishes which of a group of rounding operations to perform (e.g., round up, round down, round towards zero, and round to nearest). Thus, the round operation control field 2759A allows for changing the rounding mode on an instruction-by-instruction basis. In one embodiment of the present disclosure in which the processor includes a control register for specifying multiple rounding modes, the content of the round operation control field 2750 overrides the register value.

[0245] In the no memory access write mask control VSIZE type operation 2717 instruction template, the remainder of the beta field 2754 is interpreted as a vector length field 2759B, whose contents distinguish which of a number of data vector lengths should be executed (e.g., 128 bytes, 256 bytes, or 512 bytes).

[0246] For class B memory access 2720 instruction templates, a portion of the beta field 2754 is interpreted as a broadcast field 2757B, whose contents distinguish whether a broadcast-type data manipulation operation is to be performed or not, and the remainder of the beta field 2754 is interpreted as a vector length field 2759B. The memory access 2720 instruction templates include a scale field 2760 and, possibly, a displacement field 2762A or a displacement scale field 2762B.

[0247] With respect to the generic vector friendly instruction format 2700, a full opcode field 2774 is shown which includes a format field 2740, a primitive operation field 2742, and a data element width field 2764. Although one embodiment is shown as including the full opcode field 2774 with all of these fields, in embodiments which do not support all of these fields, the full opcode field 2774 includes less than all of these fields. The full opcode field 2774 provides an operation code (opcode).

[0248] The extended operation field 2750, data element width field 2764, and write mask field 2770 allow these characteristics to be specified on a per-instruction basis in the generic vector friendly instruction format.

[0249] The combination of the write mask field and the data element width field forms a typed instruction, in that a mask can be applied based on different data element widths.

[0250] The various instruction templates found in class A and class B are useful in different situations. In some of the embodiments of the present disclosure, different processors or different cores within a processor may support only class A, only class B, or both classes. For example, a high performance general purpose out-of-order core intended for general purpose computing may support only class B, a core intended primarily for graphics and / or scientific (throughput) computing may support only class A, and a core intended for both may support both (of course, a core may have some combination of templates and instructions from both classes, but not all templates and instructions from both classes are within the scope of the present disclosure). Also, a single processor may contain multiple cores, all of which support the same class, or different cores therein may support different classes. For example, in a processor with separate graphics and general purpose cores, one of the graphics cores intended primarily for graphics and / or scientific computing may support only class A, and one or more of the general purpose cores may be a high performance general purpose core with out-of-order execution and register renaming intended for general purpose computing that supports only class B. Another processor without a separate graphics core may include one more general-purpose in-order or out-of-order core that supports both class A and class B. Of course, functions from one class may also be implemented in other classes in different embodiments of the present disclosure. Programs written in high-level languages ​​are converted (e.g., just-in-time or statically compiled) into a variety of different executable forms, including 1) a form that has only instructions of classes supported by the target processor for execution, or 2) a form that has alternative routines written using different combinations of instructions of all classes, and has control flow code that selects which routine to execute based on the instructions supported by the processor currently executing the code. Example Vector Specific Instruction Format

[0251] FIG. 28 is a block diagram illustrating an example vector specific instruction format according to embodiments of the present disclosure. FIG. 28 illustrates a specific vector specific instruction format 2800, which is specific in the sense that it specifies the location, size, interpretation and field order, as well as values ​​for some of those fields. The specific vector specific instruction format 2800 may be used to extend the x86 instruction set, and thus some fields are similar or the same as those used in the existing x86 instruction set and its extensions (e.g., AVX). The format remains consistent with the prefix encoding field, real opcode byte field, MOD R / M field, SIB field, displacement field, and immediate field of the existing x86 instruction set with extensions. It is illustrated which fields in FIG. 27 map to which fields in FIG. 28.

[0252] Although embodiments of the present disclosure are described with reference to the specific vector instruction format 2800 in the context of the generic vector instruction format 2700 for illustrative purposes, it should be understood that the present disclosure is not limited to the specific vector instruction format 2800 except as set forth in the claims. For example, the generic vector instruction format 2700 contemplates a variety of possible sizes for various fields, while the specific vector instruction format 2800 is shown as having fields of specific sizes. By way of a specific example, the data element width field 2764 is shown in the specific vector instruction format 2800 as a one-bit field, although the present disclosure is not so limited (i.e., the generic vector instruction format 2700 contemplates data element width fields 2764 of other sizes).

[0253] The generic vector friendly instruction format 2700 includes the following fields, listed below in the order shown in FIG. 28A:

[0254] The EVEX prefix (bytes 0-3) 2802 is encoded into a 4-byte format.

[0255] Format field 2740 (EVEX byte 0, bits [7:0]) - The first byte (EVEX byte 0) is the format field 2740, which contains 0x62 (a unique value used to distinguish vector friendly instruction formats in one embodiment of the present disclosure).

[0256] The second through fourth bytes (EVEX bytes 1-3) contain a number of bit fields that provide specific capabilities.

[0257] The REX field 2805 (EVEX byte 1, bits [7-5]) - this consists of the EVEX.R bit field (EVEX byte 1, bit [7] - R), the EVEX.X bit field (EVEX byte 1, bit [6] - X) and the 2757BEX byte 1, bit [5] - B). The EVEX.R, EVEX.X and EVEX.B bit fields serve the same function as the corresponding VEX bit fields and they are encoded using one's complement format, i.e. ZMM0 is encoded as 1111B and ZMM15 is encoded as 0000B. The other fields of the instruction encode the lower three bits of the register index (rrr, xxx and bbb) as known in the art, such that Rrrr, Xxxx and Bbbb may be formed by adding EVEX.R, EVEX.X and EVEX.B.

[0258] REX' Field 2710 - This is the first part of the REX' field 2710, the EVEX.R' bit field (EVEX byte 1, bit [4]-R') that is used to encode either the top 16 or the bottom 16 of the extended 32 register set. In one embodiment of the disclosure, this bit is stored in a bit-reversed format along with others as shown below to distinguish it from the BOUND instruction (in the well-known x86 32-bit mode) whose real opcode byte is 62, but the MOD R / M field (described below) does not accept a value of 11 in the MOD field. Alternative embodiments of the disclosure do not store this bit and the others as shown below in an inverted format. A value of 1 is used to encode the bottom 16 registers. In other words, R'Rrrr is formed by combining EVEX.R', EVEX.R, and the other RRR from the other fields.

[0259] Opcode map field 2815 (EVEX byte 1, bits [3:0]-mmmm)-its contents encode the implied leading opcode byte (0F, 0F38, or 0F3).

[0260] Data Element Width field 2764 (EVEX Byte 2, Bit [7]-W)--represented by the notation EVEX.W. EVEX.W is used to define the granularity (size) of the data type (either 32-bit data elements or 64-bit data elements).

[0261] EVEX.vvvv 2820 (EVEX byte 2, bits [6:3] - vvvv) - The role of EVEX.vvvv may include: 1) EVEX.vvvv encodes the first source register operand specified in inverted (one's complement) format and is valid for instructions with two or more source operands. 2) EVEX.vvvv encodes the destination register operand specified in one's complement format for certain vector shifts. 3) EVEX.vvvv does not encode any operand, the field is reserved and should contain 1111b. Thus, the EVEX.vvvv field 2820 encodes the lower 4 bits of the first source register specifier stored in inverted (one's complement) format. Depending on the instruction, additional different EVEX bit fields are used to extend the specifier size to 32 registers.

[0262] The Class field of EVEX.U2768 (EVEX byte 2, bit [2]-U) - When EVEX.U=0, it indicates class A or EVEX.U0, when EVEX.U=1, it indicates class B or EVEX.U1.

[0263] Prefix encoding field 2825 (EVEX byte 2, bits [1:0]-pp) - provides additional bits to the basic operation field. In addition to providing support for legacy SSE instructions in EVEX prefix format, it also has the advantage of compressing the SIMD prefix (rather than requiring one byte to represent a SIMD prefix, the EVEX prefix only requires two bits). In one embodiment, to support legacy SSE instructions that use SIMD prefixes (66H, F2H, F3H) in both legacy and EVEX prefix formats, these legacy SIMD prefixes are encoded in the SIMD prefix encoding field and expanded to legacy SIMD prefixes at run-time before being provided to the PLA of the decode circuitry (so the PLA can execute both the legacy and EVEX formats of these legacy instructions without modification). Although newer instructions could directly use the contents of the EVEX prefix encoding field as an opcode extension, certain embodiments do the extension as well for consistency but allow these legacy SIMD prefixes to specify different meanings. Alternative embodiments could redesign the PLA to support 2-bit SIMD prefix encodings and thus not require the extension.

[0264] Alpha field 2752 (EVEX byte 3, bit [7]—EH, also known as EVEX.EH, EVEX.rs, EVEX.RL, EVEX.writemask control, and EVEX.N, also denoted as α): As mentioned previously, this field is context specific.

[0265] Beta field 2754 (EVEX byte 3, bits [6:4] - SSS, also known as EVEX.s2-0, EVEX.r2-0, EVEX.rr1, EVEX.LL0, EVEX.LLB, also denoted as βββ): As stated above, this field is context specific.

[0266] REX' field 2710: This is the remainder of the REX' field, the EVEX.V' bit field (EVEX byte 3, bit [3] - V'), which can be used to encode either the top 16 or the bottom 16 of the extended 32 register set. This bit is stored in bit-reversed form. A value of 1 is used to encode the bottom 16 registers. In other words, combining EVEX.V', EVEX.vvvv forms V'VVVV.

[0267] Write mask field 2770 (EVEX byte 3, bits [2:0] - kkk): its contents specify the index of a register in the write mask register, as described above. In one embodiment of the present disclosure, the special value EVEX.kkk=000 has a special behavior that indicates that there is no write mask to be used for the particular instruction (this may be implemented in a variety of ways, including a write mask that is hardwired into everything, or the use of hardware to bypass the masking hardware).

[0268] The real opcode field 2830 (byte 4) is also known as the opcode byte. Part of the opcode is specified in this field.

[0269] MOD R / M field 2840 (byte 5) includes MOD field 2842, Reg field 2844, and R / M field 2846. As previously described, the contents of MOD field 2842 distinguish between memory access and non-memory access operations. The role of Reg field 2844 can be summarized in two situations: encoding either a destination register operand or a source register operand, or being treated as an opcode extension and not used to encode any instruction operand. The role of R / M field 2846 may include encoding an instruction operand that references a memory address, and encoding either a destination register operand or a source register operand.

[0270] Scale, Index, Base (SIB) Byte (Byte 6): As previously described, the contents of the scale field 2750 are used for memory address generation. SIB.xxx 2854 and SIB.bbb 2856 - The contents of these fields have been described above with respect to register indices Xxxx and Bbbb.

[0271] Displacement Field 2762A (Bytes 7-10) - If the MOD field 2842 contains 10, then bytes 7 through 10 are the displacement field 2762A, which functions the same as the legacy 32-bit displacement (disp32), and works at byte granularity.

[0272] Displacement Factor Field 2762B (Byte 7) - When the MOD field 2842 contains 01, byte 7 is the displacement factor field 2762B. The location of this field is the same as that of the 8-bit displacement (disp8) of the legacy x86 instruction set, which works at byte granularity. Since disp8 is sign-extended, it can only address between -128 and 127 byte offsets, and for a 64-byte cache line, disp8 uses 8 bits that can only be set to the four really useful values ​​-128, -64, 0, and 64, and since a larger range is often needed, disp32 is used, but disp32 requires 4 bytes. In contrast to disp8 and disp32, the displacement factor field 2762B is a reinterpretation of disp8, and when using the displacement factor field 2762B, the actual displacement is determined by the contents of the displacement factor field multiplied by the size of the memory operand access (N). This type of displacement is referred to as disp8 x N. This results in a shorter average instruction length (a single byte used for displacement, but with a much larger range). Such a compressed displacement is based on the assumption that the effective displacement is a multiple of the granularity of the memory access, and therefore the redundant lower bits of the address offset do not need to be encoded. In other words, the displacement factor field 2762B replaces the 8-bit displacement of the legacy x86 instruction set. The displacement factor field 2762B is therefore encoded in the same way as the 8-bit displacement of the x86 instruction set, with the only exception that disp8 is overloaded to disp8×N (so there is no change in the ModRM / SIB encoding rules). In other words, there is no change in the encoding rules or encoding length, only in the interpretation of the displacement value by the hardware (to get the address offset in bytes, the displacement needs to be scaled by the size of the memory operand). The immediate field 2772 works as previously described. Full Opcode Field

[0273] 28B is a block diagram illustrating fields of a specific vector specific instruction format 2800 that form a full opcode field 2774 in accordance with one embodiment of the present disclosure. Specifically, the full opcode field 2774 includes a format 2740, a primitive operation field 2742, and a data element width (W) field 2764. The primitive operation field 2742 includes a prefix encoding field 2825, an opcode map field 2815, and a real opcode field 2830. Register Index Field

[0274] 28C is a block diagram illustrating a vector specific instruction format 2800 forming a register index field 2744 according to one embodiment of the present disclosure. Specifically, the register index field 2744 includes a REX field 2805, a REX′ field 2810, a MODR / M.reg field 2844, a MODR / Mr / m field 2846, a VVVV field 2820, a xxx field 2854, and a bbb field 2856. Extended Operation Fields

[0275] FIG. 28D is a block diagram illustrating the fields of the specific vector instruction format 2800 that form the extended operation field 2750 according to one embodiment of the present disclosure. If the class (U) field 2768 contains a 0, it means EVEX.U0 (Class A 2768A), and if it contains a 1, it means EVEX.U1 (Class B 2768B). If U=0 and the MOD field 2842 contains 11 (signifying a non-memory access operation), the alpha field 2752 (EVEX byte 3, bits [7]—EH) is interpreted as the RS field 2752A. If the RS field 2752A contains a 1 (round 2752A.1), the beta field 2754 (EVEX byte 3, bits [6:4]—SSS) is interpreted as the round control field 2754A. The round control field 2754A includes a 1-bit SAE field 2756 and a 2-bit round operation field 2758. If RS field 2752A contains 0 (data transformation 2752A.2), then beta field 2754 (EVEX byte 3, bits [6:4]—SSS) is interpreted as a 3-bit data transformation field 2754B. If U=0 and MOD field 2842 contains 00, 01 or 10 (signifying a memory access operation), then alpha field 2752 (EVEX byte 3, bit [7]—EH) is interpreted as an eviction hint (EH) field 2752B and beta field 2754 (EVEX byte 3, bits [6:4]—SSS) is interpreted as a 3-bit data manipulation field 2754C.

[0276] If U=1, the alpha field 2752 (EVEX byte 3, bit [7]—EH) is interpreted as a write mask control (Z) field 2752C. If U=1 and the MOD field 2842 contains 11 (representing a non-memory access operation), a portion of the beta field 2754 (EVEX byte 3, bit [4]—S0) is interpreted as the RL field 2757A. If it contains a 1 (round 2757A.1), the remainder of the beta field 2754 (EVEX byte 3, bits [6‐5]—S2-1) is interpreted as the round operation field 2759A, while if the RL field 2757A contains a 0 (VSIZE 2757.A2), the remainder of the beta field 2754 (EVEX byte 3, bits [6‐5]—S2-1) is interpreted as the vector length field 2759B (EVEX byte 3, bits [6‐5]—L1-0). If U=1 and the MOD field 2842 contains 00, 01, or 10 (signifying a memory access operation), the beta field 2754 (EVEX byte 3, bits [6:4]-SSS) is interpreted as the vector length field 2759B (EVEX byte 3, bits [6-5]-L1-0) and the broadcast field 2757B (EVEX byte 3, bits [4]-B). Exemplary Register Architecture

[0277] Figure 29 is a block diagram of a register architecture 2900 according to one embodiment of the present disclosure. In the embodiment shown, there are 32 vector registers 2910 that are 512 bits wide. These registers are referenced zmm0 through zmm31. The lower 256 bits of the lower 16 zmm registers overlap registers ymm0 through ymm16. The lower 128 bits of the lower 16 zmm registers (the lower 128 bits of the ymm registers) overlap registers xmm0 through xmm15. The vector specific instruction format 2800 operates on these overlapped register files as shown in the table below. [Table 2]

[0278] In other words, the vector length field 2759B selects between a maximum length and one or more other shorter lengths, each such shorter length being half the length of the preceding length, and instruction templates without the vector length field 2759B operate on the maximum vector length. Furthermore, in one embodiment, the class B instruction templates of the specific vector friendly instruction format 2800 operate on packed or scalar single / double precision floating point data, and packed or scalar integer data. A scalar operation is an operation performed on the position of the least significant data element in a zmm / ymm / xmm register. Depending on the embodiment, the positions of the more significant data elements are either kept the same as before the instruction or are written with zeros.

[0279] In the illustrated embodiment of write mask registers 2915, there are eight write mask registers (k0 through k7), each 64 bits in size. In an alternative embodiment, write mask registers 2915 are 16 bits in size. As previously mentioned, in one embodiment of the present disclosure, vector mask register k0 cannot be used as a write mask; if an encoding that would normally indicate k0 is used for a write mask, selecting a hardwired write mask of 0xFFFF effectively disables write masking for that instruction.

[0280] In the illustrated embodiment, general purpose registers 2925, there are sixteen 64-bit general purpose registers that are used in conjunction with existing x86 addressing modes to address memory operands. These registers are referenced by the following names: RAX, RBX, RCX, RDX, RBP, RSI, RDI, RSP, and R8 through R15.

[0281] Scalar floating-point stack register file (x87 stack) 2945, into which MMX packed integer flat register file 2950 is aliased - in the illustrated embodiment, the x87 stack is an 8-element stack used to perform scalar floating-point operations on 32 / 64 / 80-bit floating-point data using the x87 instruction set extensions, while the MMX registers are used to perform operations on 64-bit packed integer data, as well as to hold operands for some operations performed between MMX and XMM registers.

[0282] Alternative embodiments of the present disclosure may use wider or narrower registers. Additionally, alternative embodiments of the present disclosure may use more, fewer, or different register files and registers. Exemplary Core Architectures, Processors, and Computer Architectures

[0283] Processor cores may be implemented in different processors in different ways and for different purposes. For example, such core implementations may include 1) a general-purpose in-order core for general-purpose computing, 2) a high-performance general-purpose out-of-order core for general-purpose computing, and 3) a dedicated core primarily for graphics and / or scientific (throughput) computing. Different processor implementations may include 1) a CPU including one or more general-purpose in-order cores for general-purpose computing and / or one or more general-purpose out-of-order cores for general-purpose computing, and 2) a coprocessor including one or more dedicated cores primarily for graphics and / or scientific (throughput). Such different processors result in different computer system architectures that may include 1) a coprocessor on a separate chip from the CPU, 2) a coprocessor on a separate die in the same package as the CPU, 3) a coprocessor on the same die as the CPU (in which case such a coprocessor may be referred to as dedicated logic or dedicated cores, such as integrated graphics and / or scientific (throughput) logic, and 4) a system-on-chip that may include the above-mentioned CPU (which may be referred to as an application core or application processor), the above-mentioned coprocessor, and additional functionality on the same die. An exemplary core architecture is described next, followed by a description of an exemplary processor and computer architecture. Exemplary Core Architecture In-order / out-of-order core block diagram

[0284] FIG. 30A is a block diagram illustrating both an exemplary in-order pipeline and an exemplary register renaming, out-of-order issue / execution pipeline, according to embodiments of the present disclosure. FIG. 30B is a block diagram illustrating both an exemplary embodiment of an in-order architecture core and an exemplary register renaming, out-of-order issue / execution architecture core to be included in a processor, according to embodiments of the present disclosure. The solid lined boxes in FIG. 30A-B indicate the in-order pipeline and the in-order core, while the optionally added dashed lined boxes indicate the register renaming, out-of-order issue / execution pipeline and the core. The out-of-order aspects will be described assuming that the in-order aspects are a subset of the out-of-order aspects.

[0285] In FIG. 30A , the processor pipeline 3000 includes a fetch stage 3002, a length decode stage 3004, a decode stage 3006, an allocation stage 3008, a renaming stage 3010, a scheduling (also known as dispatch or issue) stage 3012, a register read / memory read stage 3014, an execution stage 3016, a writeback / memory write stage 3018, an exception handling stage 3022, and a commit stage 3024.

[0286] 30B shows a processor core 3090 including a front end unit 3030 coupled to an execution engine unit 3050, both coupled to a memory unit 3070. Core 3090 may be a reduced instruction set computing (RISC) core, a complex instruction set computing (CISC) core, a very long instruction word (VLIW) core, or a hybrid or alternative core type. As yet another option, core 3090 may be a special-purpose core, such as, for example, a network or communication core, a compression engine, a co-processor core, a general purpose computing graphics processing unit (GPGPU) core, a graphics core, etc.

[0287] The front-end unit 3030 includes a branch prediction unit 3032 coupled to an instruction cache unit 3034, which is coupled to an instruction translation lookaside buffer (TLB) 3036, which is coupled to an instruction fetch unit 3038, which is coupled to a decode unit 3040. The decode unit 3040 (e.g., a decode circuit) may decode instructions (e.g., macro-instructions) and generate as output one or more micro-operations, microcode entry points, microinstructions, other instructions, or other control signals decoded from or otherwise reflecting or derived from the original instruction. The decode unit 3040 may be implemented using a variety of different mechanisms. Examples of suitable mechanisms include, but are not limited to, look-up tables, hardware implementations, programmable logic arrays (PLAs), microcode read only memories (ROMs), etc. In one embodiment, the core 3090 includes a microcode ROM or other medium that stores microcode for particular macro instructions (e.g., in the decode unit 3040 or otherwise within the front end unit 3030). The decode unit 3040 is coupled to a rename / allocator unit 3052 in the execution engine unit 3050.

[0288] The execution engine units 3050 include a rename / allocator unit 3052 coupled to a retirement unit 3054 and a set of one or more scheduler units 3056. The scheduler units 3056 may represent any number of different schedulers and include reservation stations, central instruction window, etc. The scheduler units 3056 are coupled to physical register files 3058. Each of the physical register file units 3058 represents one or more physical register files, with the different files storing one or more different data types, such as scalar integer, scalar floating point, packed integer, packed floating point, vector integer, vector floating point, status (e.g., an instruction pointer, which is the address of the next instruction to be executed), tiles, etc. In one embodiment, the physical register file units 3058 include a vector register unit, a writemask register unit, and a scalar register unit. These register units may provide architectural vector registers, vector mask registers, and general purpose registers. The physical register files unit 3058 is stacked on the retirement unit 3054 to illustrate various ways in which register renaming and out-of-order execution may be implemented (e.g., using a reorder buffer and retirement register file, using a future file, a history buffer and retirement register file, using a register map and register pools, etc.). The retirement unit 3054 and the physical register files unit 3058 are coupled to the execution cluster 3060. The execution cluster 3060 includes a set of one or more execution units 3062 (e.g., execution circuits) and a set of one or more memory access units 3064. The execution units 3062 may perform various operations (e.g., shift, add, subtract, multiply) and may operate on various data types (e.g., scalar floating point, packed integer, packed floating point, vector integer, vector floating point).Some embodiments may include multiple execution units dedicated to a particular function or set of functions, while other embodiments may include only one execution unit or multiple execution units that perform all functions. Scheduler unit 3056, physical register file unit 3058, and execution clusters 3060 are shown as possibly multiple because certain embodiments form separate pipelines for some data types / operations (scalar integer pipeline, scalar floating point / packed integer / packed floating point / vector integer / vector floating point pipeline, and / or memory access pipeline each with its own scheduler unit, physical register file unit, and / or execution cluster - in the case of a separate memory access pipeline, only the execution cluster of this pipeline is implemented in a particular embodiment with memory access unit 3064). It should also be understood that if separate pipelines are used, one or more of these pipelines may be out-of-order issue / execution and the rest in-order.

[0289] The set of memory access units 3064 is coupled to a memory unit 3070 that includes a data TLB unit 3072 coupled to a data cache unit 3074 that is coupled to a secondary (L2) cache unit 3076. In an exemplary embodiment, the memory access units 3064 may include a load unit, a store address unit, and a store data unit, each of which is coupled to the data TLB unit 3072 in the memory unit 3070. The instruction cache unit 3034 is further coupled to a secondary (L2) cache unit 3076 in the memory unit 3070. The L2 cache unit 3076 is coupled to one or more other levels of cache and ultimately to main memory.

[0290] As an example, an exemplary register renaming out-of-order issue / execution core architecture may implement pipeline 3000 as follows. 1) Instruction Fetch 3038 performs the fetch and length decode stages 3002 and 3004. 2) The decoding unit 3040 performs the decoding stage 3006. 3) The rename / allocator unit 3052 performs the allocation stage 3008 and the renaming stage 3010. 4) The scheduler unit 3056 executes the schedule stage 3012. 5) The physical register file unit(s) 3058 and memory unit 3070 execute the register read / memory read stage 3014, and the execution cluster 3060 executes the execution stage 3016; 6) The memory unit 3070 and physical register file unit(s) 3058 perform the writeback / memory write stage 3018. 7) Various units may be involved in the exception handling stage 3022. 8) The retirement unit 3054 and physical register file unit(s) 3058 execute the commit stage 3024.

[0291] Core 3090 may support one or more instruction sets (e.g., the x86 instruction set (with some extensions added in newer versions), the MIPS instruction set from MIPS Technologies, Inc. of Sunnyvale, Calif., the ARM instruction set from ARM Holdings, Inc. of Sunnyvale, Calif. (with optional additional extensions such as NEON)), including the instruction(s) described herein. In one embodiment, core 3090 includes logic to support packed data instruction set extensions (e.g., AVX1, AVX2), allowing operations used by many multimedia applications to be performed using packed data.

[0292] It will be appreciated that a core may support multithreading (a set of two or more parallel operations or threads) and may do so in a variety of ways, including time-shared multithreading, simultaneous multithreading (where one physical core provides a logical core for each thread on which the physical core performs simultaneous multithreading), or a combination thereof (e.g., time-shared fetch and decode, and then simultaneous multithreading, such as Intel Hyper-Threading Technology).

[0293] Although register renaming is described in the context of out-of-order execution, it should be understood that register renaming may be used in an in-order architecture. The illustrated processor embodiment may include separate instruction and data cache units 3034 / 3074 and a shared L2 cache unit 3076, and alternative embodiments may have one internal cache for both instructions and data, such as a first level (L1) internal cache, or a multi-level internal cache. In some embodiments, the system may include a combination of internal caches and external caches that are external to the core and / or processor. Alternatively, all of the caches may be external to the core and / or processor. Specific Exemplary In-Order Core Architecture

[0294] 31A-31B show block diagrams of a more specific exemplary in-order core architecture. The core may be one of several logic blocks (including other cores of the same and / or different types) in a chip. The logic block communicates with some fixed function logic, memory I / O interfaces, and other necessary I / O logic, depending on the application, through a high bandwidth interconnect network (e.g., a ring network).

[0295] FIG. 31A illustrates a block diagram of a single processor core, along with its connection to an on-die interconnect network 3102 and its local subset of a second-level (L2) cache 3104, according to embodiments of the present disclosure. In one embodiment, an instruction decode unit 3100 supports the x86 instruction set with a packed data instruction set extension. An L1 cache 3106 allows low-latency access to cache memory for the scalar and vector units. In one embodiment, (for design simplicity) the scalar unit 3108 and the vector unit 3110 use separate register sets (scalar registers 3112 and vector registers 3114, respectively) and data transferred between them is written to the first-level (L1) cache 3106 memory and then re-read, although alternative embodiments of the present disclosure may use different approaches (e.g., using a single register set or including a communication path that allows data transfer between the two register files without writing and re-reading).

[0296] The local subset of the L2 cache 3104 is part of a global L2 cache that is divided into separate local subsets, one per processor core. Each processor core has a direct access path to its own local subset of the L2 cache 3104. Data read by a processor core is stored in its L2 cache subset 3104 and can be accessed quickly in parallel with other processor cores accessing their own local L2 cache subsets. Data written by a processor core is stored in its own L2 cache subset 3104 and is flushed from other subsets when necessary. The ring network ensures coherency of shared data. The ring network is bidirectional to allow agents such as processor cores, L2 caches, and other logic blocks to communicate with each other within the chip. Each ring data path is 1012 bits wide per direction.

[0297] FIG. 31B is an expanded view of a portion of the processor core of FIG. 31A according to embodiments of the present disclosure. FIG. 31B includes a portion of the L1 data cache 3106A of the L1 cache 3104, as well as further details regarding the vector unit 3110 and vector registers 3114. In particular, the vector unit 3110 is a 16-wide vector processing unit (VPU) (see 16-wide ALU 3128) that executes one or more of integer, single precision float, and double precision float instructions. The VPU supports swizzling of register inputs by swizzle unit 3120, numeric conversion by numeric conversion units 3122A-B, and duplication on memory inputs by duplication unit 3124. A write mask register 3126 allows for predicating of the resulting vector writes.

[0298] 32 is a block diagram of a processor 3200 that may have more than one core, an integrated memory controller, and integrated graphics in accordance with embodiments of the present disclosure. The solid lined box in FIG. 32 illustrates a processor 3200 having a single core 3202A, a system agent 3210, and a set of one or more bus controller units 3216, while the optional addition of a dashed lined box illustrates an alternative processor 3200 having multiple cores 3202A-N, a set of one or more integrated memory controller units 3214 in the system agent unit 3210, and dedicated logic 3208.

[0299] Various implementations of the processor 3200 may thus include: 1) a CPU with special purpose logic 3208 that is integrated graphics and / or scientific (throughput) logic (which may include one or more cores), and one or more general purpose cores 3202A-N (e.g., general purpose in-order cores, general purpose out-of-order cores, a combination of the two); 2) a coprocessor with many special purpose cores 3202A-N primarily for graphics and / or scientific (throughput); and 3) a coprocessor with many general purpose in-order cores 3202A-N. The processor 3200 may thus be a general purpose processor, coprocessor, or special purpose processor, such as, for example, a network or communication processor, a compression engine, a graphics processor, a GPGPU (general purpose image processing unit), a high throughput multiple integrated core (MIC) coprocessor (including 30 or more cores), an embedded processor, etc. The processor may be implemented on one or more chips. The processor 3200 may be a part of and / or may be implemented on one or more substrates using any of a number of process technologies, such as, for example, BiCMOS, CMOS, or NMOS.

[0300] The memory hierarchy includes one or more levels of cache within the core, one or more or a set of shared cache units 3206, and an external memory (not shown) coupled to a set of integrated memory controller units 3214. The set of shared cache units 3206 may include one or more mid-level caches, such as a second level (L2), third level (L3), fourth level (L4), or other level cache, a last level cache (LLC), and / or combinations thereof. In one embodiment, a ring-based interconnect unit 3212 interconnects the integrated graphics logic 3208, the set of shared cache units 3206, and the system agent unit 3210 / integrated memory controller unit 3214, although alternative embodiments may use any number of well-known techniques for interconnecting such units. In one embodiment, coherency is maintained between the one or more cache units 3206 and the cores 3202A-N.

[0301] In some embodiments, one or more of the cores 3202A-N are capable of multithreading. The system agent 3210 includes those components that coordinate and operate the cores 3202A-N. The system agent unit 3210 may include, for example, a power control unit (PCU) and a display unit. The PCU can be or include the logic and configuration components necessary to coordinate the power state of the cores 3202A-N and the integrated graphics logic 3208. The display unit is for driving one or more externally connected displays.

[0302] The cores 3202A-N may be homogenous or heterogeneous with respect to architectural instruction sets, i.e., two or more of the cores 3202A-N may be capable of executing the same instruction set, while others may be capable of executing only a subset of that instruction set, or a different instruction set. Exemplary Computer Architecture A

[0303] 33-36 are block diagrams of exemplary computer architectures. Other system designs and configurations known in the art are also suitable, including laptops, desktops, handheld PCs, personal digital assistants, engineering workstations, servers, network devices, network hubs, switches, embedded processors, digital signal processors (DSPs), graphics devices, video game devices, set-top boxes, microcontrollers, mobile phones, portable media players, handheld devices, and a variety of other electronic devices. In general, a wide variety of systems or electronic devices capable of incorporating the processors and / or other execution logic disclosed herein are generally suitable.

[0304] Referring now to FIG. 33, a block diagram of a system 3300 according to one embodiment of the present disclosure is shown. The system 3300 may include one or more processors 3310, 3315 coupled to a controller hub 3320. In one embodiment, the controller hub 3320 includes a graphics memory controller hub (GMCH) 3390 and an input / output hub (IOH) 3350 (which may reside on separate chips). The GMCH 3390 includes a memory and graphics controller to which a memory 3340 and a coprocessor 3345 are coupled. The IOH 3350 couples an input / output (I / O) device 3360 to the GMCH 3390. Alternatively, one or both of the memory and graphics controller may be integrated within the processor (as described herein) and the memory 3340 and coprocessor 3345 may be directly coupled to the processor 3310 and the controller hub 3320 in a single chip with the IOH 3350. The memory 3340 may include, for example, matrix acceleration code 3340A that, when executed, stores code that causes a processor to perform any of the methods of this disclosure.

[0305] The optional nature of the additional processor 3315 is indicated by a dashed line in Figure 33. Each processor 3310, 3315 may include one or more of the processing cores described herein and may be some version of the processor 3200.

[0306] The memory 3340 may be, for example, dynamic random access memory (DRAM), phase change memory (PCM), or a combination of the two. In at least one embodiment, the controller hub 3320 communicates with the processors 3310, 3315 via a multi-drop bus such as a front side bus (FSB), a point-to-point interface such as a quick path interconnect (QPI), or a similar connection 3395.

[0307] In one embodiment, coprocessor 3345 is a special purpose processor, such as, for example, a high throughput MIC processor, a network or communication processor, a compression engine, a graphics processor, a GPGPU, an embedded processor, etc. In one embodiment, controller hub 3320 may include an integrated graphics accelerator.

[0308] There may be a variety of differences between physical resources 3310 and 3315 in terms of a wide range of value criteria including architectural characteristics, microarchitectural characteristics, thermal characteristics, power consumption characteristics, and the like.

[0309] In one embodiment, the processor 3310 executes instructions that control a general type of data processing operation. Coprocessor instructions may be embedded within the instructions. The processor 3310 recognizes these coprocessor instructions as being of a type that should be executed by an attached coprocessor 3345. The processor 3310 therefore issues these coprocessor instructions (or control signals representing the coprocessor instructions) on a coprocessor bus or other interconnect to the coprocessor 3345. The coprocessor 3345 accepts and executes the received coprocessor instructions.

[0310] Referring now to Figure 34, a block diagram of a first more specific exemplary system 3400 according to an embodiment of the present disclosure is shown. As shown in Figure 34, the multiprocessor system 3400 is a point-to-point interconnect system, and each processor 3470 and 3480, including a first processor 3470 and a second processor 3480 coupled via a point-to-point interconnect 3450, may be some version of the processor 3200. In one embodiment of the present disclosure, the processors 3470 and 3480 are the processors 3310 and 3315, respectively, and the coprocessor 3438 is the coprocessor 3345. In another embodiment, the processors 3470 and 3480 are the processors 3310 and the coprocessor 3345, respectively.

[0311] Processors 3470 and 3480 are shown as including integrated memory controller (IMC) units 3472 and 3482, respectively. Processor 3470 also includes point-to-point (PP) interfaces 3476 and 3478 as part of its bus controller unit, and similarly, second processor 3480 includes PP interfaces 3486 and 3488. Processors 3470, 3480 may exchange information over point-to-point (PP) interface 3450 using PP interface circuits 3478, 3488. As shown in FIG. 34, IMCs 3472 and 3482 couple the processors to respective memories, i.e., memory 3432 and memory 3434, which may be part of a main memory locally attached to each processor.

[0312] Processors 3470, 3480 may each exchange information with chipset 3490 using point-to-point interface circuits 3476, 3494, 3486, 3498 via respective PP interfaces 3452, 3454. Chipset 3490 may optionally exchange information with coprocessor 3438 via high performance interface 3439. In one embodiment, coprocessor 3438 is a special purpose processor such as, for example, a high throughput MIC processor, a network or communication processor, a compression engine, a graphics processor, a GPGPU, an embedded processor, etc.

[0313] A shared cache (not shown) may be either included in the processor or external to both processors, but connected to the processors via a P-P interconnect so that local cache information of either or both processors can be stored in the shared cache when the processors enter a low power mode.

[0314] Chipset 3490 may be coupled to a first bus 3416 via an interface 3496. In one embodiment, first bus 3416 may be a bus such as a Peripheral Component Interconnect (PCI) bus, or a PCI Express bus or other third generation I / O interconnect bus, although the scope of this disclosure is not limited to these buses.

[0315] As shown in FIG. 34, various I / O devices 3414 may be coupled to the first bus 3416 along with a bus bridge 3418 coupling the first bus 3416 to a second bus 3420. In one embodiment, one or more additional processors 3415 are coupled to the first bus 3416, such as a co-processor, a high throughput MIC processor, a GPGPU, an accelerator (e.g., a graphics accelerator or a digital signal processing (DSP) unit, etc.), a field programmable gate array, or other processor. In one embodiment, the second bus 3420 may be a low pin count (LPC) bus. In one embodiment, various devices may be coupled to the second bus 3420, including, for example, a keyboard and / or mouse 3422, a communication device 3427, and a storage unit 3428, such as a disk drive or other mass storage device that may contain instructions / code and data 3430. Additionally, audio I / O 3424 may be coupled to the second bus 3420. However, other architectures are possible. For example, instead of the point-to-point architecture of FIG. 34, the system may implement a multi-drop bus or other such architecture.

[0316]

[00106] Referring now to Figure 35, a block diagram of a second, more specific, exemplary system 3500 according to an embodiment of the present disclosure is shown. Like elements in Figures 34 and 35 have like reference numbers, and certain aspects of Figure 34 have been omitted from Figure 35 to avoid obscuring other aspects of Figure 35.

[0317] Figure 35 shows that the processors 3470, 3480 may include integrated memory and I / O control logic ("CL") 3472, 3482, respectively. Thus, the CL 3472, 3482 includes an integrated memory controller unit and includes I / O control logic. Figure 35 shows that not only the memory 3432, 3434 is coupled to the control logic 3472, 3482, but also a number of I / O devices 3514 are coupled to the CL 3472, 3482. Legacy I / O devices 3515 are coupled to the chipset 3490.

[0318] Referring now to FIG. 36, a block diagram of an SoC 3600 according to an embodiment of the present disclosure is shown. Elements similar to those in FIG. 32 have similar reference numbers. Also, dashed boxes are optional features in a more advanced SoC. In FIG. 36, an interconnect unit 3602 is coupled to an application processor 3610 including a set of one or more cores 3202A-N and a shared cache unit 3206, a system agent unit 3210, a bus controller unit 3216, an integrated memory controller unit 3214, a set or one or more coprocessors 3620 that may include integrated graphics logic, image processors, audio processors, and video processors, a static random access memory (SRAM) unit 3630, a direct memory access (DMA) unit 3632, and a display unit 3640 for coupling to one or more external displays. In one embodiment, the coprocessor 3620 includes a special purpose processor, such as, for example, a network or communication processor, a compression engine, a GPGPU, a high throughput MIC processor, an embedded processor, etc.

[0319] The embodiments (e.g., mechanisms) disclosed herein may be implemented in hardware, software, firmware, or a combination of such implementation approaches. Embodiments of the present disclosure may be implemented as a computer program or program code running on a programmable system that includes at least one processor, a storage system (including volatile and non-volatile memory and / or storage elements), at least one input device, and at least one output device.

[0320] Program code, such as code 3430 shown in Figure 34, may be applied to input instructions to perform functions described herein and to generate output information. The output information may be applied to one or more output devices, in known fashion. For purposes of this application, a processing system includes any system having a processor, such as, for example, a digital signal processor (DSP), a microcontroller, an application specific integrated circuit (ASIC), or a microprocessor.

[0321] The program code may be implemented in a high level procedural or object oriented programming language to communicate with a processing system. The program code may also be implemented in assembly or machine language, if desired. Indeed, the mechanisms described herein are not limited in scope to any particular programming language. In any case, the language may be a compiled or interpreted language.

[0322] One or more aspects of at least one embodiment may be implemented by representative instructions stored on a machine-readable medium that represent various logic within a processor, which, when read by a machine, causes the machine to construct logic that causes the techniques described herein. Such representations, known as "IP cores," may be stored on tangible machine-readable media and supplied to various customers or manufacturing facilities for loading into manufacturing machines that actually create the logic or processor.

[0323] Such machine-readable recording media may include, without limitation, non-transitory, tangible articles manufactured or formed by a machine or device, including, for example, hard disks, floppy disks, optical disks, compact disk read-only memories (CD-ROMs), compact disk re-writeable (CD-RWs), and magneto-optical disks, read-only memories (ROMs), random access memories (RAMs), any other type of disk including semiconductor devices such as dynamic random access memories (DRAMs), static random access memories (SRAMs), erasable programmable read-only memories (EPROMs), flash memories, electrically erasable programmable read-only memories (EEPROMs), phase change memories (PCMs), magnetic or optical cards, or other types of media suitable for storing electronic instructions.

[0324] Accordingly, embodiments of the present disclosure also include a non-transitory, tangible, machine-readable medium that includes instructions or includes design data, such as hardware description language (HDL), that defines the functionality of the structures, circuits, devices, processors and / or systems described herein. Such embodiments may also be referred to as a program product. Emulation (including binary conversion, code morphing, etc.)

[0325] In some cases, an instruction converter may be used to convert instructions from a source instruction set to a target instruction set. For example, the instruction converter may translate, morph, emulate, or otherwise convert (e.g., using static binary translation, dynamic binary translation including dynamic compilation) the instructions into one or more other instructions to be processed by the core. The instruction converter may be implemented in software, hardware, firmware, or a combination thereof. The instruction converter may be on-processor, off-processor, or partly on-processor and partly off-processor.

[0326] Figure 37 is a block diagram contrasting the use of a software instruction converter to convert binary instructions in a source instruction set to binary instructions in a target instruction set according to embodiments of the present disclosure. In the illustrated embodiment, the instruction converter is a software instruction converter, but alternatively, the instruction converter may be implemented in software, firmware, hardware, or various combinations thereof. Figure 37 shows that a program in a high-level language 3702 can be compiled using an x86 compiler 3704 to generate x86 binary code 3706 that can be executed natively by a processor 3716 having at least one x86 instruction set core. Processor with at least one x86 instruction set core 3716 represents any processor capable of performing substantially the same functions as an Intel processor with at least one x86 instruction set core by compatibly executing or otherwise processing (1) a majority of the instruction set of the Intel x86 instruction set core, or (2) object code versions of applications or other software targeted to run on an Intel processor with at least one x86 instruction set core, to achieve substantially the same results as an Intel processor with at least one x86 instruction set core. x86 compiler 3704 represents a compiler operable to generate x86 binary code 3706 (e.g., object code) that may be executed on processor with at least one x86 instruction set core 3716, with or without additional linking operations. Similarly, FIG. 37 shows that a program in high-level language 3702 can be compiled using an alternative instruction set compiler 3708 to generate alternative instruction set binary code 3710 that can be natively executed by a processor 3714 that does not have at least one x86 instruction set core (e.g., a processor having a core that executes the MIPS instruction set from MIPS Technologies, Inc. of Sunnyvale, Calif. and / or the ARM instruction set from ARM Holdings, Inc. of Sunnyvale, Calif.).The instruction converter 3712 is used to convert the x86 binary code 3706 into code that can be executed natively by a processor 3714 that does not have an x86 instruction set core. This converted code is unlikely to be the same as the alternative instruction set binary code 3710 because an instruction converter capable of this conversion would be difficult to create. However, the converted code implements common operations and is composed of instructions from the alternative instruction set. Thus, the instruction converter 3712 represents software, firmware, hardware, or a combination thereof that allows a processor or other electronic device that does not have an x86 instruction set processor or core to execute the x86 binary code 3706, through emulation, simulation, or any other process.

[0327] Other possible items [Item 1] a matrix operation accelerator circuit having a two-dimensional grid of fused multiply-add circuits; a first plurality of registers representing at least one first input two-dimensional matrix coupled to the matrix operation accelerator circuit; a second plurality of registers representing at least one second input two-dimensional matrix coupled to the matrix operation accelerator circuit; a decoder of a core coupled to the matrix operation accelerator circuit, the decoder decoding a single instruction into a decoded single instruction and having a field identifying a storage resulting from the single instruction; execution circuitry of said core for executing said single decoded instruction; Equipped with and an execution circuit of the core causes the matrix operation accelerator circuit to transition from a first mode to a second mode in which each output of each of a first suitable subset of fused multiply-add circuits of the two-dimensional grid is transmitted to a respective input of each of a second suitable subset of fused multiply-add circuits of the two-dimensional grid downstream to form output values ​​from the at least one first input two-dimensional matrix and the at least one second input two-dimensional matrix and store the output values ​​in the resulting storage. and switching to a second mode in which each output for each of the second suitable subset of fused product-accumulator circuits of the two-dimensional grid forms a second output value from a second subset of the at least one first input two-dimensional matrix and the at least one second input two-dimensional matrix and stores the first output value in the resulting storage. [Item 2] 2. The apparatus of claim 1, wherein the single instruction has a second field indicating that the matrix operation accelerator circuit executes in the first mode if the second field is a first value, and executes in the second mode if the second field is a second value. [Item 3] 3. The apparatus of claim 2, wherein the second field is an immediate value of the single instruction. [Item 4] 2. The apparatus of claim 1, wherein the resulting storage is a third plurality of registers representing at least one output two-dimensional matrix formed by executing the decoded single instruction. [Item 5] executing the single decoded instruction, in said first mode, adding values ​​from said third plurality of registers representing at least one third input two-dimensional matrix initially stored in said third plurality of registers to said output value to form an updated output value, and storing said updated output value in said resulting storage in place of said output value; 5. The apparatus of claim 4, wherein in the second mode, the apparatus adds values ​​from the at least one third input two-dimensional matrix initially stored in the third plurality of registers to the first output value and the second output value to form updated first output value and updated second output value, and stores the updated first output value and the updated second output value in the resulting storage in place of the first output value and the second output value. [Item 6] executing the single decoded instruction, in said first mode, adding to said output value a value from at least one third input two-dimensional matrix initially stored in a third plurality of registers to form an updated output value, and storing said updated output value in said resulting storage in place of said output value; 2. The apparatus of claim 1, wherein in the second mode, the apparatus adds values ​​from the at least one third input two-dimensional matrix initially stored in the third plurality of registers to the first output value and the second output value to form updated first output value and updated second output value, and stores the updated first output value and the updated second output value in the resulting storage in place of the first output value and the second output value. [Item 7] Item 1 . The apparatus of item 1 , wherein the resulting storage is a third plurality of registers representing a plurality of output two-dimensional matrices formed by executing the single decoded instruction. [Item 8] the first suitable subset of fused multiply-add circuits is one of the rows or columns of the two-dimensional grid of fused multiply-add circuits; 2. The apparatus of claim 1, wherein the second suitable subset of fused sum-of-products circuits is the other one of the rows or columns in the two-dimensional grid of fused sum-of-products circuits. [Item 9] decoding a single instruction at a decoder of a processor core into a decoded single instruction, the processor core being coupled to a matrix operation accelerator circuit having a two-dimensional grid of fused multiply-add circuits, the matrix operation accelerator circuit being coupled to a first plurality of registers representing at least one first input two-dimensional matrix and a second plurality of registers representing at least one second input two-dimensional matrix, the single instruction having a field identifying a resulting storage; executing said decoded single instruction in execution circuitry of said processor core; Equipped with The executing step causes the matrix operation accelerator circuit to transition from a first mode to a second mode in which each output of each of the first suitable subset of fused product-accumulator circuits of the two-dimensional grid is transmitted to a respective input of each of a second suitable subset of fused product-accumulator circuits of the two-dimensional grid downstream to form output values ​​from the at least one first input two-dimensional matrix and the at least one second input two-dimensional matrix and store the output values ​​in the resulting storage. and switching to a second mode in which each output for each of the second suitable subset of fused product-accumulator circuits of the two-dimensional grid forms a second output value from a second subset of the at least one first input two-dimensional matrix and the at least one second input two-dimensional matrix and stores the first output value in the resulting storage. [Item 10] 10. The method of claim 9, wherein the single instruction has a second field indicating that the matrix operation accelerator circuit executes in the first mode if the second field is a first value, and executes in the second mode if the second field is a second value. [Item 11] 11. The method of claim 10, wherein the second field is an immediate value of the single instruction. [Item 12] 10. The method of claim 9, wherein the resulting storage is a third plurality of registers representing at least one output two-dimensional matrix formed by executing the decoded single instruction. [Item 13] executing the single decoded instruction, in said first mode, adding values ​​from said third plurality of registers representing at least one third input two-dimensional matrix initially stored in said third plurality of registers to said output value to form an updated output value, and storing said updated output value in said resulting storage in place of said output value; 13. The method of claim 12, wherein in the second mode, values ​​from the at least one third input two-dimensional matrix initially stored in the third plurality of registers are added to the first output value and the second output value to form updated first output value and updated second output value, and the updated first output value and the updated second output value are stored in the resulting storage in place of the first output value and the second output value. [Item 14] executing the single decoded instruction, in said first mode, adding to said output value a value from at least one third input two-dimensional matrix initially stored in a third plurality of registers to form an updated output value, and storing said updated output value in said resulting storage in place of said output value; 10. The method of claim 9, wherein in the second mode, values ​​from the at least one third input two-dimensional matrix initially stored in the third plurality of registers are added to the first output value and the second output value to form updated first output value and updated second output value, and the updated first output value and the updated second output value are stored in the resulting storage in place of the first output value and the second output value. [Item 15] 10. The method of claim 9, wherein the resulting storage is a third plurality of registers representing a plurality of output two-dimensional matrices formed by executing the single decoded instruction. [Item 16] the first suitable subset of fused multiply-add circuits is one of the rows or columns of the two-dimensional grid of fused multiply-add circuits; 10. The method of claim 9, wherein the second suitable subset of fused multiply-add circuits is the other one of the rows or columns in the two-dimensional grid of fused multiply-add circuits. [Item 17] A non-transitory machine-readable medium storing code that, when executed by a machine, causes the machine to perform a method, the method comprising: decoding a single instruction at a decoder of a processor core into a decoded single instruction, the processor core being coupled to a matrix operation accelerator circuit having a two-dimensional grid of fused multiply-add circuits, the matrix operation accelerator circuit being coupled to a first plurality of registers representing at least one first input two-dimensional matrix and a second plurality of registers representing at least one second input two-dimensional matrix, the single instruction having a field identifying a resulting storage; executing said decoded single instruction in execution circuitry of said processor core; Equipped with The executing step causes the matrix operation accelerator circuit to switch from a first mode to a second mode in which each output of a first suitable subset of fused multiply-add circuits of the two-dimensional grid is transmitted to a respective input of a second suitable subset of fused multiply-add circuits of the two-dimensional grid downstream to form output values ​​from the at least one first input two-dimensional matrix and the at least one second input two-dimensional matrix, and store the output values ​​in the resulting storage, such that each output of each of the first suitable subset of fused multiply-add circuits of the two-dimensional grid downstream to form output values ​​from the at least one first input two-dimensional matrix and the at least one second input two-dimensional matrix, forming first output values ​​from at least one first input two-dimensional matrix and a first subset of the at least one second input two-dimensional matrix and storing the first output values ​​in the resulting storage, and switching to a second mode in which each output for each of the second suitable subset of the two-dimensional grid fused sum-of-products circuits forms second output values ​​from a second subset of the at least one first input two-dimensional matrix and the at least one second input two-dimensional matrix and storing the second output values ​​in the resulting storage. [Item 18] Item 18. The non-transitory machine-readable medium of item 17, wherein the single instruction has a second field indicating that the matrix operation accelerator circuit executes in the first mode if the second field is a first value, and executes in the second mode if the second field is a second value. [Item 19] 20. The non-transitory machine-readable medium of claim 18, wherein the second field is an immediate value of the single instruction. [Item 20] 20. The non-transitory machine-readable medium of claim 17, wherein the resulting storage is a third plurality of registers representing at least one output two-dimensional matrix formed by executing the decoded single instruction. [Item 21] executing the single decoded instruction, in said first mode, adding values ​​from said third plurality of registers representing at least one third input two-dimensional matrix initially stored in said third plurality of registers to said output value to form an updated output value, and storing said updated output value in said resulting storage in place of said output value; 21. The non-transitory machine-readable medium of claim 20, wherein in the second mode, values ​​from the at least one third input two-dimensional matrix initially stored in the third plurality of registers are added to the first output value and the second output value to form updated first output value and updated second output value, and the updated first output value and the updated second output value are stored in the resulting storage in place of the first output value and the second output value. [Item 22] executing the single decoded instruction, in said first mode, adding to said output value a value from at least one third input two-dimensional matrix initially stored in a third plurality of registers to form an updated output value, and storing said updated output value in said resulting storage in place of said output value; 20. The non-transitory machine-readable medium of claim 17, wherein in the second mode, values ​​from the at least one third input two-dimensional matrix initially stored in the third plurality of registers are added to the first output and the second output to form updated first output values ​​and updated second output values, and the updated first output values ​​and the updated second output values ​​are stored in the resulting storage in place of the first output values ​​and the second output values. [Item 23] 20. The non-transitory machine-readable medium of claim 17, wherein the resulting storage is a third plurality of registers representing a plurality of output two-dimensional matrices formed by executing the single decoded instruction. [Item 24] the first suitable subset of fused multiply-add circuits is one of the rows or columns of the two-dimensional grid of fused multiply-add circuits; Item 18. The non-transitory machine-readable medium of item 17, wherein the second suitable subset of the fused sum-of-products circuits is the other one of the rows or columns in the two-dimensional grid of the fused sum-of-products circuits.

Claims

1. a matrix operation accelerator circuit having a two-dimensional grid of fused multiply-add circuits; a first plurality of registers representing at least one first input two-dimensional matrix coupled to the matrix operation accelerator circuit; a second plurality of registers representing at least one second input two-dimensional matrix coupled to the matrix operation accelerator circuit; a decoder of a core coupled to the matrix operation accelerator circuit, the decoder decoding a single instruction into a decoded single instruction and having a field identifying a storage resulting from the single instruction; execution circuitry of said core for executing said single decoded instruction; Equipped with and an execution circuitry of the core causes the matrix operation accelerator circuitry to transition from a first mode to a second mode in which each output of each of a first suitable subset of fused multiply-add circuits of the two-dimensional grid is transmitted to a respective input of each of a second suitable subset of fused multiply-add circuits of the two-dimensional grid downstream to form output values ​​from the at least one first input two-dimensional matrix and the at least one second input two-dimensional matrix and store the output values ​​in the resulting storage. and switching to a second mode in which each output for each of the second suitable subset of fused product-sum circuits of the two-dimensional grid forms second output values ​​from a second subset of the at least one first input two-dimensional matrix and the at least one second input two-dimensional matrix and stores the first output values ​​in the resulting storage.

2. 2. The apparatus of claim 1, wherein the single instruction has a second field indicating that the matrix operations accelerator circuit is to execute in the first mode if the second field is a first value and is to execute in the second mode if the second field is a second value.

3. 3. The apparatus of claim 2, wherein the second field is an immediate value of the single instruction.

4. 4. The apparatus of claim 1, wherein the resultant storage is a third plurality of registers representing at least one output two-dimensional matrix formed by executing the decoded single instruction.

5. executing the single decoded instruction, in the first mode, adding values ​​from the third plurality of registers representing at least one third input two-dimensional matrix initially stored in the third plurality of registers to the output value to form an updated output value, and storing the updated output value in the resulting storage in place of the output value; 5. The apparatus of claim 4, wherein in the second mode, adding values ​​from the at least one third input two-dimensional matrix initially stored in the third plurality of registers to the first output value and the second output value to form updated first output value and updated second output value, and storing the updated first output value and the updated second output value in the resulting storage in place of the first output value and the second output value.

6. executing the single decoded instruction, in the first mode, adding to the output value a value from at least one third input two-dimensional matrix initially stored in a third plurality of registers to form an updated output value, and storing the updated output value in the resulting storage in place of the output value; 2. The apparatus of claim 1, wherein in the second mode, adding values ​​from the at least one third input two-dimensional matrix initially stored in the third plurality of registers to the first output value and the second output value to form updated first output value and updated second output value, and storing the updated first output value and the updated second output value in the resulting storage in place of the first output value and the second output value.

7. 7. The apparatus of claim 1, wherein the resultant storage is a third plurality of registers representing a plurality of output two-dimensional matrices formed by executing the single decoded instruction.

8. the first suitable subset of fused sum-of-products circuits is one of a row or a column in the two-dimensional grid of fused sum-of-products circuits; 8. Apparatus according to claim 1, wherein the second suitable subset of fused sum-of-products circuits is the one of the other of the rows or the columns in the two-dimensional grid of fused sum-of-products circuits.

9. decoding a single instruction at a decoder of a processor core into a decoded single instruction, the processor core being coupled to a matrix operation accelerator circuit having a two-dimensional grid of fused multiply-add circuits, the matrix operation accelerator circuit being coupled to a first plurality of registers representing at least one first input two-dimensional matrix and a second plurality of registers representing at least one second input two-dimensional matrix, the single instruction having a field identifying a resulting storage; executing said decoded single instruction in execution circuitry of said processor core; Equipped with The executing step includes switching the matrix operations accelerator circuit from a first mode to a second mode in which each output for each of a first suitable subset of fused product-add circuits of the two-dimensional grid is transmitted to a respective input for each of a second suitable subset of fused product-add circuits of the two-dimensional grid downstream, forming output values ​​from the at least one first input two-dimensional matrix and the at least one second input two-dimensional matrix, and storing the output values ​​in the resulting storage, and switching to a second mode in which each output for each of the second suitable subset of the two-dimensional grid fused sum-of-products circuits forms a second output value from a second subset of the at least one first-input two-dimensional matrix and the at least one second-input two-dimensional matrix and stores the first output value in the resulting storage.

10. 10. The method of claim 9, wherein the single instruction has a second field indicating that the matrix operations accelerator circuit is to execute in the first mode if the second field is a first value and is to execute in the second mode if the second field is a second value.

11. 11. The method of claim 10, wherein the second field is an immediate value of the single instruction.

12. 12. A method according to any one of claims 9 to 11, wherein the resulting storage is a third plurality of registers representing at least one output two-dimensional matrix formed by executing the decoded single instruction.

13. executing the single decoded instruction, in the first mode, adding values ​​from the third plurality of registers representing at least one third input two-dimensional matrix initially stored in the third plurality of registers to the output value to form an updated output value, and storing the updated output value in the resulting storage in place of the output value; 13. The method of claim 12, wherein in the second mode, adding values ​​from the at least one third input two-dimensional matrix initially stored in the third plurality of registers to the first output value and the second output value to form updated first output value and updated second output value, and storing the updated first output value and the updated second output value in the resulting storage in place of the first output value and the second output value.

14. executing the single decoded instruction, in the first mode, adding to the output value a value from at least one third input two-dimensional matrix initially stored in a third plurality of registers to form an updated output value, and storing the updated output value in the resulting storage in place of the output value; 10. The method of claim 9, wherein in the second mode, adding values ​​from the at least one third input two-dimensional matrix initially stored in the third plurality of registers to the first output value and the second output value to form updated first output value and updated second output value, and storing the updated first output value and the updated second output value in the resulting storage in place of the first output value and the second output value.

15. 15. A method according to any one of claims 9 to 14, wherein the resulting storage is a third plurality of registers representing a plurality of output two-dimensional matrices formed by executing the single decoded instruction.

16. the first suitable subset of fused sum-of-products circuits is one of a row or a column in the two-dimensional grid of fused sum-of-products circuits; 16. A method according to claim 9, wherein the second suitable subset of fused sum-of-products circuits is the one of the other of the rows or the columns in the two-dimensional grid of fused sum-of-products circuits.

17. A program comprising instructions, which when executed by a machine, cause the machine to perform a method, the method comprising: decoding a single instruction at a decoder of a processor core into a decoded single instruction, the processor core being coupled to a matrix operation accelerator circuit having a two-dimensional grid of fused multiply-add circuits, the matrix operation accelerator circuit being coupled to a first plurality of registers representing at least one first input two-dimensional matrix and a second plurality of registers representing at least one second input two-dimensional matrix, the single instruction having a field identifying a resulting storage; executing said decoded single instruction in execution circuitry of said processor core; Equipped with The executing step includes switching the matrix operations accelerator circuit from a first mode in which each output for each of a first suitable subset of the two-dimensional grid of fused product-add circuits is transmitted to a respective input for each of a second suitable subset of the two-dimensional grid of fused product-add circuits downstream to form output values ​​from the at least one first input two-dimensional matrix and the at least one second input two-dimensional matrix, and store the output values ​​in the resulting storage, to a second mode in which each output for each of the first suitable subset of the two-dimensional grid of fused product-add circuits is transmitted to a respective input for each of a second suitable subset of the two-dimensional grid of fused product-add circuits downstream to form output values ​​from the at least one first input two-dimensional matrix and the at least one second input two-dimensional matrix, forming first output values ​​from a first subset of the at least one first input two-dimensional matrix and the at least one second input two-dimensional matrix and storing the first output values ​​in the resulting storage, and switching to a second mode in which each output for each of the second suitable subset of the two-dimensional grid fused sum-of-products circuits forms second output values ​​from a second subset of the at least one first input two-dimensional matrix and the at least one second input two-dimensional matrix and stores the second output values ​​in the resulting storage.

18. 20. The program of claim 17, wherein the single instruction has a second field indicating that the matrix operations accelerator circuit executes in the first mode if the second field is a first value and executes in the second mode if the second field is a second value.

19. 20. The program of claim 18, wherein the second field is an immediate value of the single instruction.

20. 20. The program of claim 17, wherein the resulting storage is a third plurality of registers representing at least one output two-dimensional matrix formed by executing the decoded single instruction.

21. executing the single decoded instruction, in the first mode, adding values ​​from the third plurality of registers representing at least one third input two-dimensional matrix initially stored in the third plurality of registers to the output value to form an updated output value, and storing the updated output value in the resulting storage in place of the output value; 21. The program of claim 20, wherein in the second mode, adding values ​​from the at least one third input two-dimensional matrix initially stored in the third plurality of registers to the first output value and the second output value to form updated first output value and updated second output value, and storing the updated first output value and the updated second output value in the resulting storage in place of the first output value and the second output value.

22. executing the single decoded instruction, in the first mode, adding to the output value a value from at least one third input two-dimensional matrix initially stored in a third plurality of registers to form an updated output value, and storing the updated output value in the resulting storage in place of the output value; 18. The program of claim 17, wherein in the second mode, adding values ​​from the at least one third input two-dimensional matrix initially stored in the third plurality of registers to the first output value and the second output value to form updated first output value and updated second output value, and storing the updated first output value and the updated second output value in the resulting storage in place of the first output value and the second output value.

23. 23. The program of claim 17, wherein the resulting storage is a third plurality of registers representing a plurality of output two-dimensional matrices formed by executing the single decoded instruction.

24. the first suitable subset of fused sum-of-products circuits is one of a row or a column in the two-dimensional grid of fused sum-of-products circuits; 24. The program of claim 17, wherein the second suitable subset of fused sum-of-products circuits is the one of the other of the rows or the columns in the two-dimensional grid of fused sum-of-products circuits.

25. A computer readable medium storing a program according to any one of claims 17 to 24.

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