Display device

Abstract

To provide a display device with higher moisture permeation preventing performance, in which a component is disposed inside a display area.SOLUTION: A display device according to the present invention includes a first penetration hole 10H, an array of a plurality of pixels disposed in a display area surrounding the first penetration hole and separated from each other with the first penetration hole held therebetween, a first layer 240 disposed in an intermediate area between the first penetration hole and the display area and including a first hole or a recess, and a second layer 250 existing on the first layer and including a second hole overlapping with the first hole or the recess. The second layer includes a pair of chips further extending from an inner side surface of the first layer that defines the first hole or the recess to a center of the second hole. Each of the pixels includes a light-emitting diode including a pixel electrode 221, a counter electrode 223, and an intermediate layer 222 between the pixel electrode and the counter electrode. At least one organic layer in the intermediate layer is blocked using the pair of chips as a center.SELECTED DRAWING: Figure 8

Description

[Technical field]

[0001] The present invention relates to a display device, and more particularly to a display device including a transmissive region. [Background technology]

[0002] In recent years, display devices have come to be used in a variety of applications, and the thickness and weight of the display devices have become thinner and lighter, and the range of their use has become wider.

[0003] As the area occupied by the display area of ​​a display device increases, various functions are being added to or linked with the display device. As a method for adding various functions while increasing the area, research is ongoing into display devices having areas inside the display area for adding various functions other than an image display. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Korean Patent Publication No. 10-2018-0026599 Summary of the Invention [Problem to be solved by the invention]

[0005] The present invention has been made in consideration of the above-mentioned conventional technology, and an object of the present invention is to provide a display device having a transmissive area with improved moisture prevention performance in which components are arranged inside the display area. [Means for solving the problem]

[0006] A display device according to one embodiment of the present invention, which has been made to achieve the above-mentioned object, comprises a first through hole, an array of a plurality of pixels arranged in a display region surrounding the first through hole and including pixels each spaced apart by the first through hole, a first layer arranged in an intermediate region between the first through hole and the display region and including a first hole or a recess, and a second layer located on the first layer and including a second hole overlapping the first hole or the recess, wherein the second layer includes a pair of chips extending further toward the center of the second hole than the inner surface of the first layer defining the first hole or the recess, and each of the plurality of pixels includes a light-emitting diode including a pixel electrode, a counter electrode, and an intermediate layer between the pixel electrode and the counter electrode, and at least one organic layer of the intermediate layer is interrupted at the center of the pair of chips.

[0007] The at least one organic layer may include one or more layers selected from a hole transport layer, a hole injection layer, an electron injection layer, and an electron transport layer. The opposing electrodes may be interrupted at the center of the pair of tips. The first layer may include an organic insulator and the second layer may include a metal. The display device may further include a substrate on which the array of pixels is disposed, and at least one inorganic insulating layer between the substrate and the pixel electrodes. The first layer may be disposed on the at least one inorganic insulating layer, and the second layer may pass through the first layer and directly contact a top surface of the at least one inorganic insulating layer. The display device may further include at least one organic insulating layer between the at least one inorganic insulating layer and the pixel electrode, and the first layer may include the same material as the at least one organic insulating layer. A portion of the substrate may be bent about a bending axis extending along a bending region, and the at least one inorganic insulating layer may include an opening located in the bending region. The display device may further include an organic insulating layer located in the opening of the at least one inorganic insulating layer, and the first layer may include the same material as the organic insulating layer. The display device may further include an inorganic passivation layer on the second layer. The inorganic passivation layer may continuously cover the side and bottom surfaces of the second layer and the inner surface of the first layer.

[0008] In order to achieve the above-mentioned object, a display device according to another aspect of the present invention includes a substrate, a display layer disposed on the substrate and including a plurality of pixels, a thin-film sealing layer disposed on the display layer and including at least one inorganic sealing layer and at least one organic sealing layer, a first through-hole penetrating the substrate, the display layer, and the thin-film sealing layer and positioned between two adjacent pixels among the plurality of pixels, and a groove disposed to surround the first through-hole and defined in the first layer and a second layer on the first layer, the groove including a first hole or recess in the first layer and a second hole formed in the second layer, the second layer including a pair of tips extending further toward the center of the second hole than the inner surface of the first layer defining the first hole or the recess, and at least one organic layer of the display layer is interrupted by the groove.

[0009] Each of the plurality of pixels may include a light-emitting diode including a pixel electrode, a counter electrode, and a light-emitting layer between the pixel electrode and the counter electrode, and the at least one organic layer may be located between the pixel electrode and the counter electrode. The at least one organic layer may include one or more layers selected from a hole transport layer, a hole injection layer, an electron injection layer, and an electron transport layer. The display layer may include at least one inorganic insulating layer between the substrate and the pixel electrodes, and the first layer may be located on the at least one inorganic insulating layer. The first layer may include an organic insulator. The second layer may directly contact the top surface of the at least one inorganic insulating layer through the first layer. The second layer may comprise a metal or an inorganic insulator. The display device may further include an inorganic passivation layer on the second layer. The inorganic passivation layer may continuously cover the side and bottom surfaces of the second layer and the inner surface of the first layer. A portion of the substrate may be bent about a bending axis extending along a bending region, and the at least one inorganic insulating layer may include an opening located in the bending region. The display device may further include an organic insulating layer located in the opening of the at least one inorganic insulating layer, and the first layer may include the same material as the organic insulating layer. The display device may further include a second groove surrounding the first through hole, and may further include a partition between the groove and the second groove. The partition wall may include a plurality of stacked partition wall layers, and a spacer layer including a metal may be interposed between adjacent partition wall layers among the plurality of partition wall layers. The spacing layer includes a first layer and a second layer below the first layer, an edge of the first layer protruding further outward than an edge of the second layer, and the at least one organic layer can be interrupted by an overhanging structure formed by an edge of the first layer and an edge of the second layer.

[0010] Other aspects, features, and advantages in addition to those described above will be apparent from the drawings, the claims, and the detailed description of the invention. Effect of the Invention

[0011] According to the display device of the present invention, it is possible to prevent the light-emitting diode from being damaged by moisture flowing in through the through hole or opening, and by utilizing the layers contained in the display layer, it is possible to simplify the process and reduce costs. [Brief description of the drawings]

[0012] [Figure 1] 1 is a perspective view illustrating a display device according to an embodiment of the present invention; [Diagram 2] 1 is a cross-sectional view illustrating a display device according to an embodiment of the present invention; [Diagram 3]1 is a cross-sectional view illustrating an electronic device including a display device according to an embodiment of the present invention. [Figure 4] 1 is a plan view illustrating a display panel according to an embodiment of the present invention; [Diagram 5] 1 is a perspective view illustrating a substrate of a display panel according to an embodiment of the present invention; [Figure 6] 2 is an equivalent circuit diagram illustrating a pixel of a display panel. FIG. [Figure 7] 1 is a plan view showing a portion of a display panel according to an embodiment of the present invention; [Figure 8] 1 is a cross-sectional view of a display device according to an embodiment of the present invention; [Figure 9] FIG. 2 is a cross-sectional view showing a groove structure according to an embodiment of the present invention. [Figure 10] FIG. 2 is a cross-sectional view showing a groove structure according to an embodiment of the present invention. [Figure 11] 1 is a cross-sectional view showing a display panel according to an embodiment of the present invention. [Figure 12] 1 is a cross-sectional view showing a portion of a display device according to an embodiment of the present invention. [Figure 13] FIG. 2 is a cross-sectional view showing a groove structure according to an embodiment of the present invention. [Figure 14] FIG. 2 is a cross-sectional view showing a groove structure according to an embodiment of the present invention. [Figure 15] FIG. 2 is a cross-sectional view showing a groove structure according to an embodiment of the present invention. [Figure 16] 13 is an enlarged cross-sectional view of a portion of the partition wall of FIG. 12. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0013] The present invention can be modified in various ways and can have various embodiments, but specific embodiments are illustrated in the drawings and will be described in detail in the detailed description. The effects and features of the present invention, as well as methods for achieving them, will become clear by referring to the embodiments described in detail below with the drawings. However, the present invention is not limited to the embodiments disclosed below, and can be embodied in various forms.

[0014] Hereinafter, specific examples of the embodiments of the present invention will be described in detail with reference to the drawings. In the description with reference to the drawings, the same or corresponding components are given the same reference numerals, and duplicated description thereof will be omitted.

[0015] In the following embodiments, the terms "first", "second" and the like are not used in a limiting sense but are used for the purpose of distinguishing one component from another component.

[0016] In the following embodiments, the singular expression includes the plural expression unless otherwise clearly indicated in the context.

[0017] In the following embodiments, terms such as "comprise" or "have" mean the presence of features or components described in the specification, and do not preclude the possibility that one or more other features or components may be added.

[0018] In the following embodiments, when a part such as a film, region, or component is said to be on another part, this includes not only when it is directly on top of the other part, but also when there is another film, region, component, etc. in between.

[0019] In the drawings, the size of components is exaggerated or reduced for convenience of explanation. For example, the size and thickness of each component shown in the drawings are arbitrarily depicted for convenience of explanation, and the present invention is not necessarily limited to those shown in the drawings.

[0020] It is understood that certain steps may be performed out of the order described when different embodiments may be implemented. For example, two steps described in succession may be performed substantially simultaneously or in the reverse order of those described.

[0021] In the following embodiments, when a membrane, region, component, etc. is said to be connected, it includes not only the case where the membrane, region, component, etc. are directly connected, but also the case where the membrane, region, component, etc. are indirectly connected with another membrane, region, component, etc. being interposed between them. For example, in this specification, when a membrane, region, component, etc. is electrically connected, it includes not only the case where the membrane, region, component, etc. are directly electrically connected, but also the case where the membrane, region, component, etc. are indirectly electrically connected with another membrane, region, component, etc. being interposed between them.

[0022] FIG. 1 is a perspective view illustrating a display device according to an embodiment of the present invention.

[0023] 1, a display device 1 includes a display area DA and an outer area PA surrounding the display area DA. A transmissive area TA and an intermediate area MA surrounding the transmissive area TA are disposed inside the display area DA.

[0024] A plurality of pixels, for example an array of pixels, are arranged in the display area DA. The display area DA displays an image through the array of pixels. The display area DA corresponds to an active area that displays an image. The display area DA entirely surrounds the transmissive area TA.

[0025] The transmissive area TA is an area where components that can impart various functions to the display device 1 are arranged. For example, when the components include a sensor, a camera, or the like that uses light, light emitted from or directed toward the sensor, or light directed toward the camera, passes through the transmissive area TA.

[0026] The intermediate area MA is an area disposed between the transmissive area TA and the display area DA, and surrounds the transmissive area TA. The intermediate area MA is a type of non-display area where no pixels are disposed. Lines are disposed in the intermediate area MA for providing a predetermined signal or voltage to the pixels adjacent to the transmissive area TA. Grooves, which will be described later, are disposed in the intermediate area MA.

[0027] Like the intermediate area MA, the outer area PA is a type of non-display area in which no pixels are arranged. Various types of wiring, circuits, etc. are arranged in the outer area PA.

[0028] Each pixel in the display device 1 includes a light emitting diode as a display element capable of emitting light of a predetermined hue. The light emitting diode includes an organic light emitting diode including an organic material as a light emitting layer. Alternatively, the light emitting diode includes an inorganic light emitting diode. Alternatively, the light emitting diode includes a quantum dot as a light emitting layer. For convenience of explanation, the following description will be given assuming that the light emitting diode includes an organic light emitting diode.

[0029] 1 shows the transmissive region TA disposed at the center of the display region DA along the width direction (e.g., ±x direction) of the display device 1, but the present invention is not limited thereto. In another embodiment, the transmissive region TA is disposed offset to the left or right side along the width direction of the display device 1. Alternatively, the transmissive region TA is disposed at various positions, such as at the upper side, the center, or the lower side along the longitudinal direction (e.g., ±y direction) of the display device 1.

[0030] Although FIG. 1 shows the display device 1 including one transmissive area TA, in other embodiments, the display device 1 includes multiple transmissive areas TA.

[0031] FIG. 2 is a cross-sectional view showing a simplified display device according to one embodiment of the present invention, corresponding to a cross-section along line II-II' in FIG. 1, and FIG. 3 is a cross-sectional view showing a schematic diagram of an electronic device including a display device according to one embodiment of the present invention.

[0032] 2, the display device 1 includes a display panel 10, an input sensing unit 40 disposed on the upper surface of the display panel 10, and an optical function unit 50. A window 60 is bonded to an underlying component, for example, the optical function unit 50, via an adhesive layer such as an optical clear adhesive (OCA).

[0033] The display panel 10 includes a plurality of light emitting diodes arranged in a display area DA. The display panel 10 includes lines (e.g., data lines, scan lines, driving voltage lines, common voltage lines, etc.) for providing signals or voltages to each of the plurality of light emitting diodes, and transistors coupled to each of the plurality of diodes.

[0034] The input sensing unit 40 acquires coordinate information based on an external input, for example, a touch event. The input sensing unit 40 includes touch electrodes and trace lines connected to the touch electrodes. The input sensing unit 40 is disposed on the display panel 10. The input sensing unit 40 senses an external input by a mutual capacitance method or a self-capacitance method.

[0035] The input sensing unit 40 is formed directly on the display panel 10. Alternatively, the input sensing unit 40 is formed separately and then bonded to the display panel 10 via an adhesive layer such as an optically clear adhesive (OCA). In one embodiment, as shown in FIG. 2, the input sensing unit 40 is formed directly on the display panel 10, in which case no adhesive layer is interposed between the input sensing unit 40 and the display panel 10.

[0036] The optical function unit 50 includes an anti-reflection layer. The anti-reflection layer reduces the reflectance of light (external light) incident from the outside toward the display panel 10 through the window 60. The anti-reflection layer includes a phase retarder and a polarizer. The phase retarder is a film type or a liquid crystal coating type, and includes a λ / 2 phase retarder and / or a λ / 4 phase retarder. The polarizer is also a film type or a liquid crystal coating type. The film type includes a stretched synthetic resin film, and the liquid crystal coating type includes liquid crystals arranged in a predetermined arrangement. The phase retarder and the polarizer may further include a protective film.

[0037] In another embodiment, the anti-reflection layer includes a structure of a black matrix and a color filter. The color filters are arranged in consideration of the hue of light emitted from each pixel of the display panel 10. In yet another embodiment, the anti-reflection layer includes a destructive interference structure. The destructive interference structure includes a first reflective layer and a second reflective layer disposed on different layers. The first reflected light and the second reflected light reflected by the first reflective layer and the second reflective layer, respectively, are destructively interfered with, thereby reducing the reflectance of the external light.

[0038] The optical function unit 50 includes a lens layer. The lens layer improves the light output efficiency or reduces color deviation of the light emitted from the display panel 10. The lens layer includes a layer having a concave or convex lens shape and / or includes a plurality of layers having different refractive indices. The optical function unit 50 includes both the anti-reflection layer and the lens layer described above, or includes any one of them.

[0039] 3, the display device 1 is provided in various electronic devices 2 such as a mobile phone, a tablet PC, a notebook computer, and a smart watch. The electronic device 2 includes a housing HS having an internal space, and a display panel 10 is disposed in the housing HS. A window 60 is coupled to the housing HS. As described above, the input sensing unit 40 and the optical function unit 50 are disposed on the upper surface of the display panel 10.

[0040] The component CP is disposed in the housing HS and is located between the display panel 10 and the inner bottom surface of the housing HS. The component CP may be located in a transmissive area TA. In this case, the transmissive area TA is a kind of component area in which the component CP is disposed.

[0041] The component CP includes an electronic element. For example, the component CP is an electronic element that uses light. For example, the electronic element includes a sensor that receives and uses light, such as an infrared sensor, a camera that receives light and captures an image, a sensor that outputs and senses light to measure distance or recognize fingerprints, a small lamp that outputs light, etc.

[0042] The light-utilizing electronic elements utilize light of various wavelength bands, such as visible light, infrared light, ultraviolet light, etc. If the component CP includes a camera, the transmittance of the display device 1 in the transmissive area TA is about 70% or higher. Alternatively, if the component CP includes a sensor, the transmittance of the display device 1 in the transmissive area TA is lower than 70%, for example about 50% or higher or 60% or higher.

[0043] In order to prevent a problem in which transmittance is reduced by components arranged in the traveling path of light emitted from or traveling to the component CP, the display device 1 (FIG. 2) includes an opening OP. The opening OP is formed by removing a part of one or more components included in the display device 1, for example, selected from the display panel 10, the input sensing unit 40, the optical function unit 50, and the window 60. As an embodiment, FIG. 2 shows that the display panel 10, the input sensing unit 40, and the optical function unit 50 each include first to third through holes (10H, 40H, 50H), which form the opening OP.

[0044] 2, the display panel 10 includes a first through hole 10H penetrating the top and bottom surfaces of the display panel 10, the input sensing unit 40 includes a second through hole 40H penetrating the top and bottom surfaces of the input sensing unit 40, and the optical function unit 50 includes a third through hole 50H penetrating the top and bottom surfaces of the optical function unit 50. The first through hole 10H, the second through hole 40H, and the third through hole 50H are disposed in the transmissive region TA and overlap one another.

[0045] FIG. 4 is a plan view illustrating a display panel according to an embodiment of the present invention, and FIG. 5 is a perspective view illustrating a substrate of the display panel according to an embodiment of the present invention.

[0046] 4, the display panel 10 includes pixels P arranged on a substrate 100. The pixels P are arranged in a display area DA to provide a predetermined image. Each pixel P includes a display element, such as a light emitting diode, that emits light of a predetermined color.

[0047] The first through-hole 10H is located inside the display area DA. Since the first through-hole 10H is disposed inside the display area DA, pixels P are disposed on both sides of the first through-hole 10H. For example, the first through-hole 10H is located between two adjacent pixels P.

[0048] The intermediate region MA has a predetermined area so as to surround the first through hole 10H. In the intermediate region MA, a part of the lines (e.g., data lines, scan lines, driving voltage lines, etc.) for applying signals or voltages to the pixels arranged around the first through hole 10H is located. In the intermediate region MA, a groove, which is a moisture penetration prevention structure described later, is arranged.

[0049] The outer area PA surrounds the display area. A scan driver, a data driver, etc. are arranged in the outer area PA. A pad PAD is located in the outer area PA. The pad PAD is arranged adjacent to one edge of the substrate 100. The pad PAD is exposed without being covered by an insulating layer and is electrically connected to the flexible printed circuit board FPCB. The flexible printed circuit board FPCB electrically connects the controller and the pad PAD, and supplies a signal or power transmitted from the controller to the pad PAD. In one embodiment, a data driver is arranged on the flexible printed circuit board FPCB. The pad PAD is connected to a plurality of wirings 20 to transmit a signal or voltage of the flexible printed circuit board FPCB to the pixel P.

[0050] The outer region PA includes a bending region BA. The bending region BA is disposed between the pad PAD and the display region DA. The bending region BA extends in a direction intersecting with the extension direction of the wiring 20. The bending region BA extends in a direction parallel to an edge on one side of the substrate 100. The bending region BA divides the substrate 100 into a first region 1A including the display region DA and a second region 2A opposite the first region 1A. The bending region BA is located between the first region 1A and the second region 2A. The first region 1A includes the display region DA and a portion of the outer region PA, and the second region 2A includes only a portion of the outer region.

[0051] The display panel 10 is bent around a bending area BA. In this regard, FIG. 5 shows the substrate 100 of the display panel 10 bent. The substrate 100 is bent around a bending axis BAX extending along the y direction. Thus, the display panel 10 also has a bent shape similar to the substrate 100. The substrate 100 includes various materials (e.g., polymer resin) having flexible or bendable properties. For convenience, FIG. 5 shows a structure in which the substrate 100, rather than the entire display panel 10, is bent, but layers disposed on the substrate 100 are also bent together with the substrate 100.

[0052] 4, each wiring 20 includes a first portion 21 and a second portion 22 arranged on either side of a bending area BA, and a third portion 23 connecting them. The first portion 21 is located between the display area DA and the bending area BA, the second portion 22 is located between the bending area BA and the pad PAD, and the third portion 23 is located in the bending area BA.

[0053] When the substrate 100 is bent around the bending region BA, the wire 20 may be broken or layers disposed above and below the wire 20 may be peeled off. To prevent this, the wire 20 includes the first portion 21 and the second portion 22 spaced apart from each other across the bending region BA as described above, and the first portion 21 and the second portion 22 are connected by the third portion 23 including a material having relatively excellent flexibility.

[0054] FIG. 6 is an equivalent circuit diagram that illustrates a pixel of the display panel.

[0055] 6, a light emitting diode, for example an organic light emitting diode OLED, is connected to a pixel circuit PC. The pixel circuit PC includes a first thin film transistor T1, a second thin film transistor T2, and a storage capacitor Cst. Each pixel P emits light, for example red, green, blue, or white, through the organic light emitting diode OLED.

[0056] The second thin film transistor T2 is a switching thin film transistor connected to the scan line SL and the data line DL and transmits a data voltage input from the data line DL to the first thin film transistor T1 based on a switching voltage input from the scan line SL. The storage capacitor Cst is connected to the second thin film transistor T2 and the driving voltage line PL and stores a voltage corresponding to a difference between the voltage transmitted from the second thin film transistor T2 and the first power supply voltage ELVDD supplied to the driving voltage line PL.

[0057] The first thin film transistor T1 is a driving thin film transistor connected to the driving voltage line PL and the storage capacitor Cst and controls a driving current flowing from the driving voltage line PL to the organic light emitting diode OLED in response to the voltage value stored in the storage capacitor Cst. The organic light emitting diode OLED emits light having a predetermined brightness according to the driving current. A counter electrode (e.g., a cathode) of the organic light emitting diode OLED is supplied with a second power supply voltage ELVSS.

[0058] 6 shows that the pixel circuit PC includes two thin film transistors and one storage capacitor, but the present invention is not limited thereto. The number of thin film transistors and the number of storage capacitors can be changed according to the design of the pixel circuit PC. For example, the pixel circuit PC further includes four, five or more thin film transistors in addition to the above-mentioned two thin film transistors.

[0059] FIG. 7 is a plan view showing a portion of a display panel according to an embodiment of the present invention.

[0060] 7, pixels P are arranged in a display area DA, and a first through-hole 10H is defined between adjacent pixels P. For example, on a plane, pixels P are arranged above and below (±y directions) the first through-hole 10H as a center, and pixels P are arranged to the left and right (±x directions) the first through-hole 10H as a center.

[0061] In the middle region MA, a groove G is arranged to prevent moisture from entering through the first through-hole 10H and damaging the light emitting diode of the pixel P. The grooves G are arranged concentrically. The grooves G are spaced apart from each other. Although two grooves G are shown in FIG. 7, the number of grooves G may be three or more.

[0062] Fig. 8 is a cross-sectional view of a display device according to an embodiment of the present invention, and Fig. 9 and Fig. 10 are cross-sectional views showing groove structures according to embodiments of the present invention. Fig. 8 shows a display panel and a touch sensing unit, omitting an optical function unit of the display device for convenience.

[0063] 8, a display panel 10 including a substrate 100, a display layer 200 including an array of a plurality of pixels, and a thin-film encapsulation layer 300 includes a first through-hole 10H corresponding to a transmissive region TA, and an input sensing unit 40 on the display panel 10 includes a second through-hole 40H corresponding to the transmissive region TA. The first through-hole 10H is formed to penetrate the substrate 100, the display layer 200, and the thin-film encapsulation layer 300. The first through-hole 10H and the second through-hole 40H overlap each other, and form an opening OP as previously described with reference to FIG. 2.

[0064] Referring to the display area DA of FIG. 8, the substrate 100 includes a polymer resin. In one embodiment, the substrate 100 includes a base layer including a polymer resin and an inorganic insulating layer on the base layer. For example, the substrate 100 includes two base layers and an inorganic insulating layer on each base layer. The polymer resin includes polyethersulfone, polyarylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyimide, polycarbonate, cellulose triacetate, cellulose acetate propionate, etc.

[0065] A buffer layer 201 is formed on the substrate 100 to prevent impurities from penetrating into the semiconductor layer Act of the thin film transistor TFT. The buffer layer 201 includes an inorganic insulator such as silicon nitride, silicon oxynitride, and silicon oxide, and is a single layer or multiple layers including the above-mentioned inorganic insulators.

[0066] A pixel circuit PC is disposed on the buffer layer 201. The pixel circuit PC includes a thin film transistor TFT and a storage capacitor Cst. The thin film transistor TFT includes a semiconductor layer Act, a gate electrode GE, a source electrode SE, and a drain electrode DE.

[0067] The data line DL of the pixel circuit PC is electrically connected to a switching thin film transistor included in the pixel circuit PC, which is not shown in Fig. 8. In this embodiment, the gate electrode GE is a top gate type disposed on the semiconductor layer Act with the gate insulating layer 203 interposed therebetween, but in other embodiments, the thin film transistor TFT is a bottom gate type.

[0068] The semiconductor layer Act includes polysilicon. Alternatively, the semiconductor layer Act includes amorphous silicon, an oxide semiconductor, an organic semiconductor, or the like. The gate electrode GE includes a low-resistance metal material. The gate electrode GE includes a conductive material including molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), or the like, and is formed of a multilayer or single layer including the above materials.

[0069] The gate insulating layer 203 between the semiconductor layer Act and the gate electrode GE includes an inorganic insulator such as silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, etc. The gate insulating layer 203 is a single layer or a multilayer including the above-mentioned materials.

[0070] The source electrode SE and the drain electrode DE are located on the same layer as the data line DL and contain the same material. The source electrode SE, the drain electrode DE, and the data line DL contain a material with excellent conductivity. The source electrode SE and the drain electrode DE contain conductive materials including molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), etc., and are formed of a multi-layer or single layer including the above materials. In one embodiment, the source electrode SE, the drain electrode DE, and the data line DL are formed of a multi-layer structure of a titanium layer, an aluminum layer, and a titanium layer (Ti / Al / Ti).

[0071] The storage capacitor Cst includes a lower electrode CE1 and an upper electrode CE2 that overlap with a first interlayer insulating layer 205 sandwiched therebetween. The storage capacitor Cst overlaps the thin film transistor TFT. In this regard, FIG. 8 shows that the gate electrode GE of the thin film transistor TFT is the lower electrode CE1 of the storage capacitor Cst. Although not shown, in another embodiment, the storage capacitor Cst may not overlap the thin film transistor TFT. The storage capacitor Cst is covered by a second interlayer insulating layer 207. The upper electrode CE2 of the storage capacitor Cst includes a conductive material including molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), etc., and is formed of a multilayer or single layer including the above materials.

[0072] The first interlayer insulating layer 205 and / or the second interlayer insulating layer 207 include an inorganic insulator such as silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, etc. The first interlayer insulating layer 205 and the second interlayer insulating layer 207 are a single layer or a multilayer including the above-mentioned materials.

[0073] The pixel circuit PC including the thin film transistor TFT and the storage capacitor Cst is covered by a first organic insulating layer 209. The first organic insulating layer 209 includes an upper surface that is approximately flat.

[0074] The pixel circuit PC is electrically connected to the pixel electrode 221. For example, as shown in FIG. 8, a contact metal layer CM is interposed between the thin film transistor TFT and the pixel electrode 221. The contact metal layer CM is connected to the thin film transistor TFT through a contact hole formed in the first organic insulating layer 209, and the pixel electrode 221 is connected to the contact metal layer CM through a contact hole formed in the second organic insulating layer 211 on the contact metal layer CM. The contact metal layer CM includes conductive materials including molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), etc., and is formed of a multilayer or single layer including the above materials. In one embodiment, the contact metal layer CM is formed of a multilayer of Ti / Al / Ti.

[0075] The first organic insulating layer 209 and / or the second organic insulating layer 211 include organic insulators such as common general-purpose polymers such as polymethyl methacrylate (PMMA) and polystyrene (PS), polymer derivatives having phenols, acrylic polymers, imide polymers, aryl ether polymers, amide polymers, fluorine polymers, p-xylene polymers, vinyl alcohol polymers, and blends thereof. In one embodiment, the first organic insulating layer 209 and / or the second organic insulating layer 211 includes polyimide.

[0076] The pixel electrode 221 is formed on the second organic insulating layer 211. The pixel electrode 221 is made of any of a variety of materials such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In 2 O 3In another embodiment, the pixel electrode 221 includes a reflective film including silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), or a combination thereof. In another embodiment, the pixel electrode 221 includes a reflective film including ITO, IZO, ZnO, or In, above and / or below the reflective film. 2 O 3 The present invention further includes a transparent conductive oxide film formed of

[0077] A pixel defining layer 215 is formed on the pixel electrode 221. The pixel defining layer 215 includes an opening that exposes the upper surface of the pixel electrode 221, but covers the edge of the pixel electrode 221. The pixel defining layer 215 includes an organic insulator. Alternatively, the pixel defining layer 215 may include silicon nitride (SiN x ), silicon oxynitride (SiON), or silicon oxide (SiO x Alternatively, the pixel defining layer 215 may include an organic insulator and an inorganic insulator.

[0078] The intermediate layer 222 includes a light-emitting layer 222b. The intermediate layer 222 includes a first functional layer 222a disposed under the light-emitting layer 222b and / or a second functional layer 222c disposed on the light-emitting layer 222b. The light-emitting layer 222b includes a polymer or low-molecular organic material that emits light of a predetermined hue.

[0079] The first functional layer 222a is a single layer or a multilayer. For example, when the first functional layer 222a is made of a polymeric material, the first functional layer 222a is a hole transport layer (HTL) having a single layer structure and made of poly(3,4-ethylenedihydroxythiophene) (PEDOT) or polyaniline (PAN). When the first functional layer 222a is made of a low molecular weight material, the first functional layer 222a includes a hole injection layer (HIL) and a hole transport layer (HTL).

[0080] The second functional layer 222c is optional. For example, when the first functional layer 222a and the light emitting layer 222b are made of a polymeric material, it is preferable to form the second functional layer 222c. The second functional layer 222c is a single layer or a multilayer. The second functional layer 222c includes an electron transport layer (ETL) and / or an electron injection layer (EIL).

[0081] In the intermediate layer 222, the light-emitting layer 222b is disposed for each pixel in the display area DA. The light-emitting layer 222b is patterned to correspond to the pixel electrode 221. Unlike the light-emitting layer 222b, the first functional layer 222a and / or the second functional layer 222c in the intermediate layer 222 are integrally formed on the substrate 100 so as to be located not only in the display area DA but also in the intermediate area MA.

[0082] The counter electrode 223 is made of a conductive material with a low work function. For example, the counter electrode 223 includes a (semi)transparent layer containing silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), or an alloy thereof. Alternatively, the counter electrode 223 includes a (semi)transparent layer containing the above-mentioned material and a (semi)transparent layer containing ITO, IZO, ZnO, or In. 2 O 3The counter electrode 223 is integrally formed not only on the display area DA but also on the middle area MA. The first functional layer 222a, the second functional layer 222c, and the counter electrode 223 are formed by thermal evaporation.

[0083] The capping layer 230 is located on the counter electrode 223. For example, the capping layer 230 includes a LiF layer and is formed by thermal evaporation. In one embodiment, the capping layer 230 is omitted.

[0084] A spacer 217 is formed on the pixel defining layer 215. The spacer 217 may include an organic insulator such as polyimide, or the spacer 217 may include an inorganic insulator, or may include both an organic insulator and an inorganic insulator.

[0085] The spacers 217 may include a different material than the pixel defining layer 215 or may include the same material as the pixel defining layer 215. In one embodiment, the pixel defining layer 215 and the spacers 217 include polyimide. The pixel defining layer 215 and the spacers 217 are formed together in a mask process using a half-tone mask.

[0086] The organic light emitting diode OLED is covered by a thin film encapsulation layer 300. The thin film encapsulation layer 300 includes at least one organic encapsulation layer and at least one inorganic encapsulation layer, and FIG. 8 shows the thin film encapsulation layer 300 including first and second inorganic encapsulation layers (310, 330) and an organic encapsulation layer 320 interposed therebetween. In other embodiments, the number of organic encapsulation layers, the number of inorganic encapsulation layers, and the stacking order can be changed.

[0087] The first inorganic encapsulation layer 310 and the second inorganic encapsulation layer 330 include one or more inorganic materials selected from the group consisting of aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, zinc oxide, silicon oxide, silicon nitride, and silicon oxynitride. The first inorganic encapsulation layer 310 and the second inorganic encapsulation layer 330 are single or multi-layered structures including the above-mentioned materials. The organic encapsulation layer 320 includes a polymer-based material. Examples of the polymer-based material include acrylic resins such as polymethylmethacrylate and polyacrylic acid, epoxy resins, polyimides, polyethylene, and the like. In one embodiment, the organic encapsulation layer 320 includes an acrylate polymer.

[0088] The materials of the first inorganic sealing layer 310 and the second inorganic sealing layer 330 are different from each other. For example, the first inorganic sealing layer 310 includes silicon oxynitride, and the second inorganic sealing layer 330 includes silicon nitride. The thicknesses of the first inorganic sealing layer 310 and the second inorganic sealing layer 330 are different from each other. The thickness of the first inorganic sealing layer 310 is thicker than the thickness of the second inorganic sealing layer 330. Alternatively, the thickness of the second inorganic sealing layer 330 is thicker than the thickness of the first inorganic sealing layer 310, or the thicknesses of the first inorganic sealing layer 310 and the second inorganic sealing layer 330 are the same.

[0089] 8, one or more grooves G are disposed in the intermediate region MA. The organic layers included in the intermediate layer 222, such as the first functional layer 222a and / or the second functional layer 222c, are interrupted (or separated) by the grooves G.

[0090] The groove G is formed by a first layer 240 and a second layer 250 each including a different material. The first layer 240 includes an organic insulator, and the second layer 250 includes an inorganic insulator or a metal. In one embodiment, the second layer 250 includes a metal.

[0091] 9 and 10, the first layer 240 is formed on the second interlayer insulating layer 207, which is an inorganic insulating layer, and the second layer 250 is formed on the upper surface of the first layer 240. The thickness T of the first layer 240 is greater than the thickness t of the second layer 250.

[0092] The first layer 240 includes an organic insulator such as a general-purpose polymer, a polymer derivative having a phenol, an acrylic polymer, an imide polymer, an aryl ether polymer, an amide polymer, a fluorine-based polymer, a p-xylene-based polymer, a vinyl alcohol-based polymer, and blends thereof. In one embodiment, the first layer 240 is formed before forming the first organic insulating layer 209, for example, in a process of forming an organic layer described below with reference to FIG.

[0093] The second layer 250 is in direct contact with the top surface of the first layer 240 and comprises a metal. The second layer 250 may comprise molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), etc., and may be formed of a multi-layer or single layer comprising the above materials. In one embodiment, the second layer 250 comprises the same material as the data line DL, or the source electrode SE or drain electrode DE of the thin film transistor TFT.

[0094] The groove G has an undercut structure or an overhang structure. The groove G includes a second hole 250h formed in the second layer 250 and a first hole 240h formed in the first layer 240. The groove G is formed by etching, for example, an isotropic etching process, and depending on the degree of etching, the groove G includes the second hole 250h formed in the second layer 250 and the first hole 240h formed in the first layer 240 as shown in FIG. 9, or the groove G includes the second hole 250h formed in the second layer 250 and the recess 240r formed in the first layer 240 as shown in FIG. 10. When the first layer 240 includes the recess 240r, the depth d of the groove G is smaller than the thickness T of the first layer 240. In one embodiment, the depth d of the groove G is about 3 μm or greater.

[0095] The bottom surface of the groove G is located on the same plane as the bottom surface of the first layer 240 or the top surface of the second interlayer insulating layer 207, as shown in Fig. 9. Alternatively, the bottom surface of the groove G is located between the top and bottom surfaces of the first layer 240, or between the top surface of the first layer 240 and the top surface of the second interlayer insulating layer 207, as shown in Fig. 10.

[0096] The ends of the second layer 250 that define the second hole 250h extend further toward the center of the second hole 250h than the inner surfaces of the first layer 240 that define the first hole 240h or the recess 240r. For example, the second layer 250 includes a pair of tips 251 that define the second hole 250h and that extend further toward the center of the second hole 250h than the inner surfaces of the first layer 240.

[0097] Each chip 251 has a first width W1 that is about 2 μm or greater. The first width W1 of the chip 251 is the horizontal distance from an edge of the top surface of the first layer 240 located directly below the chip 251 to an edge of the chip 251.

[0098] The groove G having the above-mentioned structure is formed before the step of forming the intermediate layer 222. The layer containing the organic matter among the layers formed on the substrate 100 becomes a path along which moisture advances. For example, as shown in FIG. 8, when the display panel 10 includes the first through-hole 10H, moisture advances along a direction parallel to the upper surface of the substrate 100 (hereinafter referred to as the lateral direction), but according to the embodiment of the present invention, the organic matter layer, for example, the first functional layer 222a and / or the second functional layer 222c is interrupted or separated by the eaves structure or undercut structure of the groove G. The first functional layer 222a and / or the second functional layer 222c are formed by a thermal evaporation method, and during the evaporation of the first functional layer 222a and / or the second functional layer 222c, the first functional layer 222a and / or the second functional layer 222c are formed discontinuously due to the structure of the chip 251.

[0099] Similarly, the LiF layer of the counter electrode 223 and / or the capping layer 230 is also formed by thermal evaporation and is discontinuously formed according to the structure of the chip 251. In one embodiment, Figures 8, 9 and 10 show a structure in which the first functional layer 222a, the second functional layer 222c, the counter electrode 223 and the capping layer 230 are spaced apart from each other around the chip 251. The first functional layer 222a, the second functional layer 222c, the counter electrode 223 and a portion of the capping layer 230 are located on the bottom surface of the groove G.

[0100] The partition wall PW is disposed between the grooves G. The partition wall PW includes a plurality of partition layers stacked in sequence. As an embodiment, as shown in FIG. 8, the partition wall PW includes a first partition layer PW1, a second partition layer PW2, and a third partition layer PW3. The first partition layer PW1 includes the same material as the first organic insulating layer 209, the second partition layer PW2 includes the same material as the second organic insulating layer 211, and the third partition layer PW3 includes the same material as the pixel defining layer 215 and / or the spacer 217.

[0101] The partition walls PW are disposed apart from the first layer 240. For example, the first partition wall layer PW1, the second partition wall layer PW2, and the third partition wall layer PW3 are each separated from the first layer 240. Between the partition wall PW and the first layer 240, the second layer 250 passes through the first layer 240 and directly contacts an inorganic insulating layer disposed below the first layer 240, for example, the second interlayer insulating layer 207. The second layer 250 passes through the outer surface of the first layer 240 and directly contacts an upper surface of the second interlayer insulating layer 207.

[0102] In a comparative example of the present invention, when the layer forming the partition wall PW comes into contact with the first layer 240, an organic path through which moisture can travel is formed. However, according to an embodiment of the present invention, the layer forming the partition wall PW and the first layer 240 are spaced apart from each other and / or the second interlayer insulating layer 207, which is an inorganic insulating layer, comes into direct contact with the second layer 250, which includes a metal, and therefore the path through which moisture can travel is blocked.

[0103] 7, the laminated structure of the first layer 240 and the second layer 250 in which the groove G is defined has a loop shape surrounding the first through hole 10H on a plane. Similarly, the partition wall PW also has a loop shape surrounding the first through hole 10H on a plane. The first layer 240 defining any one of the grooves G, the partition wall PW, and the first layer 240 defining the other groove G are spaced apart from each other and have a loop shape surrounding the first through hole 10H.

[0104] The thin film sealing layer 300 is also formed in the middle region MA. The first inorganic sealing layer 310 has a relatively better step coverage than the above-mentioned first functional layer 222a, the second functional layer 222c, the counter electrode 223, and / or the capping layer 230. The first inorganic sealing layer 310 is continuously formed as shown in FIG. 8. For example, the first inorganic sealing layer 310 continuously and entirely covers the inner surface of the groove G. The first inorganic sealing layer 310 is formed by chemical vapor deposition.

[0105] The organic sealing layer 320 overlaps the grooves G that are relatively adjacent to the display area DA among the grooves G. The grooves G adjacent to the display area DA are at least partially filled with the material that constitutes the organic sealing layer 320.

[0106] The second inorganic sealing layer 330, like the first inorganic sealing layer 310, has relatively excellent step coverage, and thus continuously covers a portion of the groove G, for example, the inner surface of the groove G between the partition wall PW and the first through hole 10H.

[0107] The input sensing unit 40 is located on a display panel 10 including a substrate 100, a display layer 200 including a pixel circuit PC and an organic light emitting diode OLED on the substrate 100, and a thin film encapsulation layer 300. The input sensing unit 40 is formed directly on the display panel 10.

[0108] The input sensing unit 40 includes a first insulating layer 410, a second insulating layer 420, a third insulating layer 440, and a fourth insulating layer 460, which are stacked in sequence. The input sensing unit 40 includes a first conductive layer 430 between the second insulating layer 420 and the third insulating layer 440, and a second conductive layer 450 between the third insulating layer 440 and the fourth insulating layer 460. The first conductive layer 430 and / or the second conductive layer 450 includes a touch electrode for sensing a touch input and a trace line connected to the touch electrode.

[0109] The first insulating layer 410, the second insulating layer 420, or the third insulating layer 440 may include an inorganic insulator such as silicon oxide, silicon nitride, or silicon oxynitride, and the fourth insulating layer 460 may include an organic insulator. For example, the fourth insulating layer 460 may include an organic insulator such as a photoresist (negative or positive) or a polymer-based organic material. The first conductive layer 430 and / or the second conductive layer 450 may include a metal or a transparent conductive oxide (TCO). In one embodiment, the first conductive layer 430 and / or the second conductive layer 450 may include a conductive material such as molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), or the like.

[0110] The first insulating layer 410, the second insulating layer 420, the third insulating layer 440, and the fourth insulating layer 460 are integrally formed to be located in the display area DA and the middle area MA. In contrast, the planarization layer 415 is located in the middle area MA. On a plane, the planarization layer 415 has a loop shape surrounding the first through hole 10H.

[0111] The planarization layer 415 is an organic insulating layer. The planarization layer 415 includes a polymer-based material. For example, the planarization layer 415 includes a silicone-based resin, an acrylic-based resin, an epoxy-based resin, a polyimide, a polyethylene, etc. The planarization layer 415 includes a material different from that of the organic encapsulation layer 320.

[0112] A portion of the planarization layer 415 adjacent to the display area DA overlaps the organic sealing layer 320. The second inorganic sealing layer 330 and the first insulating layer 410 are interposed between the organic sealing layer 320 and the planarization layer 415, which overlap each other.

[0113] The organic encapsulation layer 320 is located on one side of the barrier rib PW, and the area of ​​the intermediate region MA that is not covered by the organic encapsulation layer 320 is covered by the planarization layer 415. The planarization layer 415 is located in the area of ​​the intermediate region MA that is not covered by the organic encapsulation layer 320, thereby increasing the flatness of the display panel 10 around the first through-hole 10H. This makes it possible to prevent problems such as peeling of the input sensing unit 40 and / or the optical function unit 50 (FIG. 2) on the display panel 10.

[0114] FIG. 11 is a cross-sectional view showing a display panel according to an embodiment of the present invention.

[0115] The display area DA in Fig. 11 has the same layered structure as the display area DA previously described with reference to Fig. 10, and therefore will not be described here. The outer peripheral area of ​​the display panel 10 includes a bending area BA as previously described with reference to Figs. 4 and 5.

[0116] Referring to the outer region PA including the bending region BA in FIG. 11, the inorganic insulating structure IL arranged on the substrate 100 includes an opening IL-OP. The inorganic insulating structure IL includes at least one inorganic insulating layer. In one embodiment, the inorganic insulating structure IL includes a buffer layer 201, a gate insulating layer 203, a first interlayer insulating layer 205, and / or a second interlayer insulating layer 207. The opening 201a of the buffer layer 201, the opening 203a of the gate insulating layer 203, the opening 205a of the first interlayer insulating layer 205, and / or the opening 207a of the second interlayer insulating layer 207 overlap each other to form an opening IL-OP of the inorganic insulating structure IL. The width OW of the opening IL-OP is formed larger than the width of the bending region BA. In one embodiment, when the substrate 100 includes two base layers and an inorganic insulating layer on each base layer, the inorganic insulating layer included in the uppermost layer of the substrate 100 also includes an opening corresponding to the opening IL-OP. In this case, the base layer of the substrate 100 is exposed through the opening IL-OP, and the exposed base layer is in direct contact with the organic insulating layer 260 described below.

[0117] An organic insulating layer 260 is formed in the bending region BA. The organic insulating layer 260 at least partially fills the opening of at least one inorganic insulating layer. For example, the organic insulating layer 260 at least partially fills the opening IL-OP of the inorganic insulating structure IL. The organic insulating layer 260 is formed only in the bending region BA. The organic insulating layer 260 includes an organic insulator such as acrylic, benzocyclobutene (BCB), polyimide, or hexamethyldisiloxane (HMDSO). The organic insulating layer 260 is formed in the same process as the first layer 240 (FIG. 8) described above with reference to FIG. 8, and includes the same material as the first layer 240.

[0118] Since the inorganic insulating structure IL includes an opening IL-OP in the bending region BA, it is possible to prevent or minimize cracks from occurring in at least one inorganic insulating layer due to bending stress, and since the organic insulating layer 260 absorbs the stress generated during bending, it is possible to prevent the above-mentioned crack problem.

[0119] A first portion 21 of the wiring arranged in the first region 1A and a second portion 22 of the wiring arranged in the second region 2A are spaced apart from each other with the bending region BA as the center. The first portion 21 and the second portion 22 are located on, for example, the gate insulating layer 203. Alternatively, the first portion 21 and / or the second portion 22 are located on, for example, the first interlayer insulating layer 205.

[0120] The first portion 21 and the second portion 22 are electrically connected by the third portion 23 located on the organic insulating layer 260. The third portion 23 extends across the bending region BA. One end of the third portion 23 overlaps the first portion 21 and is connected to the first portion 21 through a contact hole that passes through the first and second interlayer insulating layers (205, 207). The other end of the third portion 23 overlaps the second portion 22 and is connected to the second portion 22 through a contact hole that passes through the first and second interlayer insulating layers (205, 207).

[0121] The third portion 23 includes a material, such as aluminum, that is softer than the first portion 21 and / or the second portion 22. In one embodiment, the third portion 23 is formed by the same process as the second layer 250 (FIG. 8) described above with reference to FIG.

[0122] One or more protective layers are disposed in the outer region PA. As an embodiment, FIG. 11 shows a first protective layer 271 and a second protective layer 272. The first protective layer 271 and the second protective layer 272 include an organic insulator. The first protective layer 271 and / or the second protective layer 272 are formed to protect the third portion 23 of the wiring, adjust the neutral plane of the display panel during bending, or distribute bending stress.

[0123] Fig. 12 is a cross-sectional view showing a part of a display device according to an embodiment of the present invention, Figs. 13 to 15 are cross-sectional views showing a groove structure according to an embodiment of the present invention, and Fig. 16 is an enlarged cross-sectional view of XVI in Fig. 12. For convenience of explanation, Fig. 12 omits the optical function unit of the display device and shows only the display panel and the input sensing unit.

[0124] Referring to the display area DA in FIG. 12, since it has the same layered structure as the display area DA previously described with reference to FIG. 10, a description thereof will be omitted here.

[0125] Referring to the middle region MA of Fig. 12, the groove G is formed in the first layer 240' and the second layer 250'. Referring to Figs. 12 and 13, the first layer 240' is formed on the second interlayer insulating layer 207, which is an inorganic insulating layer, and the second layer 250' is formed on the upper surface of the first layer 240'.

[0126] The first layer 240' comprises an organic insulator. In some embodiments, the first layer 240' is formed in the same process as the first organic insulating layer 209 shown in FIG.

[0127] The second layer 250' is in direct contact with the top surface of the first layer 240' and includes a metal. The second layer 250' is formed in the same process as the contact metal layer CM shown in FIG.

[0128] The groove G has an undercut structure or an overhanging structure. The groove G includes a second hole 250h' formed in the second layer 250' and a first hole 240h' formed in the first layer 240'. The groove G is formed by etching, for example, an isotropic etching process, and FIGS. 12 and 13 show that the second hole 250h' formed in the second layer 250' and the first hole 240h' formed in the first layer 240' form the groove G. In another embodiment, as described above with reference to FIG. 10, a recess is formed in the first layer 240' instead of the first hole 240h'.

[0129] The end of the second layer 250' that defines the second hole 250h' extends further toward the center of the second hole 250h' than the inner surface of the first layer 240' that defines the first hole 240h' or the recess, forming a pair of tips 251'. As described above, the tips 251' separate or disconnect the organic layers of the intermediate layer 222, such as the first functional layer 222a and / or the second functional layer 222c. Similarly, the counter electrode 223 and / or the capping layer 230 are also separated or disconnected by an undercut structure or an overhanging structure.

[0130] The thin film encapsulation layer 300 includes a first inorganic encapsulation layer 310, an organic encapsulation layer 320, and a second inorganic encapsulation layer 330. The first inorganic encapsulation layer 310 has relatively excellent step coverage, and thus continuously covers the inner surface of the groove G, as shown in Figures 12 and 13. The specific structure of the thin film encapsulation layer 300 and the structure of the input sensing unit 40 disposed on the thin film encapsulation layer 300 are as described above with reference to Figure 8.

[0131] 12 and 13 show that the inner surfaces of the grooves G, such as the side and bottom surfaces of the chips 251′ and the inner surfaces of the first layer 240′, are in direct contact with the first inorganic encapsulation layer 310. In one embodiment, an inorganic passivation layer PVX is disposed between the inner surfaces of the grooves G and the first inorganic encapsulation layer 310.

[0132] 14, the inorganic passivation layer PVX is located on the second layer 250'. For example, the inorganic passivation layer PVX is formed after the second layer 250' is formed and before the intermediate layer 222 (FIG. 8) is formed. Although not shown, the inorganic passivation layer PVX extends to the display area DA (FIG. 8), in which case the inorganic passivation layer PVX is disposed between the contact metal layer CM (FIG. 12) and the second organic insulating layer 211 in the display area DA.

[0133] The inorganic passivation layer PVX includes inorganic insulators such as silicon oxide, silicon nitride, and silicon oxynitride, and is formed by chemical vapor deposition or the like.

[0134] The inorganic passivation layer PVX continuously and entirely covers the inner surfaces of the grooves G. For example, the inorganic passivation layer PVX covers the top, side and bottom surfaces of the second layer 250′, and continuously covers the inner surface of the first layer 240′ and the top surface of the second interlayer insulating layer 207 directly below the first layer 240′.

[0135] After the inorganic passivation layer PVX is formed, the first functional layer 222a, the second functional layer 222c, the counter electrode 223, and / or the capping layer 230 are formed. The first functional layer 222a, the second functional layer 222c, the counter electrode 223, and / or the capping layer 230 are disconnected or separated around the pair of chips 251′.

[0136] The first inorganic sealing layer 310, formed after the capping layer 230, continuously covers the inner surface of the groove G but directly contacts the inorganic passivation layer PVX in some areas.

[0137] Although FIG. 14 illustrates the first layer 240' as a single layer, in some embodiments, the first layer 240' includes multiple layers.

[0138] 15, the first layer 240″ includes a first sub-layer 241 and a second sub-layer 242. The first sub-layer 241 includes the same material as the first organic insulating layer 209 previously described with reference to FIG. 12, and the second sub-layer 242 includes the same material as the second organic insulating layer 211. Alternatively, the first sub-layer 241 includes the same material as the organic insulating layer 260 previously described with reference to FIG. 11, and the second sub-layer 242 includes the same material as the first organic insulating layer 209.

[0139] The second layer 250" includes a metal or an inorganic insulator. The second hole 250h" of the second layer 250" and the first hole or recess 240r" of the first layer 240" form a groove G. The second layer 250" includes a pair of tips 251" protruding toward the center of the second hole 250h". The pair of tips 251" protrude further toward the center of the second hole 250h" than the inner surface of the first layer 240" to form an undercut structure or an overhanging structure.

[0140] As previously described with reference to FIG. 14, an inorganic passivation layer PVX is formed on the second layer 250'', and the first functional layer 222a, the second functional layer 222c, the counter electrode 223, and / or the capping layer 230 are disconnected or separated around the pair of chips 251''.

[0141] As described above, the inorganic passivation layer PVX continuously covers the inner surface of the groove G, and the first inorganic sealing layer 310 is in direct contact with the inorganic passivation layer PVX partially. In another embodiment, the inorganic passivation layer PVX is omitted.

[0142] 12 again, the partition walls PW are located between the grooves G. The partition walls PW include a plurality of partition layers, for example, a first partition layer PW1, a second partition layer PW2, and a third partition layer PW3. The first partition layer PW1 includes the same material as the first organic insulating layer 209, the second partition layer PW2 includes the same material as the second organic insulating layer 211, and the third partition layer PW3 includes the same material as the pixel defining layer 215 and / or the spacer 217.

[0143] Between adjacent ones of the partition layers, for example between the second partition layer PW2 and the third partition layer PW3, a metal-containing spacing layer 280 is formed. The spacing layer 280 has a fine undercut structure, and in one embodiment, the first functional layer 222a and / or the second functional layer 222c are interrupted or separated. Similarly, the counter electrode 223 and / or the capping layer 230 are also interrupted or separated.

[0144] 12 and 16, the spacing layer 280 includes a metal. The spacing layer 280 includes at least two layers with different etching selectivity. In one embodiment, the spacing layer 280 includes a first layer 281, a second layer 282, and a third layer 283. The first layer 281 and the third layer 283 include the same material, and the second layer 282 includes a different material than the first layer 281 and the third layer 283. In one embodiment, the first layer 281 and the third layer 283 include a transparent conductive oxide such as ITO, and the second layer 282 includes a metal including silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), or a compound thereof. The thickness of the second layer 282 is greater than that of the first layer 281 and the third layer 283.

[0145] During the process of forming the display panel 10 (FIG. 12), the edges of the spacing layer 280 are etched, and at this time, the second layer 282 is etched further than the first layer 281 and the third layer 283. In this case, the edges of the first layer 281 protrude further in the lateral direction than the edges of the second layer 282, and the edges of the first layer 281 have substantially the same function as the tips of the grooves G described above. That is, by the edges of the first layer 281 protruding further than the edges of the second layer 282, a fine undercut structure or overhanging structure is formed in the spacing layer 280.

[0146] The first functional layer 222a, the second functional layer 222c, the counter electrode 223, and / or the capping layer 230 are interrupted or separated when the sum of the thicknesses of the first functional layer 222a, the second functional layer 222c, the counter electrode 223, and the capping layer 230 is less than the thickness of the spacing layer 280. In this regard, FIG. 16 illustrates the first functional layer 222a, the second functional layer 222c, the counter electrode 223, and the capping layer 230 being interrupted around the edge of the spacing layer 280.

[0147] Although the embodiments of the present invention have been described in detail above with reference to the drawings, the present invention is not limited to the above-described embodiments and can be modified in various ways without departing from the technical spirit of the present invention. [Industrial Applicability]

[0148] The present invention is applicable to, for example, technical fields related to display devices. [Explanation of symbols]

[0149] 1 Display device 1A, 2A 1st, 2nd area 2 Electronic equipment 10 Display Panel 10H, 40H, 50H 1st to 3rd through holes 20 Wiring 21, 22, 23 Parts 1 to 3 40 Input sensor 50 Optical function section 60 Windows 100 Substrates 200 display layer 201 Buffer Layer 201a, 203a, 205a, 207a opening 203 Gate Insulation Layer 205, 207 First and second interlayer insulating layers 209, 211 First and second organic insulating layers 215 Pixel-defined Membrane 217 Spacer 221 Pixel electrode 222 Middle Class 222a, 222c 1st and 2nd functional layer 222b Light-emitting layer 223 Counter Electrode 230 Capping Layer 240, 240′240″ 1st layer 240h, 240h' 1st Hall 240r, 240r″ recess 241, 242 1st and 2nd sub-layers 250, 250′, 250″ 2nd layer 250h, 250h′, 250h″ Hall 2 251, 251′251″ chip 260 Organic Insulating Layer 271, 272 1st and 2nd protective layer 280 Spacing Layer 281, 282, 283 1st to 3rd layer 300 Thin film sealing layer 310, 330 First and second inorganic sealing layers 320 Organic sealing layer 410, 420, 440, 460 1st to 4th insulating layers 415 Planarization layer 430, 450 First and second conductive layers Act semiconductor layer BA bending area BAX bending axis CE1 bottom electrode CE2 upper electrode CM Contact metal layer CP Components Cst Storage Capacitor DA display area DE Drain electrode DL Data Line ELVDD, ELVSS First and second power supply voltages FPCB Flexible Printed Circuit Board G Groove GE gate electrode HS Housing IL Inorganic insulation structure IL-OP, OP opening MA intermediate area OCA Optical clear adhesive OLED Organic Light Emitting Diode OW Opening width P pixels PA Outer Area PAD PC pixel circuit PL drive voltage line PVX Inorganic Passivation Layer PW Bulkhead PW1~PW3 1st~3rd partition layer SE source electrode SL Scanline T1, T2 First and second thin film transistors TA transmission area TFT Thin Film Transistor

Claims

1. A first through hole; an array of pixels arranged in a display region surrounding the first through hole, the array including pixels spaced apart from each other across the first through hole; a first layer disposed in an intermediate region between the first through hole and the display region, the first layer including a first hole or a recess; a second layer located on the first layer and including a second hole overlapping the first hole or the recess; the second layer includes a pair of tips extending further toward the center of the second hole than an inner surface of the first layer that defines the first hole or the recess; Each of the plurality of pixels includes a light emitting diode including a pixel electrode, a counter electrode, and an intermediate layer between the pixel electrode and the counter electrode; At least one organic layer of the intermediate layer is interrupted at the center of the pair of chips, the first layer includes an organic insulator; The display device, wherein the second layer includes a metal.

2. 2. The display device according to claim 1, wherein the at least one organic layer includes at least one layer selected from a hole transport layer, a hole injection layer, an electron injection layer, and an electron transport layer.

3. 2. The display device according to claim 1, wherein the counter electrode is interrupted at a center of the pair of chips.

4. a substrate on which the array of pixels is disposed; and 2. The display device according to claim 1, further comprising at least one inorganic insulating layer between the substrate and the pixel electrodes.

5. the first layer is disposed on the at least one inorganic insulating layer; 5. The display device according to claim 4, wherein the second layer passes through the first layer and directly contacts an upper surface of the at least one inorganic insulating layer.

6. Further comprising at least one organic insulating layer between the at least one inorganic insulating layer and the pixel electrode; 5. The display device according to claim 4, wherein the first layer contains the same material as the at least one organic insulating layer.

7. a portion of the substrate is bent about a bending axis extending along a bending region; The display device according to claim 4 , wherein the at least one inorganic insulating layer includes an opening located in the bending region.

8. The insulating layer further includes an organic insulating layer located in the opening of the at least one inorganic insulating layer, The display device according to claim 7 , wherein the first layer contains the same material as the organic insulating layer.

9. 2. The display device of claim 1, further comprising an inorganic passivation layer on the second layer.

10. The display device according to claim 9 , wherein the inorganic passivation layer continuously covers the side and bottom surfaces of the second layer and the inner surface of the first layer.

11. A substrate; a display layer disposed on the substrate and including a plurality of pixels; a thin-film sealing layer disposed on the display layer and including at least one inorganic sealing layer and at least one organic sealing layer; a first through hole penetrating the substrate, the display layer, and the thin film sealing layer and positioned between two adjacent pixels among the plurality of pixels; a groove defined in a first layer and a second layer on the first layer, the groove being disposed to surround the first through hole; the groove includes a first hole or recess in the first layer and a second hole in the second layer; the second layer includes a pair of tips extending further toward the center of the second hole than an inner surface of the first layer that defines the first hole or the recess; At least one organic layer of the display layer is interrupted by the groove, Each of the plurality of pixels includes a light emitting diode including a pixel electrode, a counter electrode, and a light emitting layer between the pixel electrode and the counter electrode; the at least one organic layer is located between the pixel electrode and the counter electrode, the display layer includes at least one inorganic insulating layer between the substrate and the pixel electrodes; the first layer is located on the at least one inorganic insulating layer; The display device, wherein the first layer includes an organic insulator.

12. 12. The display device according to claim 11, wherein the at least one organic layer includes at least one layer selected from a hole transport layer, a hole injection layer, an electron injection layer, and an electron transport layer.

13. The display device according to claim 11 , wherein the second layer passes through the first layer and directly contacts an upper surface of the at least one inorganic insulating layer.

14. The display device according to claim 13 , wherein the second layer includes a metal or an inorganic insulator.

15. The display device of claim 11 , further comprising an inorganic passivation layer on the second layer.

16. The display device according to claim 15 , wherein the inorganic passivation layer continuously covers the side and bottom surfaces of the second layer and the inner surface of the first layer.

17. a portion of the substrate is bent about a bending axis extending along a bending region; The display device according to claim 11 , wherein the at least one inorganic insulating layer includes an opening located in the bending region.

18. The insulating layer further includes an organic insulating layer located in the opening of the at least one inorganic insulating layer, The display device of claim 17 , wherein the first layer includes the same material as the organic insulating layer.

19. a second groove surrounding the first through hole, The display device of claim 11, further comprising a partition between the groove and the second groove.

20. The partition wall includes a plurality of partition wall layers stacked together, 20. The display device according to claim 19, wherein a spacer layer containing a metal is interposed between adjacent ones of the plurality of partition layers.

21. the spacing layer includes a first layer and a second layer below the first layer; an edge of the first layer protrudes further outward than an edge of the second layer; 21. The display device according to claim 20, wherein the at least one organic layer is interrupted by an overhanging structure formed by an edge of the first layer and an edge of the second layer.

22. A display device according to any one of claims 1 to 21, and a component corresponding to the first through hole of the display device.

23. The electronic device of claim 22, wherein the component includes a camera or a sensor.

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