Array substrate and display device

Abstract

An array substrate and a display device are provided. The array substrate (100) includes a base substrate (110), a planar layer (160), an encapsulation layer (120), a first stop wall (130), and a plurality of first channel lines (140). The first stop wall (130) is located in a peripheral region (114) and includes a first stop wall portion (132) extending along a first direction. The plurality of first channel lines (140) are located in the peripheral region (114) and on a side of the encapsulation layer (120) away from the base substrate (110). The encapsulation layer (120) includes an organic encapsulation layer (124). The planar layer (160) includes a first edge (162) extending along a first direction, the first edge (162) being located between the first stop wall (132) and the display area (112), the orthogonal projection of the first edge (162) on the base substrate (110) being covered by the orthogonal projection of the organic encapsulation layer (124) on the base substrate (110), and the orthogonal projection of at least one of the plurality of first channel lines (140) on the base substrate (110) being located on the side of the first edge (162) away from the display area (112). The array substrate can reduce the width of the peripheral area, thereby realizing a narrow frame design for a display device employing the array substrate.

Description

[Technical field]

[0001] This application claims priority to Chinese patent application having application number 201911122242.7, filed on November 15, 2019, the entire contents of which are hereby incorporated by reference into this application.

[0002] The embodiments of the present disclosure relate to an array substrate and a display device. [Background technology]

[0003] With the development of touch technology, touch substrates with touch functions are integrated into smart electronic products such as mobile phones, tablet computers, etc. Meanwhile, with the rapid development of smart electronic products such as mobile phones, tablet computers, etc., smart electronic products such as mobile phones, tablet computers, etc. gradually adopt narrow frame and even frameless designs, that is, "all-screen" designs, thereby providing users with a better user experience. Summary of the Invention [Means for solving the problem]

[0004] The embodiments of the present disclosure provide an array substrate and a display device, in which at least some of the channel lines are disposed on the slanted surface of the encapsulation layer, so that the width of the peripheral region can be further reduced, thereby realizing a narrow frame or even a frameless design of the display device using the array substrate.

[0005] At least one embodiment of the present disclosure provides an array substrate, the array substrate including: a base substrate including a display region and a peripheral region located around the display region; a flat layer located on the base substrate; a sealing layer located on a side of the flat layer away from the base substrate; a first stop wall located in the peripheral region and including a first stop wall portion extending along a first direction; and a plurality of first channel lines located in the peripheral region and on one side of the sealing layer away from the base substrate, each of the plurality of first channel lines extending along the first direction, the channel lines are arranged along a second direction, the second direction being substantially perpendicular to the first direction, the sealing layer includes an organic sealing layer, the flat layer includes a first edge extending along the first direction, the first edge is located between the first stop wall and the display area, an orthogonal projection of the first edge on the base substrate is covered by an orthogonal projection of the organic sealing layer on the base substrate, and an orthogonal projection of at least one first channel line of the plurality of first channel lines on the base substrate is located on a side away from the display area of ​​the orthogonal projection of the first edge on the base substrate.

[0006] For example, in an array substrate according to one embodiment of the present disclosure, the organic sealing layer includes a second edge extending along the first direction, the second edge being located between the first edge and the first stop wall, and a positive projection of at least one first channel line of the plurality of first channel lines on the base substrate is located within a positive projection of the second edge on the base substrate.

[0007] For example, in an array substrate according to one embodiment of the present disclosure, the plurality of first channel lines include a plurality of first flat channel lines located on a side of the first edge portion away from the base substrate and a plurality of first inclined channel lines located on a side of the second edge portion away from the base substrate, and the spacing between two adjacent first inclined channel lines is greater than the spacing between two adjacent first flat channel lines.

[0008] For example, in an array substrate according to an embodiment of the present disclosure, the distance between two adjacent first inclined channel lines is 1.05 to 2 times the distance between two adjacent first flat channel lines.

[0009] For example, in an array substrate according to an embodiment of the present disclosure, the interval between two adjacent first inclined channel lines among the plurality of first inclined channel lines is 1.05 to 2 times the width of the first inclined channel lines.

[0010] For example, an array substrate according to an embodiment of the present disclosure further includes a pixel driving layer disposed on the base substrate, and an organic light emitting element disposed on a side of the planar layer away from the pixel driving layer, the planar layer being disposed on the side of the pixel driving layer away from the base substrate, and the encapsulation layer being disposed on the side of the organic light emitting element away from the base substrate.

[0011] For example, in an array substrate according to one embodiment of the present disclosure, one of the plurality of first channel lines that is farthest from the display area is part of a ground line, and the orthogonal projection of the one of the plurality of first channel lines that is farthest from the display area on the base substrate is located between the orthogonal projection of the organic sealing layer on the base substrate and the orthogonal projection of the first stop wall portion on the base substrate.

[0012] For example, an array substrate according to an embodiment of the present disclosure further includes: a plurality of touch driving electrodes located in the display area and located on a side of the encapsulation layer away from the base substrate, a plurality of touch sensing electrodes located in the display area and located on a side of the encapsulation layer away from the base substrate, a touch driving signal line connected to each of the touch driving electrodes and extending to the peripheral area, and a touch sensing signal line connected to each of the touch sensing electrodes and extending to the peripheral area, and at least some of the first channel lines are part of the touch driving signal line or the touch sensing signal line.

[0013] For example, in an array substrate according to one embodiment of the present disclosure, the first stop wall includes a second stop wall portion extending along the second direction, the array substrate further includes a plurality of second channel lines extending along the second direction, the flat layer includes a third edge portion extending along the second direction, the third edge portion is located between the second stop wall portion and the display area, an orthogonal projection of the third edge portion on the base substrate is covered by an orthogonal projection of the organic sealing layer on the base substrate, and an orthogonal projection of at least one second channel line among the plurality of second channel lines on the base substrate is located on a side of the third edge portion away from the display area.

[0014] For example, an array substrate according to an embodiment of the present disclosure further includes: a plurality of touch driving electrodes located in the display area and located on a side of the encapsulation layer away from the base substrate; a plurality of touch sensing electrodes located in the display area and located on a side of the encapsulation layer away from the base substrate; a touch driving signal line connected to each of the touch driving electrodes and extending to the peripheral area; and a touch sensing signal line connected to each of the touch sensing electrodes and extending to the peripheral area, wherein each of the plurality of touch sensing electrodes extends along the first direction, the plurality of touch sensing electrodes are arranged along the second direction, at least a part of the first channel lines of the plurality of first channel lines are a part of the touch sensing signal line, each of the plurality of touch driving electrodes extends along the second direction, the plurality of touch driving electrodes are arranged along the first direction, and at least a part of the second channel lines of the plurality of second channel lines are a part of the touch driving signal line.

[0015] For example, in an array substrate according to one embodiment of the present disclosure, the organic sealing layer includes a fourth edge extending along the second direction, the fourth edge being located between the third edge and the second stop wall, and a positive projection of at least one second channel line of the plurality of second channel lines on the base substrate is located within a positive projection of the fourth edge on the base substrate.

[0016] For example, in an array substrate according to one embodiment of the present disclosure, the plurality of second channel lines include a plurality of second flat channel lines located on a side of the third edge portion away from the base substrate and a plurality of second inclined channel lines located on a side of the fourth edge portion away from the base substrate, and the distance between two adjacent second inclined channel lines is greater than the distance between two adjacent second flat channel lines.

[0017] For example, in an array substrate according to an embodiment of the present disclosure, the distance between two adjacent second inclined channel lines is 1.05 to 2 times the distance between two adjacent second flat channel lines.

[0018] For example, in an array substrate according to an embodiment of the present disclosure, the distance between two adjacent second inclined channel lines among the plurality of second inclined channel lines is 1.05 to 2 times or more the width of the first inclined channel line.

[0019] For example, an array substrate according to one embodiment of the present disclosure further includes a second stop wall disposed on the base substrate and located in the peripheral region, the second stop wall being located between the first stop wall and the display region, the second stop wall including a third stop wall portion extending along the first direction, and an orthogonal projection of at least one first channel line among the plurality of first channel lines on the base substrate is located within an orthogonal projection of the third stop wall portion on the base substrate.

[0020] For example, an array substrate according to one embodiment of the present disclosure further includes a second stop wall disposed on the base substrate and located in the peripheral region, the second stop wall being located between the first stop wall and the display region, the second stop wall including a third stop wall portion extending along the first direction, and the orthogonal projections of the plurality of first channel lines on the base substrate are located on a side closer to the display region than the orthogonal projections of the third stop wall portion on the base substrate.

[0021] For example, in an array substrate according to an embodiment of the present disclosure, the organic light emitting device includes an anode, an emission layer, and a cathode, which are sequentially stacked in a direction away from the base substrate.

[0022] For example, in an array substrate according to one embodiment of the present disclosure, the sealing layer further includes a first inorganic sealing layer located on a side of the organic light-emitting element facing away from the base substrate, and a second inorganic sealing layer located on a side of the organic sealing layer facing away from the first inorganic sealing layer, the first inorganic sealing layer and the second inorganic sealing layer covering the first stop wall, the organic sealing layer being interposed between the first inorganic sealing layer and the second inorganic sealing layer, and the multiple first channel lines being located on a side of the second inorganic sealing layer facing away from the base substrate.

[0023] An embodiment of the present disclosure further provides an array substrate, the array substrate including: a base substrate including a display region and a peripheral region located around the display region; a pixel driving layer located on the base substrate; an organic light-emitting element located on the pixel driving layer; a sealing layer located on the organic light-emitting element, the sealing layer including a first inorganic sealing layer and an organic sealing layer sequentially arranged; and a plurality of first channels located in the peripheral region and on a side of the sealing layer away from the base substrate, each of the plurality of first channel lines extending along a first direction, the plurality of first channel lines being arranged along a second direction, the second direction being approximately perpendicular to the first direction; in the peripheral region, the first inorganic sealing layer includes a first inorganic sealing portion, an inorganic sealing connection portion, and a second inorganic sealing portion that are successively arranged in a direction from the display region to the peripheral region, and the inorganic sealing connection portion is a first inorganic sealing portion and a second inorganic sealing portion. and a first inorganic sealing portion and a second organic sealing portion disposed successively in a direction from the display region to the peripheral region, the organic sealing layer includes a first organic sealing portion and a second organic sealing portion disposed successively, an edge of the second organic sealing portion away from the display region is an edge of the organic sealing layer, an orthogonal projection of the first organic sealing portion on the base substrate overlaps with an orthogonal projection of the first inorganic sealing portion and the inorganic sealing connection portion on the base substrate, an orthogonal projection of the second organic sealing portion on the base substrate overlaps with an orthogonal projection of the second inorganic sealing portion on the base substrate, a distance d1 between the first inorganic sealing portion and the base substrate is greater than a distance d2 between the second inorganic sealing portion and the base substrate in a direction perpendicular to the base substrate, and an orthogonal projection of at least one first channel line of the plurality of first channel lines on the base substrate is located within an orthogonal projection of the second inorganic sealing portion on the base substrate.

[0024] For example, an array substrate according to one embodiment of the present disclosure further includes a first stop wall located in the peripheral region and including a first stop wall portion extending along the first direction, and a flat layer located on a side of the pixel driving layer away from the base substrate, the flat layer including a first edge portion extending along the first direction, the first edge portion being located between the first stop wall portion and the display region, an orthogonal projection of the first inorganic sealing portion and the inorganic sealing connection portion on the base substrate overlaps with an orthogonal projection of the first edge portion on the base substrate, and a difference between a distance d1 between the first inorganic sealing portion and the base substrate and a distance d2 between the second inorganic sealing portion and the base substrate is greater than or equal to a maximum thickness of a portion of the flat layer overlapping with the inorganic sealing connection portion in a direction perpendicular to the base substrate.

[0025] For example, in an array substrate according to one embodiment of the present disclosure, the flat layer includes a first sub-flat layer located on the side of the pixel driving layer away from the base substrate, and a second sub-flat layer located on the side of the first sub-flat layer away from the pixel driving layer, and the difference between the distance d1 between the first inorganic sealing portion and the base substrate and the distance d2 between the second inorganic sealing portion and the base substrate is greater than or equal to the sum of the maximum thickness of the portion of the first sub-flat layer that overlaps with the inorganic sealing connection portion in a direction perpendicular to the base substrate and the maximum thickness of the portion of the second sub-flat layer that overlaps with the inorganic sealing connection portion in a direction perpendicular to the base substrate.

[0026] For example, in an array substrate according to one embodiment of the present disclosure, the plurality of first channel lines include a plurality of first flat channel lines located on a side of the first organic sealing portion away from the base substrate and a plurality of first inclined channel lines located on a side of the second organic sealing portion away from the base substrate, and a distance between two adjacent first inclined channel lines is greater than a distance between two adjacent first flat channel lines.

[0027] For example, in an array substrate according to an embodiment of the present disclosure, the distance between two adjacent first inclined channel lines is 1.05-21.05 to 2 times the distance between two adjacent first flat channel lines.

[0028] For example, in an array substrate according to an embodiment of the present disclosure, the distance between two adjacent first inclined channel lines among the plurality of first inclined channel lines is 1.05 to 2 times the width of the first inclined channel lines.

[0029] An embodiment of the present disclosure further provides a display device including the array substrate according to any one of the above claims.

[0030] In order to more clearly describe the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments are briefly introduced below. Obviously, the drawings in the following description do not limit the present disclosure, but only relate to some embodiments of the present disclosure. [Brief description of the drawings]

[0031] [Figure 1] 2 is a schematic cross-sectional view of a peripheral region of an array substrate. FIG. [Diagram 2] 13 is a schematic cross-sectional view of a peripheral region of another array substrate. FIG. [Diagram 3] FIG. 2 is a schematic plan view of an array substrate according to an embodiment of the present disclosure. [Figure 4] 4 is a schematic cross-sectional view of the array substrate according to the embodiment of the present disclosure taken along the direction AA in FIG. 3. [Diagram 5] 4 is a schematic cross-sectional view of the array substrate according to the embodiment of the present disclosure taken along the direction BB in FIG. 3. [Figure 6] FIG. 11 is a schematic plan view of another array substrate according to an embodiment of the present disclosure. [Figure 7] 7 is a schematic cross-sectional view of the array substrate according to the embodiment of the present disclosure taken along the CC direction in FIG. 6. [Figure 8] 7 is a schematic cross-sectional view of the array substrate according to the embodiment of the present disclosure taken along the DD direction in FIG. 6. [Figure 9] FIG. 2 is a schematic plan view of an array substrate according to an embodiment of the present disclosure. [Figure 10] 10 is a schematic cross-sectional view of the array substrate according to the embodiment of the present disclosure taken along the EE direction in FIG. 9. [Figure 11] 10 is a schematic cross-sectional view of an array substrate according to an embodiment of the present disclosure taken along the FF direction in FIG. 9. [Figure 12] FIG. 11 is a schematic plan view of another array substrate according to an embodiment of the present disclosure. [Figure 13] 6 is a schematic cross-sectional view of an array substrate according to an embodiment of the present disclosure taken along the direction GG in FIG. 5. [Figure 14] 6 is a schematic cross-sectional view of an array substrate according to an embodiment of the present disclosure taken along the HH direction in FIG. 5. [Figure 15] FIG. 2 is a schematic cross-sectional view of an array substrate according to an embodiment of the present disclosure. [Figure 16] FIG. 1 is a schematic diagram of a structure of a display device according to an embodiment of the present disclosure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0032] In order to more clearly describe the objectives, technical solutions and advantages of the present disclosure, the following will clearly and completely describe the technical solutions of the embodiments of the present disclosure with reference to the drawings of the embodiments of the present disclosure. It is obvious that the described embodiments are only some embodiments of the present disclosure, and not all of the embodiments. Based on the described embodiments of the present disclosure, any other embodiments that a person skilled in the art can obtain without creative labor are all within the scope of protection of the present disclosure.

[0033] Unless otherwise defined, technical or scientific terms used in this disclosure have the ordinary meanings that would be understood by a person skilled in the art. The terms "first", "second" and similar terms used in this disclosure do not denote any order, quantity or importance, but are merely used to distinguish different components. Similar terms such as "comprise" and "include" mean that the element or thing appearing before the term includes the element or thing listed after the term and their equivalents, but do not exclude other elements or things. Similar terms such as "connected" and "connected to each other" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect.

[0034] At present, in order to realize the thin design of a display device (e.g., an organic light emitting diode display device), the display panel and the touch structure can be integrated together. Therefore, FMLOC (Flexible Multiple Layer On Cell) touch technology is born by chance, which directly fabricates various electrode layers and various wirings of the touch structure on the encapsulation layer, thereby integrating the touch structure into the display panel. As a result, the display device adopting FMLOC touch technology can not only realize the thin design of the display device, but also realize flexible display and flexible touch.

[0035] In a display device adopting FMLOC touch technology, a signal channel line connected to a touch driving electrode (Tx) and a touch sensing electrode (Rx) is provided in the peripheral region of the display device. FIG. 1 is a schematic cross-sectional view of the peripheral region of an array substrate. As shown in FIG. 1, a sealing layer 20 is provided on a base substrate 10, the sealing layer 20 includes two inorganic sealing layers 21 and an organic sealing layer 22 interposed between the two inorganic sealing layers 21, and a signal wiring 30 connected to the touch driving electrode (Tx) or the touch sensing electrode (Rx) is formed on the surface of the sealing layer 20 away from the base substrate 10. The organic sealing layer 22 undergoes a leveling process, so that a sloped portion with a gradually decreasing thickness is formed in the peripheral region of the array substrate. In order to avoid the influence of the slope on the signal wiring 30, the signal wiring 30 is generally formed at a position corresponding to the flat portion of the organic sealing layer 22, which results in a large width in the peripheral region, which is disadvantageous in realizing a narrow frame design of the display device.

[0036] FIG. 2 is a schematic cross-sectional view of another array substrate. As shown in FIG. 2, the array substrate includes a base substrate 10, a sealing layer 20, a signal wiring 30, a pixel driving layer 40, a flat layer 50, and an organic light-emitting element 60. The base substrate 10 includes a display area 11 and a peripheral area 12 around the display area 11. The pixel driving layer 40 is located on the base substrate 10 and is located in the display area 11 of the base substrate 10. The flat layer 50 is located on the side of the pixel driving layer 40 that is away from the base substrate 10. The organic light-emitting element 60 is located on the side of the flat layer 50 that is away from the pixel driving layer 40. The sealing layer 20 is located on the side of the organic light-emitting element 60 that is away from the base substrate 10. The sealing layer 20 includes two inorganic sealing layers 21 and an organic sealing layer 22 interposed between the two inorganic sealing layers 21. A signal wiring 30 connected to a touch driving electrode (Tx) or a touch sensing electrode (Rx) is formed on the surface of the sealing layer 20 that is away from the base substrate 10. Since the flat layer 50 is not installed over the entire layer, the distance between the encapsulation layer 20 and the base substrate 10 on the flat layer 50 decreases abruptly at the edge of the flat layer 50, and the organic encapsulation layer 22 undergoes a leveling process, resulting in a sloped portion with a gradually decreasing thickness in the peripheral region of the array substrate. In order to avoid the influence of the sloped portion on the signal wiring 30, the signal wiring 30 is generally formed at a position corresponding to the flat portion of the organic encapsulation layer 22, i.e., on the flat layer. As a result, the width of the frame of the display device using the array substrate includes the width of the sloped portion and the width of the flat portion, and the width of the flat portion is large, which is disadvantageous in realizing a narrow frame design.

[0037] Meanwhile, with the development of narrow frame designs, the frame of a display device becomes narrower and narrower, and the space for the signal wiring becomes smaller and smaller, so that merely reducing the line width and line spacing is not enough to meet the wiring needs of a display device adopting a narrow frame design.

[0038] In contrast, an embodiment of the present disclosure provides an array substrate and a display device. The array substrate includes a base substrate, a pixel driving layer, a planar layer, an organic light emitting element, a sealing layer, a first stop wall, and a plurality of first channel lines. The base substrate includes a display region and a peripheral region located around the display region. The pixel driving layer is located on the base substrate. The planar layer is located on a side of the pixel driving layer away from the base substrate. The organic light emitting element is located on a side of the planar layer away from the pixel driving layer, and the sealing layer is located on a side of the organic light emitting element away from the base substrate. The first stop wall is located in the peripheral region and includes a first stop wall portion extending along a first direction. The plurality of first channel lines are located in the peripheral region and on a side of the sealing layer away from the base substrate, each of the plurality of first channel lines extends along the first direction, and the plurality of first channel lines are arranged along a second direction, and the second direction is substantially perpendicular to the first direction. The sealing layer includes an organic sealing layer, and the flat layer includes a first edge extending along a first direction, the first edge being located between the first stop wall and the display area, the orthogonal projection of the first edge on the base substrate being covered by the orthogonal projection of the organic sealing layer on the base substrate, and the orthogonal projection of at least one of the plurality of first channel lines on the base substrate being located on a side of the first edge away from the display area, whereby the array substrate can reduce the width of the peripheral area by locating at least one of the plurality of first channel lines on a side of the first edge away from the display area (i.e., on the inclined portion of the sealing layer), thereby realizing a narrow frame or frameless design of a display device using the array substrate.

[0039] Hereinafter, an array substrate and a display device according to an embodiment of the present disclosure will be described in detail with reference to the drawings.

[0040] FIG. 3 is a schematic plan view of an array substrate according to an embodiment of the present disclosure, and FIG. 4 is a schematic cross-sectional view of the array substrate according to an embodiment of the present disclosure along the AA direction in FIG. 3. As shown in FIG. 3 and FIG. 4, the array substrate 100 includes a base substrate 110, a pixel driving layer 150, a flat layer 160, an organic light emitting element 170, a sealing layer 120, a first stop wall 130, and a plurality of first channel lines 140. The base substrate 110 includes a display area 112 and a peripheral area 114 located around the display area 112. The pixel driving layer 150 is located on the base substrate 110. The flat layer 160 is located on the side of the pixel driving layer 150 that is away from the base substrate 110. The organic light emitting element 170 is located on the side of the flat layer 160 that is away from the pixel driving layer 150. The sealing layer 120 is located on the side of the organic light emitting element 170 that is away from the base substrate 110. The first stop wall 130 is located in the peripheral region 114 and includes a first stop wall portion 132 extending along a first direction. The first channel lines 140 are located in the peripheral region 114 and on a side of the encapsulation layer 120 away from the base substrate 110, each of the first channel lines 140 extending along a first direction X, and the first channel lines 140 are arranged along a second direction Y, the second direction being substantially perpendicular to the first direction. It should be noted that the pixel driving layer may include a pixel circuit for driving a corresponding organic light emitting element so that the corresponding organic light emitting element emits light. The second direction being perpendicular to the first direction includes a case where the included angle between the first direction and the second direction is equal to 90 degrees and a case where the included angle between the first direction and the second direction is greater than 80 degrees and less than 100 degrees.

[0041] As shown in Figures 3 and 4, the sealing layer 120 may be directly disposed on the base substrate 110 in some regions, and other film layer structures, such as the pixel driving layer 150, the flat layer 160, the organic light emitting element 170, etc., may be disposed between the sealing layer 120 and the base substrate 110. The sealing layer 120 seals the pixel driving layer 150 and the organic light emitting element 170 formed on the base substrate 110, and can prevent the water and oxygen in the external environment from corroding the pixel driving layer 150 and the organic light emitting element 170. The first stop wall 130 is disposed on the base substrate 110 and located in the peripheral region 114. The first stop wall 130 can prevent the fluid material in the sealing layer 120 from flowing out of the first stop wall 130 during the formation of the sealing layer 120.

[0042] As shown in Figures 3 and 4, the sealing layer 120 includes an organic sealing layer 124, and the flat layer 160 includes a first edge 162 extending along a first direction X, the first edge 162 is located between the first stop wall 132 and the display area 112, the orthogonal projection of the first edge 162 on the base substrate 110 is covered by the orthogonal projection of the organic sealing layer 124 on the base substrate 110, and the orthogonal projection of at least one of the multiple first channel lines 140 on the base substrate 110 is located on the side of the first edge 162 away from the display area 112.

[0043] In the array substrate according to the embodiment of the present disclosure, since the flat layer 160 is not installed over the entire layer, the distance between the encapsulation layer 120 and the base substrate 110 decreases abruptly at the first edge 162, and the organic encapsulation layer 124 undergoes a leveling process, thereby forming a first inclined portion 1243 whose thickness gradually decreases in the peripheral region 114, and the portion of the organic encapsulation layer 124 above the first edge 162 is a first flat portion 1241. In the array substrate, at least one of the plurality of first channel lines 140 is disposed on the side of the first edge 162 away from the display area 112 (i.e., the first inclined portion 1243 or the side of the first inclined portion 1243 away from the display area 112), thereby reducing the number of first channel lines disposed on the first flat portion 1241, or not disposing the first channel lines on the first flat portion 1241, thereby reducing the width of the first flat portion 1241 and further reducing the width of the peripheral area 114. This helps the array substrate to realize a narrow frame or frameless design of the display device employing the array substrate.

[0044] For example, the display area may be a screen display area of ​​the array substrate, i.e., a light-emitting area. The peripheral area may be an area where the screen of the array substrate does not display, i.e., a non-light-emitting area. The peripheral area may surround the display area or may be located at a part of the periphery of the display area.

[0045] For example, the base substrate 110 may be a flexible base substrate 110, such as polyimide (PI), to form a flexible display device. The material of the flexible base substrate 110 is not limited to polyimide.

[0046] 3 and 4, the organic encapsulation layer 124 includes a second edge 1242 extending along the first direction, the second edge 1242 being located between the first edge 162 and the first stop wall 132, and the orthogonal projection of at least one of the plurality of first channel lines 140 on the base substrate 110 is located within the orthogonal projection of the second edge 1242 on the base substrate 110. Thus, the array substrate can reduce the number of first channel lines located on the first flat portion by locating at least one of the plurality of first channel lines on the second edge, or can not locate the first channel lines on the first flat portion, thereby reducing the width of the first flat portion and further reducing the width of the peripheral region.

[0047] In some examples, as shown in Figures 3 and 4, the first channel lines 140 include a plurality of first flat channel lines 142 located on the side of the first edge 162 away from the base substrate 110 and a plurality of first inclined channel lines 144 located on the side of the second edge 1242 away from the base substrate 110. Since general channel lines are all installed on the side of the first edge away from the base substrate, i.e., the first flat portion, the width of the first flat portion in the second direction Y is large. However, the first flat channel lines in the array substrate according to the embodiment of the present disclosure are formed on the side of the first edge away from the base substrate, and the first inclined channel lines are formed on the side of the second edge away from the base substrate, thereby reducing the number of first channel lines that the first flat portion needs to support, thereby reducing the width of the first flat portion in the second direction Y, and further reducing the width of the peripheral region of the array substrate in the second direction Y. As a result, a display device using the array substrate can have a narrow frame.

[0048] In some examples, as shown in Figures 3 and 4, the distance between two adjacent first inclined channel lines 144 is larger than the distance between two adjacent first flat channel lines 142. Since the first inclined channel lines are formed on a slope, when the performance of the exposure machine is limited during the process of forming the first flat channel lines and the first inclined channel lines by performing a patterning process on the conductive film layer, the first inclined channel lines on the slope are easily insufficiently exposed, and a short circuit occurs between the two adjacent first inclined channel lines. In the array substrate according to this example, the distance between the two adjacent first inclined channel lines is set to be larger than the distance between the two adjacent first flat channel lines, so that the array substrate can avoid various defects such as a short circuit caused by insufficient exposure of the first inclined channel lines.

[0049] In some examples, the distance between two adjacent first inclined channel lines 144 is 1.05 to 2 times the distance between two adjacent first flat channel lines 142. This allows the array substrate to avoid exposure problems caused by forming the first inclined channel lines on the first inclined portion, thereby avoiding various defects caused by the exposure problems.

[0050] For example, the interval between two adjacent first inclined channel lines 144 is 1.5 times that between two adjacent first flat channel lines 142. On the one hand, the array substrate can avoid the exposure problem caused by forming the first inclined channel lines on the first inclined portion, and on the other hand, the array substrate can further reduce the interval between two adjacent first inclined channel lines, so that more first inclined channel lines are placed on the first inclined portion.

[0051] Of course, the embodiments of the present disclosure include, but are not limited to, the interval between two adjacent first inclined channel lines may be equal to the interval between two adjacent first flat channel lines. For example, the interval between two adjacent first inclined channel lines may be equal to the interval between two adjacent first flat channel lines, but the line width of the first inclined channel line is larger than the line width of the first flat channel line. In some examples, in the plurality of first inclined channel lines 144, the interval between two adjacent first inclined channel lines 144 is 1.05 to 2 times the width of the first inclined channel line 144. Since the interval between two adjacent first inclined channel lines is set large, the array substrate can avoid exposure problems caused by forming the first inclined channel lines in the first inclined portion, thereby avoiding various defects caused by exposure problems.

[0052] In some examples, as shown in Figures 3 and 4, one of the first channel lines 140 that is farthest from the display area 112 is a part of a ground line, and the orthogonal projection of one of the first channel lines 140 that is farthest from the display area 112 on the base substrate 110 is located between the orthogonal projection of the organic sealing layer 124 on the base substrate 110 and the orthogonal projection of the first stop wall 132 on the base substrate 110. That is, one of the outermost first channel lines is a part of a ground line, and the ground line is disposed between the first stop wall and the organic sealing layer. In this way, the array substrate can further utilize the space between the first stop wall and the organic sealing layer to place a ground line, thereby further reducing the number of channel lines on the flat portion of the sealing layer and further reducing the width of the peripheral region of the array substrate.

[0053] In some examples, as shown in FIG. 3 and FIG. 4, the array substrate 100 further includes a plurality of touch driving electrodes 182, a plurality of touch sensing electrodes 184, a touch driving signal line 186, and a touch sensing signal line 188. The plurality of touch driving electrodes 182 and the plurality of touch sensing electrodes 184 are all located in the display area 112, and are located on the side of the encapsulation layer 120 away from the base substrate 110. The touch driving signal line 186 is connected to each touch driving electrode 182 and extends to the peripheral area 114. The touch sensing signal line 188 is connected to each touch sensing electrode 184 and extends to the peripheral area 114. For example, the touch driving signal line 186 and the touch sensing signal line 188 are all extended to the binding area 115 in the peripheral area 114 to bind with an external circuit, thereby realizing touch driving, data reception, and data processing. In the array substrate of this embodiment, at least some of the first channel lines 140 are part of the touch driving signal line 186 or the touch sensing signal line 188 .

[0054] For example, the touch driving electrode and the touch sensing electrode may be a transparent electrode or a metal mesh. The touch driving electrode and the touch sensing electrode may form a capacitor at an overlapping position, and when there is a touch by a finger, the coupling of the capacitor near the touch point is affected, thereby changing the capacitance of the capacitor near the touch point, and such a change in capacitance can be used to determine the touch position. The embodiments of the present disclosure are not limited thereto, and for example, the touch layer may include a mutual capacitance type touch structure or a self-capacitance type touch structure.

[0055] 5 is a schematic cross-sectional view of an array substrate according to an embodiment of the present disclosure taken along the BB direction in FIG. 3. As shown in FIG. 3, FIG. 4 and FIG. 5, the first stop wall 130 includes a second stop wall portion 134 extending along the second direction. For example, the second stop wall portion 134 is connected to the first stop wall portion 132, and the two first stop wall portions 132 and the two second stop wall portions 134 are smoothly connected to form a rectangular first stop wall 130 surrounding the display area 112.

[0056] In some examples, as shown in FIG. 5, the array substrate 100 further includes a plurality of second channel lines 190. Each of the second channel lines 190 extends along the second direction. The planar layer 160 includes a third edge 164 extending along the second direction, the third edge 164 being located between the second stop wall 134 and the display area 112, the orthogonal projection of the third edge 164 on the base substrate 110 being covered by the orthogonal projection of the organic sealing layer 124 on the base substrate 110, and the orthogonal projection of at least one of the plurality of second channel lines 190 on the base substrate 110 being located on the side of the third edge 164 away from the display area 112. Since the flat layer 160 is not disposed over the entire layer, the distance between the encapsulation layer 120 and the base substrate 110 decreases abruptly at the third edge 164, and the organic encapsulation layer 124 undergoes a leveling process, thereby forming a second inclined portion 1247 with a gradually decreasing thickness in the peripheral region 114, and the portion of the organic encapsulation layer 124 above the third edge 164 becomes a second flat portion 1246. The array substrate may reduce the number of second channel lines disposed on the second flat portion 1246 by disposing at least one second channel line 190 on the side of the third edge 164 away from the display region 112 (i.e., on the second inclined portion 1247 or the side of the second inclined portion 1247 away from the display region 112), or may not dispose the second channel line on the second flat portion 1246, thereby reducing the width of the second flat portion 1246 and further reducing the width of the peripheral region 114. This makes it possible for the array substrate to contribute to realizing a narrow frame or frameless design of a display device employing the array substrate.

[0057] In some examples, as shown in FIG. 3, FIG. 4 and FIG. 5, the array substrate 100 further includes a plurality of touch driving electrodes 182, a plurality of touch sensing electrodes 184, a touch driving signal line 186 and a touch sensing signal line 188. The plurality of touch driving electrodes 182 and the plurality of touch sensing electrodes 184 are all located in the display area 112 and are located on the side of the encapsulation layer 120 away from the base substrate 110. The touch driving signal line 186 is connected to each touch driving electrode 182 and extends to the peripheral area 114. The touch sensing signal line 188 is connected to each touch sensing electrode 184 and extends to the peripheral area 114. For example, the touch driving signal line 186 and the touch sensing signal line 188 are all extended to the binding area 115 in the peripheral area 114 to bind with an external circuit, thereby realizing touch driving, data reception and data processing. Each touch sensing electrode 184 extends along a first direction, the plurality of touch sensing electrodes 184 are arranged along the second direction, at least a portion of the plurality of first channel lines 140 are part of a touch sensing signal line 188, each of the plurality of touch driving electrodes 182 extends along a second direction, the plurality of touch driving electrodes 182 are arranged along the first direction, and at least a portion of the plurality of second channel lines 190 are part of a touch driving signal line 186.

[0058] 3, 4 and 5, the touch drive signal line 186 includes a first portion 1861 extending along the extension direction of the touch drive electrode 182, a second portion 1862 extending along the arrangement direction of the plurality of touch drive electrodes 182, and a third portion 1863 extending along the extension direction of the touch drive electrode 182. The first portion 1861 is connected to the touch drive electrode 182, the second portion 1862 is connected to the first portion 1861, and the third portion 1863 is connected to the second portion 1862. At that time, the extension direction of each touch drive electrode 182 is a first direction X, and the arrangement direction of the plurality of touch drive electrodes 182 is a second direction Y. Each first channel line 140 may be the third portion 1863 of the touch drive signal line 186.

[0059] For example, as shown in FIG. 3, FIG. 4 and FIG. 5, the touch sensing signal line 188 includes a fourth portion 1881 extending along the extension direction of the touch sensing electrode 184 and a fifth portion 1882 extending along the arrangement direction of the plurality of touch sensing electrodes 184. The fourth portion 1881 is connected to the touch sensing electrode 184, and the fifth portion 1882 is connected to the fourth portion 1881. At this time, the extension direction of each touch sensing electrode 184 is the second direction Y, and the arrangement direction of the plurality of touch sensing electrodes 184 is the first direction X. Each first channel line 140 may be the fifth portion 1882 of the touch sensing signal line 188. At this time, some of the first channel lines 140 are part of the touch driving signal line 186, and some of the first channel lines 140 are part of the touch sensing signal line 188.

[0060] In some examples, as shown in Figures 3, 4 and 5, the organic sealing layer 124 includes a fourth edge 1245 extending along the second direction, the fourth edge 1245 being located between the third edge 164 and the second stop wall 134, and a positive projection of at least one second channel line 190 of the multiple second channel lines 190 on the base substrate 110 is located within a positive projection of the fourth edge 1245 on the base substrate 110. The array substrate places at least one second channel line 190 among the plurality of second channel lines 190 within the orthogonal projection on the base substrate 110 of the fourth edge 1245 (i.e., places at least one second channel line 190 among the plurality of second channel lines 190 at the fourth edge 1245), thereby reducing the number of second channel lines placed on the second flat portion 1246, or placing no second channel lines on the second flat portion 1246, thereby reducing the width of the second flat portion 1246 and further reducing the width of the peripheral region 114. This helps the array substrate realize a narrow frame or frameless design of the display device employing the array substrate.

[0061] In some examples, as shown in Figures 3, 4 and 5, the second channel lines 190 include a plurality of second flat channel lines 192 located on the side of the third edge 164 away from the base substrate 110, and a plurality of second inclined channel lines 194 located on the side of the fourth edge 1245 away from the base substrate 110. Since general channel lines are all installed on the side of the third edge away from the base substrate, i.e., the second flat portion, the width of the second flat portion in the second direction X is large. In the array substrate according to the embodiment of the present disclosure, the second flat channel lines are formed on the side of the third edge away from the base substrate, and the second inclined channel lines are formed on the side of the fourth edge away from the base substrate, thereby reducing the number of second channel lines that the second flat portion needs to support, thereby reducing the width of the second flat portion in the first direction X, and further reducing the width of the peripheral region of the array substrate in the first direction X. As a result, the display device using the array substrate can have a narrow frame.

[0062] In some examples, as shown in Figures 3 and 5, the distance between two adjacent second inclined channel lines 194 is larger than the distance between two adjacent second flat channel lines 192. Since the second inclined channel lines are formed on a slope, when the performance of an exposure machine is limited during the process of forming the second flat channel lines and the second inclined channel lines by performing a patterning process on the conductive film layer, the second inclined channel lines on the slope are easily insufficiently exposed, and a short circuit occurs between the two adjacent second inclined channel lines. In the array substrate according to this example, the distance between the two adjacent second inclined channel lines is set to be larger than the distance between the two adjacent second flat channel lines, so that the array substrate can avoid various defects such as a short circuit caused by insufficient exposure of the second inclined channel lines.

[0063] In some examples, the distance between two adjacent second inclined channel lines 194 is 1.05 to 2 times the distance between two adjacent second flat channel lines 192. This allows the array substrate to avoid exposure problems caused by forming the second inclined channel lines on the second inclined portion, thereby avoiding various defects caused by the exposure problems.

[0064] For example, the interval between two adjacent second inclined channel lines 194 is 1.5 times the interval between two adjacent second flat channel lines 192. On the one hand, the array substrate can avoid the exposure problem caused by forming the second inclined channel lines on the second inclined portion, and on the other hand, the array substrate can also simultaneously reduce the interval between two adjacent second inclined channel lines, thereby placing more second inclined channel lines on the second inclined portion.

[0065] In some examples, the interval between two adjacent second inclined channel lines 194 in the plurality of second inclined channel lines 194 is 1.05 to 2 times the width of the second inclined channel line 194. Since the interval between two adjacent second inclined channel lines is set large, the array substrate can avoid exposure problems caused by forming the second inclined channel lines in the second inclined portion, thereby avoiding various defects caused by the exposure problems.

[0066] 3, 4, and 5, the organic light-emitting element 170 includes an anode 171, an emitting layer 172, and a cathode 173, which are sequentially stacked in a direction away from the base substrate 110. This allows the organic light-emitting element 170 to emit light through the emitting layer 172.

[0067] In some examples, as shown in Figures 3, 4 and 5, the encapsulation layer 120 further includes a first inorganic encapsulation layer 122 and a second inorganic encapsulation layer 126. The first inorganic encapsulation layer 122 is disposed on the side of the organic light emitting element 170 that is away from the base substrate 110, and the second inorganic encapsulation layer 126 is disposed on the side of the first inorganic encapsulation layer 122 that is away from the base substrate 110. The organic encapsulation layer 124 is interposed between the first inorganic encapsulation layer 122 and the second inorganic encapsulation layer 124, and the plurality of first channel lines 140 are located on the side of the second inorganic encapsulation layer 126 that is away from the base substrate 110. Thus, the encapsulation layer has a strong ability to isolate water and oxygen, and can effectively prevent the water and oxygen in the external environment from corroding the device encapsulated in the encapsulation layer.

[0068] For example, the material of the first inorganic sealing layer and the second inorganic sealing layer can be selected from one or more of silicon oxide, silicon nitride, and silicon oxynitride. Since the inorganic material has high density, it is possible to prevent water, oxygen, etc. from penetrating and affecting the performance of the light-emitting device. The material of the organic sealing layer can include a polymer resin, such as polyimide, polyacrylic ester, etc., and the organic sealing layer has functions such as planarization and stress relaxation.

[0069] 3 and 4, in the peripheral region 114, the first inorganic sealing layer 122 includes a first inorganic sealing portion 1221, a second inorganic sealing portion 1222, and an inorganic sealing connection portion 1223 that connects the first inorganic sealing portion 1221 and the second inorganic sealing portion 1222, and the orthogonal projection of the first inorganic sealing portion 1221 on the base substrate 110 overlaps with the orthogonal projection of the first edge portion 162 on the base substrate 110. That is, the first inorganic sealing portion 1221 is disposed on the first edge portion 162, and the second inorganic sealing portion 1222 is disposed on the base substrate 110 and is located on the side of the first edge portion 162 that is away from the display region 112.

[0070] The organic sealing layer 124 includes a first organic sealing portion 1248 and a second organic sealing portion 1249 which are arranged successively, and the edge of the second organic sealing portion 1249 away from the display area 112 is the edge of the organic sealing layer 124, and the orthogonal projection of the first organic sealing portion 1248 on the base substrate 110 overlaps with the orthogonal projection of the first inorganic sealing portion 1221 and the inorganic sealing connection portion 1223 on the base substrate 110, and the orthogonal projection of the second organic sealing portion 1249 on the base substrate 110 overlaps with the orthogonal projection of the second inorganic sealing portion 1222 on the base substrate 110. In a direction perpendicular to the base substrate 110, the distance d1 between the first inorganic sealing portion 1221 and the base substrate 110 is greater than the distance d2 between the second inorganic sealing portion 1222 and the base substrate 110, and the value of the difference between d1 and d2 is greater than or equal to the thickness of the flat layer 160, and the orthogonal projection of at least one of the multiple first channel lines 140 on the base substrate 110 falls within the orthogonal projection of the second inorganic sealing portion 1222 on the base substrate 110.

[0071] In an array substrate according to an embodiment of the present disclosure, the distance d1 between the first inorganic sealing portion 1221 and the base substrate 110 is greater than the distance d2 between the second inorganic sealing portion 1222 and the base substrate 110, and the difference between d1 and d2 is greater than or equal to the thickness of the flat layer 160, so that the organic sealing layer 124 formed on the first inorganic sealing layer 122 forms an inclined portion whose thickness gradually decreases at the position of the second inorganic sealing portion 1222, i.e., the second organic sealing portion 1249 is an inclined portion, and the first organic sealing portion 1248 is a flat portion. The array substrate allows the orthogonal projection of at least one of the multiple first channel lines 140 on the base substrate 110 to be within the orthogonal projection of the second inorganic sealing portion 1222 on the base substrate 110 (i.e., the second organic sealing portion 1249 or the side of the second organic sealing portion 1249 away from the display region 112), thereby reducing the number of first channel lines provided on the flat portion of the organic sealing layer 124, or not providing the first channel lines on the flat portion of the organic sealing layer 124, thereby reducing the width of the flat portion of the organic sealing layer 124 and further reducing the width of the peripheral region 114. This helps the array substrate to realize a narrow frame or frameless design of a display device employing the array substrate.

[0072] In some examples, as shown in Figures 3, 4 and 5, the array substrate 100 further includes a second stop wall 230. The second stop wall 230 is disposed on the base substrate 110 and located in the peripheral region 114. The second stop wall 230 is located between the first stop wall 130 and the display region 112, and the second stop wall 230 includes a third stop wall portion 232 extending along a first direction, and the orthogonal projection of the first channel lines 140 on the base substrate 110 is located on a side of the third stop wall portion 232 closer to the display region 112 than the orthogonal projection on the base substrate 110. It should be understood that the embodiments of the present disclosure include, but are not limited to, this.

[0073] In some examples, as shown in Figures 3, 4 and 5, the second edge 1242 of the organic sealing layer 124 can be located on the side of the second stop wall 230 closer to the display area 112. Then, the orthogonal projection of the first channel line 140 located on the second edge on the base substrate 110 is located on the side of the orthogonal projection of the third stop wall 232 on the base substrate 110 closer to the display area 112. It should be understood that the present disclosure includes, but is not limited to, that the second edge of the organic sealing layer may extend beyond the second stop wall and be located between the second stop wall and the first stop wall. Then, the first channel line located on the second edge may be located on the second stop wall or between the second stop wall and the first stop wall.

[0074] In some examples, the pixel driving layer may include devices such as thin film transistors. For example, the pixel driving layer may include an active layer located on the base substrate, a first gate insulating layer located on the active layer's side away from the base substrate, a gate located on the first gate insulating layer's side away from the active layer, a second gate insulating layer located on the gate's side away from the first gate insulating layer, and a source and a drain located on the second gate insulating layer's side away from the gate. The active layer may include a source region, a channel region, and a drain region. The orthogonal projection of the gate on the base substrate at least partially overlaps with the orthogonal projection of the channel region on the base substrate. The source contacts the source region of the active layer, and the drain contacts the drain region of the active layer. Of course, the specific pixel structure in the pixel driving layer may refer to conventional designs, such as pixel driving structures such as 2T1C structure, 7T1C, etc.

[0075] For example, the base substrate may be a glass substrate, a polyimide substrate, or other substrate.

[0076] For example, the material of the first gate insulating layer and the second gate insulating layer can be selected from at least one of silicon oxide, silicon nitride, and silicon oxynitride.

[0077] For example, the first inorganic sealing layer 122 and the second inorganic sealing layer 126 cover the first stop wall 130 and the second stop wall 230, thereby further enhancing the sealing layer's ability to strongly isolate water and oxygen. FIG. 6 is a schematic plan view of another array substrate according to an embodiment of the present disclosure. FIG. 7 is a schematic cross-sectional view of the array substrate according to an embodiment of the present disclosure along the CC direction in FIG. 6. As shown in FIG. 6 and FIG. 7, the array substrate 100 further includes a second stop wall 230. The second stop wall 230 is disposed on the base substrate 110 and located in the peripheral region 114. The second stop wall 230 is located between the first stop wall 130 and the display area 112, and the second stop wall 230 includes a third stop wall portion 232 extending along a first direction, and an orthogonal projection of at least one of the plurality of first channel lines 140 on the base substrate 110 is located within an orthogonal projection of the third stop wall portion 232 on the base substrate 110. That is, the at least one of the plurality of first channel lines 140 is disposed on the third stop wall portion 232. At that time, by disposing the at least one of the plurality of first channel lines on the third stop wall portion, the array substrate can further reduce the width of the peripheral region, thereby further reducing the frame width of the display device adopting the array substrate, thereby realizing a narrow frame design.

[0078] It should be noted that when at least one of the multiple first channel lines is disposed on a third stop wall portion, the first inorganic sealing layer and the second inorganic sealing layer of the sealing layer may be disposed on a side of the third stop wall portion away from the base substrate, and the first channel line disposed on the third stop wall may be disposed on a side of the second inorganic sealing layer away from the base substrate.

[0079] In some examples, as shown in FIG. 7, the plurality of first channel lines 140 includes a plurality of first stop wall channel lines 146 located on the third stop wall portion 232. That is, the orthogonal projection of the plurality of first stop wall channel lines 146 on the base substrate 110 enters the orthogonal projection of the third stop wall portion 232 on the base substrate 110. As a result, in a general design, the plurality of first channel lines are all disposed on the first flat portion, and the width of the first flat portion in the second direction Y is large. However, in the array substrate according to the embodiment of the present disclosure, the first flat channel lines are formed on the first flat portion, the first inclined channel lines are formed on the first inclined portion, and the first stop wall channel lines are formed on the third stop wall portion, so that the number of first channel lines that the first flat portion needs to support is greatly reduced, and thus the width of the first flat portion in the second direction Y can be greatly reduced, and further the width of the peripheral region of the array substrate in the second direction Y can be reduced. As a result, a display device using the array substrate can have a narrow frame.

[0080] 8 is a schematic cross-sectional view of an array substrate according to an embodiment of the present disclosure taken along the DD direction in FIG. 6. As shown in FIG. 8, the second stop wall 230 includes a fourth stop wall portion 234 extending along the second direction, and the orthogonal projection of at least one second channel line 190 of the plurality of second channel lines 190 on the base substrate 110 is located within the orthogonal projection of the fourth stop wall portion 234 on the base substrate 110. That is, at least one second channel line 190 of the plurality of second channel lines 190 is disposed on the fourth stop wall portion 234. At that time, by disposing at least one second channel line 190 of the plurality of second channel lines 190 on the fourth stop wall portion, the array substrate can further reduce the width of the peripheral region, thereby further reducing the frame width of the display device adopting the array substrate, thereby realizing a narrow frame design.

[0081] In some examples, as shown in FIG. 8, the plurality of second channel lines 190 includes a plurality of second stop wall channel lines 196 located at the fourth stop wall portion 234. That is, the orthogonal projection of the plurality of second stop wall channel lines 196 on the base substrate 110 is located at the orthogonal projection of the fourth stop wall portion 234 on the base substrate 110. As a result, the second flat channel lines in the array substrate according to the embodiment of the present disclosure are formed on the second flat portion, the second inclined channel lines are formed on the second inclined portion, and the second stop wall channel lines are formed on the fourth stop wall portion, so that the number of second channel lines that the second flat portion needs to support can be greatly reduced, thereby reducing the width of the second flat portion in the first direction X, and further reducing the width of the peripheral region of the array substrate in the first direction X. As a result, the display device using the array substrate can have a narrow frame.

[0082] Another embodiment of the present disclosure further provides an array substrate. FIG. 9 is a schematic plan view of an array substrate according to an embodiment of the present disclosure. FIG. 10 is a schematic cross-sectional view of an array substrate according to an embodiment of the present disclosure along the EE direction in FIG. 9. As shown in FIGS. 9 and 10, the array substrate 100 includes a base substrate 110, an encapsulation layer 120, a first stop wall 130, and a plurality of first channel lines 140. The base substrate 110 includes a display area 112 and a peripheral area 114 located around the display area 112, and the array substrate 100 may be divided by the display area 112 and the peripheral area 114. The encapsulation layer 120 is disposed on the base substrate 110, for example, the encapsulation layer 120 may be disposed directly on the base substrate 110 in some areas, and other film layer structures, such as a light-emitting structure and a circuit structure for driving the light-emitting structure so that the light-emitting structure emits light, may be disposed between the encapsulation layer 120 and the base substrate 110. The encapsulation layer 120 encapsulates the light-emitting structure and the circuit structure formed on the base substrate 110, thereby preventing the light-emitting structure and the circuit structure from being corroded by water and oxygen in the external environment. The first stop wall 130 is disposed on the base substrate 110 and is located in the peripheral region 114. The first stop wall 130 can prevent the fluid material in the encapsulation layer 120 from flowing out of the first stop wall 130 during the formation of the encapsulation layer 120. The plurality of first channel lines 140 are located in the peripheral region 114 and on the side of the encapsulation layer 120 away from the base substrate 110.

[0083] 9 and 10, each of the first channel lines 140 extends along a first direction X, the first channel lines 140 are arranged along a second direction Y, and the first stop wall 130 includes a first stop wall portion 132 extending along the first direction X. The encapsulation layer 120 includes an organic encapsulation layer 124, and an edge portion of the organic encapsulation layer 124 extending along the first direction X is located between the first stop wall portion 132 and the display area 112, and the edge portion includes a first flat portion 1241 and a first inclined portion 1243. At least a portion of the first channel lines 140 is located on the first inclined portion 1243. It should be noted that the gradient of the first flat portion is smaller than 1 / 50, and the gradient of the first inclined portion is larger than 1 / 50. At least some of the multiple first channel lines are located on the first inclined portion means that the orthogonal projection of the multiple first channel lines on the base substrate and the orthogonal projection of the first inclined portion on the base substrate at least locally overlap.

[0084] In the array substrate according to the embodiment of the present disclosure, the organic encapsulation layer undergoes a leveling process to form a first sloped portion with a gradually decreasing thickness in the peripheral region, and the array substrate has a plurality of first channel lines at least locally disposed on the first sloped portion, thereby reducing the width of the peripheral region, thereby reducing the frame width of the display device using the array substrate, thereby realizing a narrow frame design.

[0085] 9 and 10, the organic sealing layer 124 includes a second edge 1242 extending along the first direction, i.e., the first inclined portion 1243, the second edge 1242 being located between the first edge 162 and the first stop wall 132, and the orthogonal projection of at least one of the first channel lines 140 on the base substrate 110 is located within the orthogonal projection of the second edge 1242 on the base substrate 110. Thus, the array substrate can reduce the number of first channel lines located on the first flat portion by locating the first channel lines at least locally on the second edge, and can further reduce the width of the first flat portion by not locating the first channel lines on the first flat portion.

[0086] 9 and 10, the plurality of first channel lines 140 includes a plurality of first flat channel lines 142 located on the first flat portion 1241 and a plurality of first inclined channel lines 144 located on the first inclined portion 1243. That is, the orthogonal projection of the plurality of first flat channel lines 142 on the base substrate 110 falls within the orthogonal projection of the first flat portion 1241 on the base substrate 110, and the orthogonal projection of the plurality of first inclined channel lines 144 on the base substrate 110 falls within the orthogonal projection of the first inclined portion 1243 on the base substrate 110. As a result, in a general design, a plurality of first channel lines are all disposed on the first flat portion, resulting in a large width of the first flat portion in the second direction Y, but in the array substrate according to the embodiment of the present disclosure, the first flat channel lines are formed on the first flat portion, and the first inclined channel lines are formed on the first inclined portion, thereby greatly reducing the number of first channel lines that the first flat portion needs to support, thereby reducing the width of the first flat portion in the second direction Y, and further reducing the width of the peripheral region of the array substrate in the second direction Y. As a result, a display device using the array substrate can have a narrow frame.

[0087] In some examples, as shown in Figures 9 and 10, the distance between two adjacent first inclined channel lines 144 is larger than the distance between two adjacent first flat channel lines 142. Since the first inclined channel lines are formed on a slope, when the performance of the exposure machine is limited during the process of forming the first flat channel lines and the first inclined channel lines by performing a patterning process on the conductive film layer, the first inclined channel lines on the slope are easily insufficiently exposed, which causes a short circuit between the two adjacent first inclined channel lines. In the array substrate according to this example, the distance between the two adjacent first inclined channel lines is set to be larger than the distance between the two adjacent first flat channel lines, so that the array substrate can avoid various defects such as a short circuit caused by insufficient exposure of the first inclined channel lines.

[0088] In some examples, the distance between two adjacent first inclined channel lines 144 is 1.05 to 2 times the distance between two adjacent first flat channel lines 142. This allows the array substrate to avoid exposure problems caused by forming the first inclined channel lines on the first inclined portion, thereby avoiding various defects caused by the exposure problem.

[0089] 9 and 10, in some examples, the interval between two adjacent first inclined channel lines 144 is 1.5 times or more than the interval between two adjacent first flat channel lines 142. By setting the interval between two adjacent first inclined channel lines to be 1.5 times or more than the interval between two adjacent first flat channel lines, the array substrate can avoid the exposure problem caused by forming the first inclined channel lines on the first inclined portion, thereby avoiding various defects caused by the exposure problem.

[0090] For example, since the first inclined channel line is formed on the first inclined portion, in the process of forming the first flat channel line and the first inclined channel line by performing a patterning process on the conductive film layer, if the performance of the exposure machine is limited, the first inclined channel line is likely to be insufficiently exposed, which causes a short circuit between two adjacent first inclined channel lines. In the array substrate of this embodiment, the distance between two adjacent first inclined channel lines is set to be 1.5 times or more the distance between two adjacent first flat channel lines, so that the array substrate can avoid the short circuit caused by the insufficient exposure of the first inclined channel lines.

[0091] In some examples, the interval between two adjacent first inclined channel lines 144 in the plurality of first inclined channel lines 144 is 1.05 to 2 times the width of the first inclined channel line 144. Since the interval between two adjacent first inclined channel lines is set large, the array substrate can avoid exposure problems caused by forming the first inclined channel lines in the first inclined portion, thereby avoiding various defects caused by the exposure problems.

[0092] 9 and 10, in some examples, the interval between two adjacent first inclined channel lines 144 among the plurality of first inclined channel lines is 1.5 times the width (i.e., line width) of the first inclined channel line 144. By setting the interval between two adjacent first inclined channel lines to be large, the array substrate can avoid exposure problems caused by forming the first inclined channel lines at the first inclined portion, thereby avoiding various defects caused by exposure problems.

[0093] 9 and 10, the first inclined portion 1243 and the first flat portion 1241 are disposed continuously along the second direction Y, and the first inclined portion 1243 is located on a side of the first flat portion 1241 closer to the first stop wall portion 132. That is, the first inclined portion and the first flat portion are two continuous portions of a first edge portion extending along the first direction X, which is formed by leveling the organic sealing layer.

[0094] 9 and 10, among the plurality of first channel lines 140, the first channel line 140 furthest from the display area 112 is located at the edge of the first inclined portion 1243 away from the display area 112. That is, the entire upper portion of the first inclined portion 1243 is used to install the first channel line 140 (i.e., the first inclined channel line 144), which can significantly reduce the width of the peripheral area of ​​the array substrate, thereby helping to realize a narrow frame design.

[0095] In some examples, as shown in FIG. 10, the sealing layer 120 further includes a first inorganic sealing layer 122 and a second inorganic sealing layer 126. The first inorganic sealing layer 122 is disposed on the base substrate 110, and the second inorganic sealing layer 126 is disposed on the side of the first inorganic sealing layer 122 that is away from the base substrate 110. The organic sealing layer 124 is interposed between the first inorganic sealing layer 122 and the second inorganic sealing layer 124. This allows the sealing layer to have a strong ability to isolate water and oxygen, thereby effectively preventing water and oxygen in the external environment from corroding the device sealed in the sealing layer.

[0096] For example, the material of the first inorganic sealing layer and the second inorganic sealing layer may be selected from one or more of silicon oxide, silicon nitride, and silicon oxynitride, and the material of the organic sealing layer may be an organic resin.

[0097] In some examples, as shown in FIG. 9 and FIG. 10, the array substrate 100 further includes a plurality of touch driving electrodes 182, a plurality of touch sensing electrodes 184, a touch driving signal line 186, and a touch sensing signal line 188. The plurality of touch driving electrodes 182 and the plurality of touch sensing electrodes 184 are all located in the display area 112, and are located on the side of the encapsulation layer 120 away from the base substrate 110. The touch driving signal line 186 is connected to each touch driving electrode 182 and extends to the peripheral area 114. The touch sensing signal line 188 is connected to each touch sensing electrode 184 and extends to the peripheral area 114. For example, the touch driving signal line 186 and the touch sensing signal line 188 are all extended to the binding area 115 in the peripheral area 114 to bind with an external circuit, thereby realizing touch driving, data reception, and data processing. In the array substrate of this embodiment, each of the first channel lines 140 is a part of a touch driving signal line 186 or a touch sensing signal line 188 .

[0098] 9 and 10, the touch driving signal line 186 includes a first portion 1861 extending along the extension direction of the touch driving electrode 182, a second portion 1862 extending along the arrangement direction of the plurality of touch driving electrodes 182, and a third portion 1863 extending along the extension direction of the touch driving electrode 182. The first portion 1861 is connected to the touch driving electrode 182, the second portion 1862 is connected to the first portion 1861, and the third portion 1863 is connected to the second portion 1862. At that time, the extension direction of each touch driving electrode 182 is a first direction X, and the arrangement direction of the plurality of touch driving electrodes 182 is a second direction Y. Each first channel line 140 may be the third portion 1863 of the touch driving signal line 186.

[0099] For example, as shown in FIG. 9 and FIG. 10, the touch sensing signal line 188 includes a fourth portion 1881 extending along the extension direction of the touch sensing electrode 184 and a fifth portion 1882 extending along the arrangement direction of the plurality of touch sensing electrodes 184. The fourth portion 1881 is connected to the touch sensing electrode 184, and the fifth portion 1882 is connected to the fourth portion 1881. At this time, the extension direction of each touch sensing electrode 184 is the second direction Y, and the arrangement direction of the plurality of touch sensing electrodes 184 is the first direction X. Each first channel line 140 may be the fifth portion 1882 of the touch sensing signal line 188. At this time, some of the first channel lines 140 are part of the touch driving signal line 186, and some of the first channel lines 140 are part of the touch sensing signal line 188.

[0100] 11 is a schematic cross-sectional view of an array substrate according to an embodiment of the present disclosure taken along the FF direction in FIG. 9. As shown in FIG. 9, FIG. 10 and FIG. 11, the first stop wall 130 includes a second stop wall portion 134 extending along the second direction. For example, the second stop wall portion 134 is connected to the first stop wall portion 132, and the two first stop wall portions 132 and the two second stop wall portions 134 are smoothly connected to form a rectangular first stop wall 130 surrounding the display area 112.

[0101] In some examples, as shown in FIG. 11, the array substrate 100 further includes a plurality of second channel lines 190. Each of the second channel lines 190 extends along the second direction. The edge of the organic sealing layer 124 extending along the second direction is located between the second stop wall 134 and the display area 112. The edge includes a second flat portion 1246 and a second inclined portion 1247, and at least a portion of the second channel lines 190 is located on the second inclined portion 1247. That is, the orthogonal projection of the second channel lines 190 on the base substrate 110 at least locally overlaps with the orthogonal projection of the second inclined portion 1247 on the base substrate 110. In the array substrate according to this embodiment, the organic sealing layer undergoes a leveling process, thereby forming the second inclined portion in the peripheral region. Since the plurality of second channel lines are at least partially disposed on the second inclined portion, the array substrate can reduce the width of the peripheral region in the first direction, thereby reducing the frame width of the display device employing the array substrate, thereby realizing a narrow frame design.

[0102] 11 , the plurality of second channel lines 190 includes a plurality of second flat channel lines 192 located on the second flat portion 1246 and a plurality of second inclined channel lines 194 located on the second inclined portion 1247. That is, the orthogonal projection of the plurality of second flat channel lines 192 on the base substrate 110 falls within the orthogonal projection of the second flat portion 1246 on the base substrate 110, and the orthogonal projection of the plurality of second inclined channel lines 194 on the base substrate 110 falls within the orthogonal projection of the second inclined portion 1247 on the base substrate 110. As a result, in a general design, a plurality of second channel lines are all disposed on the second flat portion, and therefore the width of the second flat portion in the first direction X is large, but in the array substrate of the present embodiment, the second flat channel lines are formed on the second flat portion, and the second inclined channel lines are formed on the second inclined portion, thereby greatly reducing the number of second channel lines that the second flat portion needs to support, thereby reducing the width of the second flat portion in the first direction X, and further reducing the width of the peripheral region of the array substrate in the first direction, so that a display device using the array substrate can have a narrow frame.

[0103] 11, in some examples, the interval between two adjacent second inclined channel lines 194 is 1.5 times or more than the interval between two adjacent second flat channel lines 192. By setting the interval between two adjacent second inclined channel lines to be 1.5 times or more than the interval between two adjacent second flat channel lines, the array substrate can avoid the exposure problem caused by forming the second inclined channel lines on the second inclined portion, thereby avoiding various defects caused by the exposure problem.

[0104] For example, since the second inclined channel line is formed in the second inclined portion, in the process of forming the second flat channel line and the second inclined channel line by performing a patterning process on the conductive film layer, if the performance of the exposure machine is limited, the second inclined channel line is likely to be insufficiently exposed, which causes a short circuit between two adjacent second inclined channel lines. In the array substrate of this embodiment, the distance between two adjacent second inclined channel lines is set to be 1.5 times or more the distance between two adjacent second flat channel lines, so that the array substrate can avoid the short circuit caused by the insufficient exposure of the second inclined channel lines.

[0105] In some examples, as shown in FIG. 11, the spacing between two adjacent second inclined channel lines 194 among the plurality of second inclined channel lines is 1.5 times the width (i.e., line width) of the second inclined channel lines 194.

[0106] 11 , the second inclined portion 1247 and the second flat portion 1246 are disposed continuously along the first direction X, and the second inclined portion 1247 is located on a side of the second flat portion 1246 closer to the second stop wall portion 134. That is, the second inclined portion and the second flat portion are two continuous portions of a second edge portion extending along the second direction X formed by leveling the organic sealing layer.

[0107] 11, the second channel line 190 farthest from the display area 112 among the plurality of second channel lines 190 is located at the edge of the second inclined portion 1247 away from the display area 112. That is, any position above the second inclined portion 1247 is used to locate the second channel line 190 (i.e., the second inclined channel line 194), which can greatly reduce the width of the peripheral area of ​​the array substrate, thereby helping to realize a narrow frame design.

[0108] 9 and 11, the touch drive signal line 186 includes a first portion 1861 extending along the extension direction of the touch drive electrode 182, a second portion 1862 extending along the arrangement direction of the plurality of touch drive electrodes 182, and a third portion 1863 extending along the extension direction of the touch drive electrode 182. The first portion 1861 is connected to the touch drive electrode 182, the second portion 1862 is connected to the first portion 1861, and the third portion 1863 is connected to the second portion 1862. At that time, the extension direction of each touch drive electrode 182 is the first direction X, and the arrangement direction of the plurality of touch drive electrodes 182 is the second direction Y. The second channel line 190 may be the second portion 1862 of the touch drive signal line 186.

[0109] It should be noted that in the array substrate shown in the above-mentioned Figures 9, 10 and 11, the extension direction of the first channel line (i.e., the first direction) is the extension direction of the touch driving signal line, and the extension direction of the second channel line (i.e., the second direction) is the extension direction of the touch sensing signal line. However, the above-mentioned Figures 9, 10 and 11 are merely examples of the array substrate according to the embodiment of the present disclosure, and the embodiment of the present disclosure is not limited thereto, and the extension direction of the first channel line (i.e., the first direction) may be the extension direction of the touch sensing signal line, and the extension direction of the second channel line (i.e., the second direction) may be the extension direction of the touch driving signal line. In addition, the array substrate may include only the first channel line, and may not have the second channel line.

[0110] 10 and 11, the array substrate 100 further includes an organic light emitting element 170. The organic light emitting element 170 is located in the display area 112, and is located between the encapsulation layer 120 and the base substrate 110. At this time, the encapsulation layer 120 encapsulates the organic light emitting element 170, thereby preventing water and oxygen in the external environment from corroding the organic light emitting element 170.

[0111] For example, the organic light emitting device 170 can include an anode 171, an organic light emitting layer 172, and a cathode 173. It should be understood that the organic light emitting device 170 can further include other functional layers, such as a hole transport layer, an electron transport layer, etc., which are not described in the embodiments of the present disclosure here.

[0112] FIG. 12 is a schematic plan view of another array substrate according to an embodiment of the present disclosure. FIG. 13 is a schematic cross-sectional view of the array substrate according to an embodiment of the present disclosure along the GG direction in FIG. 12. As shown in FIGS. 12 and 13, the array substrate 100 further includes a second stop wall 230. The second stop wall 230 is disposed on the base substrate 110 and located in the peripheral region 114. The second stop wall 230 is disposed between the first stop wall 130 and the display region 112, and the second stop wall 230 includes a third stop wall portion 232 extending along the first direction, and the orthogonal projection of the plurality of first channel lines 140 on the base substrate 110 at least locally overlaps with the orthogonal projection of the third stop wall portion 232 on the base substrate 110. That is, at least a portion of the plurality of first channel lines 140 is disposed on the third stop wall portion 232. At this time, by installing a plurality of first channel lines, at least a portion of which is located on the third stop wall portion, the array substrate can further reduce the width of the peripheral region, thereby further reducing the frame width of the display device employing the array substrate, thereby realizing a narrow frame design.

[0113] It should be noted that when a plurality of first channel lines are at least locally disposed on the third stop wall portion, the first inorganic sealing layer and the second inorganic sealing layer of the sealing layer may be disposed on the side of the third stop wall portion away from the base substrate, and the first channel lines disposed on the third stop wall may be disposed on the side of the second inorganic sealing layer away from the base substrate.

[0114] In some examples, as shown in FIG. 13, the plurality of first channel lines 140 includes a plurality of first stop wall channel lines 146 located at the third stop wall portion 232. That is, the orthogonal projection of the plurality of first stop wall channel lines 146 on the base substrate 110 is located at the orthogonal projection of the third stop wall portion 232 on the base substrate 110. As a result, in a general design, the plurality of first channel lines are all installed on the first flat portion, and the width of the first flat portion in the second direction Y is large. However, in the array substrate according to the embodiment of the present disclosure, the first flat channel lines are formed on the first flat portion, the first inclined channel lines are formed on the first inclined portion, and the first stop wall channel lines are formed on the third stop wall portion, thereby greatly reducing the number of first channel lines that the first flat portion needs to support, thereby greatly reducing the width of the first flat portion in the second direction Y, and further reducing the width of the peripheral region of the array substrate in the second direction Y. As a result, a display device using the array substrate can have a narrow frame.

[0115] 14 is a schematic cross-sectional view of an array substrate according to an embodiment of the present disclosure taken along the HH direction in FIG. 12. As shown in FIG. 14, the second stop wall 230 includes a fourth stop wall portion 234 extending along the second direction, and the orthogonal projection of the second channel lines 190 on the base substrate 110 at least locally overlaps with the orthogonal projection of the fourth stop wall portion 234 on the base substrate 110. That is, the second channel lines 190 are at least partially disposed on the fourth stop wall portion 234. At that time, by disposing the second channel lines at least locally on the fourth stop wall portion, the array substrate can further reduce the width of the peripheral region, thereby further reducing the frame width of the display device adopting the array substrate, thereby realizing a narrow frame design.

[0116] In some examples, as shown in FIG. 14, the plurality of second channel lines 190 includes a plurality of second stop wall channel lines 196 located at the fourth stop wall portion 234. That is, the orthogonal projection of the plurality of second stop wall channel lines 196 on the base substrate 110 enters the orthogonal projection of the fourth stop wall portion 234 on the base substrate 110. As a result, the second flat channel lines in the array substrate according to the embodiment of the present disclosure are formed on the second flat portion, the second inclined channel lines are formed on the second inclined portion, and the second stop wall channel lines are formed on the fourth stop wall portion, so that the number of second channel lines that the second flat portion needs to support can be greatly reduced, thereby reducing the width of the second flat portion in the first direction X, and further reducing the width of the peripheral region of the array substrate in the first direction X. As a result, the display device using the array substrate can have a narrow frame.

[0117] An embodiment of the present disclosure further provides an array substrate. FIG. 15 is a schematic cross-sectional view of an array substrate according to an embodiment of the present disclosure. As shown in FIG. 15, the array substrate includes a base substrate 110, a pixel driving layer 150, an organic light emitting element 170, an encapsulation layer 120, and a plurality of first channel lines 140. The base substrate 110 includes a display area 112 and a peripheral area 114 located around the display area 112. The pixel driving layer 150 is located on the base substrate 110. The organic light emitting element 170 is located on a side of the planar layer 160 that is away from the pixel driving layer 150. The encapsulation layer 120 is located on a side of the organic light emitting element 170 that is away from the base substrate 110. The plurality of first channel lines 140 are located in the peripheral region 114 and on the side of the encapsulation layer 120 away from the base substrate 110, and each of the first channel lines 140 extends along a first direction X, and the plurality of first channel lines 140 are arranged along a second direction Y, which is substantially perpendicular to the first direction X. It should be noted that the pixel driving layer may include a pixel circuit for driving the corresponding organic light emitting element to emit light. In addition, the second direction being perpendicular to the first direction includes a case where the included angle between the first direction and the second direction is equal to 90 degrees, and a case where the included angle between the first direction and the second direction is greater than 80 degrees and less than 100 degrees.

[0118] As shown in FIG. 15, the sealing layer 120 includes a first inorganic sealing layer 122 and an organic sealing layer 124 that are sequentially arranged. In the peripheral region 114, in the direction from the display region 112 to the peripheral region 114, the first inorganic sealing layer 122 includes a first inorganic sealing portion 1221, an inorganic sealing connection portion 1223, and a second inorganic sealing portion 1222 that are sequentially arranged. The inorganic sealing connection portion 1223 is for connecting the first inorganic sealing portion 1221 and the second inorganic sealing portion 1222. In the peripheral region 114, in the direction from the display region 112 to the peripheral region 114, the organic sealing layer 124 includes a first organic sealing portion 1241 and a second organic sealing portion 1242 that are sequentially arranged, and the edge of the second organic sealing portion 1242 that is away from the display region is the edge of the organic sealing layer 124. The orthogonal projection of the first organic sealing portion 1241 on the base substrate 110 overlaps with the orthogonal projection of the first inorganic sealing portion 1221 and the inorganic sealing connection portion 1223 on the base substrate 110. In the direction perpendicular to the base substrate 110, the distance d1 between the first inorganic sealing portion 1221 and the base substrate 110 is greater than the distance d2 between the second inorganic sealing portion 1222 and the base substrate 110, and the orthogonal projection of at least one of the multiple first channel lines 140 on the base substrate 110 falls within the orthogonal projection of the second inorganic sealing portion 1222 on the base substrate 110.

[0119] In the array substrate according to an embodiment of the present disclosure, since the distance d1 between the first inorganic sealing portion 1221 and the base substrate 110 is greater than the distance d2 between the second inorganic sealing portion 1222 and the base substrate 110, the distance between the first organic sealing portion 1241 and the base substrate 110 is abruptly reduced, and the organic sealing layer 124 undergoes a leveling process, so that the second organic sealing portion 1242 forms a first inclined portion 1243 in the peripheral region 114, the thickness of which gradually decreases. The array substrate has at least one of the first channel lines 140 projected on the base substrate 110 within the orthogonal projection of the second inorganic sealing portion 1222 on the base substrate 110 (i.e., the first inclined portion 1243 or the side of the first inclined portion 1243 away from the display region 112), thereby reducing the number of first channel lines provided on the relatively flat first organic sealing portion 1241, or not providing the first channel lines on the first organic sealing portion 1241, thereby reducing the width of the first organic sealing portion 1241 and further reducing the width of the peripheral region 114. This helps to realize a narrow frame or frameless design of the display device employing the array substrate.

[0120] 15, the array substrate further includes a first stop wall 130 and a planar layer 160. The planar layer 160 is located on a side of the pixel driving layer 150 away from the base substrate 110. The organic light emitting element 170 is located on a side of the planar layer 160 away from the pixel driving layer 150. The first stop wall 130 includes a first stop wall portion 132 located in the peripheral region 114 and extending along a first direction. The flat layer 160 includes a first edge 162 extending along a first direction, the first edge 162 being located between the first stop wall 132 and the display area 112, a perpendicular projection of the first inorganic sealing portion 1221 on the base substrate 110 overlaps with a perpendicular projection of the first edge 162 on the base substrate 110, and a difference between a distance d1 between the first inorganic sealing portion 1221 and the base substrate 110 and a distance d2 between the second inorganic sealing portion 1222 and the base substrate 110 is greater than or equal to the maximum thickness of a portion where the flat layer 160 overlaps with the inorganic sealing connection portion 1223 in a direction perpendicular to the base substrate 110.

[0121] In some examples, as shown in FIG. 15, the flat layer 160 includes a first sub-flat layer 1601 and a second sub-flat layer 1602. The first sub-flat layer 1601 is located on the side of the pixel driving layer 150 that is away from the base substrate 110. The second sub-flat layer 1602 is located on the side of the first sub-flat layer 1601 that is away from the pixel driving layer 150. The difference between the distance d1 between the first inorganic sealing portion 1221 and the base substrate 110 and the distance d2 between the second inorganic sealing portion 1222 and the base substrate 110 is equal to or greater than the sum of the maximum thickness of the portion where the first sub-flat layer 1601 overlaps with the inorganic sealing connection portion 1223 in a direction perpendicular to the base substrate 110 and the maximum thickness of the portion where the second sub-flat layer 1602 overlaps with the inorganic sealing connection portion 1223 in a direction perpendicular to the base substrate 110.

[0122] In some examples, as shown in FIG. 15, the plurality of first channel lines 140 include a plurality of first flat channel lines 142 located on the side of the first organic encapsulation portion 1241 away from the base substrate 110, and a plurality of first inclined channel lines 144 located on the side of the first organic encapsulation portion 1242 away from the base substrate 110. The distance between two adjacent first inclined channel lines 144 is larger than the distance between two adjacent first flat channel lines 142. Since the first inclined channel lines are formed on a slope, if the performance of the exposure machine is limited in the process of forming the first flat channel lines and the first inclined channel lines by performing a patterning process on the conductive film layer, the first inclined channel lines on the slope are likely to be insufficiently exposed, and a short circuit phenomenon occurs between the two adjacent first inclined channel lines. In the array substrate according to this example, the distance between the two adjacent first inclined channel lines is set to be larger than the distance between the two adjacent first flat channel lines, so that the array substrate can avoid various defects such as a short circuit caused by insufficient exposure of the first inclined channel lines.

[0123] In some examples, the distance between two adjacent first inclined channel lines 144 is 1.05 to 2 times the distance between two adjacent first flat channel lines 142. This allows the array substrate to avoid exposure problems caused by forming the first inclined channel lines on the first inclined portion, thereby avoiding various defects caused by the exposure problem.

[0124] For example, the interval between two adjacent first inclined channel lines 144 is 1.5 times that between two adjacent first flat channel lines 142. On the one hand, the array substrate can avoid the exposure problem caused by forming the first inclined channel lines on the first inclined portion, and on the other hand, the array substrate can further reduce the interval between two adjacent first inclined channel lines, thereby placing more first inclined channel lines on the first inclined portion.

[0125] It should be understood that embodiments of the present disclosure include, but are not limited to, that the spacing between two adjacent first inclined channel lines may be equal to the spacing between two adjacent first flat channel lines. For example, the spacing between two adjacent first inclined channel lines may be equal to the spacing between two adjacent first flat channel lines, but the line width of the first inclined channel lines is greater than the line width of the first flat channel lines.

[0126] In some examples, the interval between two adjacent first inclined channel lines 144 in the plurality of first inclined channel lines 144 is 1.05 to 2 times the width of the first inclined channel line 144. Since the interval between two adjacent first inclined channel lines is set large, the array substrate can avoid the exposure problem caused by forming the first inclined channel line in the first inclined portion, and thus various defects caused by the exposure problem can be avoided. In some examples, as shown in FIG. 15, the array substrate further includes a connection electrode 167 located between the first sub-flat layer 1601 and the second sub-flat layer 1602, the connection electrode 167 is connected to the drain of the thin film transistor of the pixel driving layer 150 by a through hole in the first sub-flat layer 1601, and the anode of the organic light emitting element 170 is connected to the connection electrode 167 by a through hole in the second sub-flat layer 1602.

[0127] An embodiment of the present disclosure further provides a display device. FIG. 16 is a structural schematic diagram of a display device according to an embodiment of the present disclosure. As shown in FIG. 16, the display device 300 includes the array substrate 100. Since the organic encapsulation layer forms a first inclined portion whose thickness gradually decreases in the peripheral region, the array substrate can reduce the number of first channel lines disposed in the first flat portion by disposing at least one first channel line of the first edge portion on the side away from the display region (i.e., the first inclined portion or the side away from the display region of the first inclined portion), and can further reduce the number of first channel lines disposed in the first flat portion by not disposing the first channel line on the first flat portion, thereby reducing the width of the first flat portion and further reducing the width of the peripheral region. As a result, the display device can have a narrow frame and can realize flexible display and flexible touch. For details, refer to the relevant description of the above embodiment, and the description will be omitted here.

[0128] In some examples, the display device may be an electronic product having a display function, such as a mobile phone, a notebook computer, a tablet computer, a navigation system, or an electronic photo frame.

[0129] The following points require further clarification: (1) The drawings of the embodiments of the present disclosure relate only to the structures of the embodiments of the present disclosure, and other structures may refer to conventional designs.

[0130] (2) Features in the same and different embodiments of the present disclosure may be combined with each other if there is no conflict.

[0131] The above is only a specific embodiment of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any modification or replacement that can be easily imagined by a person skilled in the art within the technical scope disclosed in the present disclosure should be covered within the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be subject to the protection scope of the claims.

Claims

1. A base substrate including a display area and a peripheral area located around the display area; a planarization layer located on the base substrate; a sealing layer located on a side of the flat layer away from the base substrate; a first stop wall located in the peripheral region and including a first stop wall portion extending along a first direction; a plurality of first channel lines located in the peripheral region and located on a side of the sealing layer away from the base substrate, each of the plurality of first channel lines extending along the first direction, the plurality of first channel lines arranged along a second direction, the second direction being substantially perpendicular to the first direction; Wherein, the sealing layer includes an organic sealing layer, the flat layer includes a first edge extending along the first direction, the first edge is located between the first stop wall and the display area, an orthogonal projection of the first edge on the base substrate is covered by an orthogonal projection of the organic sealing layer on the base substrate, and an orthogonal projection of at least one first channel line among the plurality of first channel lines on the base substrate is located on a side of the orthogonal projection of the first edge on the base substrate that is away from the display area, The organic sealing layer includes a second edge portion extending along the first direction, the second edge portion having: between the first edge and the first stop wall, and an orthogonal projection of at least one first channel line of the plurality of first channel lines on the base substrate is located within an orthogonal projection of the second edge on the base substrate; the first channel lines include a plurality of first flat channel lines located on a side of the first edge away from the base substrate, and a plurality of first inclined channel lines located on a side of the second edge away from the base substrate; An array substrate, wherein a distance between two adjacent said first inclined channel lines is greater than a distance between two adjacent said first flat channel lines.

2. 2. The array substrate of claim 1, wherein the distance between two adjacent first inclined channel lines is 1.05 to 2 times the distance between two adjacent first flat channel lines.

3. 2. The array substrate of claim 1, wherein the interval between two adjacent first inclined channel lines among the plurality of first inclined channel lines is 1.05 to 2 times the width of the first inclined channel line.

4. a pixel driving layer disposed on the base substrate; an organic light-emitting element located on a side of the planar layer away from the pixel driving layer, The array substrate according to any one of claims 1 to 3, wherein the planar layer is located on a side of the pixel driving layer away from the base substrate, and the sealing layer is located on a side of the organic light-emitting element away from the base substrate.

5. An array substrate according to any one of claims 1 to 4, wherein one of the plurality of first channel lines that is furthest from the display area is part of a ground line, and the orthogonal projection of the one of the plurality of first channel lines that is furthest from the display area on the base substrate is located between the orthogonal projection of the organic sealing layer on the base substrate and the orthogonal projection of the first stop wall portion on the base substrate.

6. a plurality of touch drive electrodes located in the display area and on a side of the sealing layer away from the base substrate; a plurality of touch sensing electrodes located in the display area and on a side of the sealing layer away from the base substrate; touch drive signal lines connected to each of the touch drive electrodes and extending to the peripheral region; a touch sensing signal line connected to each of the touch sensing electrodes and extending to the peripheral region; 6. The array substrate according to claim 1, wherein at least some of the first channel lines are part of the touch driving signal lines or part of the touch sensing signal lines.

7. the first stop wall includes a second stop wall portion extending along the second direction, and the array substrate further comprising a plurality of second channel lines extending along the second direction; 4. The array substrate of claim 1, wherein the flat layer includes a third edge extending along the second direction, the third edge being located between the second stop wall and the display area, a orthogonal projection of the third edge on the base substrate is covered by a orthogonal projection of the organic sealing layer on the base substrate, and a orthogonal projection of at least one second channel line of the plurality of second channel lines on the base substrate is located on a side of the third edge away from the display area.

8. a plurality of touch drive electrodes located in the display area and on a side of the sealing layer away from the base substrate; a plurality of touch sensing electrodes located in the display area and on a side of the sealing layer away from the base substrate; touch drive signal lines connected to each of the touch drive electrodes and extending to the peripheral region; a touch sensing signal line connected to each of the touch sensing electrodes and extending to the peripheral region; Each of the plurality of touch sensing electrodes extends along the first direction, the plurality of touch sensing electrodes are arranged along the second direction, and at least some of the first channel lines of the plurality of first channel lines are part of the touch sensing signal lines; 8. The array substrate of claim 7, wherein each of the plurality of touch drive electrodes extends along the second direction, the plurality of touch drive electrodes are arranged along the first direction, and at least some of the plurality of second channel lines are part of the touch drive signal lines.

9. The organic sealing layer includes a fourth edge portion extending along the second direction, the fourth edge portion having:

8. The array substrate of claim 7, wherein an orthogonal projection of at least one second channel line of the plurality of second channel lines on the base substrate is located between the third edge portion and the second stop wall portion and is located within an orthogonal projection of the fourth edge on the base substrate.

10. the second channel lines include a plurality of second flat channel lines located on a side of the third edge away from the base substrate, and a plurality of second inclined channel lines located on a side of the fourth edge away from the base substrate; 10. The array substrate as claimed in claim 9, wherein a distance between two adjacent second inclined channel lines is greater than a distance between two adjacent second flat channel lines.

11. 11. The array substrate of claim 10, wherein the distance between two adjacent second inclined channel lines is 1.05 to 2 times the distance between two adjacent second flat channel lines.

12. 11. The array substrate of claim 10, wherein a distance between two adjacent second inclined channel lines among the plurality of second inclined channel lines is 1.05 to 2 times or more the width of the first inclined channel line.

13. a second stop wall disposed on the base substrate and located in the peripheral region; the second stop wall is located between the first stop wall and the display area, and the second stop wall includes a third stop wall portion extending along the first direction; An array substrate according to any one of claims 1 to 12, wherein the orthogonal projection of at least one of the plurality of first channel lines on the base substrate is located within the orthogonal projection of the third stop wall portion on the base substrate.

14. a second stop wall disposed on the base substrate and located in the peripheral region; the second stop wall is located between the first stop wall and the display area, and the second stop wall includes a third stop wall portion extending along the first direction; An array substrate according to any one of claims 1 to 13, wherein the orthogonal projection of the plurality of first channel lines on the base substrate is located on a side closer to the display area than the orthogonal projection of the third stop wall portion on the base substrate.

15. The array substrate according to claim 4 , wherein the organic light emitting element includes an anode, a light emitting layer, and a cathode, which are sequentially stacked in a direction away from the base substrate.

16. The sealing layer is a first inorganic sealing layer located on a side of the flat layer away from the base substrate of an organic light-emitting element located on a side away from the pixel driving layer located on the base substrate; a second inorganic sealing layer located on a side of the organic sealing layer away from the first inorganic sealing layer, An array substrate according to any one of claims 1 to 15, wherein the first inorganic sealing layer and the second inorganic sealing layer cover the first stop wall, the organic sealing layer is interposed between the first inorganic sealing layer and the second inorganic sealing layer, and the plurality of first channel lines are located on the side of the second inorganic sealing layer away from the base substrate.

17. A display device comprising the array substrate according to any one of claims 1 to 16.

18. A base substrate including a display area and a peripheral area located around the display area; a pixel driving layer disposed on the base substrate; a planar layer located on a side of the pixel driving layer away from the base substrate; an organic light-emitting element located on the flat layer; a sealing layer located in the organic light emitting device, the sealing layer including a first inorganic sealing layer and an organic sealing layer disposed in sequence; a plurality of first channel lines located in the peripheral region and located on a side of the sealing layer away from the base substrate, each of the plurality of first channel lines extending along a first direction, the plurality of first channel lines being arranged along a second direction, the second direction being substantially perpendicular to the first direction; In the peripheral region, the first inorganic sealing layer includes a first inorganic sealing portion, an inorganic sealing connection portion, and a second inorganic sealing portion that are continuously provided in a direction from the display region to the peripheral region, and the inorganic sealing connection portion is configured to connect the first inorganic sealing portion and the second inorganic sealing portion; the first inorganic sealing portion is located on a surface of the flat layer away from the base substrate, the inorganic sealing connection portion is located on a side wall of the flat layer, and the second inorganic sealing portion is located outside a region where the flat layer is located; In the peripheral region, in a direction from the display region to the peripheral region, the organic sealing layer includes a first organic sealing portion and a second organic sealing portion that are continuously provided, an edge of the second organic sealing portion away from the display region is an edge of the organic sealing layer, an orthogonal projection of the first organic sealing portion on the base substrate overlaps with an orthogonal projection of the first inorganic sealing portion and the inorganic sealing connection portion on the base substrate, and an orthogonal projection of the second organic sealing portion on the base substrate overlaps with an orthogonal projection of the second inorganic sealing portion on the base substrate; In a direction perpendicular to the base substrate, a distance d1 between the first inorganic sealing portion and the base substrate is greater than a distance d2 between the second inorganic sealing portion and the base substrate, and an orthogonal projection of at least one of the first channel lines on the base substrate is located within an orthogonal projection of the second inorganic sealing portion on the base substrate; the plurality of first channel lines include a plurality of first flat channel lines located on a side of the first organic sealing portion away from the base substrate, and a plurality of first inclined channel lines located on a side of the second organic sealing portion away from the base substrate, An array substrate, wherein a distance between two adjacent said first inclined channel lines is greater than a distance between two adjacent said first flat channel lines.

19. a first stop wall located in the peripheral region and including a first stop wall portion extending along the first direction; Including, the flat layer includes a first edge portion extending along the first direction, the first edge portion being located between the first stop wall portion and the display area, and an orthogonal projection of the first inorganic sealing portion and the inorganic sealing connection portion on the base substrate overlaps with an orthogonal projection of the first edge portion on the base substrate; 19. The array substrate of claim 18, wherein the difference between the distance d1 between the first inorganic sealing portion and the base substrate and the distance d2 between the second inorganic sealing portion and the base substrate is greater than or equal to the maximum thickness of the portion of the flat layer that overlaps with the inorganic sealing connection portion in a direction perpendicular to the base substrate.

20. 20. The array substrate of claim 18, wherein the distance between two adjacent first inclined channel lines is 1.05 to 2 times the distance between two adjacent first flat channel lines.

21. 20. The array substrate of claim 18, wherein a distance between two adjacent first inclined channel lines among the plurality of first inclined channel lines is 1.05 to 2 times the width of the first inclined channel line.

22. A display device comprising the array substrate according to any one of claims 18 to 21.

Images