Photoelectric conversion device, imaging system, and mobile object

Abstract

To solve a problem in which: mixing of electrostatic noise in a signal generated by a photoelectric conversion device and damage to an internal circuit may reduce reliability of an operation of the photoelectric conversion device.SOLUTION: A photoelectric conversion device has a first semiconductor substrate including a plurality of photoelectric conversion units, and a second semiconductor substrate having a signal processing circuit that processes a signal based on a signal charge, which are laminated on top of the other. The photoelectric conversion device has a pad that is connected with an outside of the photoelectric conversion device, a first protection circuit that is provided on the first semiconductor substrate, and a second protection circuit that is provided on the second semiconductor substrate. At least one of the first protection circuit and the second protection circuit is provided on an outside of an area where the pad is provided in plan view.SELECTED DRAWING: Figure 4

Description

[Technical field]

[0001] The present invention relates to a photoelectric conversion device, an imaging system, and a moving object. [Background technology]

[0002] In the field of photoelectric conversion devices, miniaturization is progressing. With this progress in miniaturization, for example, in MOS transistors, the gate oxide film is becoming thinner. This has resulted in a decrease in the voltage at which dielectric breakdown occurs in MOS transistors. To reduce this dielectric breakdown in MOS transistors, a form in which a protection circuit is provided is known.

[0003] The larger the area of ​​the protection circuit, the more the load on the photoelectric conversion device caused by electrostatic discharge can be reduced. However, increasing the area occupied by the protection circuit puts pressure on the area of ​​other circuits (internal circuits provided in the photoelectric conversion device). Alternatively, attempting to secure the area for the internal circuits results in an increase in the chip area. According to the technology described in Patent Document 1, the protection circuit is arranged in an area that overlaps, in a plan view, with a pad to which a voltage is supplied from the outside. This is said to make it possible to increase the area of ​​the protection circuit while suppressing an increase in the chip area. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] JP 2012-033878 A Summary of the Invention [Problem to be solved by the invention]

[0005] If a protection circuit is provided in an area that overlaps with a pad in a plan view, the protection circuit may be subjected to pressure when wire bonding is performed on the pad. This may change the characteristics of the protection circuit (including electrostatic resistance). As a result, electrostatic noise may be mixed into the signal generated by the photoelectric conversion device, or the internal circuitry may be damaged, reducing the reliability of the operation of the photoelectric conversion device. [Means for solving the problem]

[0006] The present invention has been made in view of the above problems, and one aspect thereof is a photoelectric conversion device in which a first semiconductor substrate having a plurality of photoelectric conversion units each generating a signal charge upon receiving incident light, and a second semiconductor substrate having a signal processing circuit to which a signal based on the signal charges is input and which processes the signal, the photoelectric conversion device including a pad to which a power supply voltage is input from outside the photoelectric conversion device, and a second semiconductor substrate provided on the first semiconductor substrate, First and second diodes a first protection circuit provided on the second semiconductor substrate, Third and fourth diodes and a second protection circuit including: at least one of the first protection circuit and the second protection circuit is provided outside a region in which the pad is provided in a plan view; at least one of the first protection circuit and the second protection circuit is connected to the pad; and in a plan view, At least a part of the first diode and at least a part of the third diode overlap, or at least a part of the second diode and at least a part of the fourth diode overlap in a plan view. The photoelectric conversion device is characterized in that Effect of the Invention

[0007] According to the present invention, it is possible to reduce changes in the characteristics of the protection circuit caused by wire bonding, thereby suppressing deterioration in the accuracy of signals from a photoelectric conversion device and deterioration in operational reliability. [Brief description of the drawings]

[0008] [Figure 1] Equivalent circuit diagram according to the first embodiment [Diagram 2] Planar layout diagram according to the first embodiment [Diagram 3] Planar layout diagram according to the first embodiment [Figure 4]Schematic cross-sectional view of the first embodiment [Diagram 5] Schematic cross-sectional view of the first embodiment [Figure 6] Planar layout diagram according to the second embodiment [Figure 7] Planar layout diagram according to the second embodiment [Figure 8] Schematic cross-sectional view of the second embodiment [Figure 9] Schematic cross-sectional view of the second embodiment [Figure 10] Planar layout diagram according to the third embodiment [Figure 11] Schematic cross-sectional view of a third embodiment [Figure 12] Planar layout diagram according to the fourth embodiment [Figure 13] 4 is a schematic cross-sectional view according to a fourth embodiment. [Figure 14] Equivalent circuit diagram according to the fifth embodiment [Figure 15] Planar layout diagram according to the fifth embodiment [Figure 16] 5. Schematic cross-sectional view of the fifth embodiment. [Figure 17] 5. Schematic cross-sectional view of the fifth embodiment. [Figure 18] Equivalent circuit diagram according to the sixth embodiment [Figure 19] Planar layout diagram according to the sixth embodiment [Figure 20] 6. Cross-sectional view of the sixth embodiment. [Figure 21] Equivalent circuit diagram according to the seventh embodiment [Figure 22] Planar layout diagram according to the seventh embodiment [Figure 23] Planar layout diagram according to the seventh embodiment [Figure 24] 13 is a schematic cross-sectional view of a seventh embodiment. [Diagram 25] Schematic diagram of the eighth embodiment [Figure 26] Planar layout diagram according to the eighth embodiment [Figure 27] Planar layout diagram according to the eighth embodiment [Figure 28]8th embodiment [Figure 29] A diagram showing the configuration of a photoelectric conversion system. [Diagram 30] A diagram showing the configuration and operation of a moving object DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] Each embodiment will be described below with reference to the drawings.

[0010] In the following embodiments, an image pickup device will be mainly described as an example of a photoelectric conversion device. However, each embodiment is not limited to an image pickup device, and can be applied to other examples of photoelectric conversion devices. For example, a distance measuring device (a device for measuring distance using focus detection or TOF (Time Of Flight)) or a photometric device (a device for measuring the amount of incident light) may be used.

[0011] In addition, the conductivity types of the semiconductor regions and wells and the dopants to be implanted described in the following embodiments are merely examples and are not limited to the conductivity types and dopants described in the embodiments. The conductivity types and dopants described in the embodiments can be changed as appropriate, and the potentials of the semiconductor regions and wells are changed as appropriate in accordance with this change.

[0012] The conductivity types of the transistors described in the following embodiments are merely examples and are not limited to those described in the examples. The conductivity types described in the embodiments can be changed as appropriate, and the potentials of the gate, source, and drain of the transistors are changed as appropriate.

[0013] For example, in the case of a transistor operated as a switch, the low and high levels of the potential supplied to the gate may be reversed in accordance with the change in the conductivity type, as compared to the description in the embodiment. The conductivity type of the semiconductor region described in the embodiment described below is also merely an example, and is not limited to the conductivity type described in the embodiment. The conductivity type may be changed as appropriate from the conductivity type described in the embodiment, and the potential of the semiconductor region may be changed as appropriate in accordance with this change.

[0014] (First embodiment) Hereinafter, the structure of the photoelectric conversion device according to this embodiment will be described with reference to the drawings.

[0015] 1 is an equivalent circuit diagram of the electrostatic protection circuit according to this embodiment. Diodes 101 and 102 are connected to an internal circuit 103. The diodes 101 and 102 are connected to a pad 100.

[0016] The cathode of the diode 101 is connected to a power supply voltage node VDD. The anode of the diode 101 and the cathode of the diode 102 are connected to the pad 100 and the internal circuit 103. The anode of the diode 102 is connected to a power supply voltage node GND. The potential of the power supply voltage node GND is typically a ground potential. The potential of the power supply voltage node VDD is typically a positive potential.

[0017] The internal circuit 103 includes, for example, a driver circuit for amplifying a signal input from the outside. In this case, the internal circuit 103 may include circuits other than the driver circuit. In addition to the circuit elements shown in FIG. 1, the internal circuit 103 may include circuit elements such as resistor elements and capacitor elements.

[0018] 1, when a power supply voltage VDD is applied to the pad 100, no current flows through the diodes 101 and 102. On the other hand, when a positive voltage higher than the potential of the power supply voltage node VDD is applied to the pad 100 due to electrostatic discharge, a current flows to the power supply voltage node VDD via the diode 101. Also, when a negative voltage is applied to the pad 100, a current flows to the power supply voltage node GND via the diode 102. This operation makes it possible to suppress destruction of the internal circuit 103 even if electrostatic discharge is applied to the pad 100.

[0019] 2 and 3 are planar layout diagrams of the electrostatic protection circuit according to this embodiment. In FIG. 2 and FIG. 3, the same reference numerals are used for components having the same functions as those shown in FIG. 1. In the photoelectric conversion device of this embodiment, the first member 202 shown in FIG. 2(a) and the second member 203 shown in FIG. 2(b) are bonded together. Typically, each of the first member 202 and the second member 203 is a chip including a semiconductor substrate and at least one wiring layer. In FIG. 2, a part of the circuit element shown in FIG. 1 is distributed and arranged in the first member 202 and the second member 203. For example, the diode 101 shown in FIG. 1 is formed by combining the diode 101A and the diode 101B shown in FIG. 2. Similarly, the diode 102 shown in FIG. 1 is formed by combining the diode 102A and the diode 102B shown in FIG. 2. Regarding the pad 100, one of the members 202 and 203 may have an opening 100 shown in FIG. 2, and the pad 100 may be provided on the other member. Alternatively, the pad 100 may be provided on both the first member 202 and the second member 203. In this case, the pad 100 on one of the first member 202 and the second member 203 is connected to the outside. Then, the pad 100 on the other member may be connected to the pad 100 on the other member to be bonded to the other member through a via plug.

[0020] The first member 202 and the second member 203 are bonded together such that the pads 100 of the first member 202 and the second member 203 overlap in plan view. Note that a plurality of pads 100 are arranged in the photoelectric conversion device, and include pads (output pads) that output signals generated in the internal circuit 103 and pads (input pads) to which voltages for driving the internal circuit are input.

[0021] 2, a partial region of the internal circuit 103A, the diode 101A, the diode 102A, and the pad 100 are arranged in a straight line. From another perspective, it can be said that the diode 101A, the diode 102A, and the pad 100 are arranged in a straight line along a direction intersecting the direction connecting the diode 101A and the internal circuit 103A. A partial region of the internal circuit 103B, the diode 101B, the diode 102B, and the pad 100 are arranged in a straight line. From another perspective, it can be said that the diode 101B, the diode 102B, and the pad 100 are arranged in a straight line along a direction intersecting the direction connecting the diode 101B and the internal circuit 103B.

[0022] In the layout shown in FIG. 3, the diode 101A, the diode 102A, and the pad 100 are arranged in a direction intersecting the direction connecting the diode 101A and the internal circuit 103A.

[0023] 2 and 3, the pad 100, the diodes 101A and 102A, the internal circuit 103A, the VDD power supply wiring 104, and the GND wiring 105 are formed on the first member 202. The pad 100, the diodes 101B and 102B, and the internal circuit 103B are formed on the member 203. In this embodiment, the VDD power supply wiring 104 and the GND wiring 105 are disposed on the member 202. As another example, the VDD power supply wiring 104 and the GND wiring 105 may be disposed on the second member 203. Both the VDD power supply wiring 104 and the GND wiring 105 may be disposed on each of the first member 202 and the second member 203.

[0024] 2, the diode 101A is disposed closer to the pad 100 than the diode 102A. Moreover, the diode 101B is disposed closer to the pad 100 than the diode 102B. This order is not limited to the above, and the diode 102A may be disposed closer to the pad 100 than the diode 101A. Moreover, the diode 102A may be disposed closer to the pad 100 than the diode 101A.

[0025] 3, the diodes 101A, 101B, 102A, and 102B are arranged between the pads 100. The arrangement order of the diodes 101A and 101B and the arrangement order of the diodes 102A and 102B may be reversed from that shown in FIG.

[0026] FIG. 4 is a cross-sectional view of the photoelectric conversion device taken along dashed line AA' shown in FIGS.

[0027] In FIG. 4, the same reference numerals are used for members having the same functions as those shown in FIG. 1 to FIG. 3. The first member 202 has a first substrate 200 and a wiring layer. The second member 203 has a second substrate 201 and a wiring layer. The first substrate 200 and the second substrate 201 are, for example, silicon semiconductor substrates. Both the first substrate 200 and the second substrate 201 have circuit elements such as MOS transistors, resistors, capacitors, and photodiodes that constitute the internal circuit 103 formed thereon. The first member 202 and the second member 203 are electrically connected at a joint 204. The first member 202 also has wiring layers 205 and 206, and contact layers 208, 209, 210, 213, and 214 that include a plurality of contacts or vias. Similarly, the second member 203 has a wiring layer 207 and contact layers 211, 212, 214, and 215 that include a plurality of contacts or vias.

[0028] The bonding portion 204, the wiring layers 205-207, and the contact layers 208-215 are formed of a metal material such as copper, aluminum, tungsten, or titanium. An interlayer insulating film is formed between the wiring layers, and is formed of, for example, a silicon oxide film, a silicon nitride film, or a silicon carbide film, or a film that is a combination of a plurality of types of films. Here, the number of wiring layers included in the first member 202 and the second member 203 can be set arbitrarily. In this embodiment, the number of wiring layers in the first member 202 is two, and the number of wiring layers in the second member 203 is one.

[0029] In this embodiment, diodes 101A and 102A are formed on the first substrate 200, and diodes 101B and 102B are formed on the second substrate 201. Diode 101A is an element that constitutes a part of diode 101, and the anode region is shown in FIG. 4. Diode 102A is an element that constitutes a part of diode 102, and the anode region is shown in FIG. 4. Diode 101B is an element that constitutes a part of diode 101, and the cathode region is shown in FIG. 4. Diode 102B is an element that constitutes a part of diode 102, and the cathode region is shown in FIG. 4.

[0030] The anode region of the diode 101A is formed by providing a p-type semiconductor region 218 on an n-type semiconductor region 217 formed on the first substrate 200. The anode region of the diode 101B is formed by providing a p-type semiconductor region 223 on an n-type semiconductor region 222 formed on the second substrate 201. The diode 102A is formed by providing an n-type semiconductor region 220 on a p-type semiconductor region 219 formed on the first substrate 200. The diode 102B is formed by providing an n-type semiconductor region 225 on a p-type semiconductor region 224 formed on the second substrate 201. An element isolation region 216 is formed between the diode 101A and the diode 102A. An element isolation region 221 is formed between the diode 101B and the diode 102B.

[0031] The diode 101A is connected to the pad 100 via the wiring layers 205 and 206 and the contact layers 209 and 212. The diode 102A is connected to the pad 100 via the wiring layers 205 and 206 and the contact layers 208 and 212. The diode 101B is connected to the pad 100 via the wiring layers 206 and 207, the junction 204, and the contact layers 211, 213, and 214. The diode 102B is connected to the pad 100 via the wiring layers 206 and 207, the junction 204, and the contact layers 210, 213, and 214. The internal circuit 103A is connected to the pad 100 via the wiring layers 205 and 207 and the contact layers 210 and 213. In this embodiment, the gate 226 of the MOS transistor is connected to the contact layer 210. As another example, the contact layer 210 may be connected to the source / drain region of the MOS transistor, or to a circuit element other than the MOS transistor. In addition, the contact layer 210 may be connected to the internal circuit 103B.

[0032] Fig. 5 is a schematic cross-sectional view of a photoelectric conversion device taken along dashed line BB' in Fig. 2 and Fig. 3. As shown in Fig. 4, an anode region 218 of diode 101A is connected to pad 100 via wiring layers 205 and 207 and contact layers 209 and 212. A cathode region of diode 101A is formed by providing an n-type semiconductor region 308 on an n-type semiconductor region 217. A cathode region of diode 101A is connected to VDD power supply wiring 104 via contact layer 303. An anode region 223 of diode 101B is connected to pad 100 via wiring layers 206 and 207, a junction 204, and contact layers 210, 213, and 214.

[0033] In the cathode region 223 of the diode 101B, an n-type semiconductor region 311 is formed on the n-type semiconductor region 222. The cathode region 223 is connected to the VDD power supply wiring 104 via the wiring layers 301, 302, the contact layers 303 to 307, and the junction 30. In this embodiment, n-type semiconductor regions 309, 311 are formed in the cathode regions of the diode 101A and the diode 101B. As another example, the contact layers may be connected to the n-type semiconductor regions 217, 222 instead of the p-type semiconductor regions 218, 223. In this embodiment, the element isolation regions 310, 312 are formed to separate the n-type semiconductor region and the p-type semiconductor region. This is not limited to this example, and the element isolation regions 310, 312 may not be formed, and the n-type semiconductor region and the p-type semiconductor region may be joined to form an isolation region by a PN junction. Although not shown, the first substrate 200 and the second substrate 201 may have a structure such as a silicide structure.

[0034] In the photoelectric conversion device according to this embodiment, an electrostatic protection circuit is disposed on both of the two stacked semiconductor substrates. As a result, compared to disposing the electrostatic protection circuit on only one of the substrates, the photoelectric conversion device according to this embodiment has the advantageous effect of being able to increase the area of ​​the electrostatic protection circuit while suppressing an increase in the chip area. Furthermore, in this embodiment, the electrostatic protection circuit is disposed in an area that does not overlap with the pad 100 in a plan view. As a result, the electrostatic protection circuit can be made less susceptible to pressure generated when connecting a wire to the pad 100, and the electrostatic protection circuit can be made less likely to break down.

[0035] Furthermore, in this embodiment, a laminated structure of two semiconductor substrates has been described, but more semiconductor substrates may be laminated.

[0036] Second embodiment The photoelectric conversion device of this embodiment will be described below with reference to Figures 6 to 9. In the following description, differences from the first embodiment will be mainly described, and descriptions of parts that overlap with the first embodiment may be omitted.

[0037] The equivalent circuit of the photoelectric conversion device of this embodiment can be the same as that of Fig. 1 described in the first embodiment. Fig. 6 and Fig. 7 are planar layout diagrams of the electrostatic protection circuit of this embodiment. In Fig. 6 and Fig. 7, members having the same functions as the members described with reference to Figs. 1 to 5 are denoted by the same reference numerals as those in Figs. 1 to 5.

[0038] In this embodiment, the photoelectric conversion device is formed by bonding a member 402 shown in Fig. 6(a) and a member 403 shown in Fig. 6(b) together. As in the first embodiment, the member 402 in Fig. 6(A) and the member 403 in Fig. 6(B) are bonded together so that the pads 100 overlap in a plan view.

[0039] 6 and 7, the pad 100, the diode 101, the internal circuit 103A, the VDD power supply wiring 104, and the GND wiring 105 are formed on the member 402. The pad 100, the diode 102, and the internal circuit 103B are formed on the member 403. In this embodiment, the VDD power supply wiring 104 and the GND wiring 105 are disposed on the member 402, but they may be disposed on the member 403. In addition, both the VDD power supply wiring 104 and the GND wiring 105 may be disposed on each of the first member 402 and the second member 403.

[0040] In the planar layout diagram shown in Fig. 6, the diodes 101 and 102 are arranged between the pad 100 and the internal circuit 103A or the internal circuit 103B. In the planar layout diagram shown in Fig. 7, the diodes 101 and 102 are arranged between the pads 100.

[0041] FIG. 8 is a schematic cross-sectional view of the photoelectric conversion device taken along the dashed line CC' in FIG. 6 and FIG. 7. In FIG. 8, the same reference numerals as those in FIG. 1 to FIG. 7 are used for members having the same functions as those described with reference to FIG. 1 to FIG. 7. In the photoelectric conversion device of this embodiment, a first member 402 having a first substrate 400 and a second member 403 having a second substrate 401 are bonded together. The first member 402 and the second member 403 are electrically connected at a joint 404. The first member 402 has wiring layers 405 and 406, and contact layers 408, 409, 411, and 412. The second member 403 has a wiring layer 407 and contact layers 410 and 413.

[0042] In this embodiment, the diode 101 is formed on the first substrate 400, and the diode 102 is formed on the second substrate 401, but the arrangement positions may be reversed. In FIG. 8, the anode region of the diode 101 and the cathode region of the diode 102 are shown. In the anode region of the diode 101, a p-type semiconductor region 415 is formed on an upper portion of an n-type semiconductor region 414 formed on the first substrate 400. In the cathode region of the diode 102, an n-type semiconductor region 417 is formed on an upper portion of a p-type semiconductor region 416 formed on the second substrate 401.

[0043] Diode 101 is connected to pad 100 via wiring layers 405 and 406 and contact layers 408 and 411. Diode 102 is connected to pad 100 via wiring layers 407 and 406, junction 404, and contact layers 410, 412, and 413. Internal circuit 103A is connected to pad 100 via wiring layers 405 and 406 and contact layers 409 and 411.

[0044] Fig. 9 is a schematic cross-sectional view of the photoelectric conversion device taken along dashed line DD' in Fig. 6 and Fig. 7. The cathode region of diode 101 is formed by providing n-type semiconductor region 506 on n-type semiconductor region 414. This cathode region is connected to VDD power supply wiring 104 via contact layer 502. In addition, the anode region of diode 102 is formed by providing p-type semiconductor region 508 on p-type semiconductor region 416. In addition, this anode region is connected to GND wiring 105 via wiring layer 501, contact layers 503 to 505, and junction 500.

[0045] In the photoelectric conversion device of this embodiment, one of the diodes 101 and 102 is disposed on each of the stacked substrates. As a result, for example, the element isolation regions 216 and 221 shown in FIG. 4 can be omitted in this embodiment. As a result, the circuit area allocated to the element isolation regions 216 and 221 in the first embodiment can be allocated to the electrostatic protection circuit. As a result, the photoelectric conversion device of this embodiment has the effect of making it possible to increase the circuit area of ​​the electrostatic protection circuit.

[0046] Third embodiment The structure of the photoelectric conversion device according to the third embodiment will be described below with reference to Fig. 10 and Fig. 11. The equivalent circuit diagram of the photoelectric conversion device according to the third embodiment is the same as that in Fig. 1.

[0047] FIG. 10 is a planar layout diagram of the electrostatic protection circuit according to the third embodiment. The same components as those in FIG. 1 to FIG. 9 are denoted by the same reference numerals, and the description thereof will be omitted. In FIG. 10, the pad 100, the diodes 101A, 101B, 102A, and 102B, the internal circuits 103A and 103B, the VDD power supply wiring 104, and the GND wiring 105 are arranged in the same manner as in FIG. 2. As another example, the arrangement may be the same as that in FIG. 3. Also, as in FIG. 6 and FIG. 7, the diodes 101 and 102 may be arranged separately in the first member 602 and the second member 603. The diodes 101C and 102C are parts of the diodes 101 and 102, respectively. In this embodiment, the diodes 101C and 102C are arranged in the first member 602, and are formed in an area overlapping the pad 100 in a planar manner. 10, the diodes 101C and 102C are arranged in positions that overlap the pad 100 in a plan view, but the arrangement is not limited to this example. For example, each of the diodes 101C and 102C may be arranged so that a portion of each of the diodes 101C and 102C overlaps the pad 100 in a plan view, and the other portion of each of the diodes 101C and 102C does not overlap the pad 100.

[0048] Fig. 11 is a schematic cross-sectional view of a photoelectric conversion device taken along dashed line EE' shown in Fig. 10. In Fig. 11, the same components as those in Figs. 1 to 10 are designated by the same reference numerals, and description thereof will be omitted.

[0049] In the photoelectric conversion device of the third embodiment, a first member 602 having a first substrate 600 and a second member 603 having a second substrate 601 are bonded together. The first member 602 and the second member 603 are electrically connected at a joint 604. The first member 602 also has wiring layers 605 and 606 and contact layers 607 to 609. The first substrate 600 is formed with diodes 101A, 102A, 101C, and 102C, and the second substrate 601 is formed with diodes 101B and 102B. The structures and connections of the diodes 101A, 102A, 101B, and 102B are the same as those described in FIG. 4. In the anode region of the diode 101C, a p-type semiconductor region 611 is formed on the upper portion of an n-type semiconductor region 610 formed on the first substrate 600. In addition, in the cathode region of the diode 102C, an n-type semiconductor region 613 is formed on an upper portion of a p-type semiconductor region 612 formed on the first substrate 600. The diode 101C is connected to the pad 100 via wiring layers 605, 606 and contact layers 607, 609. The diode 102C is connected to the pad 100 via wiring layers 605, 606 and contact layers 608, 609. Here, the diodes 101C and 102C have an area that overlaps with the pad 100 in plan view. Although not shown, the cathode of the diode 101C is connected to a VDD power supply wiring, and the anode of the diode 102C is connected to a GND wiring.

[0050] In the structure of this embodiment, in addition to the structure of the first embodiment, diodes 101C and 102C are arranged in the region overlapping with the pad 100. This allows a further increase in the area of ​​the electrostatic protection circuit. In addition, the diodes 101C and 102C may change in characteristics and electrostatic resistance due to pressure when wire bonding is formed on the pad 100. However, in this embodiment, the diodes 101A, 101B, 102A, and 102B are provided at positions that do not overlap with the pad 100 in a plan view, and are less susceptible to the influence of wire bonding. These diodes 101A, 101B, 102A, and 102B can stably operate as an electrostatic protection circuit. As a result, in the photoelectric conversion device of this embodiment, the electrostatic protection circuit as a whole can stably operate.

[0051] (Fourth embodiment) The structure of the photoelectric conversion device according to the fourth embodiment will be described below with reference to FIGS.

[0052] The equivalent circuit diagram of the photoelectric conversion device according to the fourth embodiment is the same as that in FIG.

[0053] Fig. 12 is a planar layout diagram of the electrostatic protection circuit according to the fourth embodiment. The same components as those in Figs. 1 to 11 are given the same reference numerals and their explanations are omitted. In this embodiment, the pad 100 is formed on the second member 703. No opening for the pad portion 100 is formed on the first member 702.

[0054] The arrangement of the diodes 101A, 101B, 102A, and 102B, the internal circuits 103A and 103B, the VDD power supply wiring 104, and the GND wiring 105 is the same as in Fig. 2, but may be the same as in Fig. 3. Also, the diodes 101 and 102 may be arranged separately in a first member 702 and a second member 703 as in Figs. 6, 7, and 10.

[0055] FIG. 13 is a schematic cross-sectional view of the photoelectric conversion device taken along the dashed line FF' shown in FIG.

[0056] In Fig. 13, the same components as those in Figs. 1 to 12 are denoted by the same reference numerals, and description thereof will be omitted. In the photoelectric conversion device of the fourth embodiment, a first member 702 having a first substrate 700 and a second member 703 having a second substrate 701 are bonded together. The first member 702 and the second member 703 are electrically connected at bonding portions 704 and 705. The first member 702 has wiring layers 706 and 707 and contact layers 709 to 712, and the second member 703 has a wiring layer 708 and contact layers 713 to 715. The structures of the diodes 101A, 102A, 101B, and 102B are similar to those shown in Fig. 4.

[0057] The diode 101A is connected to the pad 100 via the wiring layers 706-708, the junction 704, and the contact layers 710-713. The diode 102A is connected to the pad 100 via the wiring layers 706-708, the junction 704, and the contact layers 709, 711-713. The diode 101B is connected to the pad 100 via the wiring layer 708 and the contact layer 715. The diode 102B is connected to the pad 100 via the wiring layer 708 and the contact layer 714. The diodes 101A and 102A are connected to the VDD power supply wiring in the same manner as in FIG. 5. Similarly, the diodes 102A and 102B are connected to the GND wiring.

[0058] In the structure of this embodiment, the pad 100 is formed on the second member 703. Then, the bonding portion 705 can be disposed in a region overlapping with the pad 100 in a plan view. With this structure, the bonding strength between the first member 702 and the second member 703 can be improved.

[0059] Fifth embodiment The structure of the photoelectric conversion device according to the fifth embodiment will be described below with reference to FIGS.

[0060] 14 is an equivalent circuit diagram of a photoelectric conversion device according to the fifth embodiment. The photoelectric conversion device according to this embodiment has pads 800 and 801, diodes 802 to 805, and internal circuits 806 and 807. A first electrostatic protection circuit including the pad 800, diodes 802 and 803, and internal circuit 806, and a second electrostatic protection circuit including the pad 801, diodes 804 and 805, and internal circuit 807 each have the same configuration as the circuit shown in FIG.

[0061] Fig. 15 is a planar layout diagram of an electrostatic protection circuit according to the fifth embodiment. The same components as those in Figs. 1 to 14 are given the same reference numerals, and description thereof will be omitted. In this embodiment, the photoelectric conversion device is formed by bonding together two members (chips) shown in Figs. 15(a) and 15(b). A pad 800, diodes 802 and 803, an internal circuit 806, a VDD power supply wiring 808, and a GND wiring 809 are formed on a first member 902. A pad 801, diodes 804 and 805, an internal circuit 807, a VDD power supply wiring 810, and a GND wiring 811 are formed on a second member 903.

[0062] FIG. 16 is a schematic cross-sectional view of the photoelectric conversion device taken along the dashed line GG' shown in FIG.

[0063] In FIG. 16, the same components as those in FIG. 1 to FIG. 15 are denoted by the same reference numerals, and the description thereof will be omitted. In the photoelectric conversion device of the fifth embodiment, a first member 902 having a first substrate 900 and a second member 903 having a second substrate 901 are bonded together. The first member 902 and the second member 903 are bonded together at a joint 904. The first member 902 has wiring layers 905 and 906 and contact layers 908 to 910. The second member 903 has a wiring layer 907 and contact layers 911 to 912. Diodes 802 and 803 are formed on the first substrate 900, and diodes 804 and 805 are formed on the second substrate 901. The structures of the diodes 802 and 803 are the same as those of the diodes 101A and 102A shown in FIG. 4. The structures of the diodes 804 and 805 are the same as those of the diodes 101B and 102B shown in FIG. 4. Here, diode 802 is connected to pad 800 via wiring layers 905 and 906 and contact layers 909 and 910. Diode 803 is connected to pad 800 via wiring layers 905 and 906 and contact layers 908 and 910. Diode 804 is connected to pad 801 via wiring layer 907 and contact layer 912. Diode 805 is connected to pad 801 via wiring layer 907 and contact layer 911.

[0064] Fig. 17 is a schematic cross-sectional view of a photoelectric conversion device taken along dashed line HH' shown in Fig. 15. The same components as those in Figs. 1 to 16 are given the same reference numerals and will not be described. Diode 802 has the same structure as diode 101 in Fig. 4, and is connected to VDD power supply wiring 808 via contact layer 1001. Diode 804 has the same structure as diode 102A in Fig. 4, and is connected to VDD power supply wiring 810 via contact layer 1002.

[0065] In the structure of this embodiment, a pad 800 and diodes 802 and 803 formed on the first member side are connected to an internal circuit 806. A pad 801 and diodes 804 and 805 formed on the second member side are connected to an internal circuit 807 formed on the second member. The diodes 802 and 803 and the diodes 804 and 805 have areas that overlap in a plan view. With this configuration, even when the first member and the second member each have the pads 800 and 801, it is possible to suppress an increase in the area of ​​the electrostatic protection circuit in a plan view. In addition, since the length of the wiring between the internal circuit and the pads can be reduced, the parasitic resistance between the internal circuit and the pads can be reduced. This makes it possible to transmit electrical signals input and output via the pads 800 and 801 to the internal circuit at high speed.

[0066] Sixth embodiment The structure of the photoelectric conversion device according to the fifth embodiment will be described below with reference to FIGS.

[0067] FIG. 18 is an equivalent circuit diagram of a photoelectric conversion device according to the sixth embodiment. The photoelectric conversion device according to this embodiment has a pad 1100, a diode 1101, an NMOS type GGMOS 1102 (GGMOS stands for Gate Grounded MOS), and an internal circuit 1103. The cathode of the diode 1101 is connected to a VDD power supply wiring, and the anode is connected to the pad 1100, the drain of the GGMOS 1102, and the internal circuit 1103. The GGMOS 1102 has the same structure as a normal MOS transistor, but the gate and source are shorted and connected to a node to which a GND potential is supplied. The drain is connected to the pad 1100, the anode of the diode 1101, and the internal circuit 1103. When a voltage is applied to the drain of the GGMOS 1101, the operation is suppressed up to a certain voltage (the current between the source and drain is negligibly small), and when the voltage exceeds a certain voltage, a current flows between the source and drain (called a snapback operation).

[0068] In the equivalent circuit of Fig. 1, when a negative voltage is applied to the pad 100 during normal operation of the photoelectric conversion device, a current flows to GND via the diode 102, which may cause an increase in current consumption or a malfunction. In the protection circuit of this embodiment, even when a negative voltage is applied to the pad 1100, the GGMOS 1102 is in an operation suppressed state, and the effect on the normal operation of the photoelectric conversion device can be minimized. The diode 1101 may be changed to a GGMOS instead of a diode. In addition to the circuit elements shown in Fig. 18, for example, circuit elements such as resistors and capacitors may be provided.

[0069] 19 is a planar layout diagram of the electrostatic protection circuit according to the fifth embodiment. The same components as those in FIGS. 1 to 18 are given the same reference numerals, and the description thereof will be omitted. Here, the diodes 1101A and 1101B provided in the first member 1202 and the second member 1203 are each a part of the diode 1101. Also, the GGMOSs 1102A and 1102B provided in the first member 1202 and the second member 1203 are each a part of the GGMOS 1102. Also, the photoelectric conversion device of this embodiment has internal circuits 1103A and 1103B, a VDD power supply wiring 1104, and a GND wiring 1105.

[0070] The planar layout diagram of Fig. 19 has a configuration in which the diode 102A in the planar layout diagram shown in Fig. 2 is replaced with a GGMOS 1102A, and the diode 102B is replaced with a GGMOS 1102B. However, the configuration is not limited to this, and the diode 102A in Figs. 3, 7, 10, 12, and 15 may be replaced with a GGMOS 1102A, and the diode 102B in Figs.

[0071] FIG. 20 is a schematic cross-sectional view of the photoelectric conversion device taken along dashed line II' in FIG.

[0072] In Fig. 20, the same components as those in Figs. 1 to 19 are denoted by the same reference numerals, and the description thereof will be omitted. In the photoelectric conversion device of the sixth embodiment, a first member 1202 having a first substrate 1200 and a second member 1203 having a second substrate 1201 are bonded together. The first member 1202 and the second member 1203 are electrically connected by bonding portions 1204 and 1205. The first member 1202 has wiring layers 1206 to 1208 and contact layers 1211 to 1218. The second member 1203 has wiring layers 1209 and 1210 and contact layers 1219 to 1224. A diode 1101A and a GGMOS 1102A are formed on the first substrate 1200, and a diode 1101B and a GGMOS 1102B are formed on the second substrate 1201. Here, the structure and connection relationship of the diodes 1101A and 1101B are the same as those of the diodes 101A and 101B shown in FIG. 4. The GGMOS 1102A includes a gate electrode 1231, a drain region 1226, and a source region 1227 provided on an upper portion of a p-type semiconductor region 1225. Here, the drain region 1226 is connected to the pad 1100 via wiring layers 1207 and 1208, and contact layers 1213 and 1217. The gate electrode 1231 and the source region 1227 are connected to the GND wiring 1105 via contact layers 1211 and 1212. The GGMOS 1102B includes a gate electrode 1232, a drain region 1229, and a source region 1230 formed on an upper portion of an n-type semiconductor region 1228. Here, the drain region 1229 is connected to the pad 1100 via wiring layers 1208 and 1209, a junction 1204, and contact layers 1218, 1219, and 1222. The gate electrode 1232 and the source region 1230 are connected to the GND wiring 1105 via the wiring layer 1210 , the junction 1205 , and the contact layers 1215 , 1216 , 1220 , 1223 , and 1224 .

[0073] In this embodiment, since the electrostatic protection circuit includes a GGMOS, even if a negative voltage is applied to the pad 1100, normal operation is not affected and electrostatic protection is possible. As in the first to fifth embodiments, an electrostatic protection circuit including a GGMOS can be disposed on both of the two bonded substrates. The photoelectric conversion device of this embodiment has an effect of being less susceptible to the effects of wire bonding on the pad 1100, since the electrostatic protection circuit is provided at a position that does not overlap with the pad 1100 in a plan view. As in the first embodiment, an effect of being able to increase the area of ​​the electrostatic protection circuit is also achieved.

[0074] Seventh embodiment The structure of the photoelectric conversion device according to the fifth embodiment will be described below with reference to FIGS.

[0075] FIG. 21 is an equivalent circuit diagram of a photoelectric conversion device according to the seventh embodiment. The photoelectric conversion device according to this embodiment has a power clamp MOS transistor 1300. This power clamp MOS transistor is an RC trigger type power clamp MOS transistor. The power clamp MOS transistor 1300 includes a series circuit (hereinafter, RC series circuit) of a resistive element 1301 and a capacitive element 1302 provided between a VDD power supply wiring and a GND wiring, and a CMOS inverter 1303 having an input terminal connected to a connection point between the resistive element and the capacitive element. The output terminal of the CMOS inverter 1303 is connected to a gate electrode of a MOS transistor 1304. In this embodiment, the CMOS inverter 1303 is described as a single stage, but multiple stages may be connected. Also, although an N-type MOS transistor is described as the MOS transistor 1304, a P-type MOS transistor may be used.

[0076] The operation of the power clamp MOS transistor 1300 will be described below. When an excessively large positive voltage is applied to the VDD power supply line due to electrostatic discharge, the potential of the input terminal of the CMOS inverter 1303 becomes lower than the potential of the VDD line within the time of the time constant R×C of the RC series circuit. As a result, the potential of the output terminal of the CMOS inverter 1303 becomes high level, and the MOS transistor 1304 becomes conductive (on state). On the other hand, during normal operation, the input terminal of the CMOS inverter 1303 becomes high level, and the output terminal becomes low level. This causes the MOS transistor 1304 to become non-conductive (off state). In this way, the power clamp MOS transistor 1300 is unlikely to affect normal operation. During electrostatic discharge, the MOS transistor 1304 becomes conductive, and the charge due to static electricity can be appropriately discharged.

[0077] 22 and 23 are planar layout diagrams of the electrostatic protection circuit according to this embodiment. The same components as those in FIG. 1 to FIG. 21 are given the same reference numerals, and the description thereof will be omitted. In this embodiment, the photoelectric conversion device is formed by bonding two members (chips) shown in (a) and (b) of FIG. 22 and FIG. 23, respectively. Reference numerals 1300A and 1300B denote power clamp MOS transistors, 1305 denotes a VDD power supply wiring, and 1306 denotes a GND wiring. Here, the power clamp MOS transistor 1300A, the VDD power supply wiring 1305, and the GND wiring 1306 are formed on the first member 1402. And the power clamp MOS transistor 1300B is formed on the second member 1403.

[0078] 22, the power clamp MOS transistors 1300A and 1300B are arranged in a region that overlaps in a planar manner with at least one of the VDD power supply wiring 1305 and the GND wiring 1306. In the planar layout diagram of FIG 23, the power clamp MOS transistors 1300A and 1300B are arranged so as not to overlap in a planar manner with the VDD power supply wiring 1305 and the GND wiring 1306.

[0079] FIG. 24 is a schematic cross-sectional view of the photoelectric conversion device taken along the dashed line JJ' shown in FIGS.

[0080] In FIG. 24, the same components as those in FIG. 1 to FIG. 23 are denoted by the same reference numerals, and the description thereof will be omitted. In the photoelectric conversion device of the sixth embodiment, a first member 1402 having a first substrate 1400 and a second member 1403 having a second substrate 1401 are bonded together. The first member 1402 and the second member 1403 are electrically connected by bonding portions 1404 and 1405. The first member 1402 has wiring layers 1406 to 1407 and contact layers 1410 to 1415. The second member 1403 has wiring layers 1408 and 1409 and contact layers 1416 to 1419. A power clamp MOS transistor 1300A is formed on the first substrate 1400, and a power clamp MOS transistor 1300B is formed on the second substrate 1401. For simplification, FIG. 24 mainly illustrates the MOS transistors 1304A and 1304B. The MOS transistor 1304A includes a gate electrode 1426, a drain region 1421, and a source region 1422, which are provided on an upper portion of a p-type semiconductor region 1420. The drain region 1421 is connected to the VDD power supply wiring 1305 via a contact layer 1411. The source region 1422 is connected to the GND wiring 1306 via a contact layer 1410.

[0081] The MOS transistor 1304B includes a gate electrode 1427, a drain region 1424, and a source region 1425 provided on an upper portion of a p-type semiconductor region 1423. The drain region 1424 is connected to the VDD power supply wiring 1305 via wiring layers 1409 and 1407, a junction 1404, and contact layers 1413, 1415, 1417, and 1419. The source region 1425 is connected to the GND wiring 1306 via wiring layers 1406 and 1408, a junction 1405, and contact layers 1412, 1414, 1416, and 1418.

[0082] In this embodiment, by disposing the power clamp MOS transistors on both of the two bonded members, the circuit area of ​​the power clamp element can be increased, thereby improving the protection capability of the electrostatic protection circuit.

[0083] Eighth embodiment In the following, as the electrostatic protection circuit according to this embodiment, an electrostatic protection circuit mounted on a solid-state imaging device having a stacked structure will be described. Note that, although an image sensor (CMOS image sensor) will be described as the solid-state imaging device of this embodiment, the configuration of the image sensor described in this embodiment is merely an example and is not limited thereto. For example, it can be applied to a distance measuring device that measures the distance to an object, a photometric device that measures the intensity of light from a subject, a line sensor used in a document reading section of a copier, etc.

[0084] It should be noted that this embodiment is not limited to a stacked structure of two components (chips). As another variation, a stacked structure of three or more components (chips) may be provided. In this embodiment, it is sufficient that the electrostatic protection circuit is disposed on two or more stacked components (chips). Furthermore, the number of components (chips) constituting the stacked structure does not necessarily have to match the number of semiconductor substrates on which the electrostatic protection circuit is formed.

[0085] First, the configuration of the image sensor of this embodiment will be described with reference to Fig. 25. Fig. 25 is a block diagram showing the concept of the image sensor of this embodiment, and differs from the actual layout. The image sensor of this embodiment is an image sensor having a stacked structure as described later, and the layout of each circuit will be described later with reference to Fig. 26. Here, first, the function of each circuit in the image sensor will be described with reference to Fig. 25.

[0086] The image sensor 1500 includes a sensor array 1502 in which sensors 1501, each of which includes a photoelectric conversion element (photoelectric conversion unit) that converts incident light into a signal charge and outputs an analog electrical signal, are arranged across multiple rows and multiple columns. The image sensor 1500 also includes a control unit 1503 that controls the entire sensor, a vertical scanning unit 1504 that selects a sensor row from the sensor array 1502 that outputs an analog electrical signal, and an AD unit 1505 that performs analog-to-digital conversion of the analog electrical signal. The image sensor 1500 also includes a horizontal scanning unit 1506 that selects a column of the AD unit 1505 that outputs a digital signal, and a signal processing unit 1507 that processes the output digital signal. The peripheral circuit unit 1508 includes the control unit 1503, the vertical scanning unit 1504, the AD unit 1505, the horizontal scanning unit 1506, and the signal processing unit 1507. The image sensor 1500 also includes an electrostatic protection unit 1509 that has a function of dissipating electrostatic discharge (ESD) that enters from an input / output terminal to a VDD power supply wiring or a GND wiring. The image sensor 1500 further includes an I / O unit 1510 that includes an input / output terminal unit having a pad (PAD) that serves as an electrical connection unit with the outside by opening a part of the metal wiring.

[0087] Each sensor 1501 included in the sensor array 1502 includes a photodiode (PD) 1511, a transfer transistor (TX Tr) 1512, a reset transistor (RST Tr) 1513, and an amplification transistor 1514. Each sensor 1501 also includes a row selection transistor (SEL Tr) 1515. A pixel signal acquired by the sensor 1501 of a sensor row selected by the vertical scanning unit 1504 is transmitted to an AD unit 1505, which is a part of a peripheral circuit, via a vertical output line 1516. Note that the vertical output line 1516 and the AD unit 1505 are not limited to a configuration in which they are arranged for each column of the sensor array 1502. One AD unit 1505 of the sensor 1501 may be provided for each block that is a unit of multiple rows and columns of sensor units 1502. Also, one AD unit 1505 may be provided corresponding to one sensor array 1502.

[0088] The analog electrical signal output from the sensor array 1501 is AD converted by the AD unit 1505 and temporarily stored in a column memory. Note that the column memory is considered to be included as part of the AD unit 1505 and is omitted in the figure. The AD converted digital signal is parallel-serial converted in accordance with the drive of the horizontal scanning unit 1506, and then sequentially processed by the signal processing unit 1507 via the horizontal output line 1516. Specific examples of the signal processing performed by the signal processing unit 1507 include noise removal processing and signal correction processing using CDS (Correlated Double Sampling). The processed signal is output to the outside of the sensor via the I / O unit 1510.

[0089] FIG. 26 is a diagram showing an example of the configuration of each semiconductor substrate in an image sensor having the laminated structure of this embodiment. The image sensor 1500 has a laminated structure of a first member 1702 and a second member 1703. In this laminated structure, the first member 1702 has a sensor array 1502 in which the sensor 1501 shown in FIG. 25 is arranged, and a PAD section 1600A. Furthermore, the first member 702 has an inter-substrate connection section 1601A that electrically connects the semiconductor substrate (a) and the semiconductor substrate (b), and an I / O section 1510 including an electrostatic protection section 1509A. The semiconductor substrate (a) and the semiconductor substrate (b) can be bonded together by a well-known method described in, for example, Patent Document 1. In addition, the inter-substrate connection section 1601A that serves as a connection section in the laminated structure may be, for example, a so-called TSV (Through Silicon Via) method. Alternatively, the CCB (Cu-Cu-Bonding; multiple chips are bonded together so that the copper electrodes are bonded to each other. This is also called hybrid bonding) method. Alternatively, the microbump method may be used.

[0090] In this embodiment, the main surfaces of the semiconductor substrate (a) and the semiconductor substrate (b) are the front surface of the substrate, and the surface opposite to the main surface of each substrate is the back surface. The image sensor 1500 is configured to bond the main surface of the semiconductor substrate (a) and the main surface of the semiconductor substrate (b). As another example, the main surface and the back surface, or the back surface and the back surface of each substrate may be bonded. In the stacked connection, the inter-substrate connection section 1601 may be arranged in an arrangement suitable for each purpose, such as for control signals, power supply, and sensor signals, and does not necessarily have to be arranged on the left and right sides of the substrate. In addition to the electrical connection, in order to improve the reliability of bonding, a dummy inter-substrate connection section may be arranged in the bonding between the substrates, but is omitted in the figure. The semiconductor substrate (b) has a peripheral circuit section 1508 including a control section, an AD section, a signal processing section, a vertical scanning section, and a horizontal scanning section. Moreover, the semiconductor substrate (b) has a PAD section 1600B, an inter-substrate connection section 1601B that electrically connects the semiconductor substrate (a) and the semiconductor substrate (b), and an I / O section 1510 including an electrostatic protection section 1509B.

[0091] The image sensor 1500 has a plurality of I / O sections, including pads for outputting pixel signals based on signals photoelectrically converted by the sensor and pads for inputting voltages and the like for driving peripheral circuits supplied from the outside. After the semiconductor substrate (a) and the semiconductor substrate (b) are laminated, an external terminal is connected to the PAD section 1600B via the PAD section 1600A (opening). An example of an external terminal is a bonding wire connected to the PAD section 1600B by a wire bonding method. It is not necessary to arrange the PAD section 1600A, which is an opening, on the semiconductor substrate (a) and the PAD section 1600B on the semiconductor substrate (b). For example, a configuration in which the PAD section 1600B, which is an opening, on the semiconductor substrate (a) and the PAD section 1600A on the semiconductor substrate (b) may be used. Also, in FIG. 26, the peripheral circuit 1508 is arranged on the semiconductor substrate (b). In addition, in the control section, AD section, signal processing section, vertical scanning section, and horizontal scanning section included in the peripheral circuits, the entirety or part of each circuit can be arranged on the semiconductor substrate (a).

[0092] Fig. 27 is a planar layout diagram of the periphery of an I / O unit 1510 according to the eighth embodiment. In Fig. 27, the same components as those in Figs. 1 to 26 are given the same reference numerals, and descriptions thereof will be omitted. Here, the configuration of the electrostatic protection circuit used is the same as that shown in Fig. 2, but it may be the same as those in Figs. 3, 6, 7, 10, 12, 15, and 19, or a combination of these.

[0093] FIG. 28 is a schematic cross-sectional view of a photoelectric conversion device taken along dashed line KK' in FIG. 27. In FIG. 28, the same components as those in FIG. 1 to FIG. 27 are denoted by the same reference numerals, and the description thereof will be omitted. In the photoelectric conversion device of the eighth embodiment, a first member 1702 having a first substrate 1700 and a second member 1703 having a second substrate 1701 are bonded together. In the image sensor in FIG. 28, the electrostatic protection circuit section 1509 has the same configuration and connection relationship as the protection circuit shown in FIG. 4. In this embodiment, a peripheral circuit section 1508 is formed instead of the internal circuit 103A in FIG. 4, and a sensor array 1502 is formed instead of the internal circuit 103B.

[0094] In the sensor array 1502, an n-type semiconductor region constituting a photoelectric conversion element, an n-type semiconductor region 1705 which is the drain of a transfer transistor, and an element isolation structure 1706 are arranged. The transfer transistor 1512 has an n-type semiconductor region 1705, an n-type semiconductor region 1707, and a gate electrode 1708. At this time, the signal charge accumulated in the n-type semiconductor region 1705 is transferred to the n-type semiconductor region 1707 by the gate electrode 1708. On the back surface side of the sensor array 1502, a color filter layer 1709 including a plurality of color filters, a planarization layer 1710, and a microlens layer 1711 including a plurality of microlenses are arranged. In FIG. 28, a plurality of color filters and microlenses are arranged corresponding to one photoelectric conversion element, that is, for each pixel, but one may be arranged for each of a plurality of pixels. 28 illustrates a so-called back-illuminated image sensor in which light is incident from the microlens 1711 side and received by the N-type semiconductor region 1705 of the photoelectric conversion element, but the configuration of the image sensor described in this embodiment is merely an example and is not limited to the above. At least a part of the peripheral circuitry, such as the control unit 1503, AD unit 1505, vertical scanning unit 1504, and horizontal scanning unit 1506, is arranged in the peripheral circuitry 1508. FIG. 28 illustrates n-type transistors and p-type transistors in any circuit included in the peripheral circuitry.

[0095] In this embodiment, in an image sensor in which a plurality of semiconductor substrates are stacked, an electrostatic protection circuit is disposed on two stacked semiconductor substrates. This makes it possible to increase the area occupied by the electrostatic protection circuit without being subjected to pressure during the formation of wire bonding. This makes it possible to improve the characteristics of the electrostatic protection circuit while reducing the influence of wire bonding and ensuring operational stability. Alternatively, instead of increasing the area occupied by the electrostatic protection circuit, the area occupied by the image sensor can be increased to realize a larger number of pixels and higher sensitivity. Alternatively, instead of increasing the area occupied by the electrostatic protection circuit, the area occupied by peripheral circuits in the image sensor, such as a pixel signal readout circuit and a signal processing circuit that processes the readout pixel signals, can be increased to realize higher speed and higher functionality.

[0096] Ninth embodiment The photoelectric conversion system according to this embodiment will be described with reference to Fig. 29. Fig. 29 is a block diagram showing a schematic configuration of the photoelectric conversion system according to this embodiment.

[0097] The imaging devices described in the first to eighth embodiments are applicable to various photoelectric conversion systems. Examples of the applicable photoelectric conversion systems include digital still cameras, digital camcorders, security cameras, copiers, fax machines, mobile phones, car-mounted cameras, and observation satellites. Camera modules equipped with an optical system such as a lens and an imaging device are also included in the photoelectric conversion systems. FIG. 29 illustrates a block diagram of a digital still camera as an example of these.

[0098] 29 includes an image pickup device 1004, a lens 1002 that forms an optical image of a subject on the image pickup device 1004, an aperture 1003 that varies the amount of light passing through the lens 1002, and a barrier 1001 that protects the lens 1002. The lens 1002 and the aperture 1003 form an optical system that focuses light on the image pickup device 1004. The image pickup device 1004 is a photoelectric conversion device (image pickup device) according to any one of the above embodiments, and converts the optical image formed by the lens 1002 into an electrical signal.

[0099] The photoelectric conversion system also has a signal processing unit 1007 which is an image generating unit that generates an image by processing an output signal output from the imaging device 1004. The signal processing unit 1007 performs various corrections and compression as necessary to output image data. The signal processing unit 1007 may be formed on a semiconductor substrate on which the imaging device 1004 is provided, or may be formed on a semiconductor substrate separate from the imaging device 1004. Moreover, the imaging device 1004 and the signal processing unit 1007 may be formed on the same semiconductor substrate.

[0100] The photoelectric conversion system further includes a memory unit 1010 for temporarily storing image data, and an external interface unit (external I / F unit) 1013 for communicating with an external computer or the like. The photoelectric conversion system further includes a recording medium 1012 such as a semiconductor memory for recording or reading out imaging data, and a recording medium control interface unit (recording medium control I / F unit) 1011 for recording or reading out data on the recording medium 1012. The recording medium 1012 may be built into the photoelectric conversion system, or may be removable.

[0101] The photoelectric conversion system further includes an overall control / calculation unit 1009 that performs various calculations and controls the entire digital still camera, and a timing generation unit 1008 that outputs various timing signals to the image capture device 1004 and the signal processing unit 1007. Here, the timing signals and the like may be input from outside, and the photoelectric conversion system only needs to include at least the image capture device 1004 and the signal processing unit 1007 that processes the output signal output from the image capture device 1004.

[0102] The imaging device 1004 outputs an imaging signal to a signal processing unit 1007. The signal processing unit 1007 performs predetermined signal processing on the imaging signal output from the imaging device 1004, and outputs image data. The signal processing unit 1007 generates an image using the imaging signal.

[0103] In this way, according to this embodiment, it is possible to realize a photoelectric conversion system to which the photoelectric conversion device (imaging device) according to any one of the above embodiments is applied.

[0104] Tenth embodiment The photoelectric conversion system and the moving object of this embodiment will be described with reference to Fig. 30. Fig. 30 is a diagram showing the configuration of the photoelectric conversion system and the moving object of this embodiment.

[0105] FIG. 30(a) shows an example of a photoelectric conversion system related to an in-vehicle camera. The photoelectric conversion system 300 has an imaging device 310. The imaging device 310 is the photoelectric conversion device (imaging device) described in any of the above embodiments. The photoelectric conversion system 300 has an image processing unit 312 that performs image processing on a plurality of image data acquired by the imaging device 310, and a parallax acquisition unit 314 that calculates parallax (phase difference of parallax images) from the plurality of image data acquired by the photoelectric conversion system 300. The photoelectric conversion system 300 also has a distance acquisition unit 316 that calculates a distance to an object based on the calculated parallax, and a collision determination unit 318 that determines whether or not there is a possibility of collision based on the calculated distance. Here, the parallax acquisition unit 314 and the distance acquisition unit 316 are examples of distance information acquisition means that acquire distance information to the object. That is, the distance information is information related to the parallax, the defocus amount, the distance to the object, and the like. The collision determination unit 318 may determine the possibility of collision using any of these distance information. The distance information acquisition means may be realized by dedicated hardware, a software module, a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), or a combination of these.

[0106] The photoelectric conversion system 300 is connected to a vehicle information acquisition device 320, and can acquire vehicle information such as vehicle speed, yaw rate, and steering angle. The photoelectric conversion system 300 is also connected to a control ECU 330, which is a control device that outputs a control signal to generate a braking force for the vehicle based on the judgment result of the collision judgment unit 318. The photoelectric conversion system 300 is also connected to an alarm device 340 that issues an alarm to the driver based on the judgment result of the collision judgment unit 318. For example, when the judgment result of the collision judgment unit 318 indicates that there is a high possibility of a collision, the control ECU 330 performs vehicle control to avoid a collision and reduce damage by applying the brakes, releasing the accelerator, suppressing engine output, etc. The alarm device 340 warns the user by sounding an alarm, displaying alarm information on the screen of a car navigation system, etc., or vibrating the seat belt or steering wheel.

[0107] In this embodiment, the surroundings of the vehicle, for example, the front or rear, are imaged by the photoelectric conversion system 300. Fig. 30(b) shows the photoelectric conversion system when imaging the area in front of the vehicle (imaging range 350). The vehicle information acquisition device 320 sends instructions to the photoelectric conversion system 300 or the imaging device 310. This configuration can further improve the accuracy of distance measurement.

[0108] Although the above describes an example of control to prevent collision with other vehicles, the present invention can also be applied to control of automatic driving by following other vehicles, control of automatic driving to prevent deviation from lanes, etc. Furthermore, the photoelectric conversion system is not limited to vehicles such as the vehicle itself, but can be applied to moving bodies (moving devices) such as ships, aircraft, and industrial robots. In addition, the present invention can be applied not only to moving bodies, but also to a wide range of devices that use object recognition, such as intelligent transport systems (ITS).

[0109] [Modified embodiment] The present invention is not limited to the above-described embodiment, and various modifications are possible.

[0110] For example, an example in which part of the configuration of any one of the embodiments is added to another embodiment, or an example in which part of the configuration of another embodiment is substituted therefor, is also included in the embodiments of the present invention.

[0111] Furthermore, the photoelectric conversion systems shown in the above 9th and 10th embodiments are examples of photoelectric conversion systems to which a photoelectric conversion device can be applied, and photoelectric conversion systems to which the photoelectric conversion device of the present invention can be applied are not limited to the configurations shown in Figures 29 and 30.

[0112] It should be noted that the above-mentioned embodiments are merely examples of the implementation of the present invention, and the technical scope of the present invention should not be interpreted as being limited by these embodiments. In other words, the present invention can be implemented in various forms without departing from its technical concept or main features. [Explanation of symbols]

[0113] 100 pads 101A, 101B, 102A, 102B Diodes 103A, 103B internal circuit

Claims

1. a first semiconductor substrate including a plurality of photoelectric conversion units each of which receives incident light and generates a signal charge; a second semiconductor substrate having a signal processing circuit that processes a signal based on the signal charges, a pad to which a power supply voltage is input from outside the photoelectric conversion device; a first protection circuit provided on the first semiconductor substrate and including a first diode and a second diode; a second protection circuit provided on the second semiconductor substrate and including a third diode and a fourth diode; At least one of the first protection circuit and the second protection circuit is provided outside a region in which the pad is provided in a plan view; At least one of the first protection circuit and the second protection circuit is connected to the pad; A photoelectric conversion device characterized in that, in a planar view, at least a portion of the first diode overlaps with at least a portion of the third diode, or, in a planar view, at least a portion of the second diode overlaps with at least a portion of the fourth diode.

2. A photoelectric conversion device as described in claim 1, characterized in that, in a planar view, at least a portion of the first diode overlaps with at least a portion of the third diode, and, in a planar view, at least a portion of the second diode overlaps with at least a portion of the fourth diode.

3. A photoelectric conversion device as described in claim 1, characterized in that a first element isolation region is arranged between the first diode and the second diode, and a second element isolation region is arranged between the third diode and the fourth diode, and in a planar view, at least a portion of the first element isolation region overlaps with at least a portion of the second element isolation region.

4. The photoelectric conversion device according to claim 1 , wherein the first protection circuit and the second protection circuit are provided at positions that overlap each other in a plan view.

5. The photoelectric conversion device according to claim 1 , wherein the second protection circuit is provided at a position overlapping the pad in a plan view.

6. 2. The photoelectric conversion device according to claim 1, wherein both the first protection circuit and the second protection circuit are connected to the pad.

7. 2. The photoelectric conversion device according to claim 1, further comprising a power supply wiring for supplying a power supply voltage to the signal processing circuit, the second protection circuit being connected to the power supply wiring.

8. The photoelectric conversion device according to claim 1, characterized in that the pad is connected to a wiring arranged at a depth different from the pad in a wiring layer, and at least one of the first protection circuit and the second protection circuit overlaps with the wiring in a planar view.

9. a plurality of protection circuits including the second protection circuit are provided on the second semiconductor substrate; a wiring layer provided on the second semiconductor substrate, the wiring being disposed at a depth different from that of the pad; The pad is connected to the wiring, The photoelectric conversion device according to claim 1 , wherein the wiring is connected to the plurality of protection circuits.

10. A photoelectric conversion device as described in claim 1, characterized in that the first diode, the second diode, the third diode and the fourth diode are arranged outside the area in which the pad is provided, when viewed in a planar view.

11. 2 . The photoelectric conversion device according to claim 1 , wherein the pad is disposed between an end of the second semiconductor substrate closer to the pad and the second protection circuit in a plan view.

12. 2. The photoelectric conversion device according to claim 1, further comprising a joint portion that joins the first semiconductor substrate and the second semiconductor substrate, the first protection circuit, the second protection circuit, and the pad being connected to the joint portion.

13. A photoelectric conversion device as described in claim 1, characterized in that the first diode, the second diode, the third diode and the fourth diode are connected to the pad.

14. 2. The photoelectric conversion device according to claim 1, wherein the first protection circuit and the second protection circuit are protection circuits for protecting the photoelectric conversion device from electrostatic discharge.

15. The photoelectric conversion device according to any one of claims 1 to 14, and a signal processing unit that generates an image using a signal output from the photoelectric conversion device.

16. A moving object including the photoelectric conversion device according to any one of claims 1 to 14, A moving body comprising: a control unit that controls the movement of the moving body using a signal output from the photoelectric conversion device.

Images