Electronic circuit and method for creating a high impedance load - Patents.com

Abstract

The electronic circuit, configured to present a high impedance load between a load point and a reference point, includes a capacitive element (C) connected between a first node (node ​​A) and the reference point, a first element (D1) connected in parallel with the capacitive element (C), a first switching element (S1) connected in series between the first node (A) and a voltage source point, a second switching element (S2) connected between the first node (A) and a second node (node ​​B), the second switching element (S2), the second element (D2) connected between the load point and the reference point, and timing control logic configured to realize three stages: In the charging stage, the first switching element (S1) is closed and the second switching element (S2) is turned on to charge the node voltage v at the first node (A). D During the discharge phase, the first switching element (S1) is opened and the second switching element (S2) is opened, allowing the capacitive element (C) to discharge through the first element (D1). During the transfer phase, the second switching element (S2) is closed, connecting the first node (A) and the second node (B), and after the transfer phase, the second switching element (S2) is opened, biasing the second element (D2) to present a high impedance load.

Description

[Technical field]

[0001] The present invention relates to electronic circuits for creating a high impedance load, for example for interfacing with a sensor circuit, and to a method of operating such electronic circuits, in particular integrated semiconductor circuits, to establish a high impedance load. [Background technology]

[0002] It may be necessary to create very resistive on-chip impedances as part of semiconductor integrated circuits while attempting to minimize silicon surface area (e.g., to remain cost-effective). Such high resistance elements are used in analog filtering circuits, bias and ground circuits, and as termination elements in high impedance input stages.

[0003] An example of this is sensor applications, where the sensor elements that convert physical parameters into electrical signals often have very high output impedances. To maintain as best as possible what is usually a small signal, the input stage of the circuitry connected to such sensors must present a very high, but finite, input impedance to prevent charge build-up and undesirable loading effects on the sensor that may adversely affect proper sensor operation. A practical example is the pyroceramic elements used in passive infrared (PIR) sensors. Thermopile sensors, biosensors, gas detectors and various other sensors are also common.

[0004] Important requirements for the high impedance termination element forming part of the input stage of the sensor may include: · a predictable established operating point (its current and voltage) and means for establishing and controlling this operating point; · Predictable temperature stability within the generally applicable temperature range; · Repeatability (chip-to-chip, wafer-to-wafer); · Relative insensitivity to process variations; ·No adverse effects on the analog inputs of sensors and sensing circuits; The device and its operation should be robust enough to be realizable in standard manufacturing processes; · The implementation should use adequate silicon area to remain cost-effective.

[0005] For electronic circuits, especially integrated circuits, several solutions are possible. On-chip options include: Use of lightly doped sheet resistors, such as highly resistive polysilicon resistors. However, the use of such resistors presents challenges, including: o They are highly dependent on process parameters and temperature; o Large area results in large parasitic capacitance that degrades the already small signal that devices such as sensors typically generate; The larger area required for implementation has a significant impact on cost. Use of time-continuous current mirrors that rely on bias resistors for the reference current, but the use of such current mirrors is not suitable for pico-Ampere currents, which must present a very high impedance; or Use of a switched capacitor circuit to limit the current from the sensor while preventing charge build-up.

[0006] A more suitable solution would be to use the subthreshold characteristics of Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) devices, or exploit the exponential current-voltage relationship of diodes or Bipolar Junction Transistors (BJTs), to realize circuit elements that behave as very high impedance devices without sacrificing the silicon area typically required to realize large resistances with passive elements. However, repeatedly and accurately biasing such elements is complicated and therefore uncommon.

[0007] Applicants desire high impedance electronic circuits that solve or ameliorate at least some of these problems.

[0008] Prior art document [1] by Hellen describes that a circuit including a capacitor and a diode, such as that shown in FIG. 1, has a time-dependent voltage behavior as shown in equation (1).

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[0009] Accordingly, the present invention provides an electronic circuit configured to present a high impedance load between a load point and a reference point, the high impedance electronic circuit comprising: a capacitive element (C) provided between a first node (node ​​A) and the reference point; a first element (D1) having a nonlinear voltage-current relationship, connected in parallel with the capacitive element (C) between the first node (A) and the reference point; a first switching element (S1) provided in series between the first node (A) and a voltage source point; a second switching element (S2) provided between the first node (A) and a second node (node ​​B); a second element (D2) having a nonlinear voltage-current relationship connected between the second switching element (S2), the load point, and the reference point; a timing control logic configured to control the first switching element (S1) and the second switching element (S2) to bias the second element (D2), and which operates in at least three stages: Charging period (T CH ), the first switching element (S1) is closed and the second switching element (S2) is opened to generate a nodal voltage v at the first node (A). D (t) determines whether a sufficient or predefined initial voltage threshold V i a charging stage in which the capacitive element (C) can be charged up to Discharge period (T DCH ), the first switching element (S1) is opened and the second switching element (S2) is opened so that the current through the first element (D1) is a sufficient or predefined bias current (I BIAS ) and / or the node voltage v D (t=T CH +T DCH ) is sufficient or a predefined bias voltage (V BIAS a discharge phase during which the capacitive element (C) is allowed to discharge via the first element (D1), so that the capacitance of the first element (D1) is equal to Transmission period (T XFR ), the second switching element (S2) is closed to connect the first node (A) and the second node (B), thereby BIAS) to the contact of the second element (D2) connected to the second node (B) to apply or transmit the bias voltage (V BIAS a transmission step of biasing said second element (D2) according to The timing control logic is configured to open the second switching element (S2) after the transfer phase, and the second element (D2) is biased to present the high impedance load between the load point and the reference point.

[0010] The steps may be repeated, reordered or expanded as desired.

[0011] Strictly speaking, "transmission of a voltage" may include the transmission of an electric charge to establish a particular voltage, but for ease of explanation, this will be referred to as "transmission of a voltage."

[0012] The capacitive element (C) may be a capacitor. The capacitor may be a transistor-implemented capacitor. The capacitive element (C) may be a parasitic capacitance present in other components of the electronic circuit. The capacitive element may be a non-transistor type charge transport element.

[0013] The first element (D1) and the second element (D2) may be a diode or a transistor. When the first element (D1) is a transistor, the first element (D1) may be a diode-connected transistor. When the first element (D1) and the second element (D2) are transistors, these elements may be MOSFETs or BJTs.

[0014] The first element (D1) and the second element (D2) may have the same voltage-current relationship or may have a related (eg proportional or scaled) voltage-current relationship.

[0015] Wikipedia (https: / / en.wikipedia.org / wiki / High_impedance, accessed November 15, 2019) states, "Numerical definitions of "high impedance" vary by application." Therefore, it is considered difficult to define an exact numerical range. An important application of the present invention is considered to be in processing a signal generated by a sensor (referred to as a sensor signal). In such a case, one definition of "high impedance" can be considered from the viewpoint of the effect of preventing the sensor signal from degrading into an unusable signal.

[0016] Another way to define "high impedance" is to consider conventional impedance elements that may be substituted into electronic circuits in accordance with the present invention. Such conventional impedance elements may be on-chip resistors, e.g., polysilicon resistors, which currently exhibit values ​​in the range of 10-100 kΩ, but with exceptions of as high as 100-1000 kΩ. Thus, for purposes of the present invention, a high impedance may be at least 1 MΩ, at least 10 MΩ, at least 100 MΩ, or at least 1 GΩ.

[0017] A high impedance load may represent only resistive loads or a combination of resistive and reactive loads.

[0018] Transmission phase duration T XFR may be calculated to be long enough for effective voltage transmission between the first node (A) and the second node (B), but not so long that it adversely affects the discharge of the capacitive element (C) or the bias point of the second element (D2), which is usually a transistor. XFR uses a second switching element (S2) to generate a voltage V between a first node (A) and a second node (B). D(t) may be transmitted and calculated to maintain the charged state of the capacitive element (C) to ensure that the bias point voltage of the second node (B) of the second element (D2) exceeds ground potential (0V).

[0019] The switching elements may be simply referred to as switches for short. During the transfer phase, the first switch (S1) may remain open.

[0020] The timing control logic determines the timing of T before the next charging phase begins, depending on the accurate realization of the timing signals. IDLE The idle phase may be optional and may be configured to achieve an idle phase of T IDLE may be 0.

[0021] The timing control logic may be configured to cycle through the charging, discharging and transfer phases periodically or intermittently. The timing control logic may be configured to cycle through the charging, discharging and transfer phases in response to a load voltage v L The timing control logic may be configured to repeat at a frequency dependent on the ratio v to establish a constant real impedance. L / i L may be configured to maintain constant.

[0022] The voltage source point may be a power supply point or a power supply rail.

[0023] A resistive element may be provided connected in series with the first switching element (S1). The resistive element may limit an inrush current to the capacitive element (C).

[0024] The electronic circuitry may be, be implemented by, or form part of an integrated circuit.

[0025] The present invention extends to a method of generating a high impedance load (hereinafter referred to as a high impedance electronic circuit) between a load point and a reference point, the method comprising: Providing a high impedance electronic circuit, the high impedance electronic circuit including: a capacitive element (C) provided between a first node (node ​​A) and the reference point; a first element (D1) having a nonlinear voltage-current relationship, connected in parallel with the capacitive element (C) between the first node (A) and the reference point; a first switching element (S1) provided in series between the first node (A) and a voltage source point; a second switching element (S2) provided between the first node (A) and a second node (node ​​B); a second element (D2) having a nonlinear voltage-current relationship connected between the second switching element (S2), the load point, and the reference point; a timing control logic configured to operate the first switching element (S1) and the second switching element (S2) to bias the second element (D2), the timing control logic operating in at least three stages; Furthermore, Charging period (T CH ), the first switching element (S1) is closed and the second switching element (S2) is opened, and the node voltage v at the first node (A) is D (t) determines whether a sufficient or predefined initial voltage threshold V i charging said capacitive element (C) during a charging phase until Discharge period (T DCH ), the first switching element (S1) is opened and the second switching element (S2) is opened, and the current flowing through the first element (D1) is equal to or exceeds a sufficient or predefined bias current (I BIAS ) and / or the node voltage v D (t=T CH +T DCH ) is sufficient or a predefined bias voltage (V BIAS discharging said capacitive element (C) during a discharge phase via said first element (D1) so that Transmission period (T XFR), during a transmission phase in which the second switching element (S2) is closed to connect the first node (A) and the second node (B), the bias voltage (V BIAS ) to the contact of the second element (D2) connected to the second node (B) to apply the bias voltage (V BIAS biasing the second element (D2) according to and opening the second switching element (S2) after the transmission phase, the second element (D2) being biased to present the high impedance load between the load point and the reference point.

[0026] The method defined above may be implemented by an electronic circuit defined above.

[0027] The invention will now be further explained, by way of example only, with reference to the accompanying drawings, in which: [Brief description of the drawings]

[0028] [Figure 1] FIG. 1 shows a schematic circuit diagram of a prior art circuit showing capacitive discharge through a diode from reference [1]. [Diagram 2] 2 shows a schematic circuit diagram in which the diodes in FIG. 1 are replaced with transistors. [Diagram 3] 1 shows a schematic circuit diagram of an electronic circuit configured to generate a high impedance load according to the present invention; [Figure 4] 4 shows a graph of timing signals at various stages and switches of the operation of the electronic circuit of FIG. 3; [Diagram 5] 2 shows a schematic circuit diagram of another embodiment of an electronic circuit configured to generate a high impedance load in accordance with the present invention; [Figure 6] 4 shows a schematic circuit diagram of yet another embodiment of an electronic circuit configured to generate a high impedance load in accordance with the present invention; DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0029] The invention will be described first with reference to some possible theory and then with reference to practical implementations of that theory.

[0030] The present invention proposes that the above-mentioned properties of non-linear elements (e.g. MOS transistors, diodes, BJTs) can be used to form high impedance termination elements. One aspect of the present invention relates to the manner in which such high impedance elements can be biased in the appropriate operating region to achieve the intended result.

[0031] The present invention is based on the phenomenon explained in equation (1) and FIG. 1, but the calculation formula is changed to the diode current i D Note that if rewritten in terms of (t), for currents much larger than I0 this can be expressed as:

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[0032] This result can be extended to MOS transistors by analyzing the circuit of Figure 2, in which the diode of Figure 1 is replaced by a diode-connected NMOS (n-type MOS) transistor.

[0033] The term t / C and the nodal voltage v (in equation (1)) D It can be shown that if (t) is properly constrained, the current through a MOS transistor obeys the following equation:

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[0034] To generalize to both cases, equations (2) and (3) can be rewritten and interpreted as follows:

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[0035] The present invention uniquely utilizes the above-described properties resulting from equation (4) to establish a well-controlled bias point for the device to function as a high impedance element.

[0036] This can be illustrated using a typical field effect transistor, such as an NMOS transistor, that is typically available to circuit designers working with CMOS fabrication processes. The device has four terminals including the gate (G), drain (D), source (S) and bulk (B). In strong inversion operation, the gate-source voltage is V GS >V t However, in subthreshold operation, V GS <V t It is known that in the subthreshold region, the device has a much higher output impedance between the drain and source terminals than in strong inversion.

[0037] Referring again to the circuit of FIG. 2, at t=0, the capacitor is connected to the device's threshold voltage V t An initial voltage V well above i You can start it with V GS =V DS >V t Therefore, the device starts up from strong inversion in a very short time. GS V tThis is typically achieved in less than a few hundred nanoseconds for a 0.35 μm CMOS process, given an appropriate value for C. GS V t Any lower, the transistor enters the sub-threshold region of operation and the rate of discharge becomes significantly slower. From equation (3) and the generalized equation (4), it follows that the magnitude of the current depends only on time t, the nodal capacitance C, and the technology or device constant k.

[0038] Using equation (4), select C and determine the bias current I BIAS (i D (t=T CH +T DCH ) can be regarded as i D (t=T CH +T DCH )=I BIAS The required discharge time T DCH can be determined, and conversely, V D (t=T CH )=V i If there is an initial voltage at the node such that DCH The C value for can be determined.

[0039] The discharge device is I BIAS Since the current I is used to establish a current I, the same device cannot be used to function as a high impedance circuit element by itself. D (t=T CH +T DCH ) associated with the gate-source voltage V of the transistor GSUsing a gate bias voltage, the bias point of a transistor can be replicated by "copying" the gate voltage to another, second MOS transistor. By considering the behavior between the drain and source terminals of the second transistor, if the second transistor has the same size and operates under the same conditions at its terminals, the second transistor can be used as an intended high impedance circuit element. Sub-threshold operation is described in Gray [2]:

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[0040] Similar behavior can be expected from bipolar junction transistors (BJTs). Equation (2) can be applied to BJTs by including the forward current gain term β, in which case i C =βi B and the total current is i D =(β+1)i B However, note that the small-signal output impedance of a BJT can be approximated as

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[0041] We now turn to the practical or technical realization of the above theory. Figure 3 shows an exemplary electronic circuit 100 configured to generate a high impedance load according to the present invention. The electronic circuit 100 may be configured to realize a high impedance element or load, taking into account the conclusions drawn from equation (4). In the figure, the reference point is illustrated as a ground point.

[0042] This example shows electronic circuit 100 using an active element (D1) in the form of an NMOS transistor, which has a non-linear voltage-current relationship, although other implementations are possible (see below). Electronic circuit 100 may include three conceptual sections, each of which serves a specific purpose during various stages of operation. 1. Required load impedance Δv L / Δi L or load current bias point i L A first section (section 1) of electronic circuit 100 that generates a voltage signal that can be used to bias a transistor in the sub-threshold or low current region in response to 2. A second section (section 2) of the electronic circuit 100 that transmits the bias point voltage signal at node A of the first section to node B of the third section. 3. (Voltage at the load point) v L and i L A third section (Section 3) of the electronic circuit 100 includes elements that utilize the transmitted voltage signal to bias a transistor in a manner that establishes a high impedance load as seen from the behavior of R EFF 1 shows a high impedance load as represented by

[0043] The first and second sections can be considered the bias portion of the circuit 100, while the third section is the load presenting section.

[0044] At design time, the circuit designer determines the target current setting I for transistor D1. BIAS Alternatively, the required small signal impedance can be selected using equation (4) and / or equation (6) to determine the capacitance C and the discharge period T DCH It is necessary to derive values ​​for

[0045] The first section of the electronic circuit 100 includes three main elements: · An element that may be an active element such as a transistor or diode D1 in FIG. 3, which may be n-type or p-type depending on the exact circuit implementation; A capacitive element (C), typically a capacitor and parasitic capacitance at node A in FIG. 3; A switching element S1 in FIG. 3, which can connect and disconnect a capacitive element to and from the power supply so that an initial voltage can be set or established at the node.

[0046] Figure 4 shows a graph 200 illustrating the different stages of circuit operation that enable D2 in Figure 3 to function as a high impedance element as described above. The timing signals for closing S1 and S2 are also shown.

[0047] The four stages of circuit operation in Figure 4 can be explained as follows: 1. Phase 1 (charging): During this phase 1, switch S1 connects the charge storage node to a charging source, typically a power rail, and optionally through a resistive element to limit the inrush current to the storage element, while switch S2 is open. The node voltage v D The charging phase duration T is chosen to ensure that (t) reaches a high enough level that equation (2) applies in the case of a diode or bipolar transistor, or equation (3) applies in the case of a diode-connected MOS device. CHA small current flows through the discharge element, the NMOS transistor D1 in FIG. 3, but it is negligible compared to the charging current through S1. A sufficient initial voltage v D (t=T CH )=V i When T is reached, switch S1 is opened and T CH indicates the duration of a charging phase before the next phase is started. 2. Phase 2 (Discharge): During this phase 2, S1 and S2 are both open, v D (t=T CH )=V i is the initial voltage of node A at the beginning of the discharge phase. Now, the first part of the circuit follows the behavior of general equation (4) where the charge stored at node A is discharged through an element, the diode-connected NMOS D1 in FIG. 3. Depending on the parameters selected by the designer, during this phase the current flowing through D1 is increased by the node voltage v D (t=T CH +T DCH )=V BIAS And I BIAS Reach the target value of T DCH It should be. 3. Phase 3 (Transmission): At the end of the discharge phase, the voltage V at node A BIAS Switch S2 is closed to transmit V to node B. Ideally, the voltage at node B would be equal to the voltage at node A and remain so after S2 is opened. However, multiple iterations may be required to achieve this. In the example in FIG. 3, V BIAS will be present at the gate of D2, and the device will be biased in accordance with equations (5) and (6) to function as the intended high impedance circuit element, e.g., between the drain and source terminals of the device. During this phase 3 period T when S2 is closed, XFRneeds to be long enough for effective voltage transfer between nodes A and B, but not so long that it unduly affects the discharge circuitry and bias point. The transfer phase ends when switch S2 is opened. The total node capacitance at node B needs to be large enough to hold this voltage and limit the discharge (and voltage drop / change) for the time S2 is open. 4. Phase 4 (Idle Phase): After the bias point is transferred to the load device D2, the system will automatically start T IDLE In most cases, the idle phase lasts for a period of T IDLE will be 0. This step may be optional. 5. Repeating the process to establish and maintain bias: To establish and maintain the bias point, the above three steps may be repeated periodically or intermittently to obtain a precise V bias point, especially when bipolar devices are used that have non-negligible base currents that affect the set point at node B. BIAS Furthermore, when the bias point is first established, the capacitance ratio of nodes A and B can cause the intended bias voltage V BIAS Or its bias voltage V BIAS Node B may require multiple charge transfer cycles from node A before settling near v D (t=T CH )=V i This means that V D (t=T CH +T DCH )=V BIAS settles after multiple cycles to achieve a stable high impedance operating point applied to D2. The timing control logic may be configured to cycle through the charging, discharging and transfer phases.

[0048] Other variations of the electronic device 100 are possible, as shown in Figures 5 and 6. In a first variation of the circuit shown in Figure 3, two NMOS transistors may be realized by using bipolar junction devices (BJTs) and adapting the circuit for the necessary changes in behavior, such as the continued presence of base currents, as shown in Figure 5 as electronic device 300 according to the present invention. Such adaptation may require adding capacitance to node B, in addition to any parasitic capacitance already present, to sustain those currents while maintaining the node voltage. In a second variation of the circuit shown in Figure 3, the transistors, either MOS or BJT devices, or a combination thereof, may be realized by either n-type or p-type devices, by adapting the circuit and the associated polarities accordingly.

[0049] The method of circuit operation explained in the previous section requires that the discharge time T DCH The emphasis is on using t=T CH +T DCH The bias current I flows through D1 at BIAS With respect to frequency

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[0050] 3 and generally similar circuits may be adapted such that device D1 is geometrically different from device D2, such that the final current through D2 is a scaled version of the current through D1. For example, with respect to FIG. 3, assuming the (W / L) ratio of D2 to D1 is 2, D2 will have a given VBIAS D1 passes about twice as much current through it as D2. That is, i L =2I BIAS In this way, geometric adaptation of the device may be performed to compensate or fine-tune the current in the high impedance termination element D2 for different applications. In the case of a BJT, the emitter area can be scaled to achieve the same effect.

[0051] D2 represents a very high small-signal impedance for a given operating bias point, but the voltage v at the drain (for a field-effect transistor) or collector (for a bipolar transistor) of D2 L In another variation, such an impedance is nonlinear because T varies in absolute terms, as shown at 400 in FIG. DCH It is possible to dynamically compensate for this by adapting T TOTAL =T CH +T DCH +T XFR +T IDLE For a fixed cycle period of =1 / f, by appropriately adjusting the switching signals of S1 and S2, T DCH can be adapted independently. The frequency f may be adapted dynamically, which leads to the change in vL shown in FIG. EFF Adapting to changes in T DCH By implicitly changing R REF may be kept relatively constant.

[0052] Applicant believes that the above illustrated invention is advantageous in that the circuits 100, 300, 400 can be fabricated using cost-effective, industry-standard manufacturing processes such as silicon-based complementary metal-oxide-semiconductor (CMOS). The circuits 100, 300, 400 find application in readout circuits for Passive Infrared (PIR) sensors and other sensors.

[0053] As explained above, the present invention provides a new way of forming high impedance termination elements as part of a sensor circuit front end that meets the requirements for such circuits 100, 300, 400. As an added advantage, the circuits 100, 300, 400 and methods described above provide a highly dynamic and adaptable solution that can be cost-effectively formed as part of today's high performance integrated circuits.

[0054] References [1] Hellen, EH, “Verifying the diode-capacitor circuit voltage delay”, American Journal of Physics, Vol. 71, no. 8, 10 July 2003. [2]Grey, PR, et al, “Analysis and design of analog integrated circuits”, 4th edition, John Wiley and Sons, Inc., 2001.

Claims

1. 1. An electronic circuit configured to present a high impedance load between a load point and a reference point (hereinafter referred to as a high impedance electronic circuit), The high impedance electronic circuit includes: a capacitive element (C) provided between a first node (node ​​A) and the reference point; A first element (D) having a nonlinear voltage-current relationship is connected in parallel to the capacitive element (C) between the first node (A) and the reference point. 1 ). A first switching element (S) is provided in series between the first node (A) and a voltage source point. 1 ). A second switching element (S 2 ). The second switching element (S 2 ), and a second element (D) having a nonlinear voltage-current relationship connected between the load point and the reference point. 2 ). The first switching element (S 1 ) and the second switching element (S 2 ) to control the second element (D 2 a timing control logic configured to bias the first and second inputs, the timing control logic operating in at least three stages as follows: Charging period (T CH ) across the first switching element (S 1 ) is closed, and the second switching element (S 2 ) is opened to generate a node voltage v D (t) gives a predefined initial voltage threshold V i a charging stage in which the capacitive element (C) can be charged up to Discharge period (T DCH ) across the first switching element (S 1 ) is opened, and the second switching element (S 2 ) is opened to expose the first element (D 1 ) is a predefined bias current (I BIAS ) and / or the node voltage v D (t=T CH +T DCH ) is a predefined bias voltage (V BIAS ) the first element (D 1 a discharging stage in which the capacitive element (C) can be discharged via the Transmission period (T XFR ) across the second switching element (S 2 ) is closed to connect the first node (A) and the second node (B), thereby BIAS ) connected to the second node (B) 2 ) to the contacts of the bias voltage (V BIAS ) according to the second element (D 2 ) biasing transmission stage; The timing control logic controls the second switching element (S 2 ) and the second element (D 2 ) is biased to present the high impedance load between the load point and the reference point.

2. The first element (D 1 ) and the second element (D 2 2. The electronic circuit of claim 1, wherein each of the first and second transistors is a diode or a transistor.

3. The first element (D 1 ) is a diode-connected transistor, and the second element (D 2 3. The electronic circuit of claim 2, wherein each of the first and second transistors is a transistor.

4. The first element (D 1 ) and the second element (D 2 ) is a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) or The first element (D 1 ) and the second element (D 2 ) is a BJT (Bipolar Junction Transistor) or The first element (D 1 ) is a BJT, and the second element (D 2 ) is a MOSFET; or The first element (D 1 ) is a diode, and the second element (D 2 4. The electronic circuit of claim 3, wherein:

5. The first element (D 1 ) and the second element (D 2 2. The electronic circuit of claim 1, wherein the input and output terminals have a proportional voltage-current relationship.

6. The transmission period T XFR is the second switching element (S 2 ) to generate a voltage V between the first node (A) and the second node (B). D (t) is transmitted and the charge state of the capacitance element (C) is maintained, and the second element (D 2 2. The electronic circuit according to claim 1, wherein the bias point voltage of said second node (B) of said first input terminal (1) is calculated to ensure that the bias point voltage of said second node (B) of said first input terminal (1) is greater than ground potential (0 V).

7. The electronic circuit of claim 1 , wherein the timing control logic is configured to repeat the charging, discharging and transferring steps periodically or intermittently.

8. The timing control logic controls the charging, discharging and transferring steps in response to a load voltage v L 8. The electronic circuit of claim 7, configured to repeat at a frequency dependent on

9. The timing control logic adjusts the ratio v to establish a constant real impedance. L / i L The electronic circuit of claim 8 , configured to maintain a constant

10. 2. The electronic circuit of claim 1, which is an integrated circuit (IC) or forms part of an integrated circuit (IC).

11. 1. A method for generating a high impedance load (hereinafter referred to as a high impedance electronic circuit) between a load point and a reference point, comprising: Providing a high impedance electronic circuit, the high impedance electronic circuit comprising: a capacitive element (C) provided between a first node (node ​​A) and the reference point; A first element (D) having a nonlinear voltage-current relationship is connected in parallel to the capacitive element (C) between the first node (A) and the reference point. 1 ). A first switching element (S) is provided in series between the first node (A) and a voltage source point. 1 ). A second switching element (S 2 ). The second switching element (S 2 ), and a second element (D) having a nonlinear voltage-current relationship connected between the load point and the reference point. 2 ). The first switching element (S 1 ) and the second switching element (S 2 ) to activate the second element (D 2 ) and the timing control logic operates in at least three stages; Furthermore, Charging period (T CH ) across the first switching element (S 1 ) is closed, and the second switching element (S 2 ) and the node voltage v at the first node (A) is D (t) determines a sufficient or predefined initial voltage threshold V i charging said capacitive element (C) during a charging phase; Discharge period (T DCH ) across the first switching element (S 1 ) is opened, and the second switching element (S 2 ) and the first element (D 1 ) flows through a sufficient or predefined bias current (I BIAS ) and / or the node voltage v D (t=T CH +T DCH ) is sufficient or a predefined bias voltage (V BIAS ) so that the first element (D 1 discharging said capacitive element (C) during a discharging phase via Transmission period (T XFR ) across the second switching element (S 2 During a transmission phase in which the first node (A) and the second node (B) are connected by closing the bias voltage (V BIAS ) connected to the second node (B) 2 ) contact to apply the bias voltage (V BIAS ) according to the second element (D 2 ) biasing; After the transmission step, the second switching element (S 2 ) by opening the second element (D 2 ) is biased to present the high impedance load between the load point and the reference point.

12. The method of claim 11 , wherein the charging, discharging and transferring steps are repeated periodically or intermittently.

13. The charging, discharging and transmitting steps are performed with a load voltage v L 13. The method of claim 12, wherein the method is repeated at a frequency dependent on

14. To establish a constant real impedance, the ratio v L / i L 14. The method of claim 13, further comprising the step of maintaining constant.

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