MOSFET DEVICE AND METHOD OF MANUFACTURING THE SAME

Abstract

The present invention provides a MOSFET device and a method for manufacturing the same. First, a first implantation region that is easy to diffuse is formed, and then a second implantation region that is difficult to diffuse and has a deeper junction is sequentially formed. After the plasma implantation of the source region is completed, the first implantation region is activated, thereby forming a required well region by the junction diffusion of the first implantation region, and the second implantation region is for deepening the depth of the well region. This avoids the problem of the prior art that the substrate surface at the channel is destroyed by directly forming a P-well by multiple Al ion implantations, resulting in a rough surface of the device channel, and realizes high conductive performance of the device. In addition, the ion implantation of the first implantation region, the second implantation region, and the source region can use the same mask layer, which simplifies the process and effectively reduces the number of photolithography steps.

Description

[Technical field]

[0001] The present invention relates to the technical field of MOSFET device manufacturing, and more particularly to a MOSFET device and a method for manufacturing the same. [Background technology]

[0002] Silicon carbide (SiC) MOSFET (Metal Oxide Semiconductor Field Effect Transistor) devices have advantages such as fast switching speed and low on-resistance, and can achieve high breakdown voltage levels with a small drift layer thickness, thereby reducing the size of power switch modules and reducing energy consumption, and have obvious advantages in the application fields of power switches, converters, etc.

[0003] Since Al (aluminum) ion implantation has weak diffusion in SiC, in existing planar gate SiC MOSFET processes, a P-well of a certain depth is usually obtained by multiple Al ion implantations, and then an N+ source region, a P+ body region (also called a P+ contact region), etc. are formed in the P-well by ion implantation.

[0004] However, multiple Al ion implantations can destroy the SiC surface at the channel of planar-gate SiC MOSFETs, resulting in rough surfaces of the P-well channel and increased channel scattering, limiting the improvement of channel carrier mobility.

[0005] The above problem also exists in other planar MOSFET processes in which the P-well is formed by multiple Al ion implantations. Summary of the Invention

[0006] An object of the present invention is to provide a MOSFET device and a method for manufacturing the same that can avoid damage to the P-well channel surface due to ion implantation and achieve high conduction performance of the device.

[0007] In order to achieve the above object, the present invention provides providing a substrate; and implanting a first well ion of a first conductivity type into a front surface layer of the substrate to form a first implantation region; implanting second well ions of a first conductivity type into the substrate below the first implant region to form a second implant region; implanting source ions of a second conductivity type into a surface layer of the first implantation region to form a source region; activating first well ions in the first implantation region to diffuse the junction of the first implantation region laterally to a required width and vertically to contact the second implantation region to form a required well region; forming a gate oxide layer and a gate, sequentially deposited on the front side of the substrate, a contact area between the first implant region and the gate oxide layer defining a channel of the MOSFET device.

[0008] Optionally, before implanting the first well ions into the front surface layer of the substrate, a patterned mask layer for defining a well region is further formed on the front surface of the substrate, and then the first well ions, the second well ions, and the source ions are sequentially implanted into the substrate using the patterned mask layer as a mask.

[0009] Optionally, after forming the source region and prior to activating first well ions in the first implant region, removing the patterned mask layer; The method further includes implanting body region ions of a first conductivity type into a portion of the source region to form a body region, the body region extending deep into a portion of the first implanted region and shorting the source region and the first implanted region.

[0010] Optionally, the first well ions include boron ions or boron fluoride ions and the second well ions include aluminum ions.

[0011] Optionally, the first well ion implantation process parameters include an implantation energy of 50 keV to 300 keV and an implantation dose of 1E11 / cm 2 ~6E14 / cm 2 Includes.

[0012] Optionally, the first well ions in the first implantation region are activated by an annealing process, the annealing temperature is 1500° C.-1900° C., and the annealing time is 2 min-200 min.

[0013] Optionally, the substrate includes a silicon carbide layer of a second conductivity type, and the first implanted region and the second implanted region are both formed in the silicon carbide layer.

[0014] Optionally, the method of manufacture comprises: forming an interlevel dielectric layer on a front side of the substrate, the interlevel dielectric layer embedding the gate and exposing a portion of the source region; forming a source metal layer on the interlevel dielectric layer, electrically connected to the source region; The method further includes forming a drain metal layer on a back surface of the substrate.

[0015] Based on the same inventive concept, the present invention comprises: A substrate; a well region of a first conductivity type including a first implantation region and a second implantation region formed from top to bottom, the first implantation region being formed in a surface layer of a partial region of a front surface of the substrate, the second implantation region being formed in the substrate below a bottom of the first implantation region, and the first implantation region vertically diffusing until it contacts the second implantation region; a source region formed in a surface layer of the first implantation region; The present invention further provides a MOSFET device including a gate oxide layer and a gate sequentially stacked on a front side of the substrate, the gate also contacting both the first implanted region and the source region, the first implanted region extending laterally further at a bottom of the gate than the second implanted region.

[0016] Optionally, the substrate includes a silicon carbide layer of a second conductivity type, the first implanted region and the second implanted region are both formed in the silicon carbide layer, the ions of first conductivity type doped into the first implanted region include boron ions or boron fluoride ions, and the ions of first conductivity type doped into the second implanted region include aluminum ions.

[0017] Compared with the prior art, the technical solution of the present invention has at least one of the following beneficial effects:

[0018] 1. First, a first implantation region that is easy to diffuse is formed, and then a second implantation region that is difficult to diffuse and has a deeper junction is formed in sequence. After the plasma implantation of the source region is completed, the first implantation region is activated, and the required well region is formed by the junction diffusion of the first implantation region, and the second implantation region is for deepening the depth of the well region. This avoids the problem of the prior art that the substrate surface at the channel is destroyed by directly implanting multiple Al ions to form a P-well, resulting in a rough surface of the device channel, and realizes high conductive performance of the device.

[0019] 2. The ion implantation of the first implantation region, the second implantation region and the source region can use the same mask layer, which simplifies the process and effectively reduces the number of photolithography steps. [Brief description of the drawings]

[0020] Those skilled in the art will appreciate that the drawings provided are for a better understanding of the present invention, and are not intended to limit the scope of the present invention in any way. [Figure 1] 4 is a flowchart of a method for manufacturing a MOSFET device according to one embodiment of the present invention. [Diagram 2] 2A to 2C are cross-sectional views illustrating a device structure in a method for manufacturing the MOSFET device shown in FIG. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0021] In the following description, numerous specific details are given to provide a more thorough understanding of the present invention. However, it will be apparent to one skilled in the art that the present invention can be practiced without one or more of these details. In other instances, some technical features well known in the art are not described to avoid confusion with the present invention. It should be understood that the present invention can be embodied in different forms and should not be construed as being limited to the examples set forth herein. Rather, these examples are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the present invention to those skilled in the art. In the drawings, the sizes and relative sizes of layers and regions may be exaggerated for clarity. Like numbers refer to like elements throughout. When an element or layer is described as "on" or "connected" to another element or layer, it should be understood that it may be directly on or connected to the other element or layer, or that intervening elements or layers may be present. In contrast, when an element is described as "directly on" or "directly connected" to another element or layer, there will be no intervening elements or layers. Terms such as first, second, etc. may be used to describe various elements, members, regions, layers, and / or sections, but these elements, members, regions, layers, and / or sections should not be limited by these terms. These terms are merely intended to distinguish one element, member, region, layer, or section from another element, member, region, layer, or section. Thus, a first element, member, region, layer, or section described below can be expressed as a second element, member, region, layer, or section without departing from the teachings of the present invention. Spatial relationship terms such as "under," "underly," "below," "over," "above," "above" and the like may be used herein for convenience of description to describe the relationship of one element or feature to another element or feature shown in the figures. It should be understood that the spatial relationship terms are intended to further encompass different orientations of the device during use and operation in addition to the orientations shown in the figures.For example, if the device in the figures is turned over, elements or features described as "under", "underneath" or "below" would be oriented "above" the other elements or features. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial descriptive terms used herein interpreted accordingly. The terms used herein are intended only to describe specific examples and are not intended to limit the invention. As used herein, the singular forms "a", "one" and "said" are intended to include the plural, unless the context clearly dictates otherwise. It should also be understood that the term "comprises" is intended to determine the presence of possible features, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, steps, operations, elements, components and / or groups. As used herein, the term "and / or" includes any and all combinations of the associated listed items.

[0022] The technical solutions provided by the present invention will be described in more detail below with reference to the drawings and specific embodiments. The advantages and features of the present invention will be more apparent from the following description. It should be noted that the drawings are all in a very simplified form and all use non-precise scales, which are only intended to help easily and clearly describe the embodiments of the present invention.

[0023] 1, one embodiment of the present invention provides a method for manufacturing a MOSFET device, the method including the following steps S1, S2, S3, S4 and S5.

[0024] In S1, a substrate is prepared, and a first well ion of a first conductivity type (eg, P type) is implanted into a front surface layer of the substrate to form a first implantation region.

[0025] In S2, a second well ion of the first conductivity type is implanted into the substrate below the first implant region to form a second implant region.

[0026] In S3, source ions of a second conductivity type (eg, N-type) are implanted into a surface layer of the first implantation region to form a source region.

[0027] In S4, first well ions in the first implantation region are activated to diffuse the junction of the first implantation region to a required width laterally and to contact the second implantation region vertically, thereby forming a required well region.

[0028] In S5, a gate oxide layer and a gate are sequentially formed on the front side of the substrate, and a contact area between the first implant region and the gate oxide layer is a channel of a MOSFET device.

[0029] 2A, in step S1, any suitable semiconductor material, such as silicon carbide, silicon, etc., can be prepared to form a substrate 100. For example, the substrate 100 prepared is an N-type silicon carbide substrate, and has three layers from bottom to top, an N+ base 100a, a buffer layer 100b, and an N-drift layer 100c, in that order, and the doping concentration of N-type ions in the N-drift layer 100c is lower than the doping concentration of N-type ions in the N+ base 100a.

[0030] Specifically, referring to (A) of FIG. 2, in step S1, first, the substrate 100 can be subjected to surface cleaning and drying, and then a mask layer material is deposited on the N-drift layer 100c, and the mask layer material may be one or more selected from, for example, polysilicon (poly Si), single crystal silicon (Si), silica (SiO2), silicon nitride (SiN), etc., and may be a single layer film or a stack of films of multiple different materials. The mask layer material is photolithographically and etched to form a patterned mask layer 200 for defining the P-well to be formed. In this example, an implantation window (not shown) of the P-well to be formed is defined on both sides of the patterned mask layer 200, and then, using the patterned mask layer 200 as a mask, P-type first well ions are implanted into the surface layer of the N-drift layer 100c to form a first implantation region 101 in the surface layer of the N-drift layer 100c on both sides of the patterned mask layer 200. The first well ions selected in this step are ions that can form holes in the N-drift layer 100c and are more diffusible at high temperatures with respect to the subsequent second well ions and source ions. For example, the first well ions are boron ions or boron fluoride ions, the implantation direction may be perpendicular to the surface of the N-drift layer 100c, the implantation energy is 50 keV to 300 keV (e.g., 100 keV, 200 keV, etc.), and the implantation dose is 1E11 / cm. 2 ~6E14 / cm 2 (For example, 5E12 / cm 2 , 1E13 / cm 2 etc.).

[0031] 2B, in step S2, using the patterned mask layer 200 as a mask, P-type second well ions are implanted into the N-drift layer 100c below the first implantation region 101 to form second implantation regions 102 in the N-drift layer 100c below the first implantation region 101 on both sides of the patterned mask layer 200, so that the second implantation region 102 can form a deeper junction than the first implantation region 101. For example, depending on the depth and width requirements of the P-well design, multiple aluminum (Al) ion implantations can be performed vertically or obliquely into the N-drift layer 100c below the first implantation region 101, with the implantation temperature being 400° C. to 1000° C. (e.g., 500° C., 800° C., etc.), the implantation energy being 200 keV to 500 keV (e.g., 300 keV, 400 keV, etc.), and the implantation dose being 1E11 / cm. 2 ~6E14 / cm 2 (For example, 5E12 / cm 2 , 1E13 / cm 2 , 1E14 / cm 2 etc.).

[0032] 2C, in step S3, N-type source ions are implanted vertically or obliquely into the surface layer of the first implantation region 101 using the patterned mask layer 200 as a mask according to the depth and width requirements of the source region design to form source regions 103 in the surface layer of the first implantation region 101 on both sides of the patterned mask layer 200. For example, the N-type source ions include at least one of phosphorus (P) ions, arsenic (As) ions, nitrogen (N) ions, etc., with an implantation energy of 50 keV to 300 keV (e.g., 100 keV, 200 keV, etc.) and an implantation dose of 1E14 / cm. 2 ~1E16 / cm 2 (For example, 5E14 / cm 2 , 1E15 / cm 2 , 5E15 / cm 2 etc.).

[0033] 2D, in step S3, selectively, after forming source region 103, patterned mask layer 200 is removed, and P-type body region ions are implanted into a portion of source region 103 to form body region 104 (also referred to as a contact region), the bottom of body region 104 deeply penetrates into a portion of first implantation region 101 to short-circuit source region 103 and first implantation region 101, and the doping concentration of the P-type ions is higher than that of first implantation region 101. For example, the body region ions may include at least one of boron ions, boron fluoride ions, and aluminum ions, with an implantation energy of 50 keV to 300 keV (e.g., 100 keV, 200 keV, etc.), and an implantation dose of 1E14 / cm. 2 ~1E16 / cm 2 (For example, 5E14 / cm 2 , 1E15 / cm 2 , 5E15 / cm 2 etc.).

[0034] 2E, in step S4, the substrate 100 is annealed by a high-temperature annealing process to activate the first well ions in the first implantation region 101, as well as the second well ions in the second implantation region 102 and the P-type ions in the N-type ion body region 104 in the source region 103. The annealing temperature is 1500°C to 1900°C (e.g., 1650°C, 1700°C, 1800°C, etc.), and the annealing time is 2min to 200min (e.g., 10min, 20min, 50min, 100min, etc.). The high-temperature annealing process diffuses one well ion such as boron ion in the first implantation region 101, and the first implantation region 101' after diffusion has a bottom that contacts the top of the second implantation region 102 in the vertical direction and is expanded laterally to a width required for the P-well, thereby providing a channel width required for the subsequent process. The second well ions in the second implantation region 102 and the P-type ions in the N-type ion body region 104 in the source region 103 are both weakly diffused compared to the first well ions in the first implantation region 101, and the N-drift layer 101c between the two diffused first implantation regions 101' is a depletion region.

[0035] In this step, the required well region is composed of the first implantation region 101′ after diffusion at the top and the second implantation region 102 at the bottom, and the required channel is formed by the diffusion of the first implantation region 101, so that the roughness of the channel surface can be greatly reduced, and further the interface scattering of the channel electrons in the finally manufactured MOSFET device can be reduced, and the channel mobility can be improved.

[0036] 2F, in step S5, first, a suitable gate oxide process such as thermal oxidation process or chemical vapor deposition can be adopted to form a gate oxide layer 301 on the front surface of the body region 104, the source region 103, the first implanted region 101' after diffusion and the N-drift layer 100c, then a gate material layer can be deposited on the surface of the gate oxide layer 301, and the deposited gate material layer and the gate oxide layer 301 can be photolithographically and etched to form a gate 302. The formed gate 302 overlaps both the first implanted region 101' after diffusion and the source region 104, and the contact region between the first implanted region 101' after diffusion and the gate oxide layer 301 is the channel of the MOSFET device.

[0037] In this step, by forming a P-well by diffusion in step S4, the roughness of the channel surface can be effectively avoided, and the SiC crystal quality of the N-drift layer 100c used as the depletion region can be guaranteed to be perfect, so that the quality of the formed gate oxide layer 301 can be guaranteed, the channel defect density can be reduced, and the temperature drift performance of the device can be further improved, thereby further enhancing the reliability of the device.

[0038] Optionally, after forming the gate 302, first, the front side of the substrate 100 is covered with an interlayer dielectric layer 400 by a chemical vapor deposition process or the like, and the interlayer dielectric layer 400 may be a single-layer dielectric film structure or a multi-layer dielectric film structure. Then, the interlayer dielectric layer 400 is patterned by photolithography and etching, and the patterned interlayer dielectric layer 400 can embed the gate 302 and expose a part of the source region 103. Then, a source metal layer 500 (e.g., a metal material or an alloy such as copper, aluminum, gold, etc.) is formed on the interlayer dielectric layer 400 by a suitable process such as metal sputtering deposition or evaporation, and the source metal layer 500 is also electrically connected to both the source region 103 and the body region 104. Then, a drain metal layer (not shown) is formed on the back side of the N+ base 100a.

[0039] The manufacturing method of the MOSFET device of this embodiment forms a required well region by diffusion, which on the one hand can greatly reduce the roughness of the channel surface and reduce the interface scattering of channel electrons, thereby improving the channel mobility, and on the other hand can improve the energy level of channel defects and the gate oxygen quality, further improving the temperature drift performance of the device, and further improving the reliability of the device.

[0040] In addition, the ion implantation of the first implantation region, the second implantation region and the source region can all be performed by the same patterned mask layer 200, which simplifies the process and effectively reduces the number of photolithography steps.

[0041] 2F, one embodiment of the present invention further provides a MOSFET device, preferably fabricated by the method of fabricating a MOSFET device of the present invention, comprising: a substrate 100, a well region of a first conductivity type (e.g., P-type), a source region 103, a gate oxide layer 301, and a gate 302.

[0042] The substrate 100 may be any suitable semiconductor material. For example, the substrate 100 is an N-type silicon carbide substrate, and has three layers from bottom to top, an N+ base layer 100a, a buffer layer 100b, and an N- drift layer 100c.

[0043] The well region of a first conductivity type (e.g., P type) includes a first implantation region 101 and a second implantation region 102 formed from top to bottom, the first implantation region 101 being formed in a surface layer of a portion of the front surface of the N-drift layer 100c, the second implantation region 102 being formed in the N-drift layer 100c below a bottom of the first implantation region 101, and the first implantation region 101 diffuses vertically until it contacts the second implantation region 102, the first conductivity type ions doped into the first implantation region 101 include boron ions or boron fluoride ions, and the first conductivity type ions doped into the second implantation region 102 include aluminum ions.

[0044] The source region 103 is formed in a surface layer of the first implantation region 101 .

[0045] A gate oxide layer 301 and a gate 302 are sequentially stacked on the front side of the N-drift layer 100c, and the gate 302 overlaps both the first implanted region 103 and the source region 104, with the first implanted region 103 extending laterally farther than the second implanted region 102 at the bottom of the gate 302.

[0046] As described above, in the MOSFET device and the manufacturing method thereof of the present invention, first, a first implantation region that is easy to diffuse is formed, and then, a second implantation region that is difficult to diffuse and has a deeper junction is sequentially formed. After the plasma implantation of the source region is completed, the first implantation region is activated, and the necessary well region is formed by the junction diffusion of the first implantation region, and the second implantation region is for deepening the depth of the well region. This avoids the problem of the prior art that the substrate surface at the channel is destroyed by directly forming a P-well by multiple Al ion implantations, resulting in a rough surface of the device channel, and realizes high conductive performance of the device. In addition, the ion implantation of the first implantation region, the second implantation region, and the source region can use the same mask layer, which simplifies the process and effectively reduces the number of photolithography steps.

[0047] The above description is merely a description of preferred embodiments of the present invention, and does not limit the scope of the present invention in any way. Any changes and modifications made by those skilled in the art based on the above disclosure shall fall within the protection scope of the technical solutions of the present invention.

Claims

1. providing a substrate; forming a patterned mask layer on a front surface of the substrate to define a well region; and implanting first well ions of a first conductivity type into a front surface layer of the substrate using the patterned mask layer as a mask to form a first implantation region; implanting second well ions of a first conductivity type into the substrate below the first implant region using the patterned mask layer as a mask to form a second implant region; using the patterned mask layer as a mask, implanting source ions of a second conductivity type into a surface layer of the first implantation region to form a source region; activating first well ions in the first implantation region to diffuse the junction of the first implantation region laterally to a required width and vertically to contact the second implantation region to form a required well region; forming a gate oxide layer and a gate, successively stacked, on the front side of the substrate, the contact area between the first implanted region and the gate oxide layer being a channel of a MOSFET device; After forming the source region and prior to activating the first well ions in the first implant region, removing the patterned mask layer; and implanting body region ions of a first conductivity type into a portion of the source region to form a body region, the body region extending deep into a portion of the first implanted region and shorting the source region and the first implanted region.

1. A method for manufacturing a MOSFET device.

2. The manufacturing method described in claim 1, wherein in the process of activating the first well ions in the first implantation region, diffusion of the second well ions in the second implantation region and the source ions in the source region is weaker than that of the first well ions in the first implantation region, and a channel of the MOSFET device is formed by diffusion of the first implantation region.

3. 2. The method of claim 1, wherein the first well ions include boron ions or boron fluoride ions, and the second well ions include aluminum ions.

4. The first well ion implantation process parameters are: implantation energy 50 keV to 300 keV, implantation dose 1E11 / cm ２ ~6E14 / cm ２ The method of claim 3, comprising:

5. 4. The method of claim 3, further comprising activating the first well ions in the first implantation region by an annealing process, the annealing temperature being 1500° C. to 1900° C., and the annealing time being 2 min to 200 min.

6. 4. The method of claim 3, wherein the substrate comprises a layer of silicon carbide of a second conductivity type, and the first implanted region and the second implanted region are both formed in the silicon carbide layer.

7. forming an interlevel dielectric layer on a front side of the substrate, the interlevel dielectric layer embedding the gate and exposing a portion of the source region; forming a source metal layer on the interlevel dielectric layer, electrically connected to the source region; The method according to claim 1 , further comprising the step of: forming a drain metal layer on a back surface of the substrate.

8. A MOSFET device comprising: A substrate; a well region of a first conductivity type including a first implantation region and a second implantation region formed from top to bottom, the first implantation region being formed in a surface layer of a partial region of a front surface of the substrate, the second implantation region being formed in the substrate below a bottom of the first implantation region, and the first implantation region being vertically adjacent to the second implantation region; a source region formed in a surface layer of the first implantation region; a gate oxide layer and a gate, sequentially stacked on a front side of the substrate, the gate contacting both the first implanted region and the source region, the first implanted region extending laterally further at a bottom of the gate than the second implanted region, the area of ​​the gate oxide layer where it meets the first implanted region being used as a channel of the MOSFET device; a body region formed in a portion of the source region, the bottom of the body region penetrating into a portion of the first implantation region to short-circuit the source region and the first implantation region; 1. A MOSFET device comprising:

9. 9. The MOSFET device of claim 8, wherein the substrate comprises a silicon carbide layer of a second conductivity type, the first implanted region and the second implanted region are both formed in the silicon carbide layer, first well ions of the first conductivity type doped into the first implanted region comprise boron ions or boron fluoride ions, and second well ions of the first conductivity type doped into the second implanted region comprise aluminum ions.

Images