Electronic device and method for manufacturing same

Abstract

To provide an electronic device capable of improving visibility of an alignment mark, and a method of manufacturing the same.SOLUTION: There is provided an electronic device that comprises a first chip and a second chip, which are electrically connected by using a bump, wherein the first chip has a first alignment mark, the second chip has a second alignment mark, the first alignment mark and the second alignment mark face each other, and at least one of the first chip and the second chip has a recessed part, which is recessed along a thickness more than any other part than the recessed part of the at least one of the first chip and the second chip, and also provided with the first alignment mark or the second alignment mark which corresponds to the at least one of the first chip and the second chip.SELECTED DRAWING: Figure 3

Description

[Technical field]

[0001] The present disclosure relates to electronic devices and methods for manufacturing the same. [Background technology]

[0002] 2. Description of the Related Art There is known a technique for forming an electronic device by flip-chip mounting a chip on a substrate using bumps (see, for example, Patent Document 1). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 10-326805 Summary of the Invention [Problem to be solved by the invention]

[0004] In the flip chip mounting process, multiple chips are aligned with each other by checking the alignment marks. After flip chip mounting, the alignment marks are observed to inspect the positions. However, if the visibility of the alignment marks is poor, alignment and inspection are difficult. Therefore, an object of the present invention is to provide an electronic device capable of improving the visibility of the alignment marks, and a manufacturing method thereof. [Means for solving the problem]

[0005] An electronic device according to the present disclosure comprises a first chip and a second chip, the first chip and the second chip being electrically connected using bumps, the first chip having a first alignment mark and the second chip having a second alignment mark, the first alignment mark and the second alignment mark facing each other, at least one of the first chip and the second chip having a recess, the recess being recessed in a thickness direction relative to a portion of at least one of the first chip and the second chip other than the recess, and one of the first alignment mark and the second alignment mark corresponding to the at least one of the first chip and the second chip being provided in the recess.

[0006] The electronic device of the present disclosure comprises a first chip and a second chip, the first chip and the second chip being electrically connected using bumps, the first chip having a first alignment mark, the second chip having a second substrate, a light receiving layer, and a second alignment mark, the first alignment mark and the second alignment mark facing each other, and the second alignment mark being provided at a position within the surface of the second chip spaced apart from the light receiving layer.

[0007] The manufacturing method for an electronic device according to the present disclosure includes a step of acquiring images of a first alignment mark on a first chip and a second alignment mark on a second chip, a step of aligning the first chip and the second chip using the images of the first alignment mark and the second alignment mark so that the first alignment mark and the second alignment mark overlap, and a step of flip-chip mounting the aligned first chip and the second chip, wherein at least one of the first chip and the second chip has a recess, the recess being recessed in a thickness direction relative to a portion of at least one of the first chip and the second chip other than the recess, one of the first alignment mark and the second alignment mark corresponding to the at least one of the first chip and the second chip is provided in the recess, and the step of acquiring the images is a step of acquiring the images by photographing from a side of the at least one of the first chip and the second chip.

[0008] The manufacturing method for an electronic device according to the present disclosure includes a step of acquiring images of a first alignment mark on a first chip and a second alignment mark on a second chip, a step of aligning the first chip and the second chip using the images of the first alignment mark and the second alignment mark so that the first alignment mark and the second alignment mark overlap, and a step of flip-chip mounting the aligned first chip and the second chip, wherein the second chip has a second substrate and a light receiving layer, the light receiving layer is laminated on a portion of the second substrate, and the second alignment mark is provided on a portion of the second substrate where the light receiving layer is not laminated, and the step of acquiring the image is a step of acquiring the image by photographing from the side of the second chip. Effect of the Invention

[0009] According to the present disclosure, it is possible to provide an electronic device capable of improving the visibility of alignment marks, and a manufacturing method thereof. [Brief description of the drawings]

[0010] [Figure 1A] FIG. 1A is a schematic view illustrating a manufacturing apparatus according to the first embodiment. [Figure 1B] FIG. 1B is a block diagram showing a hardware configuration of the control unit. [Figure 2A] FIG. 2A is a plan view illustrating the electronic device according to the first embodiment. [Figure 2B] FIG. 2B is a cross-sectional view taken along line AA in FIG. 2A. [Diagram 3] FIG. 3 is an enlarged view of the periphery of the electronic device. [Figure 4A] FIG. 4A is a plan view illustrating an alignment mark of an IC chip. [Figure 4B] FIG. 4B is a plan view illustrating an alignment mark of the sensor chip. [Diagram 5] FIG. 5 is a flow chart illustrating a method for manufacturing an electronic device. [Figure 6A] FIG. 6A is a cross-sectional view illustrating a method for manufacturing an electronic device. [Figure 6B] FIG. 6B is a cross-sectional view illustrating a method for manufacturing an electronic device. [Figure 6C] FIG. 6C is a cross-sectional view illustrating a method for manufacturing an electronic device. [Figure 7A] FIG. 7A is an enlarged plan view of the alignment mark. [Figure 7B] FIG. 7B is an enlarged plan view of the alignment mark. [Figure 8] FIG. 8 is an enlarged view of the outer periphery of the electronic device according to the second embodiment. [Figure 9] FIG. 9 is an enlarged view of the outer periphery of the electronic device according to the third embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011] [Description of the embodiments of the present disclosure] First, the contents of the embodiments of the present disclosure will be listed and described.

[0012] One embodiment of the present disclosure is an electronic device comprising: (1) a first chip and a second chip, the first chip and the second chip being electrically connected using bumps, the first chip having a first alignment mark, the second chip having a second alignment mark, the first alignment mark and the second alignment mark facing each other, at least one of the first chip and the second chip having a recess, the recess being recessed in a thickness direction relative to a portion of at least one of the first chip and the second chip other than the recess, and the first alignment mark and the second alignment mark corresponding to the at least one of the first chip and the second chip being provided in the recess. At least one of the first alignment mark and the second alignment mark is provided in the recess. The thickness of at least one of the first chip and the second chip in the recess is smaller than the thickness of the portion other than the recess. The effects of aberration and scattering can be suppressed, and the visibility of the first alignment mark and the second alignment mark can be improved. (2) The first chip may have a first substrate, and the first substrate may have the recess. A first alignment mark is provided in the recess of the first substrate. The thickness of the first substrate in the recess is smaller than the thickness of the first substrate other than the recess. This can suppress the effects of aberration and scattering and improve the visibility of the first alignment mark. (3) The first substrate may be made of silicon. There is a refractive index difference between the silicon first substrate and air. Since the first alignment mark is provided in a recess of the first substrate, it is possible to suppress the influence of aberration due to the refractive index difference and improve the visibility of the first alignment mark. (4) The second chip may have a second substrate and a light receiving layer, the second substrate having the recess, and the light receiving layer may be laminated on a portion of the second substrate other than the recess. The thickness of the second substrate in the recess is smaller than the thickness of the second substrate other than the recess. The effects of aberration and scattering can be suppressed. In the recess, absorption of light by the light receiving layer can be suppressed. The visibility of the second alignment mark can be improved. (5) An electronic device including a first chip and a second chip, the first chip and the second chip being electrically connected to each other using bumps, the first chip having a first alignment mark, the second chip having a second substrate, a light receiving layer, and a second alignment mark, the first alignment mark and the second alignment mark facing each other, and the second alignment mark being provided at a position apart from the light receiving layer within the surface of the second chip. This can suppress light absorption by the light receiving layer and improve visibility of the second alignment mark. (6) The second substrate may include indium phosphide, and the light receiving layer may include indium gallium arsenide. The light absorption rate of the second substrate made of indium phosphide is lower than that of the light receiving layer made of indium gallium arsenide. This makes it possible to suppress light absorption and improve the visibility of the second alignment mark. (7) The first alignment mark and the second alignment mark may be made of metal. A high contrast is generated between the first alignment mark and the second alignment mark made of metal and the first chip and the second chip. This improves the visibility of the first alignment mark and the second alignment mark. (8) The first chip may have a plurality of the first alignment marks, and the second chip may have a plurality of the second alignment marks. By using the plurality of first alignment marks and the plurality of second alignment marks, it is possible to align the first chip and the second chip with high accuracy. (9) A method for manufacturing an electronic device, comprising the steps of: acquiring images of a first alignment mark of a first chip and a second alignment mark of a second chip; aligning the first chip and the second chip using the images of the first alignment mark and the second alignment mark so that the first alignment mark and the second alignment mark overlap; and flip-chip mounting the aligned first chip and the second chip, wherein at least one of the first chip and the second chip has a recess, the recess is recessed in a thickness direction relative to a portion of at least one of the first chip and the second chip other than the recess, one of the first alignment mark and the second alignment mark corresponding to the at least one of the first chip and the second chip is provided in the recess, and the acquiring of the images is a step of acquiring the images by photographing the at least one side of the first chip and the second chip. At least one of the first alignment mark and the second alignment mark is provided in the recess. At least one of the first chip and the second chip has a thickness smaller in the recess than in the other area, thereby suppressing the effects of aberration and scattering and improving the visibility of the first alignment mark and the second alignment mark. (10) A method for manufacturing an electronic device, comprising the steps of: acquiring images of a first alignment mark of a first chip and a second alignment mark of a second chip; aligning the first chip and the second chip using the images of the first alignment mark and the second alignment mark so that the first alignment mark and the second alignment mark overlap; and flip-chip mounting the aligned first chip and the second chip, wherein the second chip has a second substrate and a light receiving layer, the light receiving layer is laminated on a portion of the second substrate, the second alignment mark is provided on a portion of the second substrate where the light receiving layer is not laminated, and the acquiring the images is a step of acquiring the images by photographing from the second chip side. This can suppress light absorption by the light receiving layer and improve visibility of the second alignment mark.

[0013] [Details of the embodiment of the present disclosure] Specific examples of electronic devices and manufacturing methods thereof according to embodiments of the present disclosure will be described below with reference to the drawings. Note that the present disclosure is not limited to these examples, but is defined by the claims, and is intended to include all modifications within the meaning and scope of the claims.

[0014] First Embodiment (manufacturing equipment) FIG. 1A is a schematic diagram illustrating a manufacturing apparatus 100 according to the first embodiment. As shown in FIG. 1A, the manufacturing apparatus 100 includes a control unit 10, a light source 20, a stage 21, a camera 22, a filter 24, a beam splitter 26, and a tool 28. The manufacturing apparatus 100 manufactures an electronic device by flip-chip mounting an IC (Integrated Circuit) chip 40 (first chip) and a sensor chip 50 (second chip). The Z-axis direction is the direction of light propagation. The X-axis direction and the Y-axis direction are the directions of extension of the sides when the stage 21, the IC chip 40, and the sensor chip 50 are viewed in a plan view. The Z-axis direction is the direction of light propagation from the beam splitter 26 to the IC chip 40 and the sensor chip 50. The X-axis direction, the Y-axis direction, and the Z-axis direction are mutually orthogonal.

[0015] The main surface of the stage 21 is located in the XY plane. The normal direction of the main surface of the stage 21 is the Z-axis direction. An electronic device 30 is disposed on the main surface of the stage 21. The stage 21 has, for example, a built-in hot plate, and can heat anything placed on the main surface. In the example of FIG. 1A, a sensor chip 50 is placed on the stage 21.

[0016] The beam splitter 26 is located above the stage 21 in the Z-axis direction. The beam splitter 26 includes a half mirror, and transmits a portion of the incident light and reflects another portion in a direction perpendicular to the incident direction.

[0017] The light source 20 faces the beam splitter 26 in the X-axis direction. The light emitted from the light source 20 includes a plurality of lights with different wavelengths. The wavelength is, for example, an infrared band of 800 nm to 1200 nm. The light source 20 is, for example, a superluminescent diode (SLD) light source, a light emitting diode (LED) light source, a halogen light source, or the like.

[0018] Filter 24 is disposed between light source 20 and beam splitter 26, and transmits, for example, light with wavelengths of 1000 nm to 1200 nm and blocks light of other wavelengths. Camera 22 is located above beam splitter 26 in the Z-axis direction. Camera 22 includes, for example, an indium gallium arsenide (InGaAs)-based semiconductor light-receiving element, is sensitive to infrared light, and captures, for example, an alignment mark of electronic device 30.

[0019] 1A represents light. Light emitted from light source 20 enters beam splitter 26. A part of the light is reflected by beam splitter 26, propagates in the Z-axis direction, and enters IC chip 40 and sensor chip 50. Camera 22 captures images of alignment marks provided on IC chip 40 and alignment marks provided on sensor chip 50.

[0020] A lens may be disposed between the light source 20 and the beam splitter 26. A lens may be disposed between the beam splitter 26 and the electronic device 30. Light may be propagated through optical fibers between the light source 20 and the beam splitter 26, between the beam splitter 26 and the IC chip 40, and between the beam splitter 26 and the camera 22.

[0021] The tool 28 is movable in the X-axis, Y-axis, and Z-axis directions. For example, the tool 28 can pick up an object on its tip and transport the object. In the example of FIG. 1A, the tool 28 picks up the IC chip 40 and transports it above the sensor chip 50.

[0022] The control unit 10 includes, for example, a computer, and is electrically connected to the light source 20, the stage 21, the camera 22, and the tool 28. The control unit 10 functions as a light control unit 12, a position acquisition unit 14, a tool control unit 16, and a temperature control unit 18. The light control unit 12 switches the light source 20 on and off, and controls the wavelength of the light emitted from the light source 20. The position acquisition unit 14 acquires an image of the alignment mark captured by the camera 22, and acquires the positions of the IC chip 40 and the sensor chip 50 using the image. The tool control unit 16 controls the on and off of the suction by the tool 28, and the position of the tool 28. The temperature control unit 18 controls the heating by the stage 21, and changes the temperature of the object on the stage 21.

[0023] FIG. 1B is a block diagram showing a hardware configuration of the control unit 10. As shown in FIG. 1B, the control unit 10 includes a CPU (Central Processing Unit) 101, a RAM (Random Access Memory) 102, a storage device 104, and an interface 106. The CPU 101, the RAM 102, the storage device 104, and the interface 106 are connected to one another via a bus or the like. The RAM 102 is a volatile memory that temporarily stores programs, data, and the like. The storage device 104 is, for example, a ROM (Read Only Memory), a solid state drive (SSD) such as a flash memory, a hard disk drive (HDD), or the like. The storage device 104 stores a measurement program, which will be described later, and the like.

[0024] The CPU 101 executes a program stored in the RAM 102, thereby realizing the light control unit 12, the position acquisition unit 14, the tool control unit 16, the temperature control unit 18, and the like in Fig. 1A in the control unit 10. Each unit of the control unit 10 may be hardware such as a circuit.

[0025] (electronic equipment) Fig. 2A is a plan view illustrating an electronic device 30 according to a first embodiment. Fig. 2B is a cross-sectional view taken along line AA in Fig. 2A. Fig. 3 is an enlarged view of the outer periphery of the electronic device 30. A mesa 67 and an insulating film 69, which will be described later, are omitted in Fig. 2B but are illustrated in Fig. 3.

[0026] 2A to 3, the electronic device 30 includes an IC chip 40 and a sensor chip 50. The IC chip 40 and the sensor chip 50 are electrically connected by bumps 34. The sensor chip 50 outputs an electrical signal by receiving infrared light. The IC chip 40 reads the electrical signal output by the sensor chip 50. The electronic device 30 is a light receiving device that senses light such as infrared light.

[0027] 2A, the shape of the IC chip 40 and the shape of the sensor chip 50 in the XY plane are rectangular. The length L1 of the IC chip 40 in the Y-axis direction is, for example, 7.5 mm. The length L2 in the X-axis direction is, for example, 12 mm. The length L3 of the sensor chip 50 in the Y-axis direction is, for example, 4.5 mm. The length L4 in the X-axis direction is, for example, 10 mm.

[0028] 2B, the IC chip 40 and the sensor chip 50 face each other in the Z-axis direction, are spaced apart, and are flip-chip mounted using a plurality of bumps 34. The bumps 34 are made of solder. The gap (distance in the Z-axis direction) between the IC chip 40 and the sensor chip 50 is, for example, approximately 0.016 mm. An underfill 36 is filled between the IC chip 40 and the sensor chip 50. The underfill 36 is, for example, a resin such as epoxy.

[0029] As shown in FIG. 2A, the electronic device 30 has three alignment marks 44 (first alignment marks) and three alignment marks 56 (second alignment marks). The alignment marks 44 and the alignment marks 56 face each other in the Z-axis direction. The alignment marks 44 and 56 are provided at three of the four vertices of the electronic device 30. Two of the three pairs of alignment marks face each other in the X-axis direction. Two of the three pairs of alignment marks face each other in the Y-axis direction.

[0030] (IC chip) The IC chip 40 is a circuit board and has, for example, a readout circuit (ROIC: Readout Integrated Circuit). As shown in FIG. 2B and FIG. 3, the IC chip 40 has a substrate 41 (first substrate), a plurality of electrodes 42, and three alignment marks 44. The substrate 41 is made of, for example, silicon (Si). The refractive index of Si is about 3.5. Of the surfaces of the substrate 41, the surface on the sensor chip 50 side is referred to as surface 46. The surface opposite surface 46 is referred to as surface 45.

[0031] The electrodes 42 are formed of a metal such as gold (Au) and are provided on a surface 46 of the substrate 41. Some of the electrodes 42 are signal electrodes and others are ground electrodes. Bumps 34 are connected to the electrodes 42. The substrate 41 may have wiring patterns, for example, on surfaces 45, 46, and inside the substrate 41.

[0032] The IC chip 40 has a recess 47. The recess 47 is formed, for example, by etching the substrate 41, and is recessed in the thickness direction (Z-axis direction) from the surface 46 toward the surface 45. The thickness T1 of the substrate 41 other than the recess 47 shown in FIG. 3 is, for example, 0.75 mm. The thickness T2 of the substrate 41 based on the bottom surface of the recess 47 is smaller than the thickness T1, for example, 0.35 mm. The depth D1 of the recess 47 based on the surface 46 is, for example, 0.4 mm. The recess 47 may be a groove extending in the XY plane or a hole. For example, the recess 47 is a ring-shaped groove and surrounds the outer periphery of the IC chip 40. For example, the recess 47 is a hole provided near each vertex of the IC chip 40. When the recess 47 is a hole, four recesses 47 are arranged corresponding to the four vertices of the IC chip 40.

[0033] The alignment mark 44 is provided on the bottom surface of the recess 47 and is made of a metal such as Au. The alignment mark 44 is used in the flip-chip mounting process.

[0034] (sensor chip) The sensor chip 50 is a chip having a light receiving element such as an FPA (Focal Plane Array) sensor. As shown in FIG. 2B and FIG. 3, the sensor chip 50 has a substrate 51 (second substrate) and a semiconductor layer 52. The semiconductor layer 52 is provided on a surface of the substrate 51 facing the IC chip 40. Of the surfaces of the sensor chip 50, a surface on the IC chip 40 side is referred to as a surface 58. A surface opposite to the surface 58 is referred to as a surface 57. The surface 57 is coated with an antireflection film 53 for preventing light reflection. The antireflection film 53 is formed of an insulator such as silicon nitride (SiN).

[0035] 3, the semiconductor layer 52 includes an n-type semiconductor layer 60, an absorption layer 62, a semiconductor layer 63, a p-type semiconductor layer 64, and a contact layer 66. The n-type semiconductor layer 60 covers the entire surface of the substrate 51 on the IC chip 40 side.

[0036] 2B and 3, the sensor chip 50 has a mesa 59 on the central side within the XY plane, and a mesa 65 on the outer periphery side within the XY plane. The mesas 59 and 65 protrude toward the IC chip 40 side.

[0037] As shown in FIG. 3, the mesa 59 is formed of an n-type semiconductor layer 60, a light receiving layer 62, and a semiconductor layer 63, which are stacked in this order. A plurality of mesas 67 are provided in the mesa 59, and FIG. 3 illustrates one mesa 67. The plurality of mesas 67 are spaced apart from one another and arranged in an array in the XY plane. The mesas 67 protrude toward the IC chip 40. One mesa 67 corresponds to, for example, one pixel. The mesa 67 is formed of a semiconductor layer 63, a p-type semiconductor layer 64, and a contact layer 66, which are stacked in this order. The height from the surface of the substrate 51 to the tip of the mesa 67 is, for example, 6 μm.

[0038] The mesa 65 faces the recess 47 of the IC chip 40. The mesa 65 is formed of an n-type semiconductor layer 60, an absorption layer 62, and a semiconductor layer 63, which are stacked in this order. The mesa 59 and the mesa 65 are spaced apart. The absorption layer 62, the p-type semiconductor layer 64, and the contact layer 66 are not provided between the mesa 59 and the mesa 65, and the n-type semiconductor layer 60 is provided. The mesa 65 extends in the XY plane and surrounds the outer periphery of the sensor chip 50. Parts of the mesa 65 close to each vertex of the sensor chip 50 protrude upward from the sensor chip 50 more than other parts of the mesa 65. The width of the mesa 65 is, for example, 90 μm. Four mesas 65 may be provided at each vertex of the sensor chip 50. The insulating film 69 covers the surface 58, the mesa 59, the mesa 65, and the multiple mesas 67.

[0039] The substrate 51 is a semiconductor substrate made of, for example, indium phosphide (InP). The thickness T3 of the substrate 51 is, for example, 0.5 mm. The n-type semiconductor layer 60 is made of, for example, n-type InP. The p-type semiconductor layer 64 is made of, for example, p-type InP. The refractive index of InP is about 3. The light-receiving layer 62 is made of, for example, indium gallium arsenide (InGaAs). The semiconductor layer 63 is made of, for example, indium gallium arsenide phosphide (InGaAsP). The contact layer 66 is made of, for example, p-type InGaAs. The substrate 51 and the semiconductor layer 52 may be made of compound semiconductors other than those mentioned above.

[0040] The band gaps of the substrate 51, the n-type semiconductor layer 60, the semiconductor layer 63, and the p-type semiconductor layer 64 are larger than the energy of infrared light. The infrared light absorptances of the substrate 51, the n-type semiconductor layer 60, the semiconductor layer 63, and the p-type semiconductor layer 64 are lower than those of the light receiving layer 62. The infrared light absorptance of the light receiving layer 62 is higher than those of the other layers. Infrared light easily passes through the substrate 51, the n-type semiconductor layer 60, the semiconductor layer 63, and the p-type semiconductor layer 64, and is easily absorbed by the light receiving layer 62. The light receiving layer 62 absorbs infrared light and generates electrons and holes.

[0041] The sensor chip 50 has a plurality of electrodes 54. One electrode 54 is provided at the tip of one mesa 67. The electrode 54 is formed of a metal such as Au. Some of the plurality of electrodes 54 are signal electrodes and the other are ground electrodes. The signal electrodes 54 are electrically connected to the contact layer 66. The electrode 54, which is a ground electrode, is insulated from the contact layer 66 and is electrically connected to the n-type semiconductor layer 60 by a wiring (not shown). The electrode 54 is electrically connected to the electrode 42 of the IC chip 40 by the bump 34.

[0042] The alignment mark 56 is the tip of the mesa 65, and is disposed in an opening of the insulating film 69. The alignment mark 56 is made of a metal such as gold (Au). The alignment mark 56 is used in the process of flip-chip mounting.

[0043] FIG. 4A is a plan view illustrating an alignment mark 44 of the IC chip 40. As shown in FIG. 4A, the shape (planar shape) of the alignment mark 44 in the XY plane is, for example, a circular ring shape. The diameter D2 of the alignment mark 44 is, for example, 80 μm. FIG. 4B is a plan view illustrating an alignment mark 56 of the sensor chip 50. As shown in FIG. 4B, the planar shape of the alignment mark 56 is, for example, a circle. The diameter D3 of the alignment mark 56 is smaller than the diameter D2 of the alignment mark 44, and is, for example, 50 μm.

[0044] (Manufacturing method) Fig. 5 is a flow chart illustrating a method for manufacturing the electronic device 30. Figs. 6A to 6C are cross-sectional views illustrating a method for manufacturing the electronic device 30. Figs. 7A and 7B are enlarged plan views of the alignment marks 44 and 56.

[0045] 6A and 6B show the IC chip 40 and the sensor chip 50 before flip-chip mounting. The IC chip 40 before flip-chip mounting has a plurality of bumps 37. The bumps 37 are provided on the surface of the electrodes 42. The sensor chip 50 has a plurality of bumps 38. The bumps 38 are provided on the surface of the electrodes 54. The bumps 37 and 38 are made of solder. The IC chip 40 and the sensor chip 50 are exposed to air.

[0046] As shown in FIG. 5, the tool control unit 16 of the manufacturing apparatus 100 aligns the IC chip 40 and the sensor chip 50 (step S10). As shown in FIG. 6A, the sensor chip 50 is located on the stage 21. The IC chip 40 is sucked by the tool 28, and the IC chip 40 is moved onto the sensor chip 50. The light source 20 and the camera 22 shown in FIG. 1A are located on the surface 45 side of the IC chip 40. Infrared light is irradiated from the light source 20 toward the surface 45 side. The camera 22 shown in FIG. 6A observes the IC chip 40 and the sensor chip 50 from the surface 45 side, and takes images of the alignment marks 44 and 56. The camera 22 takes images of each of the three pairs of the alignment marks 44 and the alignment marks 56 shown in FIG. 2A.

[0047] The infrared light enters the substrate 41 from the surface 45, passes through the substrate 41, and is irradiated to the alignment marks 44 and 56. The substrate 41 is made of Si and is exposed to air. Due to the difference in refractive index between Si and air, the image is affected by aberration. The infrared light is scattered by the substrate 41. The thicker the substrate 41 is, the greater the effects of aberration and scattering. As shown in FIG. 3, the alignment mark 44 is provided in the recess 47 of the IC chip 40. The thickness T2 based on the bottom surface of the recess 47 is smaller than the thickness T1 outside the recess 47. Compared to the infrared light irradiated to the portion other than the recess 47, the infrared light irradiated to the recess 47 is less affected by the substrate 41. The decrease in visibility of the image due to aberration and scattering is suppressed. In other words, the images of the alignment marks 44 and 56 become clearer. The tool control unit 16 acquires the image and performs alignment based on the image. For example, as shown in Fig. 7A, the alignment mark 44 and the alignment mark 56 are aligned so that they overlap and the alignment mark 56 is disposed inside the alignment mark 44. In each of the three positions shown in Fig. 2A, the alignment mark 44 and the alignment mark 56 overlap as shown in Fig. 7A.

[0048] The tool 28 lowers the IC chip 40 toward the sensor chip 50, and brings the bumps 37 of the IC chip 40 into contact with the bumps 38 of the sensor chip 50 (step S12, FIG. 6B).

[0049] The position acquisition unit 14 acquires the coordinates (X1, Y1) of the center of the alignment mark 44 and the coordinates (X2, Y2) of the center of the alignment mark 56 from the images of the alignment mark 44 and the alignment mark 56, and acquires the distance D4 between the centers (step S14). The distance D4 between the centers is calculated, for example, by the following formula. D4 = ((X1-X2) 2 +(Y1-Y2) 2 ) 1 / 2 The coordinates (X1, Y1) of the center of the alignment mark 44, the coordinates (X2, Y2) of the center of the alignment mark 56, and the distance D4 are measured for each of the three pairs of the alignment mark 44 and the alignment mark 56. A straight line connecting two of the three pairs is calculated, and the inclination angle of the straight line is obtained, thereby obtaining the relative inclination between the sensor chip 50 and the IC chip 40.

[0050] The manufacturing apparatus 100 performs reflow (step S16). The temperature control unit 18 uses the stage 21 to heat the bumps 37 and 38 to a temperature equal to or higher than the melting point of the solder, causing them to melt. When the bumps 37 and 38 are in a melted state, the tool 28 stops sucking the IC chip 40. Due to the surface tension of the bumps 37 and 38, the position of the IC chip 40 moves within the XY plane, and self-alignment is performed. After self-alignment, the bumps 37 and 38 are cooled to a temperature equal to or lower than the melting point, and solidify, forming the bumps 34. The flip-chip mounting of the IC chip 40 and the sensor chip 50 is completed.

[0051] As shown in FIG. 7B, the alignment mark 56 moves toward the center of the alignment mark 44 by self-alignment. The camera 22 captures images of the alignment mark 44 and the alignment mark 56 after flip-chip mounting. The position acquisition unit 14 acquires the center position of the alignment mark 44 and the center position of the alignment mark 56 from the images, and acquires the distance D5 between the centers (step S18 in FIG. 5). The method of calculating the distance D5 is the same as the method of calculating the distance D4 in step S14. The distance D5 is measured for each of the three pairs of the alignment mark 44 and the alignment mark 56. Since the distance D5 acquired in step S18 is different from the distance D4 acquired in step S14, it is confirmed that the bumps have melted and self-alignment has been performed. For example, since the distance D5 is within the tolerance range, it is understood that the positions of the IC chip 40 and the sensor chip 50 are appropriate. After flip-chip mounting, the gap between the IC chip 40 and the sensor chip 50 is filled with underfill 36.

[0052] According to the first embodiment, the alignment mark 44 is provided in the recess 47 of the IC chip 40. The thickness T2 of the substrate 41 based on the bottom surface of the recess 47 is smaller than the thickness T1 of the portion other than the recess 47. The infrared light passes through the substrate 41 having the thickness T2 and is irradiated onto the alignment marks 44 and 56. The camera 22 receives the infrared light and captures images of the alignment marks 44 and 56. Since the substrate 41 is thin in the recess 47, the effects of aberration and scattering are suppressed, and the image becomes clear. The contrast between the alignment marks 44 and 56 and the portions other than the alignment marks is increased, and the visibility of the alignment marks 44 and 56 is improved. While checking the images of the alignment marks 44 and 56, the IC chip 40 and the sensor chip 50 can be accurately aligned and flip-chip mounted. The accuracy of the position measurement after flip-chip mounting is also improved.

[0053] The visibility of the alignment marks can also be improved by polishing the entire substrate 41 to make it thinner. However, the strength of the substrate 41 decreases and it becomes more susceptible to breakage. The polishing process is costly. In the first embodiment, as shown in FIG. 3, a recess 47 is provided in a part of the substrate 41, and the substrate 41 is thick in the part other than the recess 47. Since the part of the substrate 41 other than the recess 47 is thick, the decrease in the strength of the substrate 41 is suppressed, and the substrate 41 becomes less susceptible to breakage. Compared to the cost of the process of polishing the entire substrate 41, the cost of the process of providing the recess 47 by etching a part of the substrate 41 is lower.

[0054] The depth D1 of the recess 47 is preferably, for example, equal to or greater than half the thickness T1 of the substrate 41. When the thickness T2 is equal to or less than half the thickness T1, the influence of aberration and scattering can be effectively reduced. The recess 47 may extend from the surface 46 to the surface 45 as shown in FIG. 3, or may extend from the surface 45 to the surface 46.

[0055] As shown in FIG. 2B, the sensor chip 50 has a recess 47 and three alignment marks 44 on the outer periphery. The IC chip 40 has three alignment marks 56 on the outer periphery. Images of the alignment marks 44 and 56 are taken at three locations to perform alignment. The rotation angle between the IC chip 40 and the sensor chip 50 in the XY plane can be obtained. By overlapping the three alignment marks 44 and the three alignment marks 56, the IC chip 40 and the sensor chip 50 can be aligned in parallel in the X-axis direction and the Y-axis direction. The number of the alignment marks 44 and the number of the alignment marks 56 may be three or less, or may be three or more, and is preferably more than one.

[0056] The substrate 41 may be made of Si or may be made of a material other than Si. The refractive index of the substrate 41 is different from that of air. For example, the refractive index of the substrate 41 made of Si is about 3.5, which is higher than that of air. Although there is a refractive index difference between the substrate 41 and air, the thickness T2 is smaller than the thickness T1, so that the influence of aberration can be suppressed.

[0057] The alignment marks 44 and 56 are made of metal. A high contrast is obtained between the metal alignment marks 44 and 56 and the Si substrate 41. The visibility of the alignment marks 44 and 56 is improved. The shape of the alignment mark 44 may be changed from that in FIG. 4A. The shape of the alignment mark 56 may be changed from that in FIG. 4B. The sensor chip 50 and the IC chip 40 are aligned so that one of the alignment marks 44 and 56 is inside the other.

[0058] The IC chip 40 is a circuit board including a read circuit (ROIC). The sensor chip 50 is an array chip that includes a plurality of mesas 67 and detects infrared light. The electronic device 30 may include a chip other than the IC chip 40, or may include a chip other than the sensor chip 50.

[0059] The light source 20 may emit light other than infrared light. The camera 22 only needs to have sensitivity to the light emitted by the light source 20.

[0060] <Second embodiment> Fig. 8 is an enlarged view of the outer periphery of the electronic device 30a according to the second embodiment, in which the sensor chip 50 is located on the upper side and the IC chip 40 is located on the lower side, opposite to Fig. 3. Descriptions of the same configuration as in the first embodiment will be omitted.

[0061] (IC chip) 8, the IC chip 40 does not have a recess 47. The alignment mark 44 is provided on a surface 46 of the substrate 41.

[0062] (sensor chip) As shown in FIG. 8, the sensor chip 50 has a mesa 59 in the center in the XY plane, and has a recess 70 in the outer periphery without a mesa. The recess 70 is provided near three of the four vertices in the XY plane of the substrate 51. The recess 70 is recessed in the Z-axis direction from the surface 58 side toward the surface 57 side. For example, the substrate 51 is etched to form the recess 70. No semiconductor layer such as the light-receiving layer 62 is stacked on the bottom surface of the recess 70, and the InP surface of the substrate 51 is exposed. The alignment mark 56 is spaced from the light-receiving layer 62 in the XY plane and provided on the bottom surface of the recess 70.

[0063] The thickness T3 of the substrate 51 is, for example, 0.5 mm. The thickness T4 of the substrate 51 based on the bottom surface of the recess 70 is smaller than the thickness T3 and is, for example, 0.3 mm. The depth D6 of the recess 70 is, for example, 0.2 mm.

[0064] The manufacturing apparatus 100 shown in Fig. 1A is also used in the second embodiment. The process of Fig. 5 is also performed in the second embodiment. In the second embodiment, the IC chip 40 is placed on the stage 21. The sensor chip 50 is carried onto the IC chip 40 by using the tool 28.

[0065] The light source 20 and the camera 22 are located on the surface 57 side of the sensor chip 50. The infrared light emitted from the light source 20 enters the IC chip 40 from the surface 57. Since the light receiving layer 62 is not provided in the recess 70, the absorption of the infrared light is suppressed. The infrared light enters the alignment marks 56 and 44 while maintaining a high intensity. Since the thickness T4 is smaller than the thickness T3, the influence of the infrared light on the substrate 51 is suppressed. The camera 22 observes the sensor chip 50 and the IC chip 40 from the surface 57 and takes images of the alignment marks 44 and 56. Since the absorption by the light receiving layer 62 is suppressed and the influence of aberration and scattering is suppressed, a clear image can be obtained. The images of the alignment marks 56 and 44 are used to align the IC chip 40 and the sensor chip 50.

[0066] According to the second embodiment, the alignment mark 56 is provided in the recess 70. The thickness T4 of the substrate 51 based on the bottom surface of the recess 70 is smaller than the thickness T3 in other parts, and the influence of aberration and scattering due to the substrate 51 can be suppressed. Since the light receiving layer 62 is not provided in the recess 70, the absorption of infrared light by the light receiving layer 62 can be suppressed. The images of the alignment marks 44 and 56 become clearer, and the visibility is improved.

[0067] The first and second embodiments may be combined. The IC chip 40 has a recess 47. An alignment mark 44 is provided in the recess 47. The sensor chip 50 has a recess 70 at a position facing the recess 47. An alignment mark 56 is provided in the recess 70. Infrared light may be irradiated from either the IC chip 40 side or the sensor chip 50 side, and observed with the camera 22.

[0068] <Third embodiment> 9 is an enlarged view of the outer periphery of an electronic device 30b according to the third embodiment. Description of the same configuration as in the first or second embodiment will be omitted. The configuration of the IC chip 40 is the same as in the second embodiment.

[0069] (sensor chip) The sensor chip 50 has a mesa 59 in the center in the XY plane, and does not have a mesa 59 or a recess 70 on the periphery. An n-type semiconductor layer 60 is laminated on the periphery of the substrate 51, and other semiconductor layers such as a light-receiving layer 62 are not laminated on the periphery. The alignment mark 56 is spaced from the light-receiving layer 62 in the XY plane, and is provided on the surface of the n-type semiconductor layer 60.

[0070] The manufacturing apparatus 100 shown in Fig. 1A is also used in the third embodiment. The process of Fig. 5 is also performed in the third embodiment. In the third embodiment, the IC chip 40 is placed on the stage 21. The sensor chip 50 is carried onto the IC chip 40 by using the tool 28.

[0071] The light source 20 and the camera 22 are located on the surface 57 side of the sensor chip 50. The infrared light emitted from the light source 20 enters the sensor chip 50 from the surface 57. Since the light receiving layer 62 is not provided at a position overlapping with the alignment mark 56 in the Z-axis direction, absorption of the infrared light is suppressed. The infrared light enters the alignment marks 56 and 44 while maintaining a high intensity. The camera 22 observes the sensor chip 50 and the IC chip 40 from the surface 57 and captures images of the alignment marks 44 and 56. Absorption by the light receiving layer 62 is suppressed, and a clear image can be obtained. The IC chip 40 and the sensor chip 50 are aligned using the images of the alignment marks 56 and 44.

[0072] According to the third embodiment, the alignment mark 56 is provided in a portion where the light receiving layer 62 is not provided. It is possible to suppress absorption of infrared light by the light receiving layer 62. The images of the alignment marks 44 and 56 become clearer, improving visibility.

[0073] The first and third embodiments may be combined. The IC chip 40 has a recess 47, and an alignment mark 44 is provided in the recess 47. An alignment mark 56 is provided in a portion of the sensor chip 50 where the light receiving layer 62 is not present. Infrared light may be irradiated from either the IC chip 40 side or the sensor chip 50 side, and observed with the camera 22.

[0074] Although the embodiments of the present disclosure have been described in detail above, the present disclosure is not limited to such specific embodiments, and various modifications and variations are possible within the scope of the gist of the present disclosure described in the claims. [Explanation of symbols]

[0075] 10 Control section 12 Light control section 14 Position acquisition part 16 Tool control section 18 Temperature control unit 20 light source 21 Stage 22 Camera 24 Filters 26 Beam splitter 28 Tools 30, 30a, 30b electronic equipment 34, 37, 38 Bump 36 Underfill 40 IC chip 41, 51 Board 42, 54 electrodes 44, 56 Alignment marks 45, 46, 57, 58 sides 47, 70 Recess 50 Sensor Chips 52, 63 Semiconductor layer 53 Anti-reflection coating 59, 65, 67 Mesa 60 n-type semiconductor layer 62 Light-receiving layer 64 p-type semiconductor layer 66 Contact Layer 69 Insulating Film 100 Manufacturing equipment 101 CPU 102 RAM 104 Storage device 106 Interface

Claims

1. A first chip; a second chip; the first chip and the second chip are electrically connected to each other using bumps; the first chip has a first alignment mark; the second chip has a second alignment mark; the first alignment mark and the second alignment mark face each other, The first chip has a first substrate; the first substrate has a recess; the recess is recessed in a thickness direction relative to a portion of the first chip other than the recess, The first alignment mark is provided in the recess.

2. The electronic device of claim 1 , wherein the first substrate is made of silicon.

3. A first chip; a second chip; the first chip and the second chip are electrically connected to each other using bumps; the first chip has a first alignment mark; the second chip has a second alignment mark; the first alignment mark and the second alignment mark face each other, the second chip has a second substrate and a light receiving layer; the second substrate has a recess; the recess is recessed in a thickness direction relative to a portion of the second chip other than the recess; the second alignment mark is provided in the recess; The light receiving layer is laminated on a portion of the second substrate other than the recess.

4. A first chip; a second chip; the first chip and the second chip are electrically connected to each other using bumps; the first chip has a first substrate and a first alignment mark; the first substrate has a recess; the recess is recessed in a thickness direction relative to a portion of the first chip other than the recess, the first alignment mark is provided in the recess, the second chip has a second substrate, a light receiving layer, and a second alignment mark; the first alignment mark and the second alignment mark face each other, The second alignment mark is provided at a position within a surface of the second chip, the position being spaced apart from the light receiving layer.

5. the second substrate comprises indium phosphide; 5. The electronic device of claim 3, wherein the light-receiving layer comprises indium gallium arsenide.

6. The electronic device according to claim 1 , wherein the first alignment mark and the second alignment mark are made of a metal.

7. the first chip has a plurality of the first alignment marks; The electronic device according to claim 1 , wherein the second chip has a plurality of the second alignment marks.

8. acquiring an image of a first alignment mark of the first chip and an image of a second alignment mark of the second chip; aligning the first chip and the second chip using images of the first alignment mark and the second alignment mark so that the first alignment mark and the second alignment mark overlap; and flip-chip mounting the aligned first chip and second chip, The first chip has a first substrate; the first substrate has a recess; the recess is recessed in a thickness direction relative to a portion of the first chip other than the recess, the first alignment mark is provided in the recess, A method for manufacturing an electronic device, wherein the step of acquiring the image is a step of acquiring the image by photographing from the side of the first chip.

9. acquiring an image of a first alignment mark of the first chip and an image of a second alignment mark of the second chip; aligning the first chip and the second chip using images of the first alignment mark and the second alignment mark so that the first alignment mark and the second alignment mark overlap; and flip-chip mounting the aligned first chip and second chip, the second chip has a second substrate and a light receiving layer; the second substrate has a recess; the recess is recessed in a thickness direction relative to a portion of the second chip other than the recess; the second alignment mark is provided in the recess, the light receiving layer is laminated on a portion of the second substrate other than the recessed portion, A method for manufacturing an electronic device, wherein the step of acquiring the image is a step of acquiring the image by photographing from the side of the second chip.

10. acquiring an image of a first alignment mark of the first chip and an image of a second alignment mark of the second chip; aligning the first chip and the second chip using images of the first alignment mark and the second alignment mark so that the first alignment mark and the second alignment mark overlap; and flip-chip mounting the aligned first chip and second chip, The first chip has a first substrate; the first substrate has a recess; the recess is recessed in a thickness direction relative to a portion of the first chip other than the recess, the first alignment mark is provided in the recess; the second chip has a second substrate and a light receiving layer; the light receiving layer is laminated on a portion of the second substrate, the second alignment mark is provided in a portion of the second substrate on which the light receiving layer is not laminated, The method for manufacturing an electronic device, wherein the step of acquiring the image is a step of acquiring the image by photographing from the second chip side.

11. acquiring an image of a first alignment mark of the first chip and an image of a second alignment mark of the second chip; aligning the first chip and the second chip using images of the first alignment mark and the second alignment mark so that the first alignment mark and the second alignment mark overlap; and flip-chip mounting the aligned first chip and second chip, the second chip has a second substrate and a light receiving layer; the second substrate has a recess; the recess is recessed in a thickness direction relative to a portion of the second chip other than the recess; the light receiving layer is laminated on a portion of the second substrate other than the recessed portion, the second alignment mark is provided in the recess; The method for manufacturing an electronic device, wherein the step of acquiring the image is a step of acquiring the image by photographing from the second chip side.

Images