Semiconductor cell block having a cell height that is a multiple of a non-integer value - Patents.com

Abstract

To provide a semiconductor cell block having improved reliability, and a layout forming method.SOLUTION: A semiconductor cell block has a plurality of layers arranged in a stack, a first semiconductor logic cell having a first cell height in one of the plurality of layers, and a second semiconductor logic cell having a second cell height in one of the plurality of layers. The plurality of layers includes one or more first layers each having a first height and one or more second layers each having a second height, the second cell height is greater than the first cell height, and the second cell height is a multiple of a non-integer value of the first cell height.SELECTED DRAWING: Figure 1a

Description

[Technical field]

[0001] Aspects of the present invention generally relate to semiconductor cell blocks and methods of forming layouts for semiconductor cell blocks. [Background technology]

[0002] Prior art semiconductor cell blocks typically include semiconductor logic cells each having the same height or an integer multiple of the same height (e.g., dual-height or triple-height). For example, one semiconductor cell block of a chip may include semiconductor logic cells having a first height and semiconductor logic cells having a second height that is an integer multiple of the first height. Another semiconductor cell block of the chip may include semiconductor logic cells having a third height and an integer multiple of the third height. Summary of the Invention [Problem to be solved by the invention]

[0003] An object of the present invention is to provide a semiconductor cell block having improved reliability.

[0004] The problems to be solved by the present invention are not limited to those mentioned above, and other problems not mentioned will be clearly understood by those skilled in the art from the following description. [Means for solving the problem]

[0005] Aspects of the invention relate to various embodiments of a semiconductor cell block, in one embodiment, including a plurality of layers arranged in a stack, a first semiconductor logic cell in one of the layers having a first cell height, and a second semiconductor logic cell in one of the layers having a second cell height, the plurality of layers including one or more first layers each having the first height and one or more second layers each having the second height, the second cell height being greater than the first cell height, and the second cell height being a non-integer multiple of the first cell height.

[0006] Non-integer multiples may range from 1.1 to 1.9.

[0007] The first semiconductor logic cell may be located in one of the one or more first layers and the second semiconductor logic cell may be located in one of the one or more second layers.

[0008] The one or more first layers may include pairs of first layers laminated directly to one another.

[0009] The one or more first layers may include a plurality of first layers, and the one or more second layers may include a plurality of second layers, and the number of the plurality of first layers may be even greater than the number of the plurality of second layers.

[0010] The plurality of second layers may be regularly arranged in the stack, and each pair of adjacent second layers in the plurality of second layers may be spaced apart from each other by a same number of first layers in the plurality of first layers.

[0011] The number of first layers of the same number can be an even number.

[0012] The semiconductor cell block may further include a third semiconductor logic cell having a third height, where the third height may be an integer multiple of the first cell height.

[0013] The one or more first layers may include a plurality of first layers, and the third semiconductor logic cell may be located in a first layer adjacent a pair of the plurality of first layers.

[0014] The block of semiconductor cells may further include at least one power rail coupled to the first and second semiconductor logic cells.

[0015] At least one of the power rails may be a buried power rail.

[0016] The first and second semiconductor logic cells may include different types of logic cells.

[0017] The first width of the first semiconductor logic cell and the second width of the second semiconductor logic cell may be integer multiples of each other.

[0018] Aspects of the invention also relate to various embodiments of a computer-implemented method for generating a layout for a block of semiconductor cells. According to one embodiment, a method includes placing a first semiconductor cell in a first one of the layers of a stack and a second semiconductor cell in a second one of the layers of the stack using a placement and routing tool, placing pins on each of the first and second semiconductor cells using the placement and routing tool, placing vias coupled to the pins using the placement and routing tool, and placing a metal routing layer coupled to the vias using the placement and routing tool, wherein the first semiconductor cell has a first height and the second semiconductor cell has a second height greater than the first height, and the second cell height may be a non-integer multiple of the first cell height.

[0019] Non-integer multiples may range from 1.1 to 1.9.

[0020] The first layer may have a first height and the second layer may have a second height, which may be greater than the first height and which may be a non-integer multiple of the first height.

[0021] The method may further include placing at least one power rail on a layer of the stack using a place and route tool.

[0022] The method may further include placing a third semiconductor logic cell in the stack using the place and route tool, the third cell height being an integer multiple of the first cell height.

[0023] The first layer may be one of a plurality of first layers, where the plurality of first layers may include a pair of first layers directly laminated to one another, and the second layer may be one of a plurality of second layers, where the second layers are located between adjacent pairs of the first layers.

[0024] The multiple first layers of the plurality of first layers may be greater than the multiple second layers of the plurality of second layers.

[0025] This Summary is provided to introduce a selection of features and concepts of embodiments of the invention that are further described below in the Detailed Description. This Summary is not intended to identify key or essential features of the claimed subject matter, nor is it intended to be used to limit the scope of the claimed subject matter. One or more of the described features can be combined with one or more other described features to provide a workable device. [Brief description of the drawings]

[0026] Embodiments and other features and advantages of the present invention will become more apparent by reference to the following detailed description when considered in conjunction with the following drawings, in which like reference numerals are used to refer to like features and components throughout the drawings, and in which such numerals are not necessarily drawn to scale. [Figure 1a] 2 is a schematic diagram of a semiconductor cell block according to an embodiment of the present invention; [Figure 1b] 11 is a schematic diagram of a semiconductor cell block according to another embodiment of the present invention; [Figure 1c] 11 is a schematic diagram of a semiconductor cell block according to still another embodiment of the present invention; [Diagram 2] 4 is a flow diagram illustrating tasks of a method for forming a layout for a block of semiconductor cells in accordance with an embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0027] Aspects of the present invention include various embodiments of a semiconductor cell block including at least one semiconductor logic cell having a first height and at least one semiconductor logic cell having a height that is an integer multiple of the height of at least one other semiconductor logic cell of the semiconductor cell block. Thus, the semiconductor cell block according to various embodiments of the present invention can support both a lowest driver cell in the lowest height semiconductor logic cell and a larger driver cell in the larger semiconductor logic cell. Furthermore, the semiconductor cell block according to various embodiments of the present invention allows different device architectures to be located in the same semiconductor cell block. Aspects of the present invention also include various systems and methods for designing a layout of a semiconductor cell block including at least one semiconductor logic cell having a first height and at least one semiconductor logic cell having a second height that is greater than the first height and a non-integer multiple of the first height.

[0028] Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the technical idea of ​​the present invention can be embodied in various different forms, and should not be construed as being limited to only the embodiments described in this description. Rather, such embodiments are provided as examples so that the technical idea of ​​the present invention can be thoroughly and completely conveyed to those skilled in the art the aspects and characteristics of the technical idea of ​​the present invention. Therefore, steps, elements and techniques that are not necessary for those skilled in the art to fully understand the aspects and characteristics of the technical idea of ​​the present invention may not be described. Unless otherwise specified, the same drawing symbols indicate the same elements throughout the accompanying drawings and detailed description, and therefore the description thereof will not be repeated.

[0029] In the drawings, the relative sizes of components, layers and regions may be exaggerated and / or simplified for clarity. Spatially relative terms such as "beneath," "below," "lower," "under," "above," "upper," and the like are used herein for convenience of description to easily describe the relationship of an element or feature to the element(s) or feature(s) as shown in the drawings. It will be understood that such spatially relative terms are intended to include other orientations of the device in use or operation in addition to the orientation shown in the drawings. For example, if the device in the drawings is turned over, components described as "beneath" or "below" or "under" other elements or features would be oriented "above" the other components or features. Thus, the exemplary terms "below" and "under" can include both an orientation of above and below. Thus, the device may be otherwise oriented (eg, rotated 90 degrees or to other orientations) and the spatially relative descriptors used herein should be interpreted accordingly.

[0030] In this specification, terms such as "first", "second", "third", etc. are used to describe various components, components, regions, layers and / or sections, but these components, components, regions, layers and / or sections are not limited by these terms. These terms are used only to distinguish one component, component, region, layer or section from another component, component, region, layer or section. Thus, a first component, component, region, layer or section described below may be referred to as a second component, component, region, layer or section without departing from the spirit and scope of the present invention.

[0031] When a component or layer is referred to as "on," "connected to," or "coupled to" another component or layer, it can be directly connected, coupled, or bonded to the other component or layer, or there can be one or more intervening components or layers. Also, when a component or layer is referred to as being "between" two components or layers, there can be only one component or layer between the two components or layers, or there can be one or more intervening components or layers.

[0032] The terms used herein are for the purpose of describing particular embodiments and are not intended to limit the invention. As used herein, the singular forms "a," "an," and "the" are intended to include the plural forms unless the context clearly dictates otherwise. As used herein, the terms "comprises" and / or "comprising" refer to the presence of stated features, integers, steps, operations, components, and / or configurations, but do not preclude the additional presence of one or more other features, integers, steps, operations, elements, components, and / or configurations. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. Expressions such as "at least one" before a list of components modify the entire list of components and not the individual members of the list.

[0033] As used herein, the terms "substantially," "about," and similar terms are used as terms of approximation and not as terms of degree, and are intended to account for inherent variations in measured or calculated values ​​that may be recognized thereby. In addition, the use of "may" when describing an embodiment of the inventive concept means "one or more embodiments of the invention." As used herein, the terms "use," "using," and "used" may be considered synonymous with "utilize," "utilizing," and "utilized," respectively. In addition, the term "for example" refers to an example or illustration.

[0034] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those skilled in the art to which the present invention belongs. Furthermore, terms defined in commonly used dictionaries should be interpreted as having a meaning consistent with the meaning in the context of the relevant art and / or this specification, and should not be interpreted in an ideal or overly formal sense unless expressly defined herein.

[0035] 1a, a semiconductor cell block 100 according to one embodiment of the present invention includes a series of layers (101 and 102) (i.e., one or more first layers 101 and one or more second layers 102) stacked together to form a stack 103, and a series of semiconductor logic cells (104-106 and / or 107) located within at least a portion of the layers (101 and 102). Although in one or more embodiments, the semiconductor cell block 100 includes respective semiconductor logic cells (104-107), in one or more embodiments, the semiconductor cell block 100 may include any suitable combination of semiconductor logic cells 104-107. The layers (101 and 102) may correspond to front-end-of-line (FEOL) layers, middle-of-line (MOL) layers, and / or back-end-of-line (BEOL) layers of the semiconductor cell block 100 (e.g., insulating layer V-2, metal layer Mint on insulating layer V-1, insulating layer V-1 on metal layer Mint, metal layer M0 on insulating layer V-1, insulating layer V0 on metal layer M0, metal layer M1 on insulating layer V0, insulating layer V1 on metal layer M1, metal layer M2 on insulating layer V1, insulating layer V2 on metal layer M2, etc.).

[0036] The semiconductor logic cells 104-107 may be any type(s) of cell(s), such as, for example, an inverter, a NAND gate, a NOR gate, a counter, a flip flop, other logic circuits, or a combination thereof. The semiconductor logic cells 104-107 may have different device architectures, such as, for example, a fin or sheet-based device (e.g., a fin field effect transistor (finFET) or a nanosheet transistor, such as a horizontal nanosheet field effect transistor or a vertical field effect transistor (VFET)). Throughout the drawings, the semiconductor logic cells 104-107 are shown in a schematic manner, and components of the semiconductor logic cells 104-107 (e.g., source / drain electrodes and gates) are omitted for simplicity of the drawings.

[0037] In the illustrated embodiment, the stack 103 includes a series of first layers 101 each having a first height H1, and a series of second layers 102 each having a second height H2 greater than the first height H1. In one or more embodiments, the second height H2 of the second layers 102 is a non-integer multiple of the first height H1 of the first layers 101. For example, in one or more embodiments, the second height H2 of the second layers 102 may be greater than the first height H1 of the first layers 101, and the non-integer multiple of the first height H1 may be in the range of about 1.1 to about 1.9, such as about 1.1, about 1.15, about 1.2, about 1.3, about 1.4, about 1.5, about 1.6, about 1.8, or the like.

[0038] In the illustrated embodiment, each of the semiconductor logic cells 104-107 has a height that is the same or substantially the same as a height H1 of the first layer 101, a height that is the same or substantially the same as a height H2 of the second layer 102, or a height that is the same or substantially the same as a combined height of two or more adjacent layers (101 and 102) in the stack 103. For example, in the illustrated embodiment, the semiconductor cell block 100 includes at least one first semiconductor cell 104 located in one of the first layers 101 and having a first cell height h1 that is the same or substantially the same as a height H1 of the first layer 101 in which the first semiconductor cell 104 is located, and at least one second semiconductor cell 105 located in one of the second layers 102 and having a second cell height h2 that is the same or substantially the same as a height H2 of the second layer 102 in which the second semiconductor cell 105 is located. Thus, in the illustrated embodiment, the second cell height h2 of the semiconductor logic cells 105 in the second layer 102 is greater than the first cell height h1 of the semiconductor logic cells 104 in the first layer 101, and the second cell height h2 is a non-integer multiple of the first cell height h1. For example, in one or more embodiments, the second cell height h2 of the semiconductor logic cells 105 in the second layer 102 is greater than the first cell height h1 of the semiconductor logic cells 104 in the first layer 101, and the second cell height h2 is a non-integer multiple of the first cell height h1 in the range of about 1.1 to about 1.9.

[0039] In the illustrated embodiment, the stack 103 of the semiconductor cell block 100 includes a pair of first layers 101 stacked directly on top of one another and a single second layer 102 on the pair of first layers 101 stacked in a repeating pattern. In one or more embodiments, the semiconductor cell block 100 may include any other suitable arrangement (e.g., pattern) of the first and second layers (101 and 102) depending, for example, on the size and type of semiconductor logic cells 104-107 in the semiconductor cell block 100. For example, in one or more embodiments, the number of first layers 101 in the semiconductor cell block 100 is greater than the number of second layers 102 in the semiconductor cell block 100. In one or more embodiments, the semiconductor cell block 100 may include any number of first layers 101 between adjacent layers (e.g., two, three, or four first layers 101 between a pair of adjacent second layers 102) of second layers 102 having cell heights that are a multiple of an integer value (e.g., double-height, triple-height, or quadruple-height semiconductor cells) (and vice versa). Also, although in the illustrated embodiment, the stack 103 includes two different types of layers each having a different height (i.e., a first layer 101 having a first height H1 and a second layer 102 having a second height H2), in one or more embodiments, the stack 103 may include any other suitable number of different types of layers each having a different height (e.g., three or more types of layers each having a different height), and the three or more different types of layers may be arranged in any suitable pattern in the stack 103.

[0040] In one or more embodiments, the semiconductor cell block 100 may include first layers 101 with any even or odd number between adjacent second layers 102. FIG. 1b illustrates an embodiment of a semiconductor cell block 100 in which a stack 103 includes a repeating pattern of four first layers 101 stacked directly on top of one another and one second layer 102 on the four stacked first layers 101. In one or more embodiments, the stack 103 may have a number of adjacent first layers 101 depending on the desired height h3 of the semiconductor logic cell(s) 106 in the adjacent first layers 101 (e.g., where the desired height corresponds to an integer multiple of the height H1 of the first layers 101). Additionally, although in the illustrated embodiment adjacent second layers 102 are separated from one another by two or more first layers 101, in one or more embodiments, the stack 103 may include two or more second layers 102 stacked directly on top of one another and a repeating pattern of two or more first layers 101 located on the two or more stacked second layers 102, which allows for the placement of semiconductor logic cells 107 in two or more adjacent second layers 102 having heights that are the same or substantially the same as an integer multiple of the height H2 of the second layers 102. For example, FIG. 1c illustrates an embodiment of a semiconductor cell block 100 that includes a repeating pattern of two first layers 101 stacked directly on top of one another and two second layers 102 stacked directly on top of one another located on the two stacked first layers 101. In the embodiment shown in FIG. 1c, the semiconductor cell block 100 includes at least one semiconductor logic cell 107 having a fourth cell height h4 that is the same or substantially the same as the height H3 of the combined second layers 102 and located in two adjacent second layers 102. Thus, in the illustrated embodiment, the fourth cell height h4 of the semiconductor logic cells 107 located in the two adjacent second layers 102 is an integer multiple of the second cell height h2 of the semiconductor logic cells 105 shown in FIGS. 1a and 1b. In one or more embodiments in which the stack 103 of the semiconductor cell block 100 includes three, four, or five second layers 102 stacked directly on top of each other, the fourth cell height h4 of the semiconductor logic cells 107 located in the two adjacent second layers 102 may be three, four, or five times the height H2 of each of the second layers 102.

[0041] In the illustrated embodiment, the semiconductor cell block 100 also includes at least one power rail 108 configured to deliver power (e.g., VDD, VSS, GND) to the semiconductor logic cells 104 in the semiconductor cell block 100. In one or more embodiments, the one or more power rails 108 may be buried power rails. The one or more power rails 108 may overlap edges of the semiconductor logic cells 104-107 in a plan view. With continued reference to the embodiment shown in FIGS. 1a-1c, each of the semiconductor logic cells 104 located in one of the first layers 101 has a first cell width w1, each of the semiconductor logic cells 105 located in one of the second layers 102 has a second cell width w2, each of the semiconductor logic cells 106 extending through two or more adjacent first layers 101 has a third cell width w3, and each of the semiconductor logic cells 107 extending through two or more adjacent second layers 102 has a fourth cell width w4. In one or more embodiments, the first cell width w1 of the semiconductor logic cells 104 located in one of the first layers 101 and the second cell width w2 of the semiconductor logic cells 105 located in one of the second layers 102 are the same or substantially the same as one another. In one or more embodiments, the first cell width w1 of the semiconductor logic cells 104 located in one of the first layers 101 and the second cell width w2 of the semiconductor logic cells 105 located in one of the second layers 102 may be integer multiples of one another (e.g., the second cell width w2 of the semiconductor logic cells 105 located in one of the second layers 102 may be 1, 2, 3, or 4 times the first cell width w1 of the semiconductor logic cells 104 located in one of the first layers 101, or vice versa). Further, in one or more embodiments, the first cell width w1 of the semiconductor logic cell 104 having the first cell height h1 is the same or substantially the same as the third cell width w3 of the semiconductor logic cell 106 having the third cell height h3, but in one or more embodiments, the third cell width w3 of the semiconductor logic cell 106 having the third cell height h3 may be an integer multiple of the first cell width w1 of the semiconductor logic cell 104 having the first cell height h1 or vice versa.Also, in one or more embodiments, the second cell width w2 of the semiconductor logic cell 105 having the second cell height h2 may be the same or substantially the same as the fourth cell width w4 of the semiconductor logic cell 107 having the fourth cell height h4, but the fourth cell width w4 of the semiconductor logic cell 107 having the fourth cell height h4 may be an integer multiple of the second cell width w2 of the semiconductor logic cell 105 having the second cell height h2, or vice versa.

[0042] 2 illustrates operations of a method 200 for generating a layout for another semiconductor cell block (e.g., the embodiment of semiconductor cell block 100 shown in FIG. 1a, 1b, or 1c) according to one embodiment of the present invention. In the embodiment shown in FIG. 2, the method 200 includes an operation (205) of obtaining a stack in which one or more first layers and one or more second layers are located in a repeating pattern (e.g., the stack 103 in which one or more first layers 101 and one or more second layers 102 are located as shown in FIG. 1a, 1b, or 1c). The layers may correspond to front-end-of-line (FEOL) layers, middle-of-line (MOL) layers, and / or back-end-of-line (BEOL) layers of semiconductor cell block 100 (e.g., insulating layer V-2, metal layer Mint on insulating layer V-1, insulating layer V-1 on metal layer Mint, metal layer M0 on insulating layer V-1, insulating layer V0 on metal layer M0, metal layer M1 on insulating layer V0, insulating layer V1 on metal layer M1, metal layer M2 on insulating layer V1, insulating layer V2 on metal layer M2, etc.).

[0043] In one or more embodiments, the first layer can have a first height and the second layer can have a second height that is greater than the first height. In one or more embodiments, the second height of the second layer can be a non-integer multiple of the first height of the first layer, such as, for example, a non-integer value in the range of about 1.1 to about 1.9.

[0044] In the illustrated embodiment, the method 200 also includes an act of obtaining semiconductor logic cells (e.g., semiconductor logic cells 104-107 shown in FIGS. 1a-1c) and arranging the semiconductor logic cells in the first and second layers using place and route (PnR) (210). In act 210, the semiconductor logic cells may be obtained from a library including a set of different semiconductor cells (e.g., the semiconductor cells may be obtained from a standard cell library including semiconductor cells having different configurations of semiconductor devices). The semiconductor logic cells may have different device architectures, such as, for example, fin or sheet-based devices (e.g., fin field effect transistors or nanosheet field effect transistors, such as horizontal nanosheet field effect transistors or vertical field effect transistors). In act 210, each semiconductor logic cell arranged in the first layer has a height that is the same or substantially the same as the height of the first layer, and each semiconductor logic cell arranged in the second layer has a height that is the same or substantially the same as the height of the second layer. Therefore, the height of the semiconductor logic cells arranged on the second layer is greater than the height of the semiconductor logic cells arranged on the first layer, and the height of the semiconductor logic cells arranged on the second layer is a non-integer multiple of the height of the semiconductor logic cells arranged on the first layer, such as a non-integer multiple in the range of approximately 1.1 to approximately 1.9.

[0045] In one or more embodiments, operation (210) may include disposing one or more semiconductor logic cells in two or more adjacent first layers, where the one or more semiconductor logic cells in the two or more adjacent first layers have height(s) that are an integer multiple of the height of the respective first layers (e.g., double-tall, triple-tall, and / or quadruple-tall semiconductor logic cells). In one or more embodiments, operation (210) may include disposing one or more semiconductor logic cells in two or more adjacent second layers, where the one or more semiconductor logic cells in the two or more adjacent second layers have height(s) that are an integer multiple of the height of the respective second layers (e.g., double-tall, triple-tall, and / or quadruple-tall semiconductor logic cells).

[0046] In the illustrated embodiment, method 200 also includes an act of placing (215) a set of pins on the semiconductor logic cells placed in act (210) using a PnR tool. The pins placed in act (215) are configured to allow connection from the semiconductor logic cells placed in act (210) to one or more routing metal layers with vias dropped by the PnR tool in a subsequent act. As used herein, the term "pin" refers to a metal wire within each semiconductor logic cell that defines a connection point for an external connection of the semiconductor logic cell (e.g., an inter-cell connection between one semiconductor logic cell and another semiconductor logic cell). Additionally, a pin may be an output pin (e.g., a connection point for an output signal of the semiconductor logic cell), an input pin (e.g., a connection point for an input signal of the semiconductor logic cell), or a combination of input and output pins. In one or more embodiments, the pins may be placed in one or more middle-of-line (MOL) layers and may define source, drain, and gate contacts of the semiconductor logic cells.

[0047] In act 215, the pins can be placed anywhere within legal boundaries (i.e., anywhere within the area that does not violate ground rules). In one or more embodiments, the pins in act 215 can be oriented on a routing grid or off of a routing grid. The term "routing grid" refers to the grid to which the objects of the semiconductor cell block 100 are aligned, and the routing grid, according to one or more embodiments, refers to the finest granularity that can be achieved during the manufacturing process for producing semiconductor logic cells and semiconductor cell blocks. In one or more embodiments, the pins in act 215 are oriented vertically and / or horizontally in a plan view. In one or more embodiments, act 215 can include iteratively redefining the location of the pins in congested areas to improve routing quality of results (QoR). The act of defining the pins 215 includes positioning the pins so as not to block other pin access on the same semiconductor logic cell or semiconductor logic cells located near the virtual pin. Additionally, the act of defining the pins (215) may include positioning the pins such that the semiconductor logic cell may be routed without creating design rule conflicts with the semiconductor logic cell or other nearby semiconductor logic cells, and the act of defining the pins (215) may include positioning the pins such that the pins do not violate ground rules for other routing metal features.

[0048] In one or more embodiments, method 200 may include an operation 220 of defining one or more blocking regions that define the obstruction. In the illustrated embodiment, the one or more blocking regions may be defined on the same layer as the pins. The blocking regions define areas where pins cannot be placed.

[0049] In the illustrated embodiment, method 200 also includes an operation (225) of defining tie vias (i.e., pin access vias) that overlap the pins placed in operation (215) (e.g., the PnR tool constrains the tie vias to be placed on the pins). The tie vias define via locations that allow for connections between pins and metal routing layers placed by the PnR tool during subsequent operations of method 200. In one or more embodiments, the operation (225) of defining tie vias includes identifying violations of ground rules for middle-of-line (MOL) shapes and layers and placing the tie vias in any suitable locations using any suitable algorithm known to those skilled in the art. That is, the PnR tool in operation (225) places the tie vias based on a set of ground rule restrictions, including a minimum area for placing the tie vias in a ground rule clean manner based on the ground rule restrictions (e.g., the operation of placing vias prevents design rule violations that would change the shape of vias placed on the same layer).

[0050] 2, the method 200 also includes an act of defining 230 a metal routing layer over the interconnect vias for interconnecting the interconnect vias in a ground rule clean manner. The act of defining 230 a metal routing layer may be performed by any suitable algorithm or algorithms known to those of skill in the art.

[0051] In the embodiment shown in FIG. 2, method 200 includes an act of defining (235) one or more power rails configured to deliver power (e.g., VDD, VSS, GND) to semiconductor logic cells in the semiconductor cell block. In one or more embodiments, the power rails disposed in act (235) may be buried power rails. In one or more embodiments, act (235) may include defining one or more power and ground staples or stripes in addition to the one or more power rails (e.g., act (235) may include defining one or more pairs of dual power staples). The one or more power rails (and / or power and ground staples or stripes) are areas where power rails (and / or power staples or power stripes) may be added depending on the appropriate power required by the intended application. The act of defining (235) one or more power rails (and / or power and ground staples or stripes) may be added prior to disposing semiconductor logic cells within the semiconductor cell block.

[0052] In the illustrated embodiment, after the design layout is complete, method 200 may include taping (240) the final layout (i.e., the graphics for the semiconductor cell blocks to a photomask are transferred to a manufacturing facility). Taping (240) the final layout may include outputting a final GDSII or other suitable file format by the PnR tool for generating a photomask. Additionally, in one or more embodiments, method 200 may include fabricating semiconductor die to form integrated semiconductor cell blocks and one or more packing and assembly operations to generate a completed semiconductor chip.

[0053] In one or more embodiments, the method 200 of the present invention, when executed by a processor, may be implemented and / or performed by computer executable commands stored in a non-volatile memory device that cause the processor to perform the operations described above. Additionally, the operations described above may include laying out semiconductor cells and displaying the semiconductor integrated circuit on a display. The term "processor" is used herein to include any combination of hardware, firmware, and software used to process data or digital signals. Processor hardware may include, for example, application specific integrated circuits (ASICs), general purpose or special purpose central processors (CPUs), digital signal processors (DSPs), graphic processors (GPUs), and programmable logic devices such as field programmable gate arrays (FPGAs). As used herein, in a processor, each function is performed by hardware configured to perform that function, i.e., more general purpose hardware such as a CPU configured to execute commands stored in a hardwired or non-transitory storage medium. The processors can be distributed across a single printed wiring board (PWB) or across multiple interconnected printed wiring boards. The processors can include, for example, two processors interconnected on a printed wiring board, an FPGA, and other processors that can include a central processor.

[0054] Although the invention has been described in detail with reference to specific embodiments, the embodiments described herein are not intended to confine or restrict the scope of the invention to the precise form disclosed. Those skilled in the art to which the invention pertains will recognize that modifications may be made to the structure and method of assembly and operation described without departing from the principles, spirit and scope of the invention. [Explanation of symbols]

[0055] 100 Semiconductor cell block 101 1st layer 102 2nd layer 103 Stack 104~107 Semiconductor logic cells

Claims

1. a plurality of layers arranged in a stack; a first semiconductor logic cell having a first cell height in one of the layers; a second semiconductor logic cell in one of the layers having a second cell height; at least one power rail coupled to the first semiconductor logic cell and the second semiconductor logic cell; the plurality of layers includes one or more first layers each having a first height and one or more second layers each having a second height; the second cell height is greater than the first cell height, the second cell height being a non-integer multiple of the first cell height; The first height and the second height are defined in a vertical direction that is perpendicular to a plane in which the at least one power rail extends.

2. 2. The semiconductor cell block of claim 1, wherein the non-integer multiple has a range of 1.1 to 1.

9.

3. 2. The semiconductor cell block of claim 1, wherein the first semiconductor logic cell is located in one of the one or more first layers and the second semiconductor logic cell is located in one of the one or more second layers.

4. The semiconductor cell block of claim 1 , wherein the one or more first layers include a plurality of first layer pairs stacked directly on one another.

5. the one or more first layers include a plurality of first layers; the one or more second layers include a plurality of second layers; The semiconductor cell block of claim 1 , wherein the number of the first layers is greater than the number of the second layers.

6. the plurality of second layers are regularly arranged in the stack; 6. The semiconductor cell block of claim 5, wherein adjacent pairs of the second layers of the plurality of second layers are spaced apart from each other by an equal number of the first layers of the plurality of first layers.

7. 7. The semiconductor cell block of claim 6, wherein said equal number is an even number.

8. a third semiconductor logic cell having a third height; The semiconductor cell block of claim 1 , wherein the third height is an integer multiple of the first cell height.

9. the one or more first layers include a plurality of first layers; The semiconductor cell block of claim 8 , wherein the third semiconductor logic cells are located in a pair of adjacent first layers of the plurality of first layers.

10. The semiconductor cell block of claim 1, wherein the plurality of layers includes at least one front-end-of-line (FEOL) layer, a middle-of-line (MOL) layer, and a back-end-of-line (BEOL) layer.

11. 2. The semiconductor cell block of claim 1, wherein said at least one power rail is a buried power rail.

12. The semiconductor cell block of claim 1 , wherein the first semiconductor logic cells and the second semiconductor logic cells include logic cells of different types.

13. 2 . The semiconductor cell block of claim 1 , wherein the first width of the first semiconductor logic cell and the second width of the second semiconductor logic cell are integer multiples of each other.

14. placing a first semiconductor logic cell in a first one of the layers of the stack using a place and route tool and placing a second semiconductor logic cell in a second one of the layers of the stack, the first semiconductor logic cell having a first cell height and the second semiconductor logic cell having a second cell height that is greater than the first cell height, the second cell height being a non-integer multiple of the first cell height; placing pins on each of the first and second semiconductor logic cells using the place and route tool; placing vias coupled to the pins using the placement and routing tool; placing a metal routing layer coupled to the vias using the placement and routing tool; placing at least one power rail on a layer of the stack using the place and route tool; 11. A computer-implemented method for generating a layout for a block of semiconductor cells, wherein the first cell height and the second cell height are defined in a vertical direction that is perpendicular to a plane in which the at least one power rail extends.

15. 15. The computer-implemented method of generating a layout for a block of semiconductor cells of claim 14, wherein the non-integer multiple has a range of 1.1 to 1.

9.

16. the first layer has a first height and the second layer has a second height; 15. The computer-implemented method of generating a layout for a block of semiconductor cells of claim 14, wherein the second height is greater than the first height and the second height is a non-integer multiple of the first height.

17. The computer-implemented method of generating a layout for a semiconductor cell block of claim 14, wherein the layers of the stack include at least one front-end-of-line (FEOL) layer, a middle-of-line (MOL) layer, and a back-end-of-line (BEOL) layer.

18. placing a third semiconductor logic cell having a third cell height in the stack using the place and route tool; 15. The computer-implemented method of generating a layout for a block of semiconductor cells of claim 14, wherein the third cell height is an integer multiple of the first cell height.

19. the first layer is one of a plurality of first layers, the plurality of first layers including a pair of first layers directly stacked on one another; 15. The computer-implemented method of generating a layout for a block of semiconductor cells of claim 14, wherein the second layer is one of a plurality of second layers, the second layer being located between the pair of first layers.

20. 20. The computer-implemented method of generating a layout for a block of semiconductor cells of claim 19, wherein a number of the plurality of first layers is greater than a number of the plurality of second layers.

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