System and method for ISA support for load and store indirect references for efficient access to compressed lists in graph applications - Patents.com

Abstract

To provide a multi-level indirect reference load and store single instruction for efficiently accessing a compressed graphic list in a graph application.SOLUTION: A pipeline indirect reference system 100 executes a Load.ind single instruction. A first computing engine 110 associated with a first data location 115 receives an indirect reference request IND-IND-LD from a load store queue 105 and calculates a second data location 125 associated with a second computing engine 120. The second computing engine 120 calculates a third data location 135 associated with a third computing engine 130 in response to an indirect reference request IND-LD. Further, the third computing engine 130 receives data from the third data location 135 and loads the received data into the load store queue 105 in response to an indirect reference request OP-load. Access to a compressed graphics list is performed as described above.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The field of the invention relates generally to computer processor architecture, and more specifically to a system and method for indirect load and store references for efficient access to compressed lists in graph applications. [Background technology]

[0002] Large sparse matrices are compressed into a Compressed Row Storage (CSR) format. The CSR format is a vectorized list of non-zero entries in a sparse matrix. A sparse matrix represented in the CSR format has three one-dimensional arrays. Before finding the target location, each indirect load or store increases performance overhead in that a pre-constructed adjacent index read is performed from the list in memory, the adjacent index values ​​are dereferenced to find the target value location, and a load or store request is sent to that final value.

[0003] Supporting load and store indirections to efficiently access compressed lists in graph applications can help meet processor needs, such as providing the ability to combine multiple operations into a single instruction, which reduces overall latency and increases code efficiency. [Brief description of the drawings]

[0004] The present invention is illustrated by way of example and not limitation in the figures of the accompanying drawings, in which like reference symbols indicate similar elements and in which:

[0005] [Figure 1] 1 illustrates a block diagram of a pipelined indirection system architecture based on multiple indirection, according to one embodiment of the present invention;

[0006] [Diagram 2]1 illustrates a block diagram of a pipelined indirection system based on single indirection, in accordance with one embodiment of the present invention;

[0007] [Diagram 3] 3 illustrates example embodiments of a method for accessing a compressed graphics list as detailed herein;

[0008] [Figure 4] 1 depicts a table illustrating instruction definitions for three operations according to certain embodiments detailed herein.

[0009] [Diagram 5] 4 illustrates exemplary pseudocode for performing a double dereference load in accordance with one embodiment of the present invention.

[0010] [Figure 6] 4 illustrates an exemplary base+offset address format, according to one embodiment of the present invention.

[0011] [Figure 7] FIG. 1 is a block diagram illustrating a generic vector friendly instruction format and its instruction templates according to embodiments of the present invention. [Figure 8] FIG. 1 is a block diagram illustrating a generic vector friendly instruction format and its instruction templates according to embodiments of the present invention.

[0012] [Figure 9A] 1 illustrates an exemplary vector specific instruction format according to embodiments of the present invention. [Figure 9B] 1 illustrates an exemplary vector specific instruction format according to embodiments of the present invention. [Figure 9C] 1 illustrates an exemplary vector specific instruction format according to embodiments of the present invention. [Figure 9D] 1 illustrates an exemplary vector specific instruction format according to embodiments of the present invention.

[0013] [Figure 10] FIG. 2 is a block diagram of a register architecture according to one embodiment of the present invention.

[0014] [Figure 11A] 1 is a block diagram illustrating both an exemplary in-order pipeline and an exemplary register renaming, out-of-order issue / execution pipeline, in accordance with multiple embodiments of the present invention.

[0015] [Figure 11B] 2 is a block diagram illustrating both an exemplary embodiment in-order architecture core and an exemplary register renaming, out-of-order issue / execution architecture core included in a processor in accordance with multiple embodiments of the present invention.

[0016] [Figure 12A] 1 shows a block diagram of a more specific exemplary in-order core architecture, where the core is one of several logic blocks (including other cores of the same and / or different types) within a chip. [Figure 12B] 1 shows a block diagram of a more specific exemplary in-order core architecture, where the core is one of several logic blocks (including other cores of the same and / or different types) within a chip.

[0017] [Figure 13] FIG. 17 is a block diagram of a processor 1700, which may have more than one core, may have an integrated memory controller, and may have integrated graphics, in accordance with embodiments of the present invention.

[0018] [Figure 14] FIG. 1 is a block diagram of an exemplary computer architecture. [Figure 15] FIG. 1 is a block diagram of an exemplary computer architecture. [Figure 16]FIG. 1 is a block diagram of an exemplary computer architecture. [Figure 17] FIG. 1 is a block diagram of an exemplary computer architecture.

[0019] [Figure 18] 1 is a block diagram contrasting the use of a software instruction converter to convert binary instructions in a source instruction set to binary instructions in a target instruction set in accordance with multiple embodiments of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0020] In the following description, numerous specific details are set forth. However, it is understood that embodiments of the present invention may be practiced without these specific details. In other instances, well-known circuits, structures and techniques have not been shown in detail in order not to obscure an understanding of this description.

[0021] References herein to "one embodiment," "embodiment," "exemplary embodiment," and the like indicate that the embodiment being described may include a particular feature, structure, or characteristic, but not every embodiment necessarily includes the particular feature, structure, or characteristic. Moreover, such phrases do not necessarily refer to the same embodiment. Moreover, when a particular feature, structure, or characteristic is described in connection with an embodiment, it is believed to be within the knowledge of one of ordinary skill in the art to affect such feature, structure, or characteristic in connection with other embodiments, whether or not explicitly described.

[0022] A pipeline indirection system is a system that accesses list data structures, compressed lists (e.g., compressed graphics lists) in a graph application, or any other suitable list. Compressed lists may be accessed via indirection requests. As used herein, the term "indirection request" may be used to refer to a request to access a compressed list in a graph application that includes an indirect load operation, an indirect store operation, and / or a store acknowledgement.

[0023] Supporting load and store indirections for efficient access to compressed lists, as described herein, provides performance improvements by combining multiple operations into a single instruction and supporting remote address computations that increase code efficiency. Additionally, supporting load and store indirections, as described herein, eliminates the round-trip latency per memory access while reducing the latency per operation.

[0024] For example, a pipelined indirection system may begin by fetching and decoding a single instruction that accesses a compressed graphics list. The compressed graphics list is accessed by receiving an indirection request from a load store queue at a first compute engine associated with a first data location. A second data location associated with a second compute engine is calculated by the first compute engine. A third data location associated with a third compute engine is calculated by the second compute engine, and a data response is provided to the load store queue in response to receiving data from the third data location.

[0025] FIG. 1 illustrates a block diagram of a pipeline indirection system architecture with multiple indirections, according to an embodiment of the present invention. As shown, pipeline indirection system 100 includes a pipeline 102 communicatively and operatively coupled to a load store queue (e.g., LSQ 105), one or more computation engines (e.g., computation engines 110, 120, and 130), one or more data locations (e.g., data locations 115, 125, and 135), and one or more additional systems, components, etc. It should be understood that pipeline indirection system 100 may include more, fewer, and / or different components / systems than those illustrated in FIG. 1, and thus it is intended that the principles, methods, systems, processes, etc. of the present disclosure may be applicable with any other pipeline indirection system configuration. It should also be understood that the principles of the present disclosure contemplate that they may be applied to a variety of other applications.

[0026] As shown, the pipeline indirection system 100 includes a pipeline 102. A single instruction (e.g., a load.ind instruction, a store.ind instruction, etc.) is issued to the pipeline indirection system 100 in the pipeline 102. In some embodiments, an indirection level may be determined for an indirect load operation and / or an indirect store operation. The indirection level may indicate a multi-level indirection (e.g., a double indirection) or a single level indirection (e.g., a single indirection). As described herein, if the indirection level (e.g., a LEV-IND qualifier) ​​is set to one, then an indirection request (e.g., an indirect load or an indirect store request) that dereferences the address of the final data location may be provided to at least two data locations (e.g., the next list location).

[0027] In this regard, LSQ 105 issues a single instruction containing an indirect reference request (e.g., a double indirect reference such as an IND-IND-LD packet) to compute engine 110. As used herein, the term "load store queue (LSQ)" may be used to refer to a queue that stores data and / or information associated with one or more instructions. In some embodiments, data stored in LSQ 105 may be passed or otherwise provided between instructions, one or more compute engines (e.g., compute engines 110, 120, 130, etc.), or any other suitable component. A compute engine (e.g., compute engine 110) may be located near the list memory.

[0028] The indirect reference request may instruct the compute engine 110 to read a first pointer from a data location 115. As used herein, the term "data location" may be used to refer to a scratchpad memory, a double data rate (DDR) memory, or any other suitable storage location. The first pointer from the data location 115 may be used to determine the location of a second pointer.

[0029] The computing engine 110 may then calculate or otherwise determine the next pointer location (e.g., a register such as r3 as referenced in the table of FIG. 4 herein). For example, the computing engine 110 may determine that the next pointer location is data location 125 associated with the computing engine 120. The computing engine 110 may send, pass, or otherwise provide an indirect reference request to the computing engine 120. For example, the computing engine 110 may send or otherwise provide an indirect reference request (e.g., an IND-LD packet) to the computing engine 120. In some embodiments, the computing engine 110 may generate an indirect reference request (e.g., a second indirect reference request such as, but not limited to, an IND-LD packet) to provide to the computing engine 120. The indirect reference request may include a second register such as r4 that calculates a pointer at data location 125 (as described herein with reference to FIG. 4).

[0030] At data location 125, compute engine 120 may read a pointer from memory and perform pointer arithmetic using the register values ​​to determine that the next pointer location is data location 135. Computation engine 120 then sends an indirection request (e.g., a computation load request) to data location 135, which is read or otherwise received by compute engine 130 at data location 135.

[0031] Data is read by the computation engine 130 from the data location 135 in response to the indirect reference request, and a data response (eg, a data value, a data acknowledgment, or a combination thereof) is provided (eg, sent) to the LSQ 105 .

[0032] 2 illustrates a block diagram of a pipeline indirection system architecture, according to one embodiment of the present invention. A single instruction (e.g., a load.ind instruction) is issued to pipeline indirection system 100 in pipeline 102. LSQ 105 issues a single instruction containing an indirection request (e.g., a single indirection such as an IND-LD packet) that is provided to compute engine 210. If the indirection level (e.g., a LEV-IND qualifier) ​​is set to 0, a store or load is provided to a data location (e.g., a dereferenced location such as data locations 215 and / or 225) and a data response (e.g., a data value, a data acknowledgement, or a combination thereof) is returned to LSQ 105.

[0033] Thus, the computation engine 210 may receive an indirect reference request (e.g., an IND-LD packet). At data location 215, the computation engine 210 may read a pointer from memory and perform a pointer arithmetic using the register values ​​to determine that the next pointer location is data location 225. The computation engine 210 may then send or otherwise provide the indirect reference request to the computation engine 220. For example, the computation engine 210 may send or otherwise provide an indirect reference request (e.g., a computation load request) to data location 225, which is read or otherwise received by the computation engine 220 at data location 225.

[0034] Data is read by the computation engine 220 from the data location 225 in response to the indirect reference request, and a data response (eg, a data value, a data acknowledgment, or a combination thereof) is provided (eg, sent) to the LSQ 105 .

[0035] 3 illustrates several example embodiments of accessing a compressed graphics list, triggered in response to an instruction (e.g., a load.ind instruction) issued to the pipeline, and the operations of the method are performed by components of a processor or core, including, but not limited to, a processor as detailed herein.

[0036] 3 illustrates one embodiment of a processor that executes a single instruction to access a compressed graphics list. At 301, the processor fetches the single instruction using a fetch circuit. The single instruction includes at least one of a list load, a pointer dereference, a load indirect operation, or a store indirect operation. Advantageously, including multiple operations (e.g., a list load, a pointer dereference, a load indirect operation, or a data load / store) in a single instruction increases code efficiency and reduces latency per operation by supporting remote address calculation and removing the round-trip latency per memory access.

[0037] The fetched single instruction is decoded. For example, the fetched single instruction is decoded by a decode circuit as detailed herein. Execution of the decoded single instruction results in accessing the compressed graphics list by receiving an indirection request. The indirection request includes an indirection operation. The indirection operation may include an indirection load operation or an indirection store operation. In some embodiments, an indirection level may be determined for the indirection load operation and / or the indirection store operation. In this regard, the indirection level may indicate multi-level indirection or single-level indirection. In some embodiments, the multi-level indirection includes multiple individual loads. In some embodiments, the multi-level indirection includes multiple individual stores. In some embodiments, the multi-level indirection includes a combination of one or more individual loads and one or more individual stores. The single level indirection includes an individual load or an individual store.

[0038] In some embodiments, the indirection request may include an address associated with a load store queue. An address associated with the load store queue may be included in an indirection request that returns data to a load store queue in one or more compute engines of a pipelined indirection system. In some embodiments, the address of the load store queue may be transmitted with each indirection request that successfully returns data, regardless of the location of the indirection request.

[0039] In some embodiments, an indirection request may be received from a load store queue (LSQ) at a first compute engine, the first compute engine being associated with a first data location, the data location including a memory location within a pipelined indirection system.

[0040] The processor responds to the decoded single instruction by executing the decoded single instruction that accesses the compressed graphics list using an execution circuit (e.g., an existing atomic execution unit at the memory interface, as described herein with reference to FIG. 11A and FIG. 11B). At 305, the processor calculates, by the first computation engine, a second data location associated with the second computation engine. In this regard, the first computation engine reads a first pointer from the first data location (e.g., a first location associated with the first computation engine). The first pointer may be utilized to determine a location of the second pointer. The processor may calculate a second data location associated with the second pointer based on the location determined according to the first pointer. The processor may then provide an indirection request to the second computation engine at the determined second data location.

[0041] At 307, the processor calculates, by the second computing engine, a third data location associated with the third computing engine in response to the indirection request. The processor may read a second pointer from the second data location and, in response, calculate a third data location associated with the third pointer. The processor may then provide, by the second computing engine, the indirection request to the third computing engine.

[0042] At 309, the processor provides a data response to the load store queue in response to receiving the data from the third data location by the third compute engine, e.g., the compute engine reads the data from the third data location and sends a data response (e.g., a data acknowledgement) to the load store queue.

[0043] FIG. 4 illustrates a table showing instruction definitions for three operations, according to some embodiments. As shown, the table includes indirect load and store operations, descriptions, and inputs to pipeline indirection system 100. Each of these operations is supported by one or more compute engines (e.g., compute engines 110, 120, and 130) of pipeline indirection system 100. Pipeline indirection system 100 may take the form of a multi-threaded pipeline. In some embodiments, once a memory operation is issued, the thread is set aside until the operation is completed. The thread may then advantageously re-enter the pipeline, eliminating the need for forwarding. In some embodiments, the multi-threaded pipeline may include fencing, such that the indirect operation (e.g., any operation such as load.ind or storeack.ind) waits until the indirect operation is completed.

[0044] LSQ 105 sends a request to a compute engine (e.g., compute engines 110, 120, and 130) located near the list memory (e.g., an address in or of r2). The compute engine then performs the list read and dereference. In embodiments where the indirection level (e.g., LEV-IND qualifier) ​​is set to 1, an indirection request may then be provided to at least two data locations (e.g., next list locations such as data locations 115 and 125) that dereferences the address of the final data location (e.g., data location 135). In some embodiments, the indirection request (e.g., double indirection) may include an operand such as register r4 to support a second pointer that dereferences the next data location. Operand r4 may provide a base value for the new data structure, which advantageously eliminates any requirement to place data structures adjacent to one another to reuse the same base value. When the address of the final data location is dereferenced, a data response (eg, a data value, a data acknowledgment, or a combination thereof) is returned to LSQ 105.

[0045] If the indirection level (e.g., the LEV-IND qualifier) ​​is set to 0, a store or load (e.g., IND-LD) is provided to a data location (e.g., a dereferenced location such as data locations 215 and / or 225) and a data response (e.g., a data value, a data acknowledgment, or a combination thereof) is returned to LSQ 105.

[0046] 5 illustrates an example pseudocode for performing a double indirect load, according to one embodiment as described herein. A loop is performed for each vertex v over its neighbors. The double indirect load is shown in line 3 as the code logprimes[labelvec[neighbors[i]]. The return value from the indirect load is t, which is accumulated in "sum". When written as a single machine code instruction, the double indirect code is: Load.ind ret_reg,neighbors[i],labelvec_base,logprimes_base, SIZE=64,AM=O,OS=64,OT=U,LEV-IND=1 Convert it to:

[0047] Ret_reg: The local register into which the data is loaded

[0048] neighbors[i]: is the variable from the above code segment that indicates where the first "list" of pointers is located.

[0049] Labelvec_base: This is the address value that performs a "base+offset" address dereference on the first indirection.

[0050] Logprimes_base: This is the address value that performs a "base+offset" address dereference on the second indirection.

[0051] FIG. 6 illustrates an exemplary base+offset address format according to one embodiment as described herein. In some embodiments, data structures for sparse graphs and matrices (e.g., compressed row storage) represent vertex or column IDs in memory as contiguous blocks of integers. These integers may be used to index data structures with non-uniform layouts (e.g., gather, scatter, or broadcast). In some embodiments, a compute engine (e.g., compute engines 110, 120, and 130) may interpret the list represented in a list of offset format. In this regard, a base value (e.g., a 64-bit regular address) and an address of the packed offset list may be provided as part of the operation as separate registers. The list stored in memory may then include an integer representing the count of elements. Advantageously, this allows for the provision of the original ID (e.g., vertex ID) without scaling the ID with the individual element size. In some embodiments, the integers in the list may range from a scalable lower bound to a scalable upper bound (e.g., the integers may be x number of bytes, such as, but not limited to, 4 bytes, 8 bytes, etc.). Alternatively or additionally, the integers may be signed or unsigned.

[0052] A 32-bit unsigned integer offset value is shown, where AM=O, OT=U, and OS=32 bits. The base address of the list is rSrc(r2). Conversion of the integer offset to a 64-bit address value may be performed according to the formula Dest_addr=(Offset_0×SIZE)+r3. The integer represents a distance from the base value r3 (e.g., a distance in data elements of SIZE). The position of the data element of interest is the integer offset multiplied by SIZE and added to r3.

[0053] Detailed herein are examples of hardware, software, etc. that execute the instructions described above. For example, the following description details aspects of instruction execution including various pipeline stages, such as fetching, decoding, scheduling, executing, retiring, etc.

[0054] Instruction Set

[0055] An instruction set may include one or more instruction formats. A given instruction format may define various fields (e.g., number of bits, bit positions) that specify, among other things, the operation to be performed (e.g., opcode) and the operands on which the operation is performed, and / or other data fields (e.g., masks). Some instruction formats are further categorized through the definition of instruction templates (or sub-formats). For example, instruction templates of a given instruction format may be defined to have different subsets of the instruction format's fields (where the included fields are typically in the same order, but at least some have different bit positions because fewer fields are included) and / or to have given fields that are interpreted differently. Thus, each instruction of an Instruction Set Architecture (ISA) is represented using a given instruction format (and, if defined, in a given one of the instruction templates of the instruction format) and includes fields for specifying the operation and the operands. For example, an exemplary ADD instruction has an instruction format that includes a particular opcode, an opcode field that specifies the opcode, and operand fields that select the operands (source 1 / destination and source 2), and when this ADD instruction appears in an instruction stream, it has particular contents in the operand fields that select the particular operands.

[0056] The embodiments of the invention described herein may be embodied in different formats. Further, exemplary systems, architectures, and pipelines are detailed below. The embodiments of the invention may be implemented on such systems, architectures, and pipelines, but are not limited to those detailed.

[0057] An instruction set may include one or more instruction formats. A given instruction format may define various fields (e.g., number of bits, bit positions) that specify, among other things, the operation to be performed (e.g., opcode) and the operands on which the operation is performed, and / or other data fields (e.g., masks). Some instruction formats are further categorized through the definition of instruction templates (or sub-formats). For example, instruction templates of a given instruction format may be defined to have different subsets of the instruction format's fields (where the included fields are typically in the same order, but at least some have different bit positions because fewer fields are included) and / or to have given fields that are interpreted differently. Thus, each instruction of the ISA is represented using a given instruction format (and, if defined, in a given one of the instruction templates of the instruction format) and includes fields for specifying the operation and the operands. For example, an exemplary ADD instruction has an instruction format that includes a particular opcode, an opcode field that specifies the opcode, and operand fields that select the operands (source1 / destination and source2), such that when this ADD instruction appears in an instruction stream, it has particular contents in the operand fields that select the particular operand. A set of SIMD extensions, referred to as Advanced Vector Extensions (AVX) (AVX1 and AVX2), that use the Vector Extensions (VEX) encoding scheme, has been released and / or published (see, e.g., Intel® 64 and IA-32 Architectures Software Developer's Manual, September 2014, and Intel® Advanced Vector Extensions Programming Reference, October 2014). Example Instruction Format

[0058] The embodiments of the invention described herein may be embodied in different formats. Further, exemplary systems, architectures, and pipelines are detailed below. The embodiments of the invention may be implemented on such systems, architectures, and pipelines, but are not limited to those detailed. Generic Vector Instruction Format

[0059] The vector friendly instruction format is an instruction format that is suitable for vector instructions (e.g., there are certain fields that are specific to vector operations). Although embodiments are described in which both vector and scalar operations are supported by the vector friendly instruction format, alternative embodiments use only vector operations of the vector friendly instruction format.

[0060] 12A-12B are block diagrams illustrating a generic vector friendly instruction format and its instruction templates according to embodiments of the present invention. FIG. 7 is a block diagram illustrating a generic vector friendly instruction format and its class A instruction templates according to embodiments of the present invention, while FIG. 8 is a block diagram illustrating a generic vector friendly instruction format and its class B instruction templates according to embodiments of the present invention. Specifically, a generic vector friendly instruction format 800 defines class A and class B instruction templates, both of which include a no memory access 805 instruction template and a memory access 820 instruction template. The term generic in the context of the vector friendly instruction format refers to an instruction format that is not tied to any particular instruction set.

[0061] The vector friendly instruction format supports vector operand lengths (or sizes) of 64 bytes with data element widths (or sizes) of 32 bits (4 bytes) or 64 bits (8 bytes) (so a 64 byte vector consists of either 16 doubleword sized elements or, alternatively, 8 quadword sized elements), vector operand lengths (or sizes) of 64 bytes with data element widths (or sizes) of 16 bits (2 bytes) or 8 bits (1 byte), and vector operand lengths (or sizes) of 32 bits (4 bytes), 64 bits (8 bytes), 16 bits (2 bytes), or 8 bits (1 byte) Although embodiments of the invention are described supporting vector operand lengths (or sizes) of 32 bytes having a 32-bit (4-byte), 64-bit (8-byte), 16-bit (2-byte), or 8-bit (1-byte) data element widths (or sizes), alternative embodiments may support more, less, and / or different vector operand sizes (e.g., 256-byte vector operands) having more, less, or different data element widths (e.g., a 128-bit (16-byte) data element width).

[0062] The class A instruction templates in Figure 7 include 1) a no memory access, full round control type operation 810 instruction template and a no memory access, data transform type operation 815 instruction template, which are shown in the no memory access 805 instruction templates, and 2) a memory access, primary 825 instruction template and a memory access, non-temporal 830 instruction template, which are shown in the memory access 820 instruction templates. The class B instruction templates in Figure 8 include 1) a no memory access, write mask control, partial round control type operation 812 instruction template and a no memory access, write mask control, VSIZE type operation 817 instruction template, which are shown in the no memory access 805 instruction templates, and 2) a memory access, write mask control 827 instruction template, which is shown in the memory access 820 instruction templates.

[0063] The generic vector friendly instruction format 800 includes the following fields, listed below in the order shown in FIGS.

[0064] Format field 840 - a unique value (the value of the instruction format identifier) ​​in this field uniquely identifies the vector friendly instruction format and therefore the occurrence of an instruction within the vector friendly instruction format in an instruction stream. As such, this field is optional in the sense that it is not required for an instruction set that has only a generic vector friendly instruction format.

[0065] Basic operation field 842 - its contents distinguish between different basic operations.

[0066] A register index field 844 - its contents specify, either directly or through address generation, the location of the source and destination operands, whether they are in registers or in memory. It contains enough bits to select N registers from a PxQ (e.g., 32x512, 16x128, 32x1024, 64x1024) register file. In one embodiment, N can be up to three source and one destination register, although alternative embodiments can support more or fewer source and destination registers (e.g., up to two sources with one of these sources also acting as a destination, up to three sources with one of these sources also acting as a destination, up to two sources and one destination).

[0067] Qualifier field 846 - its contents distinguish occurrences of instructions in the generic vector instruction format that specify memory access from those that do not, i.e., distinguishing between no-memory access 805 instruction templates and memory access 820 instruction templates. Memory access operations read and / or write to the memory hierarchy (possibly using values ​​in registers to specify source and / or destination addresses), while non-memory access operations do not (e.g., source and destination are registers). In one embodiment, this field also selects among three different ways of performing memory address calculations, although alternative embodiments may support more, fewer, or different ways of performing memory address calculations.

[0068] Extended operation field 850 - its contents distinguish which of a variety of different operations are performed in addition to the basic operations. This field is context specific. In one embodiment of the invention, this field is split into a class field 868, an alpha field 852, and a beta field 854. The extended operation field 850 allows a common group of operations to be performed in a single instruction rather than 2, 3, or 4 instructions.

[0069] Scale field 860 - its contents are used to scale the memory address generation (e.g., 2 scale This allows scaling the contents of the index field for address generation using the base x index + address base.

[0070] Displacement field 862A - its contents are used to generate memory addresses (e.g., 2 scale × index + base + displacement) for address generation.

[0071] Displacement factor field 862B (note that the juxtaposition of displacement field 862A immediately above displacement factor field 862B indicates that one or the other is used) - its contents are used as part of the address generation. It specifies a displacement factor that is scaled by the size (N) of the memory access - where N is the number of bits in the memory access (e.g., 2 scale The displacement factor field 862A is the number of bytes in the memory operand (for address generation using index + base + scaled displacement × index + base + scaled displacement). Redundant low-order bits are ignored, so the contents of the displacement factor field are multiplied by the total size of the memory operand (N) to generate the final displacement used in calculating the effective address. The value of N is determined by the processor hardware at run-time based on the full opcode field 874 (described later in this specification) and the data manipulation field 854C. The displacement field 862A and the displacement factor field 862B are optional in the sense that they are not used for non-memory access 805 instruction templates and / or different embodiments may implement only one of the two or none of the two.

[0072] Data element width field 864 - its contents distinguish which of multiple data element widths is used (in some embodiments for all instructions, in other embodiments only for some instructions). This field is optional in the sense that it is not needed if only one data element width is supported and / or multiple data element widths are supported using some aspect of the opcode.

[0073] Write mask field 870 - its contents control, for each data element position, whether that data element position in the destination vector operand reflects the results of the basic and extended operations. Class A instruction templates support merging-writemasking, while class B instruction templates support both merging-writemasking and zeroing-writemasking. When merging, the vector mask allows any set of elements in the destination to be protected from updates during the execution of any operation (specified by the basic and extended operations), and in one embodiment, preserves the old value of each element in the destination whose corresponding mask bit has a zero. In contrast, when zeroing, the vector mask allows any set of elements in the destination to be zeroed during the execution of any operation (specified by the basic and extended operations), and in one embodiment, an element in the destination is set to zero when its corresponding mask bit has a zero value. A subset of this functionality is the ability to control the vector length of the operation being performed (i.e., the range of elements being modified, from first to last). However, the elements being modified need not be contiguous. Thus, the write mask field 870 allows for partial vector operations including loads, stores, arithmetic, logical, etc. Although embodiments of the invention are described in which the contents of the write mask field 870 select one of multiple write mask registers that contains the write mask to be used (thus the contents of the write mask field 870 indirectly identify the masking to be performed), alternative embodiments allow the contents of the mask write field 870 to instead or additionally directly specify the masking to be performed.

[0074] Immediate field 872 - its contents allow the specification of an immediate value. This field is optional in the sense that it is not present in implementations of the generic vector friendly format that do not support immediate values ​​and is not present in instructions that do not use immediate values.

[0075] Class field 868 - its contents distinguish between different classes of instructions. With reference to Figures 7-8, the contents of this field select between class A and class B instructions. In Figures 7-8, a rounded corner rectangle is used to indicate that a unique value exists in the field (e.g., class A 868A and class B 868B, respectively, for class field 868 in Figures 7-8). Class A instruction template

[0076] For class A no memory access 805 instruction templates, the alpha field 852 is interpreted as an RS field 852A, whose content distinguishes which of the different extended operation types is performed (e.g., round 852A.1 and data transform 852A.2 are specified for the no memory access, round type operation 810 and no memory access, data transform type operation 815 instruction templates, respectively), while the beta field 854 distinguishes which of the specified types of operations is performed. In the no memory access 805 instruction templates, the scale field 860, the displacement field 862A, and the displacement scale field 862B are not present. Non-memory access instruction template - full round control type operation

[0077] In the no memory access full round control type operation 810 instruction template, the beta field 854 is interpreted as a round control field 854A, the contents of which provide the static round. In the described embodiments of the invention, the round control field 854A includes a suppress all floating-point exceptions (SAE) field 856 and a round operation control field 858, although alternative embodiments may support both of these concepts, may encode them in the same field, or may only have one or the other of these concepts / fields (e.g., may only have the round operation control field 858).

[0078] SAE field 856 - its contents distinguish whether to disable exception event reporting. When the contents of SAE field 856 indicate that suppression is in effect, the given instruction will not report any floating-point exception flags of any kind and will not raise any floating-point exception handlers.

[0079] Round operation control field 858 - its contents distinguish which round operation of a group of round operations to perform (e.g., round up, round down, round to zero, and round to nearest). The round operation control field 858 thus allows the round mode to be changed on a per instruction basis. In one embodiment of the invention in which the processor includes a control register for specifying the round mode, the contents of the round operation control field 850 override that register value. Non-memory access instruction templates - data conversion type operations

[0080] In the no memory access data transform type operation 815 instruction template, the beta field 854 is interpreted as a data transform field 854B, whose content distinguishes which of a number of data transforms is performed (e.g., no data transform, swizzle, broadcast).

[0081] For memory access 820 instruction templates of class A, the alpha field 852 is interpreted as an eviction hint field 852B, whose content distinguishes which of the eviction hints should be used (in FIG. 7, temporal 852B.1 and non-temporal 852B.2 are specified for the memory access, primary 825 instruction template and the memory access, non-temporal 830 instruction template, respectively), while the beta field 854 is interpreted as a data manipulation field 854C, whose content distinguishes which of a number of data manipulation operations (also known as primitives) should be performed (e.g., no manipulation, broadcast, up-conversion of source, down-conversion of destination). The memory access 820 instruction templates include a scale field 860 and, optionally, a displacement field 862A or a displacement scale field 862B.

[0082] Vector memory instructions perform vector loads from memory and vector stores to memory, with conversion support. Similar to regular vector instructions, vector memory instructions transfer data from / to memory in a data element-by-data element manner, where the elements actually transferred are dictated by the contents of a vector mask, which is selected as the write mask. Memory Access Instruction Templates - Temporal

[0083] Transient data is data that is likely to be reused quickly enough to benefit from caching, however this is a hint and different processors may implement it in different ways, including ignoring the hint entirely. Memory Access Instruction Templates - Non-temporal

[0084] Non-temporal data is data that is unlikely to be reused fast enough to benefit from caching in the first level cache and should be given priority for eviction. However, this is a hint, and different processors may implement it in different ways, including ignoring the hint entirely. Class B instruction template

[0085] For class B instruction templates, the alpha field 852 is interpreted as a write mask control (Z) field 852C, whose content distinguishes whether the write masking controlled by the write mask field 870 should be merging or zeroing.

[0086] For class B no memory access 805 instruction templates, a portion of the beta field 854 is interpreted as an RL field 857A, whose contents distinguish which of the different extended operation types are performed (e.g., round 857A.1 and vector length (VSIZE) 857A.2 are specified for the no memory access, write mask control, partial round control type operation 812 instruction template and the no memory access, write mask control, VSIZE type operation 817 instruction template, respectively), while the remainder of the beta field 854 distinguishes which of the specified types of operations are performed. In the no memory access 805 instruction templates, the scale field 860, the displacement field 862A, and the displacement scale field 862B are not present.

[0087] In the no memory access, write mask control, partial round control type operation 810 instruction template, the remainder of the beta field 854 is interpreted as the round operation field 859A and exception event reporting is disabled (the given instruction does not report any kind of floating-point exception flags or raise any floating-point exception handlers).

[0088] Round operation control field 859A - similar to round operation control field 858, its contents distinguish which round operation of a group of round operations to perform (e.g., round up, round down, round to zero, and round to nearest). Thus, the round operation control field 859A allows the round mode to be changed on a per-instruction basis. In one embodiment of the invention in which the processor includes a control register for specifying the round mode, the contents of the round operation control field 850 override that register value.

[0089] In the no memory access, write mask control, VSIZE type operation 817 instruction template, the remainder of the beta field 854 is interpreted as a vector length field 859B, whose contents distinguish which of a number of data vector lengths should be implemented (e.g., 128, 256, or 512 bytes).

[0090] For class B memory access 820 instruction templates, a portion of the beta field 854 is interpreted as a broadcast field 857B, whose content distinguishes whether a broadcast type data manipulation operation should be performed or not, while the remainder of the beta field 854 is interpreted as a vector length field 859B. The memory access 820 instruction templates include a scale field 860 and, optionally, a displacement field 862A or a displacement scale field 862B.

[0091] With respect to the generic vector friendly instruction format 800, a full opcode field 874 is shown that includes a format field 840, a basic operation field 842, and a data element width field 864. While one embodiment is shown in which the full opcode field 874 includes all of these fields, in embodiments that do not support all of them, the full opcode field 874 includes less than all of these fields. The full opcode field 874 provides an operation code (opcode).

[0092] The extended operation field 850, data element width field 864, and write mask field 870 allow these functions to be specified on a per-instruction basis in the generic vector friendly instruction format.

[0093] The combination of the write mask field and the data element width field creates a classified instruction in that it allows masks to be applied based on different data element widths.

[0094] The various instruction templates found in class A and class B are useful in different situations. In some embodiments of the invention, different processors or different cores within a processor may support only class A, only class B, or both classes. For example, a high performance general purpose out-of-order core intended for general purpose computing may support only class B, a core intended primarily for graphics and / or scientific (throughput) computing may support only class A, and a core intended for both may support both (of course, cores having some mix of templates and instructions from both classes, but not all templates and instructions from both classes, are within the scope of the invention). Also, a single processor may contain multiple cores, all of which support the same class, or different cores therein supporting different classes. For example, in a processor with separate graphics and general purpose cores, one of the graphics cores intended primarily for graphics and / or scientific computing may support only class A, while one or more general purpose cores may be a high performance general purpose core with out-of-order execution and register renaming intended for general purpose computing supporting only class B. Other processors that do not have a separate graphics core may include another general-purpose in-order or out-of-order core that supports both class A and class B. Of course, in different embodiments of the invention, functionality from one class may also be implemented in the other class. Programs written in high-level languages ​​may be converted (e.g., just-in-time compiled or statically compiled) into a variety of different executable formats, including 1) a format that has only instructions of classes supported by the target processor for execution, or 2) a format that has alternative routines written using different combinations of instructions from all classes, with control flow code that selects which routine to execute based on the instructions supported by the processor currently executing the code. Example Vector Specific Instruction Format

[0095] FIG. 9A is a block diagram illustrating an exemplary vector specific instruction format according to multiple embodiments of the present invention. FIG. 9A illustrates a specific vector specific instruction format 900 that is unique in the sense that it specifies the location, size, interpretation, and order of fields, as well as the values ​​of some of those fields. The specific vector specific instruction format 900 may be used to extend the x86 instruction set, and thus some fields are similar or identical to those used in the existing x86 instruction set and its extensions (e.g., AVX). The format remains consistent with the prefix encoding field, real opcode byte field, MOD R / M field, SIB field, displacement field, and immediate field of the existing x86 instruction set with its extensions. The fields of FIG. 8 are mapped to which fields of FIG. 9A are illustrated.

[0096] Although embodiments of the present invention are described with reference to the specific vector instruction format 900 in the context of the generic vector instruction format 800 for illustrative purposes, it should be understood that the present invention is not limited to the specific vector instruction format 900 except as claimed. For example, the generic vector instruction format 800 contemplates a variety of possible sizes for various fields, but the specific vector instruction format 900 is illustrated as having fields of specific sizes. As a specific example, although the data element width field 864 is illustrated as a one-bit field in the specific vector instruction format 900, the present invention is not so limited (i.e., the generic vector instruction format 800 contemplates data element width fields 864 of other sizes).

[0097] The generic vector friendly instruction format 800 includes the following fields, listed below in the order shown in FIG. 9A:

[0098] EVEX Prefix (bytes 0-3) 902 - Encoded in 4-byte format.

[0099] Format field 840 (EVEX byte 0, bits [7:0]) - The first byte (EVEX byte 0) is the format field 840, which contains 0x62 (a unique value used to distinguish vector friendly instruction formats in one embodiment of the invention).

[0100] The second through fourth bytes (EVEX bytes 1-3) contain a number of bit fields that provide specific functions.

[0101] The REX field 905 (EVEX byte 1, bits [7-5] - consists of the EVEX.R bit field (EVEX byte 1, bit [7] - R), the EVEX.X bit field (EVEX byte 1, bit [6] - X), and the 857BEX byte 1, bit [5] - B). The EVEX.R, EVEX.X, and EVEX.B bit fields serve the same function as the corresponding VEX bit fields and are encoded using one's complement format, i.e., ZMM0 is encoded as 1111B and ZMM15 is encoded as 0000B. The other fields of the instruction encode the lower three bits of the register index (rrr, xxx, and bbb) as known in the art, so that Rrrr, Xxxx, and Bbbb may be formed by appending EVEX.R, EVEX.X, and EVEX.B.

[0102] REX' Field 810 - This is the first portion of the REX' field 810, the EVEX.R' bit field (EVEX byte 1, bit [4]-R') that is used to encode either the top 16 or the bottom 16 of the extended 32 register set. In one embodiment of the invention, this bit, along with the other bits shown below, are stored in a bit-reversed format to distinguish (in well-known x86 32-bit mode) from the BOUND instruction, whose real opcode byte is 62, but the MOD R / M field (described below) does not accept a value of 11 in the MOD field. Alternative embodiments of the invention do not store this and the other bits shown below in an inverted format. A value of 1 is used to encode the bottom 16 registers. In other words, R'Rrrr is formed by combining EVEX.R', EVEX.R, and the other RRR from the other fields.

[0103] Opcode map field 915 (EVEX byte 1, bits [3:0]-mmmm)-its contents encode the implied preceding opcode byte (0F, 0F38, or 0F3).

[0104] Data Element Width field 864 (EVEX byte 2, bit [7]-W)--represented by the notation EVEX.W. EVEX.W is used to define the granularity (size) of the data type (either 32-bit data elements or 64-bit data elements).

[0105] EVEX.vvvv 920 (EVEX byte 2, bits [6:3] - vvvv) - The role of EVEX.vvvv may include: 1) EVEX.vvvv encodes the first source register operand specified in inverted (one's complement) form and is valid for instructions with two or more source operands. 2) EVEX.vvvv encodes the destination register operand, specified in one's complement form for certain vector shifts. 3) EVEX.vvvv does not encode any operand, the field is reserved and should contain 1111b. Thus, EVEX.vvvv field 920 encodes the lower 4 bits of the first source register specifier stored in inverted (one's complement) form. Depending on the instruction, additional different EVEX bit fields are used to extend the specifier size to 32 registers.

[0106] EVEX.U868 Class field (EVEX byte 2, bit [2] - U) - If EVEX.U=0, it indicates class A or EVEX.U0, if EVEX.U=1, it indicates class B or EVEX.U1.

[0107] Prefix encoding field 925 (EVEX byte 2, bits [1:0]-pp) - provides additional bits to the basic operation field. In addition to providing support for legacy SSE instructions in EVEX prefix format, this also has the advantage of compressing the SIMD prefix (rather than requiring one byte to represent a SIMD prefix, the EVEX prefix only requires two bits). In one embodiment, to support legacy SSE instructions that use SIMD prefixes (66H, F2H, F3H) in both the legacy and EVEX prefix formats, these legacy SIMD prefixes are encoded in the SIMD prefix encoding field and expanded at run-time to the legacy SIMD prefixes before being provided to the decoder's PLA (so that the PLA can execute both the legacy and EVEX formats of these legacy instructions without modification). Although newer instructions can directly use the contents of the EVEX prefix encoding field as an opcode extension, certain embodiments extend them in a similar manner for consistency but allow different meanings to be specified by these legacy SIMD prefixes. Alternative embodiments may redesign the PLA to support 2-bit SIMD prefix encodings and therefore not require the extension.

[0108] Alpha field 852 (EVEX byte 3, bit [7] - EH, also known as EVEX.EH, EVEX.rs, EVEX.RL, EVEX.writemask control, and EVEX.N, also denoted as α) - As previously mentioned, this field is context specific.

[0109] Beta field 854 (EVEX byte 3, bits [6:4] - SSS, EVEX.s 2-0 , EVEX.r 2-0 , EVEX.rr1, EVEX.LL0, EVEX.LLB, and also denoted as βββ) - as stated above, this field is context specific.

[0110] REX' field 810 - this is the remainder of the REX' field, the EVEX.V' bit field (EVEX byte 3, bit [3] - V') which can be used to encode either the top 16 or the bottom 16 of the extended 32 register set. This bit is stored in bit-reversed format. A value of 1 is used to encode the bottom 16 registers. In other words, V'VVVV is formed by concatenating EVEX.V' and EVEX.vvvv.

[0111] Write mask field 870 (EVEX byte 3, bits [2:0]-kkk) - its contents specify the index of a register in the write mask register as described above. In one embodiment of the invention, the unique value EVEX.kkk=000 has a special behavior that implies that no write mask is used for the particular instruction (this can be implemented in a variety of ways, including using a write mask that is hardwired to everything, or in hardware that bypasses the masking hardware).

[0112] The real opcode field 930 (byte 4) is also known as the opcode byte. Part of the opcode is specified in this field.

[0113] MOD R / M field 940 (byte 5) includes MOD field 942, Reg field 944, and R / M field 946. As previously described, the contents of MOD field 942 distinguish between memory access and non-memory access operations. The role of Reg field 944 can be summarized in two situations: encoding either a destination register operand or a source register operand, or being treated as an opcode extension and not used to encode any instruction operand. The role of R / M field 946 can include encoding an instruction operand that references a memory address, or encoding either a destination register operand or a source register operand.

[0114] Scale, Index, Base (SIB) Byte (Byte 6) - As previously described, the contents of the scale field 850 are used for memory address generation. SIB.xxx 954 and SIB.bbb 956 - The contents of these fields were previously referenced in relation to the register indices Xxxx and Bbbb.

[0115] Displacement Field 862A (Bytes 7-10) - When the MOD field 942 contains 10, bytes 7-10 are the displacement field 862A, which functions the same as the legacy 32-bit displacement (disp32) and works at byte granularity.

[0116] Displacement factor field 862B (byte 7) - When MOD field 942 contains 01, byte 7 is the displacement factor field 862B. This field location is identical to that of the legacy x86 instruction set 8-bit displacement (disp8), which works at byte granularity. Since disp8 is sign-extended, it can only be addressed between -128 and 127 byte offsets. For a 64-byte cache line, disp8 uses 8 bits that can only be set to four really useful values ​​-128, -64, 0, and 64. Since a wider range is often needed, disp32 is used. However, disp32 is in contrast to disp8 and disp32, which require 4 bytes, because the displacement factor field 862B is a reinterpretation of disp8, and when using the displacement factor field 862B, the actual displacement is determined by the contents of the displacement factor field multiplied by the size of the memory operand access (N). This type of displacement is referred to as disp8 x N. This reduces the average instruction length (a single byte used for displacement, but with a much wider range). Such a compressed displacement is based on the assumption that the effective displacement is a multiple of the granularity of the memory access, and thus the redundant lower bits of the address offset do not need to be encoded. In other words, the displacement factor field 862B replaces the 8-bit displacement of the legacy x86 instruction set. Thus, the displacement factor field 862B is encoded in the same way as the 8-bit displacement of the x86 instruction set (so there is no change to the ModRM / SIB encoding rules), except only that disp8 is overloaded to disp8×N. In other words, there is no change in the encoding rules or encoding length, but only in the interpretation of the displacement value by the hardware (which needs to scale the displacement by the size of the memory operand to get the address offset per byte). The immediate field 872 operates as described above. Full Opcode Field

[0117] 9B is a block diagram illustrating the fields of the vector specific instruction format 900 that make up the full opcode field 874, in accordance with one embodiment of the present invention. Specifically, the full opcode field 874 includes a format field 840, a base operation field 842, and a data element width (W) field 864. The base operation field 842 includes a prefix encoding field 925, an opcode map field 915, and a real opcode field 930. Register Index Field

[0118] 9C is a block diagram illustrating the fields of the specific vector instruction format 900 that make up the register index field 844, in accordance with one embodiment of the present invention. Specifically, the register index field 844 includes a REX field 905, a REX′ field 910, a MODR / M.reg field 944, a MODR / Mr / M field 946, a VVVV field 920, a xxx field 954, and a bbb field 956. Extended computed fields

[0119] 9D is a block diagram illustrating the fields of the specific vector instruction format 900 that make up the extended operation field 850, according to one embodiment of the present invention. When the class (U) field 868 contains a 0, it represents EVEX.U0 (Class A 868A), and when it contains a 1, it represents EVEX.U1 (Class B 868B). When U=0 and the MOD field 942 contains an 11 (signifying a non-memory access operation), the alpha field 852 (EVEX byte 3, bit [7] - EH) is interpreted as an RS field 852A. When the RS field 852A contains a 1 (round 852A.1), the beta field 854 (EVEX byte 3, bits [6:4] - SSS) is interpreted as a round control field 854A. The round control field 854A includes a one-bit SAE field 856 and a two-bit round operation field 858. When RS field 852A contains 0 (data transformation 852A.2), beta field 854 (EVEX byte 3, bits [6:4] - SSS) is interpreted as a 3-bit data transformation field 854B. When U=0 and MOD field 942 contains 00, 01, or 10 (signifying a memory access operation), alpha field 852 (EVEX byte 3, bit [7] - EH) is interpreted as an eviction hint (EH) field 852B and beta field 854 (EVEX byte 3, bits [6:4] - SSS) is interpreted as a 3-bit data manipulation field 854C.

[0120] When U=1, the alpha field 852 (EVEX byte 3, bit [7] - EH) is interpreted as a write mask control (Z) field 852C. When U=1 and the MOD field 942 contains 11 (indicating a non-memory access operation), a portion of the beta field 854 (EVEX byte 3, bit [4] - S0) is interpreted as the RL field 857A, and when it contains 1 (round 857A.1), the remainder of the beta field 854 (EVEX byte 3, bit [6-5] - S 2-1) is interpreted as round operation field 859A, while RL field 857A contains zero (VSIZE857.A2), the remainder of beta field 854 (EVEX byte 3, bits [6-5]-S 2-1 ) in vector length field 859B (EVEX byte 3, bits [6-5]-L 1-0 When U=1 and the MOD field 942 contains 00, 01, or 10 (indicating a memory access operation), the beta field 854 (EVEX byte 3, bits [6:4] - SSS) is interpreted as the vector length field 859B (EVEX byte 3, bits [6-5] - L 1-0 ) and broadcast field 857B (EVEX byte 3, bit [4]-B). Exemplary Register Architecture

[0121] 10 is a block diagram of a register architecture 1000 according to one embodiment of the invention. In the embodiment shown, there are 32 vector registers 1010 that are 58 bits wide, and these registers are referenced as zmm0-zmm31. The lower 256 bits of the lower 16 zmm registers are stacked in registers ymm0-16. The lower 128 bits of the lower 16 zmm registers (the lower 128 bits of the ymm registers) are stacked in registers xmm0-15. The vector specific instruction format 1300 operates on these stacked register files as shown in the table below. [Table 1]

[0122] In other words, the vector length field 859B selects between a maximum length and one or more other shorter lengths, each such shorter length being half the length of the preceding length, and instruction templates without a vector length field 859B operate on the maximum vector length. Additionally, in one embodiment, class B instruction templates of the specific vector friendly instruction format 1300 operate on packed or scalar single / double precision floating point data and packed or scalar integer data. Scalar operations are operations performed on the lowest data element positions in zmm / ymm / xmm registers, with higher data element positions either left as they were before the instruction or zeroed out, depending on the embodiment.

[0123] Write Mask Registers 1015 - In one embodiment shown, there are eight write mask registers (k0 through k7) each 64 bits in size. In an alternative embodiment, the write mask registers 1015 are 16 bits in size. As previously mentioned, in one embodiment of the invention, the vector mask register k0 cannot be used as a write mask; when an encoding that normally indicates k0 is used for the write mask, it selects a hardwired write mask of 0xFFFF, effectively disabling write masking for that instruction.

[0124] General Purpose Registers 1025 - In the embodiment shown, there are sixteen 64-bit general purpose registers that are used with the existing x86 addressing modes to address memory operands. These registers are referenced by the names RAX, RBX, RCX, RDX, RBP, RSI, RDI, RSP, and R8 through R15.

[0125] Scalar floating-point stack register file (x87 stack) 1045 into which the MMX packed integer flat register file 1050 is aliased - in one embodiment shown, the x87 stack is an 8-element stack used to perform scalar floating-point operations on 32 / 64 / 80-bit floating-point data using the x87 instruction set extensions, while the MMX registers are used to perform operations on 64-bit packed integer data and to hold operands for some operations performed between the MMX and xmm registers.

[0126] Alternative embodiments of the invention may use wider or narrower registers. Additionally, alternative embodiments of the invention may use more, fewer, or different register files and registers. Exemplary Core Architectures, Processors, and Computer Architectures

[0127] Processor cores may be implemented in different ways and for different purposes in different processors. For example, implementations of such cores may include: 1) a general purpose in-order core for general purpose computing; 2) a high performance general purpose out-of-order core for general purpose computing; 3) a specialized core primarily for graphics and / or scientific (throughput) computing. Implementations of different processors may include: 1) a CPU that includes one or more general purpose in-order cores for general purpose computing and / or one or more general purpose out-of-order cores for general purpose computing; 2) a co-processor that includes one or more specialized cores primarily for graphics and / or scientific (throughput). Such different processors result in different computer system architectures, which may include: 1) coprocessors on a separate chip from the CPU, 2) coprocessors on a separate die in the same package as the CPU, 3) coprocessors on the same die as the CPU (in which case such coprocessors are sometimes referred to as special purpose logic, such as integrated graphics and / or scientific (throughput) logic, or special purpose cores), and 4) systems-on-chips that may include the described CPU (sometimes referred to as an application core or application processor), the coprocessors described above, and additional functionality on the same die. Exemplary core architectures are described next, followed by descriptions of exemplary processors and computer architectures. Exemplary Core Architecture In-order and out-of-order core block diagram

[0128] FIGURE 11A is a block diagram illustrating both an exemplary in-order pipeline and an exemplary register renaming, out-of-order issue / execution pipeline, according to multiple embodiments of the present invention. FIGURE 11B is a block diagram illustrating both an exemplary embodiment in-order architecture core and an exemplary register renaming, out-of-order issue / execution architecture core included in a processor, according to multiple embodiments of the present invention. The solid lined boxes in FIGURES 11A-11B show the in-order pipeline and the in-order core, while the optional addition of dashed lined boxes shows the register renaming, out-of-order issue / execution pipeline, and the core. The out-of-order aspects will be described assuming that the in-order aspects are a subset of the out-of-order aspects.

[0129] In FIG. 11A , the processor pipeline 1100 includes a fetch stage 1102, a length decode stage 1104, a decode stage 1106, an allocation stage 1108, a rename stage 1110, a scheduling (also known as dispatch or issue) stage 1512, a register read / memory read stage 1114, an execution stage 1112, a writeback / memory write stage 1118, an exception handling stage 1122, and a commit stage 1124.

[0130] 11B shows a processor core 1190 including a front end unit 1130 coupled to an execution engine unit 1150, both coupled to a memory unit 1170. Core 1190 may be a reduced instruction set computing (RISC) core, a complex instruction set computing (CISC) core, a very long instruction word (VLIW) core, or a hybrid or alternative core type. As yet another option, core 1190 may be a special-purpose core such as, for example, a network or communication core, a compression engine, a co-processor core, a general purpose computational graphics processing unit (GPGPU) core, a graphics core, or the like.

[0131] The front-end unit 1130 includes a branch prediction unit 1132 coupled to an instruction cache unit 1134, which is coupled to an instruction translation lookaside buffer (TLB) 1136, which is coupled to an instruction fetch unit 1138, which is coupled to a decode unit 1140. The decode unit 1140 (or decoder) may decode instructions and generate as output one or more micro-operations, microcode entry points, microinstructions, other instructions, or other control signals that are decoded from or otherwise reflect or are derived from the original instruction. The decode unit 1140 may be implemented using a variety of different mechanisms. Examples of suitable mechanisms include, but are not limited to, lookup tables, hardware implementations, programmable logic arrays (PLAs), microcode read-only memories (ROMs), etc. In one embodiment, core 1190 includes a microcode ROM or other medium that stores microcode for particular macro-instructions (e.g., within decode unit 1140 or otherwise within front-end unit 1130). Decode unit 1140 is coupled to a rename / allocator unit 1152 within execution engine unit 1150.

[0132] The execution engine unit 1150 includes a rename / allocator unit 1152 coupled to a retirement unit 1154 and a set of one or more scheduler units 1156. The scheduler units 1156 represent any number of different schedulers including reservation stations, central instruction window, etc. The scheduler units 1156 are coupled to physical register file units 1158. Each of the physical register file units 1158 represents one or more physical register files, different ones of which store one or more different data types, such as scalar integer, scalar floating point, packed integer, packed floating point, vector integer, vector floating point, status (e.g., an instruction pointer, which is the address of the next instruction to be executed), etc. In one embodiment, the physical register file units 1158 include a vector register unit, a writemask register unit, and a scalar register unit. These register units may provide architectural vector registers, vector mask registers, and general purpose registers. The physical register files unit 1158 is overlaid by the retirement unit 1154 to illustrate various ways in which register renaming and out-of-order execution may be implemented (e.g., using a reorder buffer and a retirement register file, using a future file, a history buffer, and a retirement register file, using register mapping and pools of registers, etc.). The retirement unit 1154 and the physical register files unit 1158 are coupled to the execution clusters 1160. The execution clusters 1160 include a set of one or more execution units 1162 and a set of one or more memory access units 1164. The execution units 1162 may perform various operations (e.g., shift, add, subtract, multiply) on various types of data (e.g., scalar floating point, packed integer, packed floating point, vector integer, vector floating point). Some embodiments may include multiple execution units dedicated to a particular function or set of functions, while other embodiments may include only one execution unit or multiple execution units that all perform all functions.Scheduler unit 1156, physical register file unit 1158, and execution cluster 1160 are shown as possibly multiple because certain embodiments create separate pipelines for particular types of data / operations (e.g., a scalar integer pipeline, a scalar floating point / packed integer / packed floating point / vector integer / vector floating point pipeline, and / or a memory access pipeline, each with its own scheduler unit, physical register file unit, and / or execution cluster - in the case of a separate memory access pipeline, certain embodiments are implemented where only the execution cluster of this pipeline has a memory access unit 1164). It should also be understood that if separate pipelines are used, one or more of these pipelines may be out-of-order issue / execution and the rest may be in-order.

[0133] The set of memory access units 1164 is coupled to a memory unit 1170, which includes a data TLB unit 1172 coupled to a data cache unit 1174, which is coupled to a level 2 (L2) cache unit 1176. In one exemplary embodiment, the memory access units 1164 may include a load unit, a store address unit, and a store data unit, each of which is coupled to the data TLB unit 1172 in the memory unit 1170. The instruction cache unit 1134 is further coupled to a level 2 (L2) cache unit 1176 in the memory unit 1170. The L2 cache unit 1176 is coupled to one or more other levels of cache and ultimately to main memory.

[0134] By way of example, an exemplary register renaming, out-of-order issue / execution core architecture may implement the pipeline 1100 as follows: 1) the instruction fetch 1138 performs the fetch stage 1102 and the length decode stage 1104; 2) the decode unit 1140 performs the decode stage 1106; 3) the rename / allocator unit 1152 performs the allocation stage 1108 and the rename stage 1110; 4) the scheduler unit performs the scheduling stage 1512; 5) the physical register file unit 1158 and the memory unit 1170 perform the register read / memory read stage 1114, and the execution clusters 1160 perform the execution stage 1112; 6) the memory unit 1170 and the physical register file unit 1158 perform the writeback / memory write stage 1118; 7) various units may be involved in the exception handling stage 1122. 8) The retirement unit 1154 and the physical register file unit 1158 execute the commit stage 1124.

[0135] Core 1190 may support one or more instruction sets (e.g., the x86 instruction set (with some extensions added in newer versions), the MIPS instruction set from MIPS Technologies of Sunnyvale, Calif., the ARM instruction set (with optional additional extensions such as NEON) from ARM Holdings of Sunnyvale, Calif.), including the instructions described herein. In one embodiment, core 1190 includes logic to support packed data instruction set extensions (e.g., AVX1, AVX2), allowing operations used by many multimedia applications to be performed using packed data.

[0136] It should be understood that a core may support multithreading (executing two or more parallel sets of operations or threads) in a variety of ways, including time sliced ​​multithreading, simultaneous multithreading (wherein a single physical core provides a logical core for each of the threads that the physical core is multithreading simultaneously), or a combination thereof (e.g., time sliced ​​fetch and decode followed by simultaneous multithreading, such as in Intel® Hyper-Threading Technology).

[0137] Although register renaming is described in the context of out-of-order execution, it should be understood that register renaming may be used in in-order architectures. The illustrated embodiment of the processor also includes separate instruction and data cache units 1134 / 1174 and a shared L2 cache unit 1176, although alternative embodiments may have a single internal cache for both instructions and data, such as a level 1 (L1) internal cache or multiple levels of internal cache. In some embodiments, the system may include a combination of an internal cache and an external cache that is external to the core and / or processor. Alternatively, all of the cache may be external to the core and / or processor. Specific Exemplary In-Order Core Architecture

[0138] 12A-12B show block diagrams of a more specific exemplary in-order core architecture, where the core is one of several logic blocks (including other cores of the same and / or different types) in a chip. The logic block communicates with some fixed function logic, memory I / O interfaces, and other necessary I / O logic, depending on the application, via a high bandwidth interconnect network (e.g., a ring network).

[0139] 12A is a block diagram of a single processor core along with its connection to an on-die interconnect network 1202 and its local subset of a level 2 (L2) cache 1204, in accordance with embodiments of the present invention. In one embodiment, an instruction decoder 1200 supports the x86 instruction set with a packed data instruction set extension. An L1 cache 1206 allows low-latency access to cache memory for the scalar and vector units. Although in one embodiment (to simplify the design) the scalar unit 1208 and the vector unit 1210 use separate register sets (scalar registers 1212 and vector registers 1214, respectively) and data transfers between them are written to memory and then read back from the level 1 (L1) cache 1206, alternative embodiments of the present invention may use different approaches (e.g., using a single register set or including a communication path that allows data to be transferred between the two register files without writes and reads back).

[0140] The local subset of L2 cache 1204 is part of a global L2 cache that is divided into separate local subsets, one per processor core. Each processor core has a direct access path to its own local subset of L2 cache 1204. Data read by a processor core is stored in its L2 cache subset 1204 and can be accessed quickly in parallel with other processor cores accessing their own local L2 cache subsets. Data written by a processor core is stored in its own L2 cache subset 1204 and is flushed from other subsets when necessary. The ring network ensures coherency for shared data. The ring network is bidirectional to allow agents such as processor cores, L2 caches, and other logic blocks to communicate with each other within the chip. Each ring data path is 1012 bits wide per direction.

[0141] Figure 12B is an expanded view of a portion of the processor core of Figure 12A in accordance with embodiments of the present invention. Figure 12B includes an L1 data cache 1206A, which is part of the L1 cache 1204, and more details regarding the vector unit 1210 and vector registers 1214. In particular, the vector unit 1210 is a 12-wide vector processing unit (VPU) (see 12-wide ALU 1228), which executes one or more of integer, single precision float, and double precision float instructions. The VPU supports swizzling of register inputs using swizzle unit 1220, numeric conversion using numeric conversion units 1222A-B, and duplication for memory inputs using duplication unit 1224. A write mask register 1226 allows for the resulting vector writes to be predicated.

[0142] 13 is a block diagram of a processor 1300 that may have more than one core, may have an integrated memory controller, and may have integrated graphics, in accordance with embodiments of the present invention. The solid lined box in FIG. 13 illustrates a processor 1300 with a single core 1302A, a system agent 1310, and a set of one or more bus controller units 1312, while the optional addition of a dashed lined box illustrates an alternative processor 1300 with multiple cores 1302A-N, a set of one or more integrated memory controller units 1314 in the system agent unit 1310, and dedicated logic 1308.

[0143] Thus, different implementations of the processor 1300 may include: 1) a CPU with special purpose logic 1308 that is integrated graphics and / or scientific (throughput) logic (which may include one or more cores) and one or more general purpose cores 1302A-N (e.g., general purpose in-order cores, general purpose out-of-order cores, a combination of the two); 2) a coprocessor with many special purpose cores 1302A-N primarily for graphics and / or scientific (throughput); and 3) a coprocessor with many general purpose in-order cores 1302A-N. Thus, the processor 1300 may be a general purpose processor, coprocessor, or special purpose processor, such as, for example, a network or communication processor, a compression engine, a graphics processor, a GPGPU (general purpose graphics processing unit), a high throughput multiple integrated core (MIC) coprocessor (including 30 or more cores), an embedded processor, or the like. The processor may be implemented on one or more chips. The processor 1300 may be a part of and / or implemented on one or more substrates using any of a number of process technologies, such as, for example, BiCMOS, CMOS, or NMOS.

[0144] The memory hierarchy includes one or more levels of cache within the core, a set of shared cache units 1306 or one or more shared cache units 1306, and an external memory (not shown) coupled to a set of integrated memory controller units 1314. The set of shared cache units 1306 may include one or more mid-level caches, such as a level 2 (L2), level 3 (L3), level 4 (L4) or other level cache, a last level cache (LLC), and / or combinations thereof. In one embodiment, a ring-based interconnect unit 1312 interconnects the integrated graphics logic 1308 (the integrated graphics logic 1308 is an example of dedicated logic and is also referred to herein as dedicated logic), the set of shared cache units 1306, and the system agent unit 1310 / integrated memory controller unit 1314, although alternative embodiments may use any number of well-known techniques for interconnecting such units. In one embodiment, coherency is maintained between the one or more cache units 1306 and the cores 1302A-N.

[0145] In some embodiments, one or more of the cores 1302A-N are capable of multithreading. The system agent 1310 includes these components that coordinate the operation of the cores 1302A-N. The system agent unit 1310 may include, for example, a power control unit (PCU) and a display unit. The PCU may be or may include the logic and components necessary to coordinate the power state of the cores 1302A-N and the integrated graphics logic 1308. The display unit is for driving one or more externally connected displays.

[0146] The cores 1302A-N may be homogenous or heterogeneous with respect to architectural instruction sets, i.e., two or more cores 1302A-N may be capable of executing the same instruction set, while other cores may be capable of executing only a subset of the instruction set or a different instruction set. Exemplary Computer Architecture

[0147] 14-17 are block diagrams of exemplary computer architectures. Other system designs and configurations known in the art for laptops, desktops, handheld PCs, personal digital assistants, engineering workstations, servers, network devices, network hubs, switches, embedded processors, digital signal processors (DSPs), graphics devices, video game devices, set-top boxes, microcontrollers, mobile phones, portable media players, handheld devices, and a variety of other electronic devices are also suitable. In general, a variety of systems or electronic devices capable of incorporating a processor and / or other execution logic as disclosed herein are generally suitable.

[0148] 14, a block diagram of a system 1400 is shown, according to one embodiment of the present invention. The system 1400 may include one or more processors 1410, 1415 coupled to a controller hub 1420. In one embodiment, the controller hub 1420 includes a graphics memory controller hub (GMCH) 1490 and an input / output hub (IOH) 1450 (which may be on separate chips). The GMCH 1490 includes a memory and graphics controller to which the memory 1440 and coprocessor 1445 are coupled. The IOH 1450 couples input / output (I / O) devices 1460 to the GMCH 1490. Alternatively, one or both of the memory and graphics controller are integrated within the processor (as described herein) and the memory 1440 and coprocessor 1445 are directly coupled to the controller hub 1420 in a single chip with the processor 1410 and IOH 1450.

[0149] The optional nature of the additional processor 1415 is indicated in Figure 14 by the dashed lines. Each processor 1410, 1415 may include one or more processing cores as described herein and may be some version of the processor 1300.

[0150] The memory 1440 may be, for example, dynamic random access memory (DRAM), phase change memory (PCM), or a combination of the two. For at least one embodiment, the controller hub 1420 communicates with the processors 1410, 1415 via a multi-drop bus such as a front side bus (FSB), a point-to-point interface such as a QuickPath Interconnect (QPI), or a similar connection 1495.

[0151] In one embodiment, the coprocessor 1445 is a special purpose processor, such as, for example, a high throughput MIC processor, a network or communication processor, a compression engine, a graphics processor, a GPGPU, an embedded processor, or the like. In one embodiment, the controller hub 1420 may include an integrated graphics accelerator.

[0152] There may be various differences between the physical resources 1410, 1415 with respect to a set of metrics of merit including architectural characteristics, microarchitectural characteristics, thermal characteristics, power consumption characteristics, and the like.

[0153] In one embodiment, the processor 1410 executes instructions that control data processing operations of a general type. Coprocessor instructions may be embedded within the instructions. The processor 1410 recognizes these coprocessor instructions as being of a type that should be executed by an attached coprocessor 1445. Thus, the processor 1410 issues these coprocessor instructions (or control signals representing the coprocessor instructions) to the coprocessor 1445 over a coprocessor bus or other interconnect. The coprocessor 1445 accepts the received coprocessor instructions and executes them.

[0154] 15, there is shown a block diagram of a first more specific exemplary system 1500 according to one embodiment of the present invention. As shown in FIG. 15, the multiprocessor system 1500 is a point-to-point interconnect system and includes a first processor 1570 and a second processor 1580 coupled via a point-to-point interconnect 1550. Each of the processors 1570 and 1580 may be some version of the processor 1300. In one embodiment of the present invention, the processors 1570 and 1580 are the processors 1410 and 1415, respectively, while the coprocessor 1538 is the coprocessor 1445. In another embodiment, the processors 1570 and 1580 are the processors 1410 and 1445, respectively.

[0155] Processors 1570 and 1580 are shown as including integrated memory controller (IMC) units 1572 and 1582, respectively. Processor 1570 also includes point-to-point (PP) interfaces 1576 and 1578 as part of its bus controller unit, and similarly, second processor 1580 includes PP interfaces 1586 and 1588. Processors 1570, 1580 may exchange information using PP interface circuits 1578, 1588 via point-to-point (PP) interface 1550. As shown in FIG. 15, IMCs 1572 and 1582 couple the processors to respective memories, i.e., memory 1532 and memory 1534, which may be part of main memory locally attached to the respective processors.

[0156] Processors 1570, 1580 may each exchange information with chipset 1590 via respective PP interfaces 1552, 1554 using point-to-point interface circuits 1576, 1594, 1586, 1598. Chipset 1590 may optionally exchange information with coprocessor 1538 via high performance interface 1592. In one embodiment, coprocessor 1538 is a special purpose processor, such as, for example, a high throughput MIC processor, a network or communication processor, a compression engine, a graphics processor, a GPGPU, an embedded processor, or the like.

[0157] A shared cache (not shown) may be included within either processor or external to both processors and may be further connected to the processors via the PP interconnect so that when the processors are placed in a low power mode, local cache information of either or both processors may be stored in the shared cache.

[0158] Chipset 1590 may be coupled to a first bus 1516 via an interface 1596. In one embodiment, first bus 1516 may be a bus such as a Peripheral Component Interconnect (PCI) bus, or a PCI Express bus or other third generation I / O interconnect bus, although the scope of the invention is not limited in this respect.

[0159] As shown in FIG. 15, various I / O devices 1514 may be coupled to the first bus 1516, along with a bus bridge 1518 that couples the first bus 1516 to a second bus 1520. In one embodiment, one or more additional processors 1515, such as a co-processor, a high throughput MIC processor, a GPGPU, an accelerator (e.g., a graphics accelerator or a digital signal processing (DSP) unit), a field programmable gate array, or any other processor, are coupled to the first bus 1516. In one embodiment, the second bus 1516 may be a low pin count (LPC) bus. In one embodiment, various devices may be coupled to the second bus 1516, including, for example, a keyboard and / or mouse 1522, a communication device 1527, and a storage unit 1528, such as a disk drive or other mass storage device, that may contain instructions / code and data 1530. Additionally, audio I / O 1524 may be coupled to the second bus 1516. It should also be noted that other architectures are possible, for example, instead of the point-to-point architecture of Figure 15, the system could implement a multi-drop bus or other such architecture.

[0160] Referring now to Figure 16, there is shown a block diagram of a second, more specific, exemplary system 1600, in accordance with one embodiment of the present invention. Like elements in Figures 15 and 16 have like reference numbers, and certain aspects of Figure 15 have been omitted from Figure 16 to avoid obscuring other aspects of Figure 16.

[0161] FIG. 16 shows that processors 1570, 1580 may include integrated memory and I / O control logic (“CL”) 1572 and 1582, respectively. Thus, CL 1572, 1582 includes an integrated memory controller unit and includes I / O control logic. FIG. 16 shows that memory 1532, 1534 is coupled to CL 1572, 1582, as well as I / O devices 1614 are coupled to control logic 1572, 1582. Legacy I / O devices 1615 are coupled to chipset 1590.

[0162] Referring now to FIG. 17, a block diagram of an SoC 1700 is shown according to an embodiment of the present invention. Similar elements in FIG. 13 have similar reference numbers. Also, the dashed boxes are optional features on a more advanced SoC. In FIG. 17, an interconnect unit 1702 is coupled to an application processor 1710 including a set of one or more cores 1302A-N including cache units 1304A-N and a shared cache unit 1306, a system agent unit 1310, a bus controller unit 1316, an integrated memory controller unit 1314, a set or one or more coprocessors 1716 that may include integrated graphics logic, an image processor, an audio processor, and a video processor, a static random access memory (SRAM) unit 1730, a direct memory access (DMA) unit 1732, and a display unit 1740 for coupling to one or more external displays. In one embodiment, the coprocessor 1720 includes a special purpose processor, such as, for example, a network or communication processor, a compression engine, a GPGPU, a high-throughput MIC processor, an embedded processor, or the like.

[0163] The embodiments of the mechanisms disclosed herein may be implemented in hardware, software, firmware, or a combination of such implementation approaches. The embodiments of the present invention may be implemented as a computer program or program code running on a programmable system comprising at least one processor, a storage system (including volatile and non-volatile memory and / or storage elements), at least one input device, and at least one output device.

[0164] Program code, such as code 1530 shown in Figure 15, may be applied to input instructions to perform functions described herein and to generate output information. The output information may be applied to one or more output devices, in known fashion. For purposes of this application, a processing system includes any system that has a processor, such as, for example, a digital signal processor (DSP), a microcontroller, an application specific integrated circuit (ASIC), or a microprocessor.

[0165] The program code may be implemented in a high level procedural or object-oriented programming language to communicate with a processing system. The program code may also be implemented in assembly or machine language, if desired. Indeed, the mechanisms described herein are not limited in scope to any particular programming language. In any case, the language may be a compiled or interpreted language.

[0166] One or more aspects of at least one embodiment may be implemented by representative instructions stored on a machine-readable medium that represent various logic within a processor, which, when read by a machine, causes the machine to produce logic that performs the techniques described herein. Such representations, known as "IP cores," may be stored on tangible machine-readable media and supplied to various customers or manufacturing facilities for loading into manufacturing machines that actually create the logic or processors.

[0167] Such machine-readable storage media may include non-transitory, tangible arrangements of articles manufactured or formed by a machine or device, including, without limitation, storage media such as hard disks, floppy disks, optical disks, any other type of disk including compact disk read-only memory (CD-ROM), compact disk re-writable (CD-RW), and magneto-optical disks, read-only memory (ROM), random access memory (RAM) such as dynamic random access memory (DRAM), static random access memory (SRAM), erasable programmable read-only memory (EPROM), flash memory, electrically erasable programmable read-only memory (EEPROM), phase change memory (PCM), semiconductor devices such as magnetic or optical cards, or any other type of medium suitable for storing electronic instructions.

[0168] Accordingly, embodiments of the present invention also include non-transitory, tangible, machine-readable media that include instructions or that include design data, such as a hardware description language (HDL), that define the structures, circuits, devices, processors, and / or system functions described herein. Such embodiments may also be referred to as program products. Emulation (including binary conversion, code morphing, etc.)

[0169] In some cases, an instruction converter may be used to convert instructions from a source instruction set to a target instruction set. For example, the instruction converter may translate, morph, emulate, or otherwise convert (e.g., using static binary translation, dynamic binary translation including dynamic compilation), instructions into one or more other instructions to be processed by the core. The instruction converter may be implemented in software, hardware, firmware, or a combination thereof. The instruction converter may be on-processor, off-processor, or partly on-processor and partly off-processor.

[0170] Figure 18 is a block diagram contrasting the use of a software instruction converter to convert binary instructions in a source instruction set to binary instructions in a target instruction set, according to multiple embodiments of the present invention. In the illustrated embodiment, the instruction converter is a software instruction converter, but alternatively, the instruction converter may be implemented in software, firmware, hardware, or various combinations thereof. Figure 18 illustrates that a program in a high-level language 1802 may be compiled using an x86 compiler 1804 to generate x86 binary code 1806 that may be natively executed by a processor having at least one x86 instruction set core 1816. Processor with at least one x86 instruction set core 1816 represents any processor capable of performing substantially the same functions as an Intel processor with at least one x86 instruction set core by compatibly executing or otherwise processing (1) a substantial portion of the instruction set of the Intel x86 instruction set core, or (2) object code versions of applications or other software intended to invoke an Intel processor with at least one x86 instruction set core, to achieve substantially the same results as an Intel processor with at least one x86 instruction set core. x86 compiler 1804 represents a compiler operable to generate x86 binary code 1806 (e.g., object code) that can be executed on a processor with at least one x86 instruction set core 1816, with or without additional linking operations. Similarly, FIG. 18 shows that a program in a high-level language 1802 may be compiled using an alternative instruction set compiler 1808 to generate alternative instruction set binary code 1810 that may be natively executed by a processor that does not have at least one x86 instruction set core 1814 (e.g., a processor that executes the MIP instruction set from MIPS Technologies of Sunnyvale, Calif. and / or that has a core that executes the ARM instruction set from ARM Holdings of Sunnyvale, Calif.).An instruction converter 1812 is used to convert the x86 binary code 1806 into code that can be executed natively by a processor 1814 that does not have an x86 instruction set core. This converted code is unlikely to be identical to the alternative instruction set binary code 1810 because an instruction converter that could do this would be difficult to create. However, the converted code implements common operations and is composed of instructions from the alternative instruction set. Thus, the instruction converter 1812 represents software, firmware, hardware, or a combination thereof that allows a processor or other electronic device that does not have an x86 instruction set processor or core to execute the x86 binary code 1806, via emulation, simulation, or any other process.

[0171] Further examples:

[0172] (Example 1) A processor comprising: a fetch circuit that fetches a single instruction that accesses a compressed graphics list; a decode circuit that decodes the fetched single instruction; and an execute circuit that executes the decoded single instruction that provides access to the compressed graphics list by receiving an indirect reference request from a load store queue at a first arithmetic engine associated with a first data location, calculating by the first arithmetic engine a second data location associated with a second arithmetic engine in response to the indirect reference request, calculating by the second arithmetic engine a third data location associated with a third arithmetic engine in response to receiving data from the third data location by the third arithmetic engine, and providing a data response to the load store queue.

[0173] (Example 2) The processor of Example 1, wherein the single instruction includes at least one of a list load, a pointer dereference, a load indirect reference operation, or a store indirect reference operation.

[0174] (Example 3) The processor of Example 1, wherein the first computation engine reads a first pointer from the first data location and calculates the second data location associated with a second pointer.

[0175] (Example 4) The processor of Example 3, wherein the second calculation engine reads the second pointer from the second data location and calculates the third data location associated with a third pointer.

[0176] (Example 5) The processor of Example 1, wherein the data location includes a memory location in a pipelined indirection system.

[0177] (Example 6) The processor of Example 1, wherein the indirect reference request includes at least one of a multiple indirect reference or a single indirect reference.

[0178] (Example 7) The processor of Example 1, wherein the indirect reference request includes an indirect reference operation, and the indirect reference operation includes an indirect reference load operation or an indirect reference store operation.

[0179] (Example 8) The processor of Example 7, further comprising determining a level of indirection of the indirect load operation or the indirect store operation.

[0180] (Example 9) The processor of Example 1, wherein the data response includes at least one of a data value or a data acknowledgment.

[0181] (Example 10) The processor of Example 1, wherein the indirect reference request includes an address associated with the load store queue, and the address associated with the load store queue is sent in the indirect reference request to return data to the load store queue in one or more arithmetic engines of the pipeline indirect reference system.

[0182] (Example 11) A method comprising the steps of fetching and decoding a single instruction that accesses a compressed graphics list using a fetch circuit and a decode circuit, and responding to the decoded instruction using an execution circuit by receiving an indirect reference request at a first computation engine associated with a first data location from a load store queue, determining by the first computation engine a second data location associated with a second computation engine in response to the indirect reference request, determining by the second computation engine a third data location associated with a third computation engine, and providing a data response to the load store queue in response to receiving data from the third data location by the third computation engine.

[0183] (Example 12) The method of Example 11, wherein the single instruction includes at least one of a list load, a pointer dereference, a load indirection operation, or a store indirection operation.

[0184] (Example 13) The method of Example 11, wherein the first computation engine reads a first pointer from the first data location and calculates the second data location associated with a second pointer.

[0185] (Example 14) The method of Example 11, wherein the second computation engine reads the second pointer from the second data location and calculates the third data location associated with a third pointer.

[0186] (Example 15) The method of Example 11, wherein the indirection request includes an indirection level, and the indirection level indicates a multi-level indirection.

[0187] (Example 16) The method of Example 11, wherein the indirect reference request includes an indirect reference operation, and the indirect reference operation includes an indirect reference load operation or an indirect reference store operation.

[0188] (Example 17) The method of example 11, wherein the data response includes a data value.

[0189] (Example 18) The method of Example 11, wherein the indirect reference request includes an address associated with the load store queue, and the address associated with the load store queue is sent in the indirect reference request to return data to the load store queue in one or more arithmetic engines of the pipeline indirect reference system.

[0190] (Example 19) A system comprising a memory; a processor having a fetch circuit that fetches a single instruction that accesses a compressed graphics list; a decode circuit that decodes the fetched single instruction; and an execute circuit that executes the decoded single instruction that provides access to the compressed graphics list by receiving an indirect reference request at a first arithmetic engine associated with a first data location from a load store queue, calculating by the first arithmetic engine a second data location associated with a second arithmetic engine in response to the indirect reference request, calculating by the second arithmetic engine a third data location associated with a third arithmetic engine in response to receiving data from the third data location by the third arithmetic engine, and providing a data response to the load store queue.

[0191] (Example 20) The system of Example 19, wherein the data response includes at least one of a data value or a data acknowledgment. [Other possible items] [Item 1] a fetch circuit for fetching a single instruction that accesses the compressed graphics list; a decode circuit for decoding the single fetched instruction; receiving an indirection request at a first compute engine associated with the first data location from a load store queue; calculating, by the first computation engine, a second data location associated with a second computation engine; calculating, by the second computation engine, a third data location associated with a third computation engine in response to the indirect reference request; and providing a data response to the load store queue in response to receiving data from the third data location by the third compute engine; an execution circuit for executing said decoded single instruction providing access to said compressed graphics list by A processor comprising: [Item 2] 2. The processor of claim 1, wherein the single instruction includes at least one of a list load, a pointer dereference, a load indirect reference operation, or a store indirect reference operation. [Item 3] The first calculation engine includes: Reading a first pointer from the first data location; calculating said second data location associated with said second pointer; Item 1. The processor of item 1. [Item 4] The second calculation engine includes: reading the second pointer from the second data location; calculating said third data location associated with the third pointer; Item 3. The processor of item 3. [Item 5] 2. The processor of claim 1, wherein the data location comprises a memory location in a pipeline indirection system. [Item 6] 2. The processor of claim 1, wherein the indirect reference request includes at least one of a multiple indirect reference or a single indirect reference. [Item 7] 2. The processor of claim 1, wherein the indirect reference request includes an indirect reference operation, and the indirect reference operation includes an indirect reference load operation or an indirect reference store operation. [Item 8] 8. The processor of claim 7, further comprising determining a level of indirection of the indirect load operation or the indirect store operation. [Item 9] 2. The processor of claim 1, wherein the data response includes at least one of a data value or a data acknowledgment. [Item 10] 2. The processor of claim 1, wherein the indirect reference request includes an address associated with the load store queue, and the address associated with the load store queue is sent in the indirect reference request to return data to the load store queue in one or more arithmetic engines of the pipeline indirect reference system. [Item 11] fetching and decoding, using fetch and decode circuitry, a single instruction that accesses the compressed graphics list; receiving an indirection request at a first compute engine associated with the first data location from a load store queue; determining, by the first computation engine, a second data location associated with a second computation engine; determining, by the second computing engine, in response to the indirect reference request, a third data location associated with a third computing engine; and providing a data response to the load store queue in response to receiving data from the third data location by the third compute engine; responding to the decoded instructions using execution circuitry according to A method comprising: [Item 12] Item 12. The method of item 11, wherein the single instruction includes at least one of a list load, a pointer dereference, a load indirect reference operation, or a store indirect reference operation. [Item 13] The first computing engine is Reading a first pointer from the first data location; calculating said second data location associated with said second pointer; Item 12. The method according to item 11. [Item 14] The second calculation engine includes: reading the second pointer from the second data location; calculating said third data location associated with the third pointer; Item 12. The method according to item 11. [Item 15] Item 12. The method of item 11, wherein the indirection request includes an indirection level, the indirection level indicating multiple levels of indirection. [Item 16] Item 12. The method of item 11, wherein the indirection request includes an indirection operation, and the indirection operation includes an indirection load operation or an indirection store operation. [Item 17] Item 12. The method of item 11, wherein the data response includes a data value. [Item 18] Item 12. The method of item 11, wherein the indirect reference request includes an address associated with the load store queue, and the address associated with the load store queue is sent in the indirect reference request to return data to the load store queue in one or more arithmetic engines of the pipeline indirect reference system. [Item 19] Memory, 1. A processor comprising: a fetch circuit for fetching a single instruction that accesses the compressed graphics list; a decode circuit for decoding the single fetched instruction; receiving an indirection request at a first compute engine associated with the first data location from a load store queue; calculating, by the first computation engine, a second data location associated with a second computation engine; calculating, by the second computation engine, a third data location associated with a third computation engine in response to the indirect reference request; and providing a data response to the load store queue in response to receiving data from the third data location by the third compute engine; an execution circuit for executing said decoded single instruction providing access to said compressed graphics list by a processor having A system comprising: [Item 20] 20. The system of claim 19, wherein the data response includes at least one of a data value or a data acknowledgment.

Claims

1. a fetch circuit for fetching a single instruction that accesses the compressed graphics list; a decode circuit for decoding the single fetched instruction; receiving an indirection request at a first compute engine associated with the first data location from a load store queue; calculating, by the first computation engine, a second data location associated with a second computation engine; reading, by the second computing engine, in response to the indirect reference request, a pointer from the second data location to calculate a third data location associated with a third computing engine; and providing a data response to the load store queue in response to accessing data at the third data location by the third compute engine. an execution circuit for executing the decoded single instruction providing access to the compressed graphics list by Equipped with 2. A processor, comprising: a first computation engine that uses register values ​​to calculate the second data location; and a second computation engine that uses register values ​​to calculate the third data location.

2. The processor of claim 1 , wherein the single instruction comprises at least one of a list load, a pointer dereference, a load indirect operation, or a store indirect operation.

3. The first computation engine comprises: reading a first pointer from the first data location; Calculating the second data location associated with a second pointer; 3. A processor according to claim 1 or 2.

4. The second computing engine includes: reading the second pointer from the second data location; Calculating the third data location associated with a third pointer; The processor of claim 3.

5. 5. A processor as claimed in claim 1, wherein the data locations comprise memory locations in a pipelined indirection system.

6. The processor of claim 1 , wherein the indirection request includes a multiple indirection.

7. The processor of claim 1 , wherein the indirect reference request comprises an indirect reference operation, and the indirect reference operation comprises an indirect reference load operation or an indirect reference store operation.

8. The processor of claim 7 , further comprising determining a level of indirection of the indirect load operation or the indirect store operation.

9. The processor of claim 1 , wherein the data response includes at least one of a data value or a data acknowledgement.

10. 2. The processor of claim 1, wherein the indirect reference request includes an address associated with the load store queue, and the address associated with the load store queue is transmitted in the indirect reference request to return data to the load store queue in one or more compute engines of a pipelined indirect reference system.

11. fetching and decoding, using fetch and decode circuitry, a single instruction that accesses the compressed graphics list; receiving an indirection request at a first compute engine associated with the first data location from a load store queue; determining, by the first computation engine, a second data location associated with a second computation engine; reading, by the second computing engine, in response to the indirect reference request, a pointer from the second data location to determine a third data location associated with a third computing engine; and providing a data response to the load store queue in response to accessing data at the third data location by the third compute engine. responding to the decoded instructions using execution circuitry according to Equipped with The method of claim 1, wherein the first computation engine at least one of calculates the second data location using a register value and calculates the third data location using a register value.

12. 12. The method of claim 11, wherein the single instruction includes at least one of a list load, a pointer dereference, a load indirect operation, or a store indirect operation.

13. The first computation engine comprises: reading a first pointer from the first data location; Calculating the second data location associated with a second pointer; 13. The method according to claim 11 or 12.

14. The second computing engine includes: reading a second pointer from the second data location; Calculating the third data location associated with a third pointer; 14. The method according to any one of claims 11 to 13.

15. The method of claim 11 , wherein the indirection request includes an indirection level, the indirection level indicating multiple levels of indirection.

16. The method of claim 11 , wherein the indirection request comprises an indirection operation, and the indirection operation comprises an indirection load operation or an indirection store operation.

17. The method of claim 11 , wherein the data response includes a data value.

18. 12. The method of claim 11, wherein the indirection request includes an address associated with the load store queue, and the address associated with the load store queue is transmitted in the indirection request to return data to the load store queue in one or more compute engines of a pipelined indirection system.

19. Memory, 1. A processor comprising: a fetch circuit for fetching a single instruction that accesses the compressed graphics list; a decode circuit for decoding the single fetched instruction; receiving an indirection request at a first compute engine associated with the first data location from a load store queue; calculating, by the first computation engine, a second data location associated with a second computation engine; reading, by the second computing engine, in response to the indirect reference request, a pointer from the second data location to calculate a third data location associated with a third computing engine; and providing a data response to the load store queue in response to accessing data at the third data location by the third compute engine. an execution circuit for executing the decoded single instruction providing access to the compressed graphics list by a processor having Equipped with The system, wherein the first computation engine at least one of calculates the second data location using register values ​​and calculates the third data location using register values.

20. 20. The system of claim 19, wherein the data response includes at least one of a data value or a data acknowledgment.

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