Fault Identification and Compensation in Heater Arrays

Abstract

To provide a system, an apparatus, a method, and a computer program for identification of a failure and compensation for a failure in a heater array.SOLUTION: A system and a method include a step of identifying two X buses and two Y buses of a heater array including the location of a failure. Confirmation of a single failure within the heater array is executed after identifying the two X buses and two Y buses. Once the single failure is confirmed, the location of the failure is identified. The method includes a step of compensating for the single failure by adjusting a duty cycle of a heater at the location of the failure, adjusting additional duty cycles of heaters along the same X bus as the failed heater and the same Y bus as the failed heater, and maintaining remaining duty cycles of power provided to remaining heaters of the heater array.SELECTED DRAWING: Figure 4B

Description

[Technical field]

[0001] The present disclosure relates to systems and methods for fault identification and fault compensation in heater arrays. [Background technology]

[0002] The plasma tool includes a radio frequency (RF) generator and a plasma chamber. The RF generator is coupled to the plasma chamber through a matcher. The RF generator generates an RF signal and provides the RF signal to the plasma chamber through the matcher.

[0003] A substrate is processed in the plasma chamber using a plasma that is generated when an RF signal is provided to the plasma chamber along with one or more gases. During processing of the substrate, a temperature in the plasma chamber is controlled. One or more heaters in the plasma chamber are controlled to control the temperature.

[0004] It is in this context that the embodiments described in this disclosure arise.

[0005] The description of the background art provided herein is intended to provide a general background to the present disclosure, and the work of the inventors named herein, to the extent described in this background art, together with aspects of the description that would not ordinarily be considered prior art at the time of filing, are not admitted, expressly or impliedly, as prior art to the present disclosure. Summary of the Invention

[0006] The embodiments of the present disclosure provide a system, an apparatus, a method, and a computer program for fault identification and fault compensation in a heater array. It should be appreciated that the embodiments can be embodied in various forms, such as a process, an apparatus, a system, a device, or a method recorded on a computer readable medium. Some embodiments are described below.

[0007] A plasma chamber component (such as an electrostatic chuck or showerhead) has a heater matrix, where each node (i.e., heater) has a diode and a resistive heating element. The heater matrix is ​​sometimes referred to as a heater array. If a diode fails, multiple unaddressed heaters of the heater matrix will receive undesired bonus currents that cause uncontrollable heating profiles on the wafer being processed. The diode failure goes undetected. Therefore, there is no recovery method implemented when a diode failure occurs. After a diode failure is detected, the component is scrapped, the plasma tool with the plasma chamber is shut down, and a replacement component is ordered. Also, all wafers processed with the failed diode are scrapped. Wafer loss is very costly. Replacement components are costly. Also, system downtime occurs because the plasma tool cannot operate until the replacement component arrives and is installed in the plasma tool. The systems and methods disclosed herein provide detection of diode failures, which can prevent wafer scrapping. Additionally, the systems and methods disclosed herein provide additional time to order replacement parts without taking the plasma tool out of service and compromising the quality of wafer processing.

[0008] The systems and methods disclosed herein provide single diode failure confirmation, location, and recovery. A component with a single diode failure is transparently available after a single diode failure, thereby extending the life of the component, and plasma tool downtime is reduced by ordering a replacement component while utilizing the component with the single diode failure. When the component experiences an additional diode failure, a replacement component is readily available.

[0009] In one embodiment, a method for identifying and compensating for a fault in a heater array is disclosed. The method comprises a first step of verifying that the fault is limited to a single heater in the heater array (e.g., a shorted diode). If more than one heater in the heater array has failed, the component or part of the plasma tool in which the heater array is incorporated is replaced. The method further comprises a second step of identifying a location of the fault in the heater array. The method comprises a third step of performing a fault recovery process to compensate for the fault at that location.

[0010] In one embodiment, the first, second and third steps are performed in order, for example the second step is performed after the first step.

[0011] In one embodiment, the heater arrays described herein are used for fine temperature control in a plasma chamber, with larger heaters for coarse temperature control, the larger heaters being called zone heaters.

[0012] In one embodiment, a method is disclosed for adjusting power supplied to a heater array having a faulty heater. The method comprises accessing mitigation data identifying a location of the faulty heater. The faulty heater is located on an X bus and a Y bus. The method further comprises adjusting a duty cycle of power applied to the faulty heater to output an adjusted duty cycle, and applying the adjusted duty cycle to the faulty heater. The adjusted duty cycle reduces the power to the faulty heater. The method comprises applying a further adjusted duty cycle to a series of heaters on the X bus and on the Y bus without adjusting the remaining duty cycles applied to the remaining heaters of the heater array. The further adjusted duty cycle reduces the power to the series of heaters.

[0013] In one embodiment, a system is disclosed. The system includes a heater array having a plurality of X buses, a plurality of Y buses, and a plurality of heaters distributed within a plasma chamber. The system further includes a power supply circuit for setting a duty cycle of power to each of the plurality of heaters. The power supply circuit is configured to adjust a duty cycle of a faulty heater of the plurality of heaters and to adjust a duty cycle of power supplied to first and second groups of heaters of the plurality of heaters. The plurality of X buses includes an X bus associated with the faulty heater, and the plurality of Y buses includes a Y bus associated with the faulty heater. The first group of heaters is located on the X bus associated with the faulty heater, and the second group of heaters is located on the Y bus associated with the faulty heater.

[0014] In one embodiment, a plasma system is disclosed. The plasma system includes a radio frequency generator configured to generate a radio frequency signal, and an impedance matching circuit connected to the radio frequency generator to receive the radio frequency signal. The impedance matching circuit modulates the radio frequency signal to output a modulated radio frequency signal. The plasma system further includes a plasma chamber connected to the impedance matching circuit to receive the modulated radio frequency signal. The plasma chamber includes a heater array including a plurality of X buses, a plurality of Y buses, and a plurality of heaters. The plasma system further includes the above-mentioned power supply circuit connected to the plurality of heaters to set a duty cycle of power to each of the plurality of heaters.

[0015] Some advantages of the systems and methods disclosed herein for identifying and compensating for failures in a heater array are that a component having a single heater failure does not need to be immediately discarded. The life of the component can be extended until two or more heaters in the heater array fail. Also, the cost of a new replacement chuck does not need to be immediately incurred. A further advantage of the systems and methods disclosed herein is that the confirmation of the failure of a single heater in a heater array and the identification of the location of the single heater can be performed in situ on the tool. If a single heater failure is confirmed, a recovery mode can compensate for any impact on the processing of the substrate due to the failure and the component can be operated so that the plasma tool continues to operate for wafer processing. The impact on productivity when processing wafers is minimized. An additional advantage of the systems and methods disclosed herein is that a replacement component (such as a replacement chuck) can be pre-ordered before the component having the failure becomes unrecoverable due to two or more heater failures. This minimizes the downtime of the tool when replacing the component with the replacement component.

[0016] Other aspects will become apparent from the following detailed description taken in conjunction with the accompanying drawings. [Brief description of the drawings]

[0017] The embodiments are best understood by reference to the following description taken in conjunction with the accompanying drawings.

[0018] [Figure 1] FIG. 1 shows one embodiment of a system to illustrate real-time control of temperature in a plasma chamber by controlling multiple heaters.

[0019] [Figure 2A-1] FIG. 14 illustrates an embodiment of a heater array with a failed heater diode at location X2Y3 to illustrate the symmetry between currents measured from heaters at multiple locations on or along the X1 bus and a heater at the X6 bus.

[0020] [Figure 2A-2] FIG. 13 illustrates an embodiment of a heater array with a failed heater diode at location X2Y3 to illustrate the symmetry of current flow at heater array locations X1Y3 and X6Y3.

[0021] [Figure 2B-1] FIG. 14 illustrates an embodiment of a heater array with a failed heater diode at location X2Y3 to account for the asymmetry between the current measured from the heaters at all locations on the X2 bus except one location along the X2 bus, and at all locations on the X5 bus except one location along the X5 bus.

[0022] [Figure 2B-2] FIG. 13 illustrates an embodiment of a heater array with a failed heater diode at location X2Y3 to illustrate the symmetry of current flow at locations X2Y3 and X5Y3 in the heater array.

[0023] [Figure 3A-1] FIG. 1 illustrates one embodiment of a heater array to illustrate the symmetry between the currents measured from the heaters at multiple locations on the Y1 bus and multiple locations on the Y6 bus of the heater array.

[0024] [Figure 3A-2] FIG. 13 shows an embodiment to illustrate that the current is symmetric at positions Y1X2 and Y6X2 of the heater array.

[0025] [Figure 3B-1] FIG. 1 illustrates one embodiment of a heater array to illustrate the asymmetry between the currents measured from the heaters at all positions on the Y3 bus except one position along the Y3 bus of the heater array, and at all positions on the Y4 bus except one position along the Y4 bus.

[0026] [Figure 3B-2]FIG. 13 shows an embodiment to illustrate that the current is symmetrical at positions X2Y3 and X2Y4 of the heater array.

[0027] [Figure 4A] FIG. 13 illustrates an embodiment of a graph for identifying a single fault in a heater array.

[0028] [Figure 4B] 13 illustrates an embodiment of a graph for identifying a single fault in a heater array.

[0029] [Figure 4C] FIG. 13 illustrates an embodiment of a graph to illustrate more than a single fault in a heater array.

[0030] [Figure 4D] FIG. 13 illustrates an embodiment of a graph to illustrate more than a single fault in a heater array.

[0031] [Figure 4E] FIG. 13 illustrates an embodiment of a graph to illustrate more than a single fault in a heater array.

[0032] [Figure 4F] FIG. 13 illustrates an embodiment of a graph to illustrate more than a single fault in a heater array.

[0033] [Diagram 5] FIG. 1 illustrates an embodiment of a heater array to illustrate determining a single fault location within the heater array.

[0034] [Figure 6] FIG. 13 illustrates one embodiment of a heater array to illustrate adjusting the duty cycle of operation of multiple heaters in the heater array to compensate for a single fault at a faulty heater location X2Y3 in the heater array.

[0035] [Figure 7]FIG. 1 illustrates an embodiment of a capacitively coupled plasma (CCP) system to illustrate the use of a heater array within the CCP system.

[0036] [Figure 8] FIG. 1 illustrates an embodiment of a plasma-enhanced atomic layer deposition (PEALD) or plasma-enhanced chemical vapor deposition (PECVD) tool to illustrate the use of a heater array within a PEALD or PECVD system.

[0037] [Figure 9] FIG. 1 illustrates an embodiment of an inductively coupled plasma (ICP) system to demonstrate the use of a heater array within the ICP system.

[0038] [Figure 10A] FIG. 1 illustrates one embodiment of a system to illustrate a notification that is displayed on a display device when a single fault in a heater array is identified or when a faulty heater location in a heater array is identified by a processor.

[0039] [Figure 10B] FIG. 13 illustrates an embodiment of a display device to illustrate another notification that is displayed on the display device when a single fault in a heater array is confirmed or when a faulty heater location in a heater array is identified. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0040] The following embodiments describe systems and methods for real-time control of temperature in a plasma chamber. It will be apparent that the embodiments may be practiced without some or all of these specific details. Additionally, detailed descriptions of well-known process operations have been omitted in order to avoid unnecessarily obscuring the embodiments.

[0041] FIG. 1 illustrates an embodiment of a system 100 for illustrating real-time control of temperature in a plasma chamber by controlling multiple heaters. The system 100 includes a voltage source Vs, a heater array 102, a multiplexer 108, a non-volatile memory 110, and a user interface system (UIS) 112. The multiplexer used herein is fabricated as a printed circuit board assembly (PCBA). For example, the terms multiplexer and PCBA are used interchangeably herein. Examples of non-volatile memory used herein include flash memory and ferroelectric random access memory (RAM). Examples of the voltage source Vs include a power supply. For example, the voltage source Vs provides an amount of voltage. The heater array 102 is disposed in a substrate support, a chuck, a showerhead, or an upper electrode assembly. The upper electrode assembly includes an upper electrode and other components, such as a dielectric surrounding the upper electrode and an upper electrode extension surrounding the dielectric. Examples of the user interface 112 include a host computer, a desktop computer, a laptop computer, a smart phone, and a server. The user interface 112, the multiplexer 108, and the non-volatile memory 110 are parts or components of the power supply circuit 104.

[0042] The heater array 102 comprises a plurality of switches SX1, SX2, SX3, SX4, SX5, SX6, SY1, SY2, SY3, SY4, SY5, and SY6. Furthermore, the heater array 102 comprises a plurality of X buses X1, X2, X3, X4, X5, and X6, and a plurality of Y buses Y1, Y2, Y3, Y4, Y5, and Y6. The heater array 102 comprises a plurality of positions, each position comprising a heater. The heaters of the heater array 102 are distributed to form a heater matrix. The position XjYi of the heater array 102 comprises a heater further comprising a diode DXjYi and a resistor RXjYi, where j ranges from 1 to 6 and i ranges from 1 to 6. For example, a location X1Y1 of the heater array 102 includes a heater with a diode DX1Y1 and a resistor RX1Y1, and another location X2Y2 of the heater array 102 includes a diode DX2Y2 and a resistor RX2Y2. The diode of a heater at a location is connected in series with the resistor of that heater. As used herein, an example of a bus is a conductor such as a wire. As used herein, an example of a switch is a relay. As another example, a switch as used herein includes one or more transistors connected together.

[0043] The multiplexer 108 is connected to switch SY1 via line LY1, to switch SY2 via line LY2, to switch SY3 via line LY3, to switch SY4 via line LY4, to switch SY5 via line LY5, to switch SY6 via line LY6, to switch SX1 via line LX1, to switch SX2 via line LX2, to switch SX3 via line LX3, to switch SX4 via line LX4, to switch SX5 via line LX5, and to switch SX6 via line LX6. An example of a line as used herein is a conductor such as a wire.

[0044] The user interface system 112 includes a processor 106, a memory device 114, and a display device 116. A processor, as used herein, is an application specific integrated circuit (ASIC), a field programmable gate array (FPFA), a programmable logic device (PLD), a central processing unit (CPU), a multiprocessor, a digital signal processor, or a microcontroller. Examples of memory devices, as used herein, include random access memory (RAM) and read only memory (ROM). For example, memory devices include flash memory, hard disks, or storage devices. A memory device is an example of a computer readable medium. Examples of the display device 116 include a liquid crystal display device, a light emitting diode display device, and a plasma display device.

[0045] The non-volatile memory 110 includes one or more mappings (e.g., one-to-one, corresponding, associated, or unique) between temperature values ​​to be achieved in the plasma chamber, duty cycles of operation of the heaters of the heater array 102, and nominal values ​​of voltages to be generated by the voltage source Vs. For example, to achieve a temperature value Temp1 in a plasma chamber with the heater array 102, the voltage source Vs is operated to generate a nominal voltage amount Vnominal1, the heater at location X1Y1 is operated with a duty cycle DCX1Y1, the heater at location X1Y2 is operated with a duty cycle DCX1Y2, and so on, with the heater at location X6Y6 being operated with a duty cycle DCX6Y6. The duty cycles of operation of the heaters of the heater array 102 are the time during a duty cycle or clock cycle that power is provided to the heaters from the voltage source Vs.

[0046] Further, it is noted that the non-volatile memory 110 is pre-loaded with a mapping specific to the heater array 102 upon delivery of the heater array 102 to a user. As another example, the heater duty cycles of the heater array 102 are pre-calibrated at the factory where the heater array 102 is manufactured, assuming that the voltage source Vs generates and supplies a voltage of a constant value (such as a nominal value Vnorminal1). At the factory prior to delivery to a user, information regarding the off and on periods of the heater duty cycles of the heater array 102 are calculated and stored in the non-volatile memory 110.

[0047] The processor 106 receives or accesses one or more mappings from the non-volatile memory 110 and identifies from the one or more mappings a duty cycle at which the heater elements of the heater array 102 in the plasma chamber are operated to achieve a temperature value Temp1 in the plasma chamber. The voltage source Vs can generate a nominal voltage value to achieve the temperature value. The temperature value Temp1 is achieved as part of a recipe for processing a substrate in the plasma chamber having the heater array 102. An example of a substrate as used herein includes a semiconductor wafer, which may be a test wafer or a wafer to be processed. For example, the substrate includes multiple stack layers overlaid on a substrate layer such as silicon. The recipe includes other values, such as an operating frequency of a radio frequency (RF) generator, an operating power level of the RF generator, a gap between an upper electrode and a lower electrode in the plasma chamber, a pressure in the plasma chamber, and a chemistry of a process gas supplied to the plasma chamber. The processor 106 accesses recipes stored in the memory device 114 and executes the recipes accordingly by controlling the RF generators and the plasma chamber having the heater array 102 .

[0048] During processing of a substrate in a plasma chamber having the heater array 102, a voltage source Vs generates a nominal voltage value to supply one or more of the heaters of the heater array 102. Additionally, during processing of the substrate, the processor 106 identifies from the recipe that a temperature value Temp1 is to be achieved in the plasma chamber in which the heater array 102 is located. As the substrate is being processed, the processor 106 sends a duty cycle control signal to a multiplexer 108 for addressing one or more X busses and one or more Y busses of the heater array to control the heaters of the heater array 102 to set or achieve a duty cycle for each of the heaters. The duty cycle control signal includes a frequency for opening and closing the switches SX1-SX6 and SY1-SY6 to achieve a duty cycle for the heater elements of the heater array 102.

[0049] Upon receiving the duty cycle control signal, multiplexer 108 manages the opening and closing of switches SX1-SX6 and SY1-SY6 accordingly, thereby achieving a duty cycle of operation of the heaters in heater array 102. For example, upon receiving a duty cycle control signal to close switches SY1 and SX1 and open the remaining switches SY2-SY6 and SX2-SX6, multiplexer 108 sends a signal to switch SY1 via line LY1 to close switch SY1, sends another signal to switch SX1 via line LX1 to close switch SX1, stops sending signals to switches SX2-SX6 via lines LX2-LX6 to open switches SX2-SX6, and stops sending signals to switches SY2-SY6 via lines LY2-LY6 to open switches SY2-SY6. During the period when the switches SY1 and SX1 are closed and the remaining switches SX2-SX6 and SY2-SY6 are open, the current generated by the nominal voltage output from the voltage source Vs is transferred to the ground potential via the switch SY1, the bus Y1, the diode DX1Y1, the resistor RX1Y1, the bus X1, and the switch SX1. The current flowing through the heater at the position X1Y1 also flows through the ammeter 202X1 connected to the terminal of the switch SX1. Thus, the current flowing through the heater at the position X1Y1 is measured and monitored, while the duty cycle of the heater at the position X1Y1 is controlled by the multiplexer 108. The measured current is transmitted from the ammeter 202X1 to the processor 106. One or more of the further ammeters 202X2, 202X3, 202X4, 202X5, and 202X6 are described below.

[0050] Continuing in this example, upon receiving another duty cycle control signal to open switches SY1 and SX1 and to keep the remaining switches SY2-SY6 and SX2-SX6 open, multiplexer 108 stops sending a signal to switch SY1 via LY1 to open switch SY1 and stops sending a signal to switch SX1 via line LX1 to open switch SX1. When switches SY1 and SX1 are open, no current is transferred to ground potential via switch SY1, bus Y1, diode DX1Y1, resistor RX1Y1, bus X1, and switch SX1. The duty cycle of the heater at position X1Y1 is established or set for the period of the cycle of the clock signal during which switches SX1 and SY1 are closed and the remaining switches SX2-SX6 and SY2-SY6 are open. Similarly, the duty cycles and measured currents of the remaining heaters at the remaining positions in heater array 102 are controlled by processor 106 via multiplexer 108.

[0051] Depending on the application and construction or manufacture of the heater array 102, heaters at locations that are flipped around the central line or x-axis CLX or the central y-axis or CLY have similar resistances and therefore approximately the same amount of current. For example, heaters at locations X1Y1 and X6Y1 are flipped around the central x-axis CLX and have approximately the same amount of current, heaters at locations X2Y2 and X5Y2 are flipped around the central x-axis CLX and have approximately the same amount of current, heaters at locations X1Y1 and X1Y6 are flipped around the central y-axis CLY and have approximately the same amount of current, and heaters at locations X2Y2 and X2Y5 are flipped around the central y-axis CLY and have approximately the same amount of current.

[0052] In some embodiments, the heater array 102 includes any number of heaters, any number of switches, and any number of buses. For example, the heater array 102 includes 144 heaters. As another example, the heater array 102 includes 100 heaters.

[0053] In various embodiments, instead of ground potential, a reference potential is used, such as a positive or negative potential amount that is less than the potential of the voltage source Vs.

[0054] In one embodiment, the power supply circuit 104 includes a user interface system 112, a multiplexer 108, a memory 110, switches SX1-SX6, switches SY1-SY6, buses X1-X6, and buses Y1-Y6.

[0055] FIG. 2A-1 illustrates an embodiment of a heater array 102 with a failed heater diode at location X2Y3 to illustrate the symmetry between the current measured from a heater at the X1 bus location (i.e., a location at or along the X1 bus) and a heater at the X6 bus location. Note that bus X2 is associated with the failed heater at location X2Y3. For example, the failed heater at location X2Y3 is located on bus X2. Similarly, bus Y3 is associated with the failed heater at location X2Y3. For example, the failed heater at location X2Y3 is located on bus Y3. An example of a bus location or a location at or along a bus includes the location of a heater having a terminal connected to a bus. For example, positions X1Y1, X1Y2, X1Y3, X1Y4, X1Y5, and X1Y6 are along bus X1, and positions X1Y1, X2Y1, X3Y1, X4Y1, X5Y1, and X6Y1 are along bus Y1. A terminal of a heater at position X1Y1 is connected to the X1 bus, a terminal of a heater at position X1Y2 is connected to the X1 bus, a terminal of a heater at position X1Y3 is connected to the X1 bus, a terminal of a heater at position X1Y4 is connected to the X1 bus, a terminal of a heater at position X1Y5 is connected to the X1 bus, and a terminal of a heater at position X1Y6 is connected to the X1 bus.

[0056] 1 sends a control signal (such as a duty cycle control signal) to multiplexer 108 (FIG. 1) to close switches SY1 and SX1 and open the remaining switches SY2-SY6 and SX2-SX6. Upon receiving the control signal, multiplexer 108 sends a signal to switches SY1 and SX1 to close switches SY1 and SX1, and does not send a signal to switches SY2-SY6 and SX2-SX6 to open switches SY2-SY6 and SX2-SX6.

[0057] When switches SY1 and SX1 are closed, normal current IN1 flows from voltage source Vs through path N1 to ground. As an example, normal current as used herein flows through a non-faulty heater. Path N1 starts at voltage source Vs and extends through switch SY1, bus Y1, heater at location X1Y1, bus X1, and switch SX1 to ground. Furthermore, since there is a fault in the heater at location X2Y3, when switches SY1 and SX1 are closed, extraneous current IUW1 flows from voltage source Vs through path UW1 to ground. Note that the terms extraneous current, bonus current, unwanted (UW) current, and leakage current are used interchangeably herein. Furthermore, a fault at one location of the heater is the result of a shorted diode at that location.

[0058] The path UW1 starts from the voltage source Vs and extends to ground potential through switch SY1, bus Y1, heater at position X2Y1, bus X2, heater at position X2Y3, Y3 bus, heater at position X1Y3, bus X1, and switch SX1. The ammeter 202X1 measures the sum I(N1+UW1) of the normal current IN1 and the external current IUW1 at the terminal of the switch SX1. The ammeter 202X1 is connected to the terminal of the switch SX1, and the terminal is connected to ground potential. Examples of ammeters used in this specification include current sensors or current measuring devices that measure the amount of current flowing through a bus.

[0059] Similarly, when the switches SY1 and SX6 are closed, the normal current IN2 flows from the voltage source Vs to the ground potential through the path N2. The path N2 starts from the voltage source Vs and extends to the ground potential through the switch SY1, the bus Y1, the heater at the position X6Y1, the bus X6, and the switch SX6. Furthermore, since the heater at the position X2Y3 has a fault, when the switches SY1 and SX6 are closed, the external current IUW2 flows from the voltage source Vs to the ground potential through the path UW2. The path UW2 starts from the voltage source Vs and extends to the ground potential through the switch SY1, the bus Y1, the heater at the position X2Y1, the bus X2, the heater at the position X2Y3, the Y3 bus, the heater at the position X6Y3, the bus X6, and the switch SX6. The ammeter 202X6 measures the sum (N2+UW2) of the normal current IN2 and the external current IUW2 at the terminal of the switch SX6. Ammeter 202X6 is connected to a terminal of switch SX6, which is connected to ground potential. As shown in FIG. 2A-1, any heaters not on the same bus with the faulty heater at location X2Y3 (such as heaters at locations X1Y1 and X6Y1) will have an extraneous current received from voltage source Vs through the faulty heater. The bus with the faulty heater at location X2Y3 is bus X2 or bus Y3.

[0060] Each ammeter described herein is connected to a processor 106. The processor 106 receives the measurements of the current sums I(N1+UW1) and I(N2+UW2) and determines whether the current sum I(N1+UW1) is symmetrical with respect to the current sum I(N2+UW2). For example, the processor 106 determines whether the current sum I(N1+UW1) is within a predetermined range from the current sum I(N2+UW2). Examples of measurements of currents within the predetermined range include measurements that have a difference of less than 0.2 amperes or less than 0.3 amperes. Upon determining that the measurement of the current sum I(N1+UW1) is within a predetermined range from the measurement of the current sum I(N2+UW2), the processor 106 determines that the measurements are symmetrical with respect to each other, i.e., the heaters at the locations X1Y1 and X6Y1 are symmetrical with respect to each other. On the other hand, in response to determining that the measured current sum I(N1+UW1) is not within, or outside, the predetermined range from the measured current sum I(N2+UW2), processor 106 determines that the measurements are asymmetric, i.e., the heaters at locations X1Y1 and X6Y1 are asymmetric with respect to one another. An example of a current measurement that is outside, or not within, the predetermined range is a measurement that has a difference that is greater than a predetermined limit, such as a difference of greater than 1 amp or greater than 0.5 amp.

[0061] Similarly, the processor 106 controls the multiplexer 108 to further control the switches SY2 and SX1 to be closed while opening the remaining switches SX2-SX6, SY1, and SY3-SY6. The processor 106 receives a current measurement from the ammeter 202X1 when the switches SY2 and SX1 are closed and the remaining switches SX2-SX6, SY1, and SY3-SY6 are open. The processor 106 also controls the multiplexer 108 to further control the switches SY2 and SX6 to be closed while opening the remaining switches SX1-SX5, SY1, and SY3-SY6. The processor 106 receives a current measurement from the ammeter 202X6 when the switches SY2 and SX6 are closed and the remaining switches SX1-SX5, SY1, and SY3-SY6 are open. To compare the measurements received from ammeters 202X1 and 202X6, processor 106 determines that the measurements, ie, heaters at locations X1Y2 and X6Y2, are symmetrical with respect to each other in the same manner as described above.

[0062] The processor 106 further controls the switches SY4 and SX1 to close and the remaining switches SY1-SY3, SY5, SY6, and SX2-SX6 to open to obtain a current measurement from the ammeter 202X1. The processor 106 further controls the switches SY4 and SX6 to close and the remaining switches SY1-SY3, SY5, SY6, and SX1-SX5 to open to obtain a current measurement from the ammeter 202X6. The processor 106 compares the measurements received from the ammeters 202X1 and 202X6 to determine that the measurements, i.e., the heaters at the positions X1Y4 and X6Y4, are symmetrical with respect to each other in the same manner as described above.

[0063] Further, the processor 106 controls the switches SY5 and SX1 to close and the remaining switches SY1-SY4, SY6, and SX2-SX6 to open to obtain a current measurement from the ammeter 202X1. The processor 106 controls the switches SY5 and SX6 to close and the remaining switches SY1-SY4, SY6, and SX1-SX5 to open to obtain a current measurement from the ammeter 202X6. The processor 106 compares the measurements received from the ammeters 202X1 and 202X6 to determine that the measurements, i.e., the heaters at the positions X1Y5 and X6Y5, are symmetrical with respect to each other in the same manner as described above.

[0064] Further, the processor 106 controls the switches SY6 and SX1 to close and the remaining switches SY1-SY5 and SX2-SX6 to open to obtain a current measurement from the ammeter 202X1. The processor 106 controls the switches SY6 and SX6 to close and the remaining switches SY1-SY5 and SX1-SX5 to open to obtain a current measurement from the ammeter 202X6. The processor 106 compares the measurements received from the ammeters 202X1 and 202X6 to determine that the measurements, i.e., the heaters at the positions X1Y6 and X6Y6, are symmetrical with respect to each other in the same manner as described above. When the switches of the heater array 102 are controlled so that current passes through positions X1Y1 and X6Y1, positions X1Y2 and X6Y2, positions X1Y4 and X6Y4, positions X1Y5 and X6Y5, and positions X1Y6 and X6Y6, the processor 106 determines that the current is symmetric between positions X1Y1 and X6Y1, positions X1Y2 and X6Y2, positions X1Y4 and X6Y4, positions X1Y5 and X6Y5, and positions X1Y6 and X6Y6. As shown in FIG. 2A-1, any heaters of the heater array 102 that are not on the same Y3 bus as the failed heater at position X2Y3 (such as the heaters at positions X1Y1 and X6Y1) will have an extraneous current measurement from the extraneous current flowing from the voltage source Vs through the heater at position X2Y3, but will remain symmetric.

[0065] Note that buses X1 and X6 are symmetric (e.g., symmetrically positioned) about a central x-axis CLX. For example, bus X1 is separated from the central x-axis CLX by two buses X2 and X3, and bus X6 is separated from the central x-axis CLX by the same number of buses (X4 and X5). Each of the X buses X1-X6 is shown parallel to the central x-axis.

[0066] FIG. 2A-2 is a diagram illustrating an embodiment to explain that the current is symmetrical at the X1 bus position and the X6 bus position. The processor 106 in FIG. 1 sends a control signal to the multiplexer 108 (FIG. 1) to close the switches SY3 and SX1 and open the remaining switches SY1, SY2, SY4-SY6, and SX2-SX6. Upon receiving the control signal, the multiplexer 108 sends a signal to the switches SY3 and SX1 to close the switches SY3 and SX1, and does not send a signal to the switches SY1, SY2, SY4-SY6, and SX2-SX6 to open the switches SY1, SY2, SY4-SY6, and SX2-SX6.

[0067] When switches SY3 and SX1 are closed, normal current IN1' flows from voltage source Vs through path N1' to ground potential. Path N1' starts at voltage source Vs and extends through switch SY3, bus Y3, heater at location X1Y3, bus X1, and switch SX1 to ground potential. Ammeter 202X1 measures normal current IN1' at the terminal of switch SX1. When switches SY3 and SX1 are closed and switches SY1, SY2, SY4-SY6, and SX2-SX6 are open, no external current flows through bus X1 due to the failure of the heater at location X2Y3.

[0068] Similarly, the processor 106 sends a control signal to the multiplexer 108 to close the switches SY3 and SX6 and open the remaining switches SY1, SY2, SY4-SY6, and SX1-SX5. Upon receiving the control signal, the multiplexer 108 sends a signal to the switches SY3 and SX6 to close the switches SY3 and SX6, and does not send a signal to the switches SY1, SY2, SY4-SY6, and SX1-SX5 to open the switches SY1, SY2, SY4-SY6, and SX1-SX5.

[0069] When switches SY3 and SX6 are closed, normal current IN2' flows from voltage source Vs through path N2' to ground potential. Path N2' starts at voltage source Vs and extends to ground potential through switch SY3, bus Y3, heater at location X6Y3, bus X6, and switch SX6. Ammeter 202X6 measures normal current IN2' at the terminal of switch SX6. When switches SY3 and SX6 are closed and switches SY1, SY2, SY4-SY6, and SX1-SX5 are open, no external current flows through bus X6 due to the failure of the heater at location X2Y3.

[0070] The processor 106 receives and compares the measurements of currents IN1' and IN2' and determines that the measurements are symmetrical with respect to each other, i.e., the heaters at locations X1Y3 and X6Y3 are symmetrical with respect to each other. For example, the processor 106 determines that the measurement of current IN1' is within a predetermined range from the measurement of current IN2'. As shown in FIG. 2A-2, any heaters on the same Y3 bus as the faulty heater at location X2Y3 (such as the heater at location X1Y3 and the heater at location X6Y3) remain symmetrical even though they do not have an extraneous current flowing from the voltage source Vs through the heater at location X2Y3. Referring to FIG. 2A-1 and FIG. 2A-2, the processor 106 determines that the currents are symmetrical between all locations of the heaters along the X1 and X6 buses.

[0071] Further, just as all positions of the X1 and X6 buses, i.e., all positions along the buses, are determined to be symmetrical by processor 106, all positions of the X3 and X4 buses, i.e., all positions along the buses, are determined to be symmetrical by processor 106. For example, processor 106 determines that the currents between positions X3Y1 and X4Y1 are symmetrical, the currents between positions X3Y2 and X4Y2 are symmetrical, the currents between positions X3Y3 and X4Y3 are symmetrical, the currents between positions X3Y4 ​​and X4Y4 are symmetrical, the currents between positions X3Y5 and X4Y5 are symmetrical, and the currents between positions X3Y6 and X4Y6 are symmetrical.

[0072] FIG. 2B-1 illustrates one embodiment of heater array 102 to illustrate the asymmetry between the currents measured from heaters at all positions along the X2 bus except one position along the X2 bus and at all positions along the X5 bus except one position along the X5 bus. Processor 106 of FIG. 1 sends a control signal to multiplexer 108 (FIG. 1) to close switches SY1 and SX2 and open the remaining switches SY2-SY6, SX1, and SX3-SX6. Upon receiving the control signal, multiplexer 108 sends a signal to switches SY1 and SX2 to close switches SY1 and SX2 and does not send a signal to switches SY2-SY6, SX1, and SX3-SX6 to open switches SY2-SY6, SX1, and SX3-SX6.

[0073] When switches SY1 and SX2 are closed and the remaining switches SY2-SY6, SX1, and SX3-SX6 are open, a normal current IN3 flows from the voltage source Vs through a path N3 to ground potential. The path N3 starts at the voltage source Vs and extends to ground potential through switch SY1, bus Y1, the heater at location X2Y1, bus X2, and switch SX2. An ammeter 202X2 measures the current IN3 at the terminal of switch SX2. The ammeter 202X2 is connected to the terminal of switch SX2 that is connected to ground potential.

[0074] Similarly, when the switches SY1 and SX5 are closed and the remaining switches SY2-SY6, SX1-SX4, and SX6 are open, a normal current IN4 flows from the voltage source Vs to the ground potential through a path N4. The path N4 starts from the voltage source Vs and extends to the ground potential through the switch SY1, the bus Y1, the heater at the position X5Y1, the bus X5, and the switch SX5. Furthermore, since there is a failure in the heater at the position X2Y3, when the switches SY1 and SX5 are closed, an external current IUW4 flows from the voltage source Vs to the ground potential through a path UW4. The path UW4 starts from the voltage source Vs and extends to the ground potential through the switch SY1, the bus Y1, the heater at the position X2Y1, the bus X2, the heater at the position X2Y3, the Y3 bus, the heater at the position X5Y3, the bus X5, and the switch SX5. The ammeter 202X5 measures the sum I(N4+UW4) of the normal current IN4 and the external current IUW4 at the terminal of the switch SX5. The ammeter 202X5 is connected to the terminal of the switch SX5, and the terminal is connected to the ground potential.

[0075] Note that due to the manufacture or design of the heater array 102, currents IN3 and IN4 are approximately identical. The processor 106 receives the measurements of currents IN3 and I(N4+UW4) and determines that the measurements are asymmetric, i.e., the heaters at locations X2Y1 and X5Y1 are asymmetric with respect to each other. For example, the processor 106 determines that the measurement of current IN3 is outside a predetermined range from the measurement of current I(N4+UW4).

[0076] Similarly, the processor 106 controls the multiplexer 108 to further control the switches SY2 and SX2 to be closed while opening the remaining switches SX1, SX3-SX6, SY1, and SY3-SY6. The processor 106 receives current measurements from the ammeter 202X2 when the switches SY2 and SX2 are closed and the remaining switches SX1, SX3-SX6, SY1, and SY3-SY6 are open. The processor 106 also controls the multiplexer 108 to further control the switches SY2 and SX5 to be closed while opening the remaining switches SX1-SX4, SX6, SY1, and SY3-SY6. The processor 106 receives current measurements from the ammeter 202X5 when the switches SY2 and SX5 are closed and the remaining switches SX1-SX4, SX6, SY1, and SY3-SY6 are open. Processor 106 compares the measurements received from ammeters 202X2 and 202X5 and determines that the measurements of the currents, ie, heaters at locations X2Y2 and X5Y2, are asymmetric with respect to one another in the same manner as described above.

[0077] The processor 106 then controls the switches SY4 and SX2 to close, and the remaining switches SY1 to SY3, SY5, SY6, SX1, and SX3 to SX6 to open, to obtain a current measurement value from the ammeter 202X2. The processor 106 then controls the switches SY4 and SX5 to close, and the remaining switches SY1 to SY3, SY5, SY6, SX1 to SX4, and SX6 to open, to obtain a current measurement value from the ammeter 202X5 ... 5 and determines that the measurements of the currents, i.e., heaters at locations X2Y4 and X5Y4, are asymmetric with respect to one another in the same manner as described above.

[0078] Further, the processor 106 controls the switches SY5 and SX2 to close and the remaining switches SY1-SY4, SY6, SX1, and SX3-SX6 to open to obtain a current measurement from the ammeter 202X2. The processor 106 controls the switches SY5 and SX5 to close and the remaining switches SY1-SY4, SY6, SX1-SX4, and SX6 to open to obtain a current measurement from the ammeter 202X5. The processor 106 compares the measurements received from the ammeters 202X2 and 202X5 to determine that the current measurements, i.e., the heaters at the locations X2Y5 and X5Y5, are asymmetric with respect to each other in the same manner as described above.

[0079] Further, the processor 106 controls the switches SY6 and SX2 to close and the remaining switches SY1-SY5, SX1, and SX3-SX6 to open to obtain a current measurement from the ammeter 202X2. The processor 106 controls the switches SY6 and SX5 to close and the remaining switches SY1-SY5, SX1-SX4, and SX6 to open to obtain a current measurement from the ammeter 202X5. The processor 106 compares the measurements received from the ammeters 202X2 and 202X5 to determine that the measurements, i.e., the heaters at the positions X2Y6 and X5Y6, are asymmetric with respect to each other in the same manner as described above. Thus, when the switches of the heater array 102 are controlled so that the current passes successively through positions X2Y1 and X5Y1, positions X2Y2 and X5Y2, positions X2Y4 and X5Y4, positions X2Y5 and X5Y5, and positions X2Y6 and X5Y6, the processor 106 determines that the current is asymmetric between positions X2Y1 and X5Y1, between positions X2Y2 and X5Y2, between positions X2Y4 and X5Y4, between positions X2Y5 and X5Y5, and between positions X2Y6 and X5Y6.

[0080] It should be noted that buses X2 and X5 are symmetrical (symmetrically positioned, symmetrically manufactured, etc.) with respect to the central x-axis CLX. For example, bus X2 is separated from the central x-axis CLX by one bus X3, and bus X5 is separated from the central x-axis CLX by one bus X4.

[0081] FIG. 2B-2 is a diagram illustrating an embodiment to explain that the currents are symmetrical at positions X2Y3 and X5Y3. The processor 106 in FIG. 1 sends a control signal to the multiplexer 108 (FIG. 1) to close the switches SY3 and SX2 and open the remaining switches SY1, SY2, SY4-SY6, SX1, and SX3-SX6. Upon receiving the control signal, the multiplexer 108 sends a signal to the switches SY3 and SX2 to close the switches SY3 and SX2 and opens the remaining switches SY1, SY2, SY4-SY6, SX1, and SX3-SX6. 3 To open SX6, switches SY1, SY2, SY4~SY6, SX1, and SX 3 ~No signal is sent to SX6.

[0082] When switches SY3 and SX2 are closed, normal current IN3' flows from voltage source Vs through path N3' to ground. Path N3' starts at voltage source Vs, passes through switch SY3, bus Y3, the heater at location X2Y3, bus X2, and switch SX2, and then to ground. Ammeter 202X2 measures normal current IN3' at the terminal of switch SX2.

[0083] Similarly, the processor 106 sends a control signal to the multiplexer 108 to close the switches SY3 and SX5 and open the remaining switches SY1, SY2, SY4-SY6, SX1-SX4, and SX6. Upon receiving the control signal, the multiplexer 108 sends a signal to the switches SY3 and SX5 to close the switches SY3 and SX5, and does not send a signal to the switches SY1, SY2, SY4-SY6, SX1-SX4, and SX6 to open the switches SY1, SY2, SY4-SY6, SX1-SX4, and SX6.

[0084] When switches SY3 and SX5 are closed, normal current IN4' flows from voltage source Vs through path N4' to ground. Path N4' starts at voltage source Vs, passes through switch SY3, bus Y3, the heater at location X5Y3, bus X5, and switch SX5, and then to ground. Ammeter 202X5 measures normal current IN4' at the terminal of switch SX5.

[0085] Processor 106 receives the measurements of currents IN3' and IN4' and determines that the measurement of current IN3' is symmetrical with respect to the measurement of current IN4', i.e., the heaters at locations X2Y3 and X5Y3 are asymmetrical with respect to each other. For example, processor 106 determines that the measurement of current IN3' is within a predetermined range from the measurement of current IN4'.

[0086] As shown in FIG. 2B-2, the processor 106 determines that the current is symmetric between the positions X2Y3 and X5Y3. Also, as shown in FIG. 2B-1, the processor 106 determines that the current is asymmetric between at least one of each of the heater positions along the X2 and X5 buses to identify the X2 and X5 buses from all buses X1-X6 of the heater array 102. The positions where the current is asymmetric along the X2 and X5 buses include positions X2Y1 and X5Y1, X2Y2 and X5Y2, X2Y4 and X5Y4, X2Y5 and X5Y5, and X2Y6 and X5Y6. The currents received from positions X2Y3 and X5Y3 are symmetric.

[0087] FIG. 3A-1 illustrates one embodiment of the heater array 102 to illustrate the symmetry between the currents measured from the heater at the Y1 bus position and the heater at the Y6 bus position. The processor 106 in FIG. 1 sends a control signal to the multiplexer 108 (FIG. 1) to close the switches SY1 and SX6 and open the remaining switches SY2-SY6 and SX1-SX5. Upon receiving the control signal, the multiplexer 108 sends a signal to the switches SY1 and SX6 to close the switches SY1 and SX6 and does not send a signal to the switches SY2-SY6 and SX1-SX5 to open the switches SY2-SY6 and SX1-SX5.

[0088] When switches SY1 and SX6 are closed, normal current IN5 flows from voltage source Vs to ground potential through path N5. Path N5 starts from voltage source Vs and extends to ground potential through switch SY1, bus Y1, heater at position X6Y1, bus X6, and switch SX6. Furthermore, since there is a fault in the heater at position X2Y3, when switches SY1 and SX6 are closed, external current IUW5 flows from voltage source Vs to ground potential through path UW5. Path UW5 starts from voltage source Vs and extends to ground potential through switch SY1, bus Y1, heater at position X1Y1, bus X2, heater at position X2Y3, bus Y3, heater at position X6Y3, bus X6, and switch SX6. Ammeter 202X6 is connected to switch SX 6 The sum (N5+UW5) of the normal current IN5 and the external current IUW5 is measured at the terminal of the switch SX6. The ammeter 202X6 is connected to a terminal of the switch SX6, which is connected to the ground potential.

[0089] Similarly, when the switches SY6 and SX6 are closed, the normal current IN6 flows from the voltage source Vs to the ground potential through the path N6. The path N6 starts from the voltage source Vs and extends to the ground potential through the switch SY6, the bus Y6, the heater at the position X6Y6, the bus X6, and the switch SX6. Furthermore, since the heater at the position X2Y3 has a fault, when the switches SY6 and SX6 are closed, the external current IUW6 flows from the voltage source Vs to the ground potential through the path UW6. The path UW6 starts from the voltage source Vs and extends to the ground potential through the switch SY6, the bus Y6, the heater at the position X1Y6, the bus X2, the heater at the position X2Y3, the Y3 bus, the heater at the position X6Y3, the bus X6, and the switch SX6. The ammeter 202X6 measures the sum (N6+UW6) of the normal current IN6 and the external current IUW6 at the terminal of the switch SX6.

[0090] Note that currents I(N5) and I(N6) are approximately the same due to the fabrication of heater array 102, as are currents I(UW5) and I(UW6). Processor 106 receives the measurements of current sums I(N5+UW5) and I(N6+UW6) and determines that the measurement of current sum (N6+UW6) is symmetrical with respect to the measurement of current sum I(N5+UW5), and further determines that the heaters at locations X6Y1 and X6Y6 are symmetrical with respect to each other. For example, processor 106 determines that the measurement of current sum I(N5+UW5) is within a predetermined range from the measurement of current sum I(N6+UW6).

[0091] Similarly, the processor 106 controls the multiplexer 108 to further control the switches SY1 and SX5 to be closed while opening the remaining switches SX1-SX4, SX6, and SY2-SY6. The processor 106 receives current measurements from the ammeter 202X5 when the switches SY1 and SX5 are closed and the remaining switches SX1-SX4, SX6, and SY2-SY6 are open. The processor 106 also controls the multiplexer 108 to further control the switches SY6 and SX5 to be closed while opening the remaining switches SX1-SX4, SX6, and SY1-SY5. The processor 106 receives current measurements from the ammeter 202X5 when the switches SY6 and SX5 are closed and the remaining switches SX1-SX4, SX6, and SY1-SY5 are open. The processor 106 compares the measurements received from the ammeter 202X5 and determines that the measurements, ie, the heaters at locations X5Y1 and X5Y6, are symmetrical with respect to each other in the same manner as described above.

[0092] The processor 106 further controls the switches SY1 and SX4 to close and the remaining switches SY2-SY6, SX1-SX3, SX5, and SX6 to open to obtain a current measurement from the ammeter 202X4. The processor 106 further controls the switches SY6 and SX4 to close and the remaining switches SY1-SY5, SX1-SX3, SX5, and SX6 to open to obtain a current measurement from the ammeter 202X4. The processor 106 compares the measurements received from the ammeter 202X4 to determine that the measurements, i.e., the heaters at the positions X4Y1 and X4Y6, are symmetrical with respect to each other in the same manner as described above.

[0093] Further, the processor 106 controls the switches SY1 and SX3 to close and the remaining switches SY2-SY6, SX1, SX2, and SX4-SX6 to open to obtain a current measurement from the ammeter 202X3. The processor 106 controls the switches SY6 and SX3 to close and the remaining switches SY1-SY5, SX1, SX2, and SX4-SX6 to open to obtain a current measurement from the ammeter 202X3. The processor 106 compares the measurements received from the ammeter 202X3 to determine that the measurements, i.e., the heaters at the positions X3Y1 and X3Y6, are symmetrical with respect to each other in the same manner as described above.

[0094] Further, the processor 106 controls the switches SY1 and SX1 to close and the remaining switches SY2-SY6 and SX2-SX6 to open to obtain a current measurement from the ammeter 202X1. The processor 106 controls the switches SY6 and SX1 to close and the remaining switches SY1-SY5 and SX2-SX6 to open to obtain a current measurement from the ammeter 202X1. The processor 106 compares the measurements received from the ammeter 202X1 to determine that the measurements, i.e., the heaters at the positions X1Y1 and X1Y6, are symmetrical with respect to each other in the same manner as described above. When the switches of the heater array 102 are controlled so that current passes through positions X1Y1 and X1Y6, positions X3Y1 and X3Y6, positions X4Y1 and X4Y6, positions X5Y1 and X5Y6, and positions X6Y1 and X6Y6, the processor 106 determines that the current is symmetric between positions X1Y1 and X1Y6, between positions X3Y1 and X3Y6, between positions X4Y1 and X4Y6, between positions X5Y1 and X5Y6, and between positions X6Y1 and X6Y6.

[0095] Note that buses Y1 and Y6 are symmetric (symmetrically positioned, symmetrically manufactured, etc.) about the central y-axis CLY. For example, bus Y1 is separated from the central y-axis CLY by two buses Y2 and Y3, and bus Y6 is separated from the central y-axis CLY by an equal number of two buses (Y4 and Y5). The Y buses Y1-Y6 are shown parallel to the central y-axis.

[0096] FIG. 3A-2 is a diagram illustrating an embodiment to explain that the currents are symmetrical at positions X2Y1 and X2Y6. The processor 106 in FIG. 1 sends a control signal to the multiplexer 108 (FIG. 1) to close the switches SY1 and SX2 and open the remaining switches SY2-SY6, SX1, and SX3-SX6. Upon receiving the control signal, the multiplexer 108 sends a signal to the switches SY1 and SX2 to close the switches SY1 and SX2, and does not send a signal to the switches SY2-SY6, SX1, and SX3-SX6 to open the switches SY2-SY6, SX1, and SX3-SX6.

[0097] When switches SY1 and SX2 are closed, normal current IN5' flows from voltage source Vs through path N5' to ground potential. Path N5' starts at voltage source Vs and extends to ground potential through switch SY1, bus Y1, heater at location X2Y1, bus X2, and switch SX2. Ammeter 202X2 measures normal current IN5' at the terminal of switch SX2. When switches SY1 and SX2 are closed and switches SY2-SY6, SX1, and SX3-SX6 are open, no external current flows through bus X2 due to the failure of the heater at location X2Y3.

[0098] Similarly, the processor 106 sends a control signal to the multiplexer 108 to close the switches SY6 and SX2 and open the remaining switches SY1-SY5, SX1, and SX3-SX6. Upon receiving the control signal, the multiplexer 108 sends a signal to the switches SY6 and SX2 to close the switches SY6 and SX2, and does not send a signal to the switches SY1-SY5, SX1, and SX3-SX6 to open the switches SY1-SY5, SX1, and SX3-SX6.

[0099] When switches SY6 and SX2 are closed, normal current IN6' flows from voltage source Vs through path N6' to ground potential. Path N6' starts at voltage source Vs and extends through switch SY6, bus Y6, heater at location X2Y6, bus X2, and switch SX2 to ground potential. Ammeter 202X2 measures normal current IN6' at the terminal of switch SX2. When switches SY6 and SX2 are closed and switches SY1-SY5, SX1, and SX3-SX6 are open, no external current flows through bus X2 due to the failure of the heater at location X2Y3.

[0100] It is noted that IN5' and IN6' are approximately equal or approximately the same due to the fabrication of the heater array 102. The processor 106 receives the measurements of currents IN5' and IN6' and determines that the currents are symmetrical between positions X2Y1 and X2Y6. For example, the processor 106 determines that the measurement of current IN5' is within a predetermined range from the measurement of current IN6'. With reference to Figures 3A-1 and 3A-2, the processor 106 determines that the currents are symmetrical between all positions of the heater along the Y1 and Y6 axes.

[0101] Further, all positions along the Y2 and Y5 buses are determined to be symmetrical by processor 106 in the same manner that all positions along the Y1 and Y6 buses are determined to be symmetrical by processor 106. For example, processor 106 determines that the current between positions X1Y2 and X1Y5 is symmetrical, the current between positions X2Y2 and X2Y5 is symmetrical, the current between positions X3Y2 and X3Y5 is symmetrical, the current between positions X4Y2 and X4Y5 is symmetrical, the current between positions X5Y2 and X5Y5 is symmetrical, and the current between positions X6Y2 and X6Y5 is symmetrical.

[0102] FIG. 3B-1 illustrates one embodiment of the heater array 102 to illustrate the asymmetry between the currents measured from the heaters at all positions of the Y3 bus except one position along the Y3 bus and at all positions of the Y4 bus except one position along the Y4 bus. The processor 106 of FIG. 1 sends a control signal to the multiplexer 108 (FIG. 1) to close the switches SY3 and SX6 and open the remaining switches SY1, SY2, SY4-SY6, and SX1-SX5. Upon receiving the control signal, the multiplexer 108 sends a signal to the switches SY3 and SX6 to close the switches SY3 and SX6 and does not send a signal to the remaining switches SY1, SY2, SY4-SY6, and SX1-SX5 to open the remaining switches SY1, SY2, SY4-SY6, and SX1-SX5.

[0103] When switches SY3 and SX6 are closed and the remaining switches SY1, SY2, SY4-SY6, and SX1-SX5 are open, a normal current IN7 flows from voltage source Vs through path N7 to ground. Path N7 starts at voltage source Vs and extends through switch SY3, bus Y3, the heater at location X6Y3, bus X6, and switch SX6 to ground. Ammeter 202X6 measures the normal current IN7 at the terminals of switch SX6. Note that no unwanted current flows through switch SX6 as measured by ammeter 202X6.

[0104] Similarly, when the switches SY4 and SX6 are closed and the remaining switches SY1-SY3, SY5, SY6, and SX1-SX5 are open, a normal current IN8 flows from the voltage source Vs to the ground potential through the path N8. The path N8 starts from the voltage source Vs and extends to the ground potential through the switch SY4, the bus Y4, the heater at the position X6Y4, the bus X6, and the switch SX6. Furthermore, since the heater at the position X2Y3 has a fault, when the switches SY4 and SX6 are closed, an external current IUW8 flows from the voltage source Vs to the ground potential through the path UW8. The path UW8 starts from the voltage source Vs and extends to the ground potential through the switch SY4, the bus Y4, the heater at the position X2Y4, the bus X2, the heater at the position X2Y3, the Y3 bus, the heater at the position X6Y3, the bus X6, and the switch SX6. The ammeter 202X6 measures the sum (N8+UW8) of the normal current IN8 and the external current IUW8 at the terminals of the switch SX6.

[0105] Note that currents IN7 and IN8 are approximately equal due to the fabrication of heater array 102. Processor 106 receives the measurements of currents IN7 and I(N8+UW8) and determines that the measurements are asymmetric, i.e., the heaters at locations X6Y3 and X6Y4 are asymmetric with respect to each other. For example, processor 106 determines that the measurement of current IN7 is not within, i.e., outside, a predetermined range from the measurement of current I(N8+UW8).

[0106] Similarly, the processor 106 controls the multiplexer 108 to further control the switches SY3 and SX5 to be closed while opening the remaining switches SX1-SX4, SX6, SY1, SY2, and SY4-SY6. The processor 106 receives current measurements from the ammeter 202X5 when the switches SY3 and SX5 are closed and the remaining switches SX1-SX4, SX6, SY1, SY2, and SY4-SY6 are open. The processor 106 also controls the multiplexer 108 to further control the switches SY4 and SX5 to be closed while opening the remaining switches SY1-SY3, SY5, SY6, SX1-SX4, and SX6. The processor 106 receives current measurements from the ammeter 202X5 when the switches SY4 and SX5 are closed and the remaining switches SY1-SY3, SY5, SY6, SX1-SX4, and SX6 are open. The processor 106 compares the measurements received from the ammeter 202X5 and determines that the measurements of the currents, ie, the heaters at locations X5Y3 and X5Y4, are asymmetric with respect to one another in the same manner as described above.

[0107] The processor 106 further controls the switches SY3 and SX4 to close and the remaining switches SY1, SY2, SY4-SY6, SX1-SX3, SX5, and SX6 to open to obtain a current measurement from the ammeter 202X4. The processor 106 further controls the switches SY4 and SX4 to close and the remaining switches SY1-SY3, SY5, SY6, SX1-SX3, SX5, and SX6 to open to obtain a current measurement from the ammeter 202X4. The processor 106 compares the measurements received from the ammeter 202X4 to determine that the current measurements, i.e., the heaters at the positions X4Y3 and X4Y4, are asymmetric with respect to each other in the same manner as described above.

[0108] Further, the processor 106 controls the switches SY3 and SX3 to close and the remaining switches SY1, SY2, SY4-SY6, SX1, SX2, and SX4-SX6 to open to obtain current measurements from the ammeter 202X3. The processor 106 controls the switches SY4 and SX3 to close and the remaining switches SY1-SY3, SY5, SY6, SX1, SX2, and SX4-SX6 to open to obtain current measurements from the ammeter 202X3. The processor 106 compares the measurements received from the ammeter 202X3 to determine that the measurements of current from the heaters at the positions X3Y3 and X3Y4 ​​are asymmetric with respect to each other in the same manner as described above.

[0109] Further, the processor 106 controls the switches SY3 and SX1 to close and the remaining switches SY1, SY2, SY4-SY6, and SX2-SX6 to open to obtain a current measurement from the ammeter 202X1. The processor 106 controls the switches SY4 and SX1 to close and the remaining switches SY1-SY3, SY5, SY6, and SX2-SX6 to open to obtain a current measurement from the ammeter 202X1. The processor 106 compares the measurements received from the ammeter 202X1 and determines that the measurements, i.e., the heaters at the positions X1Y3 and X1Y4, are asymmetric with respect to each other in the same manner as described above. When the switches of the heater array 102 are controlled so that current passes through positions X6Y3 and X6Y4, positions X5Y3 and X5Y4, positions X4Y3 and X4Y4, positions X3Y3 and X3Y4, and positions X1Y3 and X1Y4, the processor 106 determines that the current is asymmetric between positions X6Y3 and X6Y4, between positions X5Y3 and X5Y4, between positions X4Y3 and X4Y4, between positions X3Y3 and X3Y4, and between positions X1Y3 and X1Y4.

[0110] Note that buses Y3 and Y4 are symmetrical (i.e., symmetrically positioned) about the central y-axis CLY. For example, bus Y3 is the first bus from the central y-axis CLY, and bus Y4 is the first bus from the central y-axis CLY. There are no buses separating bus Y3 from the central y-axis CLY, and there are no buses separating bus Y4 from the central y-axis CLY.

[0111] FIG. 3B-2 is a diagram illustrating an embodiment to explain that the currents are symmetrical at positions X2Y3 and X2Y4. The processor 106 of FIG. 1 sends a control signal to the multiplexer 108 (FIG. 1) to close the switches SY3 and SX2 and open the remaining switches SY1, SY2, SY4-SY6, SX1, and SX3-SX6. When the switches SY3 and SX2 are closed and the remaining switches SY1, SY2, SY4-SY6, SX1, and SX 3 When SX6 is open, normal current IN7' flows from voltage source Vs through path N7' to ground. Path N7' starts at voltage source Vs, passes through switch SY3, bus Y3, the heater at location X2Y3, bus X2, and switch SX2, and then to ground. Ammeter 202X2 measures normal current IN7' at the terminal of switch SX2.

[0112] Similarly, the processor 106 sends a control signal to the multiplexer 108 to close the switches SY4 and SX2 and open the remaining switches SY1-SY3, SY5, SY6, SX1, and SX3-SX6. Upon receiving the control signal, the multiplexer 108 sends a signal to the switches SY4 and SX2 to close the switches SY4 and SX2, and does not send a signal to the remaining switches SY1-SY3, SY5, SY6, SX1, and SX3-SX6 to open the remaining switches SY1-SY3, SY5, SY6, SX1, and SX3-SX6.

[0113] When switches SY4 and SX2 are closed, normal current IN8' flows from voltage source Vs through path N8' to ground potential. Path N8' starts at voltage source Vs, passes through switch SY4, bus Y4, the heater at location X2Y4, bus X2, and switch SX2, and then to ground potential. Ammeter 202X 2 Switch SX 2 Measure the normal current IN8' at terminal IN8.

[0114] It should be noted that currents IN7' and IN8' are approximately the same or equal due to the fabrication of heater array 102. Processor 106 receives the measurements of currents IN7' and IN8' and determines that the measurements are symmetric, i.e., heaters at locations X2Y3 and X2Y4 are symmetric with respect to each other. For example, processor 106 determines that the measurement of current IN7' is within a predetermined range from the measurement of current IN8'. Processor 106 determines that the current is asymmetric between at least one each of the heater locations along the Y3 and Y4 buses to identify the Y3 and Y4 buses from all buses Y1-Y6 of heater array 102. The locations where the current is asymmetric along the Y3 and Y4 buses include locations X1Y3 and X1Y4, X3Y3 and X3Y4, X4Y3 and X4Y4, X5Y3 and X5Y4, and X6Y3 and X6Y4. The currents received from positions X2Y3 and X2Y4 are symmetrical.

[0115] Upon determining that not all positions along the X2 and X5 buses are symmetrical and not all positions along the Y3 and Y4 buses are symmetrical, processor 106 determines that X2, X5, Y3, and Y4 are buses in which one or more failed heaters are located. For example, processor 106 determines that the current measurements between positions X2Y1 and X5Y1 (FIG. 2B-1) are asymmetrical and that the current measurements between positions X6Y3 and X6Y4 (FIG. 3B-1) are asymmetrical, and thus determines that not all positions along the X2 and X5 buses are symmetrical and not all positions along the Y3 and Y4 buses are symmetrical.

[0116] After identifying the four buses X2, X5, Y3, and Y4 that have one or more failed heaters, the processor 106 performs processing to determine if there is a single failure within the heater array 106. For example, the processor 106 performs processing to determine if only one heater in the heater array 102 has failed or is failing.

[0117] 4A is one embodiment of a graph 402 for checking for a single fault in the heater array 102. Checking for a single fault verifies that there are no other failed heaters in the heater array 102 and is performed after identifying the four buses X2, X5, Y3, and Y4. The graph 402 plots the delta Δ or difference in current between two locations along two X buses of the heater array 102. The graph includes plots 404 showing the measured difference in current between locations X3Y1 and X4Y1, X3Y2 and X4Y2, X3Y3 and X4Y3, X3Y4 ​​and X4Y4, X3Y5 and X4Y5, and X3Y6 and X4Y6 located along the X3 and X4 buses. For example, plot 404 has a point 404A that shows the difference in current measurements between locations X3Y1 and X4Y1, and another point 404B that shows the difference in current measurements between locations X3Y2 and X4Y2.

[0118] Graph 402 further includes plots 406 illustrating current measurement differences between locations X1Y1 and X6Y1, X1Y2 and X6Y2, X1Y3 and X6Y3, X1Y4 and X6Y4, X1Y5 and X6Y5, and X1Y6 and X6Y6 located along the X1 and X6 buses. Graph 402 also includes plots 408 illustrating current measurement differences between locations X2Y1 and X5Y1, X2Y2 and X5Y2, X2Y3 and X5Y3, X2Y4 and X5Y4, X2Y5 and X5Y5, and X2Y6 and X5Y6 located along the X2 and X5 buses.

[0119] The processor 106 of FIG. 1 is connected to all locations along the X3 and X4 buses, as well as to 1 and X 6 The processor 106 determines that the current measurements between all positions along the bus are symmetrical, except for the current measurements between positions X3Y1 and X4Y1, which are within a predetermined range of each other, and the current measurements between positions X3Y2 and X4Y2, which are within a predetermined range of each other. Further, as shown with reference to FIGS. 2A-1 and 2A-2, the processor 106 determines that the current measurements between all positions along the X1 and X6 buses are symmetrical, except for the current measurements between positions X1Y1 and X6Y1, which are within a predetermined range of each other, and the current measurements between positions X1Y2 and X6Y2, which are within a predetermined range of each other. Also, as shown with reference to FIGS. 2B-1 and 2B-2, the processor 106 determines that the current measurements between all positions along the X2 and X5 buses are asymmetrical, except for the current measurements between positions X2Y3 and X5Y3. The processor 106 determines that the current measurements between locations X2Y3 and X5Y3 are symmetric. The symmetry between locations X2Y3 and X5Y3 is indicated by point 408C on plot 408.

[0120] 4B is one embodiment of a graph 410 for identifying a single fault in the heater array 102. The graph 410 plots the delta Δ of current between two locations along two Y buses of the heater array 102. The graph includes plots 412 that show the difference in current measurements between locations X1Y2 and X1Y5, between X2Y2 and X2Y5, between X3Y2 and X3Y5, between X4Y2 and X4Y5, between X5Y2 and X5Y5, and between X6Y2 and X6Y5, located along the Y2 and Y5 buses. For example, the plot 412 has a point 412A that shows the difference in current measurements between locations X1Y2 and X1Y5, and another point 412B that shows the difference in current measurements between locations X2Y2 and X2Y5.

[0121] Additionally, graph 410 includes plots 414 illustrating current measurement differences between locations X1Y1 and X1Y6, X2Y1 and X2Y6, X3Y1 and X3Y6, X4Y1 and X4Y6, X5Y1 and X5Y6, and X6Y1 and X6Y6 located along the Y1 and Y6 buses. Graph 410 also includes plots 416 illustrating current measurement differences between locations X1Y3 and X1Y4, X2Y3 and X2Y4, X3Y3 and X3Y4, X4Y3 and X4Y4, X5Y3 and X5Y4, and X6Y3 and X6Y4 located along the Y3 and Y4 buses.

[0122] The processor 106 of FIG. 1 determines that the current measurements between all positions along the Y2 and Y5 buses and all positions along the Y1 and Y6 buses are symmetrical. For example, the processor 106 determines that the current measurements between positions X1Y2 and X1Y5 are within a predetermined range of each other, and the current measurements between positions X2Y2 and X2Y5 are within a predetermined range of each other. Furthermore, as shown with reference to FIG. 3A-1 and FIG. 3A-2, the processor 106 determines that the current measurements between all positions along the Y1 and Y6 buses are symmetrical. For example, the processor 106 determines that the current measurements between positions X1Y1 and X1Y6 are within a predetermined range of each other, and the current measurements between positions X2Y1 and X2Y6 are within a predetermined range of each other. 3B-1 and 3B-2, processor 106 determines that the current measurements between all locations along the Y3 and Y4 buses are asymmetric except for the current measurements between locations X2Y3 and X2Y4. Processor 106 determines that the current measurements between locations X2Y3 and X2Y4 are symmetric. The symmetry between locations X2Y3 and X2Y4 is indicated by point 416C on plot 416.

[0123] In response to determining that all positions along the X3 bus and corresponding positions along the X4 bus are symmetrical, all positions along the X1 bus and corresponding positions along the X6 bus are symmetrical, all positions along the X2 bus and corresponding positions along the X5 bus except for one position along the X2 bus and corresponding positions along the X5 bus are asymmetrical, all positions along the Y2 bus and corresponding positions along the Y5 bus are symmetrical, all positions along the Y1 bus and corresponding positions along the Y6 bus are symmetrical, and all positions along the Y3 bus and corresponding positions along the Y4 bus except for one position along the Y3 bus and corresponding positions along the Y4 bus are asymmetrical, the processor 106 determines and confirms that a single fault is present in the heater array 102. Examples of positions along the X2 bus and corresponding positions along the X5 bus include positions that are on the same Y bus. For example, the locations along the X2 bus and the corresponding locations along the X5 bus include locations X2Y1 and X5Y1, X2Y2 and X5Y2, X2Y3 and X5Y3, X2Y4 and X5Y4, X2Y5 and X5Y5, or X2Y6 and X5Y6. Examples of locations along the Y3 bus and the corresponding locations along the Y4 bus include locations along the same X bus. For example, the locations along the Y3 bus and the corresponding locations along the Y4 bus include locations X1Y3 and X1Y4, X2Y3 and X2Y4, X3Y3 and X3Y4, X4Y3 and X4Y4, X5Y3 and X5Y4, or X6Y3 and X6Y4. Processor 106 determines that a single fault exists at a single location along the X2 and X5 and Y3 and Y4 buses. Thus, for single-fault checking, as shown in Figure 4A, processor 106 determines that an asymmetry exists in only one plot 408 of graph 402, except for the symmetry of only one location on the x-bus shown in plot 408 and the corresponding single location of another symmetrically placed x-bus. And for single-fault checking, as shown in Figure 4B, processor 106 further determines that an asymmetry exists in only one plot 416 of graph 410, except for the symmetry of only one location on the y-bus shown in plot 416 and the corresponding single location of another symmetrically placed y-bus.

[0124] 4C is an embodiment of a graph 420 for illustrating the occurrence of two or more faults in the heater array 102. For example, the graph 420 may be used to determine that the heater array has faults at multiple locations. The graph 420 plots the delta Δ of current between two locations along two X buses of the heater array 102. The graph 420 includes plots 422 that show the difference in current measurements between locations X3Y1 and X4Y1, between X3Y2 and X4Y2, between X3Y3 and X4Y3, between X3Y4 ​​and X4Y4, between X3Y5 and X4Y5, and between X3Y6 and X4Y6, located along the X3 and X4 buses. For example, the plot 422 has a point 422A that shows the difference in current measurements between locations X3Y1 and X4Y1, and another point 422B that shows the difference in current measurements between locations X3Y2 and X4Y2.

[0125] Graph 420 further includes plots 424 illustrating current measurement differences between locations X1Y1 and X6Y1, X1Y2 and X6Y2, X1Y3 and X6Y3, X1Y4 and X6Y4, X1Y5 and X6Y5, and X1Y6 and X6Y6 located along the X1 and X6 buses. Graph 420 also includes plots 426 illustrating current measurement differences between locations X2Y1 and X5Y1, X2Y2 and X5Y2, X2Y3 and X5Y3, X2Y4 and X5Y4, X2Y5 and X5Y5, and X2Y6 and X5Y6 located along the X2 and X5 buses. Because an asymmetry exists between two or more plots (such as plots 424 and 426) in graph 420, processor 106 of FIG. 1 determines that there are two or more faults in heater array 102.

[0126] 4D is one embodiment of a graph 430 to illustrate more than a single fault in the heater array 102. The graph 430 plots the delta Δ of current between two locations along two Y buses of the heater array 102. The graph 430 includes plots 432 that show the difference in current measurements between locations X1Y2 and X1Y5, between X2Y2 and X2Y5, between X3Y2 and X3Y5, between X4Y2 and X4Y5, between X5Y2 and X5Y5, and between X6Y2 and X6Y5, located along the Y2 and Y5 buses. For example, the plot 432 has a point 432A that shows the difference in current measurements between locations X1Y2 and X1Y5, and another point 432B that shows the difference in current measurements between locations X2Y2 and X2Y5.

[0127] Additionally, graph 430 includes plots 434 illustrating current measurement differences between locations X1Y1 and X1Y6, X2Y1 and X2Y6, X3Y1 and X3Y6, X4Y1 and X4Y6, X5Y1 and X5Y6, and X6Y1 and X6Y6 located along the Y1 and Y6 buses. Graph 430 also includes plots 436 illustrating current measurement differences between locations X1Y3 and X1Y4, X2Y3 and X2Y4, X3Y3 and X3Y4, X4Y3 and X4Y4, X5Y3 and X5Y4, and X6Y3 and X6Y4 located along the Y3 and Y4 buses. Because an asymmetry exists between two or more plots (such as plots 434 and 436) in graph 430, processor 106 of FIG. 1 determines that there are two or more faults in heater array 102.

[0128] 4E is one embodiment of a graph 440 for illustrating the occurrence of more than one fault in the heater array 102. For example, the graph 440 may be used to determine that the heater array 102 has faults at multiple locations. The graph 440 plots the delta Δ of current between two locations along two X buses of the heater array 102. The graph 440 includes plots 442 showing measured differences in current between locations X3Y1 and X4Y1, X3Y2 and X4Y2, X3Y3 and X4Y3, X3Y4 ​​and X4Y4, X3Y5 and X4Y5, and X3Y6 and X4Y6 located along the X3 and X4 buses.

[0129] Graph 440 further includes plots 444 illustrating current measurement differences between locations X1Y1 and X6Y1, X1Y2 and X6Y2, X1Y3 and X6Y3, X1Y4 and X6Y4, X1Y5 and X6Y5, and X1Y6 and X6Y6 located along the X1 and X6 buses. Graph 440 also includes plots 446 illustrating current measurement differences between locations X2Y1 and X5Y1, X2Y2 and X5Y2, X2Y3 and X5Y3, X2Y4 and X5Y4, X2Y5 and X5Y5, and X2Y6 and X5Y6 located along the X2 and X5 buses. Because a single asymmetry between two locations exists in only one plot 446, the processor 106 determines that the asymmetry of all locations on the plot 446 except for one location is not true, and further determines that more than one fault exists, i.e., multiple heaters have failed within the heater array 102.

[0130] 4F is one embodiment of a graph 450 to illustrate more than a single fault in the heater array 102. The graph 450 plots the delta Δ of current between two locations along two Y buses of the heater array 102. The graph 450 includes plots 452 that show the measured difference in current between locations X1Y2 and X1Y5, between X2Y2 and X2Y5, between X3Y2 and X3Y5, between X4Y2 and X4Y5, between X5Y2 and X5Y5, and between X6Y2 and X6Y5, located along the Y2 and Y5 buses.

[0131] Graph 450 further includes plots 454 illustrating current measurement differences between locations X1Y1 and X1Y6, X2Y1 and X2Y6, X3Y1 and X3Y6, X4Y1 and X4Y6, X5Y1 and X5Y6, and X6Y1 and X6Y6 located along the Y1 and Y6 buses. Graph 450 also includes plots 456 illustrating current measurement differences between locations X1Y3 and X1Y4, X2Y3 and X2Y4, X3Y3 and X3Y4, X4Y3 and X4Y4, X5Y3 and X5Y4, and X6Y3 and X6Y4 located along the Y3 and Y4 buses.

[0132] Because a single asymmetry is present in only one plot 456, the processor 106 determines that it is not the case that all locations on the plot 456 except for one location are asymmetric, and further determines that more than one fault exists, i.e., multiple heaters have failed within the heater array 102.

[0133] FIG. 5 illustrates an embodiment of the heater array 102 to illustrate the determination of a single fault location in the heater array 102. The determination of a single fault location is made by the processor 106 of FIG. 1 after identifying a single fault in the heater array 102. Identifying a single fault is described above with reference to FIGS. 4A-4F. In FIG. 4A, an outlier plot 408 is identified by the processor 106, and thus the X2 and X5 buses are identified by the processor 106 as suspected faults. Also, in FIG. 4B, an outlier plot 416 is identified by the processor 106, and thus the Y3 and Y4 buses are identified by the processor 106 as suspected faults. Referring to FIG. 2B-1, locations along the X2 bus do not receive extraneous current as a result of the failed heater at location X2Y3, but locations along the X5 bus do receive extraneous current. 3B-1, locations along the Y3 bus do not receive extraneous current as a result of the failed heater at location X2Y3 in the associated ammeter reading as measured by ammeter 202X6, but locations along the Y4 bus do receive extraneous current in the associated ammeter reading as measured by ammeter 202X6. An example of an extraneous current measured by ammeter 202X6 is IUW8. Thus, one of buses X2 and X5 having a smaller current and one of buses Y3 and Y4 having a smaller current are suspected by processor 106.

[0134] It should be noted that the heater current described herein includes the measurement of the current by the ammeter associated with the heater when the heater is actively addressed. For example, the current through the heater at location X6Y4 is the measurement of the current by ammeter 202X6 associated with the heater when the heater is actively addressed. The heater at location X6Y4 is actively addressed by processor 106. Processor 106 controls multiplexer 108 to close switches SY4 and SX6. When switches SY4 and SX6 are closed, ammeter 202X6 measures the current I(N8+UW8), as described with reference to FIG. 3B-1.

[0135] The processor 106 compares the four currents IA to ID (corresponding to the positions X2Y3, X2Y4, X5Y3, and X5Y4) acquired during the fault confirmation process. For example, the processor 106 applies a first process to determine whether the current IA is smaller than the current IC or the current IB is smaller than the current ID. If it is determined that the current IA is smaller than the current IC or the current IB is smaller than the current ID, the processor 106 excludes the bus Y4 from the buses in which the failed heater is located. In this example, the processor 106 applies a second process to determine whether the current IA is smaller than the current IB or whether the current IC is smaller than the current ID. If it is determined that the current IA is smaller than the current IB or the current IC is smaller than the current ID, the processor 106 excludes the bus X5 from the buses in which the failed heater is located. The processor 106 determines that the current IA is smaller than the current IC and smaller than the current IB, and determines that the fault location is X2Y3. The fault location X2Y3 of the failed heater is stored by the processor 106 in the memory device 114 of FIG. 1 as mitigation data.

[0136] 1 to close switches SY3 and SX2 and to open the remaining switches SY1, SY2, SY4-SY6, SX1, and SX3-SX6. When switches SY3 and SX2 are closed and the remaining switches SY1, SY2, SY4-SY6, SX1, and SX3-SX6 are open, ammeter 202X2 measures the amount of current IA passing from voltage source VS through switch SY3, bus Y3, the heater at location X2Y3, bus X2, and switch SX2 to ground potential.

[0137] Similarly, current IC is measured when processor 106, during the fault confirmation process, further controls multiplexer 108 to close switches SY4 and SX2 and open the remaining switches SY1-SY3, SY5, SY6, SX1, and SX3-SX6. When switches SY4 and SX2 are closed and the remaining switches SY1-SY3, SY5, SY6, SX1, and SX3-SX6 are open, ammeter 202X2 measures the amount of current IC passing from voltage source VS through switch SY4, bus Y4, heater at location X2Y4, bus X2, and switch SX2 to ground potential.

[0138] Further, current IB is measured when processor 106, during the fault confirmation process, further controls multiplexer 108 to close switch SY3 and switch SX5 and open the remaining switches SY1, SY2, SY4-SY6, SX1-SX4, and SX6. When switches SY3 and SX5 are closed and the remaining switches SY1, SY2, SY4-SY6, SX1-SX4, and SX6 are open, ammeter 202X5 measures the amount of current IB passing from voltage source VS through switch SY3, bus Y3, heater at location X5Y3, bus X5, and switch SX5 to ground potential.

[0139] Current ID is also measured when processor 106, during the fault confirmation process, controls multiplexer 108 to further close switches SY4 and SX5 and open the remaining switches SY1-SY3, SY5, SY6, SX1-SX4, and SX6. When switches SY4 and SX5 are closed and the remaining switches SY1-SY3, SY5, SY6, SX1-SX4, and SX6 are open, ammeter 202X5 measures the amount of current ID passing from voltage source VS through switch SY4, bus Y4, heater at location X5Y4, bus X5, and switch SX5 to ground potential.

[0140] 6 is a diagram illustrating one embodiment of the heater array 102 to illustrate adjusting the duty cycles of operation of multiple heaters in the heater array 102 to compensate for a single failure at a failed heater location X2Y3 in the heater array 102. Location X2Y3 is shown in FIG. 6 as a solid circle. Additionally, locations on or along the same Y bus that includes location X2Y3 are shown as X's and are classified as group 2. Additionally, locations on or along the same X bus that includes location X2Y3 are shown as open circles and are classified as group 3. The remaining locations of the heater array that are not on or along the same X bus or Y bus that includes location X2Y3 are shown as triangles and are classified as group 1.

[0141] After determining the presence of a single fault at location X2Y3 in the heater array 102, the processor 106 accesses (e.g., reads) the mitigation data from the memory device 114 of FIG. 1 to identify the location X2Y3 of the faulty heater in the heater array 102 and controls the duty cycles of operation of the multiple heaters of the heater array 102 to achieve a temperature value Temp1 in the plasma chamber for processing a substrate in the plasma chamber. For example, after determining the presence of a single fault at location X2Y3, the processor 106 maintains the duty cycles of heaters in group 1 that are not located on the same X bus or the same Y bus that includes location X2Y3 and does not change the duty cycles. The duty cycles of heaters in group 1 that are not located on the same X bus or the same Y bus that includes location X2Y3 are the same before and after identifying the location of the single fault. Furthermore, in this example, the processor 106 modifies or adjusts the original duty cycles DCX of heaters in group 2 that are located on the same Y bus that includes location X2Y3 to output an adjusted duty cycle DCXA. For example, the processor 106 reduces or decreases the original duty cycle DCXa of the heater at location X3Y3 by the product of the original duty cycle DCXa and the amount of extraneous power supplied to location X3Y3 from the voltage source Vs to output an adjusted duty cycle DCXAa for the heater at location X3Y3. The amount of extraneous power is supplied to the heater at location X3Y3 due to a single failure of the heater at location X2Y3. The amount of extraneous power is a percentage of the power supplied by the voltage source Vs. The processor 106 generates a difference between the original duty cycle DCXa of the heater at location X3Y3 and the product of the heater's original duty cycle DCXa and the amount of extraneous power supplied to location X3Y3 to output an adjusted duty cycle DCXAa. Processor 106 controls the heater at location X3Y3 via multiplexer 108 and switches SX3 and SY3 such that the heater at location X3Y3 operates at an adjusted duty cycle DCXAa.

[0142] Continuing in this example, processor 106 modifies or adjusts the original duty cycles DCO of heaters in group 3 at locations on the same X bus, including location X2Y3, to output an adjusted duty cycle DCOA. For example, processor 106 reduces the original duty cycle DCOa of the heater at location X2Y4 by the product of the heater's original duty cycle DCOa and the extraneous amount of power supplied to location X2Y4 from voltage source Vs to output an adjusted duty cycle DCOAa for the heater at location X2Y4. The extraneous amount of power is supplied to the heater at location X2Y4 due to a single failure of the heater at location X2Y3. The extraneous amount of power is a percentage of the power supplied by voltage source Vs. The processor 106 generates a difference between the original duty cycle DCOa of the heater at location X2Y4 and the product of the heater's original duty cycle DCOa and the amount of extraneous power supplied to location X2Y4 to output an adjusted duty cycle DCOAa. The processor 106 controls the heater at location X2Y4 via the multiplexer 108 and the switches SX2 and SY4 such that the heater at location X2Y4 operates at the adjusted duty cycle DCOAa.

[0143] Further, in this example, the processor 106 modifies or adjusts the original duty cycle DC of the failed heater at the location X2Y3 to output an adjusted duty cycle DCA of the heater. For example, the processor 106 reduces the original duty cycle DC of the heater at the location X2Y3 by the product of the original duty cycle DC of the heater and the amount of extraneous power supplied from the voltage source Vs to the location X2Y3 to output an adjusted duty cycle DCA for the heater at the location X2Y3. The amount of extraneous power is supplied to the heater at the location X2Y3 due to a single failure of the heater at the location X2Y3. The single failure of the location X2Y3 causes extraneous currents to the remaining locations in the heater array 102, and some of the extraneous currents at the remaining locations leak back to the heater at the location X2Y3. The processor 106 generates a difference between the original duty cycle DC of the heater at location X2Y3 and the product of the heater's original duty cycle DC and the amount of extraneous power supplied to location X2Y3 to generate an adjusted duty cycle DCA. The processor 106 controls the heater at location X2Y3 via the multiplexer 108 and the switches SX2 and SY3 such that the heater at location X2Y3 operates at the adjusted duty cycle DCA.

[0144] The processor 106 transmits an adjusted duty cycle DCA to the heater at the position X2Y3, including the position X2Y3. Y Applying the adjusted duty cycle DCXA to heaters at positions along or on the bus, including positions X2 and Y3 XThe adjusted duty cycle DCOA is applied to heaters at positions along or above the bus to compensate for the failure of the heater at position X2Y3. For example, the processor 106 controls the multiplexer 108 to close switches SY3 and SX2 and open the remaining switches SY1, SY2, SY4-SY6, SX1, and SX3-SX6 for a period of time during which power is applied from the voltage source Vs to the heater at position X2Y3 in the heater array 102 to achieve the adjusted duty cycle DCA. As another example, the processor 106 controls the multiplexer 108 to close switches SY3 and SX1 and open the remaining switches SY1, SY2, SY4-SY6, and SX2-SX6 for a period of time during which power is applied from the voltage source Vs to the heater at position X1Y3 to achieve the adjusted duty cycle for the heater at position X1Y3. As another example, the processor 106 controls the multiplexer 108 to close switches SY4 and SX2 and open the remaining switches SY1-SY3, SY5, SY6, SX1, and SX3-SX6 for the period of time that power is applied from the voltage source Vs to the heater at location X2Y4 to achieve the adjusted duty cycle for the heater at location X2Y4. Note that reducing the duty cycle of the heaters in the heater array 102 reduces the power supplied to the heaters from the voltage source Vs by shortening the time that power is supplied.

[0145] The processor 106 determines the positions X1Y1, X1Y2, X1Y4, X1Y5, X1Y6, X3Y1, X3Y4, X3Y5, X3Y6, X4Y1, X4Y2, X4Y3, X4Y4, X4Y5, X4 ... Y2, X4Y4, X4Y5, X4Y6, X5Y1, X5Y2, X5Y4, X5Y5, X5Y6, X6Y1, X6Y2, X6Y4, X6Y5, and X6Y6 are maintained at the same duty cycle as they were before the fault at location X2Y3 was identified. The processor 106 does not adjust or change the duty cycle of the remaining heaters. Adjusting (e.g., reducing) the duty cycle of the heaters at the locations indicated with filled circles, open circles, and Xs extends the life of the heater array 102 and the life of portions of the plasma chamber in which the heater array 102 is incorporated. Examples of such portions include the substrate support, the chuck, the showerhead, and the upper electrode assembly.

[0146] It should be noted that the temperature profile with the adjusted duty cycle of the heater array 102 with a single fault is identical to the temperature profile with the original duty cycle of the heater array 102 without a single fault, and therefore the wafer processing recipe remains unchanged after adjusting the original duty cycle.

[0147] In one embodiment, the processor 106 stores the adjusted duty cycles DCA, DCOA, and DCXA in the non-volatile memory 110 where the duty cycles DC, DCO, and DCX are stored. The adjusted duty cycles DCA, DCOA, and DCXA are used to achieve a temperature value Temp1 in the plasma chamber. The method described above with reference to FIGS. 1-6 for identifying the bus of the heater array 102 including the location of the faulty heater, verifying that only one fault exists in the heater array 102, identifying the location of the fault, and determining the adjusted duty cycles DCA, DCOA, and DCXA is performed before or during processing of a substrate in the plasma chamber. If the method described above with reference to FIGS. 1-6 is performed before processing of a substrate, there is no further computational overhead during processing. The adjusted duty cycles DCA, DCOA, and DCXA are applied during processing without determining the adjusted duty cycle during processing.

[0148] 7 illustrates an embodiment of a plasma system 700 to illustrate the use of a heater array 102 in a capacitively coupled plasma (CCP) chamber 702. The plasma system 700 includes a plasma chamber 702, a radio frequency generator (RFG) 704, an impedance matching circuit (IMC) 706, a user interface system 112, and a multiplexer 108. The impedance matching circuit, as used herein, may also be referred to as an impedance matching network or impedance matcher. An input of the impedance matching circuit 706 is connected to the RF generator 704 via an RF cable, and an output of the impedance matching circuit 706 is connected to a lower electrode 712 of the plasma chamber 702 via an RF transmission line.

[0149] An impedance matching circuit as described herein is a network of one or more components (such as one or more resistors, or one or more capacitors, or one or more inductors, or a combination thereof) that matches the impedance of a load connected to the output of the impedance matching circuit with the impedance of a source connected to one or more inputs of the impedance matching circuit. Examples of loads connected to the output of the impedance matching circuit 706 include the plasma chamber 702 and an RF transmission line. Additionally, examples of sources connected to the input of the impedance matching circuit 706 include an RF cable and an RF generator 704.

[0150] The plasma chamber 702 includes an upper electrode 708 and a substrate support 710 (such as a chuck). The substrate support 710 includes a heater array 102 and a lower electrode 712. On the upper surface of the substrate support 710, a substrate S (such as a semiconductor wafer) is disposed for processing of the substrate S. Examples of processing of the substrate S include deposition of a material on the substrate S, etching of the substrate S, cleaning of the substrate S, and sputtering of the substrate S. The substrate support 710 faces the upper electrode 708. The upper electrode 708 is connected to a ground potential. Each of the lower electrode 712 and the upper electrode 708 is formed of a metal such as aluminum or an aluminum alloy. The lower electrode 712 is disposed above the heater array 102.

[0151] The user interface system 112 is connected to the RF generator 704 via a transmission cable. The processor 106 of the user interface system 112 provides one or more power levels and / or one or more frequency levels to the RF generator 704. The one or more power levels and the one or more frequency levels are part of a recipe, which is stored in the memory device 114 of the user interface system 112. The RF generator 704 generates an RF signal having one or more power levels and / or one or more frequency levels and provides the RF signal to an impedance matching circuit 706 via an RF cable. The impedance matching circuit 706 matches the impedance of a load connected to an output of the impedance matching circuit 706 with the impedance of a source connected to an input of the impedance matching circuit 706 to provide a matching impedance to the RF cable. Le The impedance matching circuit 706 generates a modulated RF signal from an RF signal received via the N A modulated RF signal is delivered to the lower electrode 712 of the plasma chamber 702 via a cascade.

[0152] When one or more process gases are supplied to the plasma chamber 702 in addition to supplying a modulated RF signal, a plasma is ignited or maintained in the plasma chamber 702 to process the substrate S. An example of the one or more process gases includes an oxygen-containing gas (such as O2). Other examples of the one or more process gases include a fluorine-containing gas, such as tetrafluoromethane (CF4), sulfur hexafluoride (SF6), hexafluoroethane (C2F6), and the like.

[0153] Prior to or during processing of the substrate S, the processor 106 of the user interface system 112 identifies a single fault location of a heater in the heater array 102 of the substrate support 710 using the method described above with reference to Figures 1-5. Once the single fault location is identified, the processor 106 adjusts the original duty cycles DC, DCO, and DCX to corresponding adjusted duty cycles DCA, DCOA, and DCXA to achieve a temperature value Temp1 in the plasma chamber 702. The duty cycles DC, DCO, and DCX are adjusted during processing of the substrate S.

[0154] In one embodiment, instead of being embedded in the substrate support 710, the heater array 102 is embedded in an upper electrode assembly that includes an upper electrode 708, and a lower electrode 712 is connected to ground potential.

[0155] In one embodiment, instead of being embedded in the substrate support 710, the heater array 102 is embedded within an upper electrode assembly that includes an upper electrode 708 and a lower electrode 712 that is connected to one or more RF generators.

[0156] In one embodiment, instead of being connected to ground potential, the upper electrode 708 is connected to one or more RF generators.

[0157] 8 illustrates one embodiment of a system 800 to illustrate the use of a heater array 102 in a showerhead 802 of a plasma chamber 804. The system 800 includes a voltage source Vs, a multiplexer 108, a user interface system 112, a radio frequency generator 704, an impedance matching circuit 706, and a plasma chamber 804.

[0158] The output of the impedance matching circuit 706 is connected to an upper electrode 708 in the showerhead 802 via an RF transmission line. The plasma chamber 804 includes a substrate support 806 facing the showerhead 802 to form a processing gap between the showerhead 802 and the substrate support 806. A lower electrode 712 is embedded in the substrate support 806. Further, a heater array 102 is embedded in the showerhead 802. The heater array 102 is disposed above the upper electrode 708. The lower electrode 712 is connected to a ground potential. A substrate S is disposed on top of the substrate support 806 for processing of the substrate S.

[0159] Upon receiving an RF signal from the RF generator 704, the impedance matching circuit 706 modulates the received RF signal to output a modulated RF signal so as to match the impedance of a load connected to the output of the impedance matching circuit 706 with the impedance of a source connected to the input of the impedance matching circuit 706. Examples of loads connected to the output of the impedance matching circuit 706 include the plasma chamber 804 and the RF transmission line connecting the impedance matching circuit 706 to the showerhead 802.

[0160] The showerhead 802 includes a plurality of holes that are used to deliver one or more process gases or one or more liquid metals to a process gap between the showerhead 802 and a substrate support 806. When one or more process gases or one or more liquid metals are delivered to the gap between the showerhead 802 and the substrate support 806, in addition to providing a modulated RF signal from the impedance match circuit 706 to the upper electrode 708, a plasma is ignited or sustained in the process gap to process the substrate S. For example, the showerhead 802 is used to perform plasma-enhanced atomic layer deposition (PEALD) or plasma-enhanced chemical vapor deposition (PECVD) on the substrate S.

[0161] Prior to or during processing of the substrate S, the processor 106 of the user interface system 112 identifies a single fault location of a heater in the heater array 102 embedded in the showerhead 802 using the methods described above with reference to Figures 1-5. Once the single fault location is identified, the processor 106 adjusts the original duty cycles DC, DCO, and DCX to corresponding adjusted duty cycles DCA, DCOA, and DCXA to achieve a temperature value Temp1 in the plasma chamber 804.

[0162] In one embodiment, instead of the lower electrode 712 being connected to ground potential, the upper electrode 708 is connected to ground potential and the lower electrode 712 is connected to the RF generator 704 via an RF transmission line (not shown), an impedance matching circuit (not shown), and an RF cable (not shown).

[0163] In one embodiment, the upper electrode 708 is connected to an RF generator 704 and the lower electrode 712 is connected to another RF generator (not shown) through an impedance matching network (not shown).

[0164] 9 illustrates an embodiment of a system 900 to illustrate the use of a heater array 102 in an inductively coupled plasma (ICP) chamber 902. The system 900 includes a user interface system 112, a multiplexer 108, an RF generator 704, an impedance matching circuit 706, an RF coil 904, and a plasma chamber 902. The plasma chamber 902 includes a dielectric window 906. The RF coil 904 is disposed above the dielectric window 906.

[0165] The output of the impedance matching circuit 706 is connected to an RF coil 904 via an RF transmission line. The plasma chamber 902 includes a substrate support 710 having a lower electrode 712 embedded therein. The heater array 102 is disposed within the substrate support 710. The lower electrode 712 is connected to ground potential. The heater array 102 is disposed below the lower electrode 712. A substrate S is placed on top of the substrate support 710 for processing.

[0166] Upon receiving the RF signal from the RF generator 704, the impedance matching circuit 706 matches the impedance of a load connected to the output of the impedance matching circuit 706 with the impedance of a source connected to the input of the impedance matching circuit 706 to output a modulated RF signal at the output of the impedance matching circuit. An example of a load connected to the output of the impedance matching circuit includes an RF transmission line connected to the output of the impedance matching circuit and an RF coil 904. The RF coil 904 receives the modulated RF signal from the output of the impedance matching circuit 706 via the RF transmission line. One or more process gases are pumped into the plasma chamber. 902 904, and the RF power of the modulated RF signal supplied to the RF coil 904 is applied to the plasma chamber 902 When inductively coupled to the plasma, a plasma is generated in the plasma chamber for processing the substrate S. 902 It is ignited or maintained within

[0167] Prior to or during processing of the substrate S, the processor 106 of the user interface system 112 identifies a single fault location of a heater in the heater array 102 embedded in the substrate support 710 using the methods described above with reference to Figures 1-5. Once the single fault location is identified, the processor 106 adjusts the original duty cycles DC, DCO, and DCX to corresponding adjusted duty cycles DCA, DCOA, and DCXA to achieve a temperature value Temp1 in the plasma chamber 902.

[0168] In some embodiments, instead of the RF coil 904, multiple RF coils are placed above the dielectric window 906. In various embodiments, instead of or in addition to the RF coil 904, one or more RF coils are disposed in the plasma chamber. 902 In some embodiments, a Faraday shield is positioned below and adjacent the dielectric window 906 to clean the dielectric window 906 and remove any material deposited thereon.

[0169] In various embodiments, the lower electrode 712, instead of being connected to ground potential, is connected to another RF generator (not shown) through an impedance matching circuit.

[0170] 1A is a diagram illustrating one embodiment of a system 1000 to illustrate a notification 1002 that is displayed on a display device 116 when a single fault in the heater array 102 of FIG. 1 is confirmed or when a single fault location of a heater in the heater array 102 is identified by the processor 106 (FIG. 1). The system 1000 includes a display device 116, a central processing unit (CPU) 1004, and a mouse 1006. The CPU 1004 has a housing that houses the processor 106. The mouse 1006 is an example of an input device that a user may use to provide commands to the processor 106.

[0171] Upon identifying a single fault in the heater array 102, the processor 106 controls the display device 116 to display a notification 1002. The notification 1002 indicates to the user that there is a fault in the heater array 102, which is an example of a heater system. Additionally, the notification 1002 indicates to the user that the user should order a new chuck that incorporates the heater array 102.

[0172] In one embodiment, once a single location within the heater array (eg, location X2Y2) is identified by the processor 106, the processor 106 controls the display device 116 to display the notification 1002.

[0173] 10B is a diagram illustrating one embodiment of the display device 116 to illustrate another notification 1010 that is displayed on the display device 116 when a single fault in the heater array 102 of FIG. 1 is confirmed or when the location of a single fault in the heater array 102 is identified by the processor 106 (FIG. 1). The notification 1010 indicates to the user that there is a fault in the heater array 102 and that the fault does not require stopping processing of the substrate S. The notification 1010 further indicates that the user should order a new chuck.

[0174] In one embodiment, a notification, such as notification 1002 or notification 1010 in FIG. 10A, is displayed on the display device 116 before, during, or after the processor 106 adjusts the duty cycles DC, DCO, and DCX.

[0175] In one embodiment, instead of a displayed notification, the processor 106 controls an audio device to output a sound indicating that there is a fault in the heater array 102 and that the user should order a replacement part for the substrate support or showerhead in which the heater array 102 is embedded.

[0176] Providing a notification to the user saves substrate processing time. While the replacement part is being received by the user, the processor 106 continues to control the plasma system (such as system 700 of FIG. 7, system 800 of FIG. 8, or system 900 of FIG. 9) to process the substrate S and any additional substrates. The processor 106 applies the adjusted duty cycles DCA, DCOA, and DCXA while the replacement part is received by the user so that no or minimal downtime occurs for the processing of substrate S and further substrates due to a single failure at location X2Y3 in heater array 102.

[0177] Note that location X2Y3 is for illustrative purposes only: in one embodiment, instead of the heater at location X2Y3, another heater at another location in heater array 102 may have a fault.

[0178] The embodiments described herein may be practiced with a variety of computer system configurations, including handheld hardware units, microprocessor systems, microprocessor-based or programmable consumer electronics, minicomputers, mainframe computers, etc. The embodiments may also be practiced in distributed computing environments where tasks are performed by remote processing hardware units linked through a network.

[0179] In some embodiments, the controller described herein is part of a system, which may be part of the examples described above. Such systems include semiconductor processing equipment, such as one or more processing tools, one or more chambers, one or more platforms for processing, and / or specific processing components (wafer pedestal, gas flow system, etc.). These systems are integrated with electronics for controlling the operation of the system before, during, and after processing of a semiconductor wafer or substrate. The electronics may be referred to as a "controller" and may control various components or subparts of one or more systems. The controller is programmed to control any of the processes disclosed herein, such as supply of process gases, temperature settings (e.g., heating and / or cooling), pressure settings, vacuum settings, power settings, RF generator settings, RF matching circuit settings, frequency settings, flow settings, fluid supply settings, position and motion settings, and wafer movement in and out of load locks connected or coupled with tools and other moving tools and / or systems, depending on the processing requirements and / or type of system.

[0180] In general, in various embodiments, a controller is defined as electronic equipment having various integrated circuits, logic, memory, and / or software that receive instructions, issue instructions, control operations, enable cleaning operations, enable endpoint measurements, etc. Integrated circuits include chips in the form of firmware that store program instructions, digital signal processors (DSPs), chips defined as ASICs, PLDs, and / or one or more microprocessors or microcontrollers that execute program instructions (e.g., software). Program instructions are instructions that are communicated to the controller in the form of various individual settings (or program files) to define parameters, factors, variables, etc., for or to a system to perform a particular process on or for a semiconductor wafer. Program instructions, in some embodiments, are part of a recipe defined by a process engineer to accomplish one or more process steps during the processing of one or more layers, materials, metals, oxides, silicon, silicon dioxide, surfaces, circuits, and / or dies of a wafer.

[0181] The controller, in some embodiments, is part of or connected to a computer that is integrated with, connected to, or otherwise networked with the system, or a combination thereof. For example, the controller may be in the "cloud" or may be all or part of a fab host computer system that allows remote access of wafer processing. The computer allows remote access to the system to monitor the current progress of a manufacturing operation, look at the history of past manufacturing operations, or look at trends or performance indicators from multiple manufacturing operations, to change parameters of a current process, set up processing steps according to a current process, or initiate a new process.

[0182] In some embodiments, a remote computer (e.g., a server) provides process recipes to the system over a network (including a local network or the Internet). The remote computer includes a user interface that allows for input or programming of parameters and / or settings, which are communicated from the remote computer to the system. In some examples, the controller receives instructions in the form of data, which specify parameters, factors, and / or variables for each of the process steps to be performed during one or more operations. It should be understood that the parameters, factors, and / or variables are specific to the type of process to be performed and the type of tool the controller is configured to interface with or control. Thus, as described above, the controller is distributed, such as by having one or more separate controllers that are networked and operate toward a common purpose (such as the process and control described herein). One example of a distributed controller for such purposes includes one or more integrated circuits on the chamber that communicate with one or more remotely located integrated circuits (such as at the platform level or located as part of the remote computer) that cooperate to control the process in the chamber.

[0183] Without being limited thereto, in various embodiments, examples of systems to which the methods may be applied include a plasma etch chamber or module, a deposition chamber or module, a spin rinse chamber or module, a metal plating chamber or module, a cleaning chamber or module, a bevel edge etch chamber or module, a physical vapor deposition (PVD) chamber or module, a chemical vapor deposition (CVD) chamber or module, an atomic layer deposition (ALD) chamber or module, an atomic layer etch (ALE) chamber or module, an ion implantation chamber or module, a track chamber or module, and any other semiconductor processing system that may be associated with or utilized in the fabrication and / or manufacturing of semiconductor wafers.

[0184] It should also be noted that in some embodiments, the above operations apply to several types of plasma chambers, such as inductively coupled plasma (ICP) reactors, transformer coupled plasma chambers, plasma chambers with conductor tools, dielectric tools, plasma chambers with electron cyclotron resonance (ECR) reactors, etc. For example, one or more RF generators are connected to an inductor in an ICP reactor. Examples of inductor shapes include a solenoid, a dome coil, a flat coil, etc.

[0185] As described above, depending on the processing step or steps being performed by the tool, the host computer communicates with one or more of other tool circuits or modules, other tool components, cluster tools, other tool interfaces, adjacent tools, nearby tools, tools located throughout the factory, a main computer, another controller, or tools used in material transport to carry containers of wafers to and from tool locations and / or load ports within the semiconductor manufacturing factory.

[0186] With the above embodiments in mind, it should be understood that some of the embodiments employ various computer-implemented operations involving data stored in computer systems. These operations are operations that physically manipulate physical quantities. Any of the operations described herein that form part of the present embodiments are useful machine operations.

[0187] Some of the embodiments further relate to hardware units or devices for performing these operations. The device is specially configured for a special purpose computer. When defined as a special purpose computer, the computer can operate for a specific purpose while performing other processes, program executions or routines that are not included in the specific purpose.

[0188] In some embodiments, operations may be processed on a computer selectively activated or configured by one or more computer programs stored in a computer memory, cache, or obtained over a computer network. When data is obtained over a computer network, the data may be processed by other computers on the computer network (e.g., a cloud of computing resources).

[0189] One or more embodiments may be manufactured as computer readable code on a non-transitory computer readable medium. A non-transitory computer readable medium is any data storage hardware unit (e.g., memory device, etc.) that stores data, which is then read by a computer system. Examples of non-transitory computer readable media include hard drives, network attached storage (NAS), ROM, RAM, compact disc-ROM (CD-ROM), CD-recordable (CD-R), CD-rewritable (CD-RW), magnetic tape, and other optical and non-optical data storage hardware units. In some embodiments, the non-transitory computer readable medium includes a computer readable tangible medium distributed over a networked computer system such that the computer readable code is stored and executed in a distributed manner.

[0190] Although the method operations described above are presented in a particular order, it should be understood that in various embodiments, other housekeeping processes are performed between operations, or the method operations are performed at slightly different times, distributed across a system that allows method operations to occur at various intervals, or arranged to be performed in an order different from that described above.

[0191] Furthermore, it should be noted that in one embodiment, one or more features of any embodiment described herein may be combined with one or more features of any other embodiment without departing from the scope described in the various embodiments described in this disclosure.

[0192] Although the present embodiments have been described in some detail for purposes of clarity of understanding, it will be apparent that certain changes and modifications may be practiced within the scope of the appended claims. The present embodiments are therefore to be considered as illustrative and not restrictive, and the embodiments are not to be limited to the details given herein. Furthermore, the present disclosure can be realized in the following forms. [Form 1] 1. A method for regulating power supplied to a heater array having a failed heater, comprising: accessing mitigation data identifying a location of the failed heater, the failed heater being located on both an X bus and a Y bus; adjusting a duty cycle of power applied to the failed heater to output an adjusted duty cycle; applying the adjusted duty cycle to the failed heater, the adjusted duty cycle reducing power to the failed heater; applying a further adjusted duty cycle to a series of heaters on the X bus and the Y bus without adjusting a remaining duty cycle applied to remaining heaters of the heater array, the further adjusted duty cycle reducing power to the series of heaters; A method comprising: [Form 2] 2. A method according to claim 1, wherein the X bus is one of a plurality of X buses of the heater array, and the Y bus is one of a plurality of Y buses of the heater array, the method further comprising: receiving a plurality of measurements of current output from the plurality of X buses of the heater array; receiving a plurality of measurements of current output from the plurality of Y-buses of the heater array; identifying two X buses from the plurality of X buses where a first difference between two of the plurality of measurements received from the plurality of X buses is outside a predetermined range, the two X buses being symmetrically positioned about a central X axis of the heater array; identifying two Y buses from the plurality of Y buses in which a second difference between two of the plurality of measurements received from the plurality of Y buses is outside a predetermined range, the two Y buses being symmetrically disposed with respect to a central Y axis of the heater array; A method comprising: [Form 3] 3. The method of claim 2, further comprising the step of verifying that there is no failure of another failed heater in the heater array. [Form 4] The method of embodiment 3, further comprising: receiving a plurality of measurements of current output from the two X buses and the two Y buses; determining the location of the failed heater from the plurality of measurements of current output from the two X buses and the two Y buses; A method comprising: [Form 5] 2. The method of claim 1, wherein the mitigation data includes the location of the failed heater, the location of the failed heater being identified by the X bus and the Y bus. [Form 6] 2. The method of claim 1, wherein adjusting the duty cycle comprises reducing the duty cycle of operation of the faulty heater. [Form 7] 2. The method of claim 1, wherein applying the further adjusted duty cycle to the set of heaters on the X bus and the Y bus comprises reducing a plurality of duty cycles of the set of heaters on the X bus and the Y bus. [Form 8] 2. The method of claim 1, wherein the remaining duty cycle applied to the remaining heaters of the heater array is the same before and after the location of the failed heater is identified. [Form 9] 1. A system comprising: a heater array having a plurality of X buses, a plurality of Y buses, and a plurality of heaters distributed within the plasma chamber; a power supply circuit for setting a duty cycle of power to each of the plurality of heaters; Equipped with the power supply circuit is configured to adjust the duty cycle of a faulty heater of the plurality of heaters and to adjust the duty cycle of power supplied to first and second groups of heaters of the plurality of heaters, the plurality of X buses including an X bus associated with the faulty heater and the plurality of Y buses including a Y bus associated with the faulty heater, the first group of heaters located on the X bus associated with the faulty heater and the second group of heaters located on the Y bus associated with the faulty heater. [Form 10] 10. The system according to claim 9, wherein the power supply circuit includes a processor, the processor comprising: receiving a plurality of measurements of current output from the plurality of X buses of the heater array; receiving a plurality of measurements of current output from the plurality of Y-buses of the heater array; identifying two X buses from the plurality of X buses where a first difference between two of the plurality of measurements received from the plurality of X buses is outside a predetermined range, the two X buses being symmetrically positioned about a central X axis of the heater array; identifying two Y buses from the plurality of Y buses in which a second difference between two of the plurality of measurements received from the plurality of Y buses is outside a predetermined range, the two Y buses being symmetrically disposed with respect to a central Y axis of the heater array; A system that is configured to run [Form 11] 11. The system of claim 10, wherein the processor is configured to perform a step of verifying that there is no failure of another failed heater in the heater array. [Form 12] 12. The system of claim 11, wherein the processor: receiving a plurality of measurements of current output from the two X buses and the two Y buses; determining a location of the failed heater from the plurality of measurements of current output from the two X buses and the two Y buses; A system that is configured to run [Form 13] 13. The system of claim 12, wherein the power supply circuit is configured to maintain a remaining duty cycle applied to the remaining heaters of the heater array the same before and after the location of the failed heater is identified. [Form 14] 10. A system as described in claim 9, wherein the power supply circuit includes a processor, the processor configured to determine a location of the failed heater, the location of the failed heater being determined by the X bus associated with the failed heater and the Y bus associated with the failed heater. [Form 15] 10. The system of claim 9, wherein the power supply circuit is configured to reduce the duty cycle of operation of the failed heater to adjust the duty cycle of the failed heater. [Form 16] A system as described in claim 9, wherein the power supply circuit is configured to reduce the duty cycle of the power supplied to the first and second groups of heaters in order to adjust the duty cycle of the power supplied to the first and second groups of heaters.

Claims

1. 1. A method for locating a faulty heater in a heater array of a plasma chamber, comprising: receiving a first series of measurements of current from a first plurality of X buses of the heater array, the heater array including heaters; receiving a second series of measurements of current from a first plurality of Y buses of the heater array, the heater being at one of the first plurality of X buses and one of the first plurality of Y buses; determining whether a first measurement in the first series of measurements is within a predetermined range of a second measurement in the first series of measurements; determining whether a first measurement in the second series of measurements is within a predetermined range from a second measurement in the second series of measurements; identifying the heater at the location as faulty after determining that the first measurement in the first series of measurements is outside the predetermined range from the second measurement in the first series of measurements and that the first measurement in the second series of measurements is outside the predetermined range from the second measurement in the second series of measurements; A method comprising:

2. 10. The method of claim 1 further comprising: determining whether a third measurement in the first series of measurements is within a predetermined range from a fourth measurement in the first series of measurements; determining whether a third measurement in the second series of measurements is within a predetermined range from a fourth measurement in the second series of measurements; the step of identifying that the heater at the location is faulty occurs after determining that the third measurement in the first series of measurements is within the predetermined range of the fourth measurement in the first series of measurements and the third measurement in the second series of measurements is within the predetermined range of the fourth measurement in the second series of measurements.

3. 10. The method of claim 1 further comprising: receiving a third series of current measurements from a second plurality of X buses of the heater array; receiving a fourth series of current measurements from a second plurality of Y buses of the heater array; determining whether a first measurement in the third series of measurements is within the predetermined range from a second measurement in the third series of measurements; determining whether a first measurement in the fourth series of measurements is within the predetermined range from a second measurement in the fourth series of measurements; wherein the step of identifying that the heater at the location is faulty occurs after determining that the first measurement in the third series of measurements is within the predetermined range of the second measurement in the third series of measurements and the first measurement in the fourth series of measurements is within the predetermined range of the second measurement in the fourth series of measurements.

4. 4. The method of claim 3 further comprising: determining whether a third measurement in the third series of measurements is within the predetermined range from a fourth measurement in the third series of measurements; determining whether a third measurement in the fourth series of measurements is within the predetermined range from a fourth measurement in the fourth series of measurements; the step of identifying that the heater at the location is faulty occurs after determining that the third measurement in the third series of measurements is within the predetermined range from the fourth measurement in the third series of measurements and that the third measurement in the fourth series of measurements is within the predetermined range from the fourth measurement in the fourth series of measurements.

5. 2. The method of claim 1 , The method according to claim 1, wherein the heater is connected to a diode.

6. 6. The method of claim 5, The method of claim 1, wherein the heater is connected in series with the diode.

7. 7. The method of claim 6, The method of claim 1, wherein the heater is connected to the one of the first plurality of X busses and the diode is connected to the one of the first plurality of Y busses.

8. 1. A system for locating a faulty heater in a heater array of a plasma chamber, comprising:

1. A processor comprising: receiving a first series of measurements of current from a first plurality of X buses of the heater array, the heater array including heaters; receiving a second series of measurements of current from a first plurality of Y buses of the heater array, the heater being at one of the first plurality of X buses and one of the first plurality of Y buses; determining whether a first measurement in the first series of measurements is within a predetermined range from a second measurement in the first series of measurements; determining whether a first measurement in the second series of measurements is within a predetermined range from a second measurement in the second series of measurements; a processor configured to identify that the heater at the location is faulty after determining that the first measurement in the first series of measurements is outside the predetermined range from the second measurement in the first series of measurements and the first measurement in the second series of measurements is outside the predetermined range from the second measurement in the second series of measurements; a memory device coupled to the processor; A system comprising:

9. 9. The system of claim 8, The processor, determining whether a third measurement in the first series of measurements is within the predetermined range from a fourth measurement in the first series of measurements; configured to determine whether a third measurement in the second series of measurements is within the predetermined range from a fourth measurement in the second series of measurements; the heater at the location is identified as faulty after determining that the third measurement in the first series of measurements is within the predetermined range from the fourth measurement in the first series of measurements and the third measurement in the second series of measurements is within the predetermined range from the fourth measurement in the second series of measurements.

10. 9. The system of claim 8, The processor, receiving a third series of current measurements from a second plurality of X buses of the heater array; receiving a fourth series of current measurements from a second plurality of Y buses of the heater array; determining whether a first measurement in the third series of measurements is within the predetermined range from a second measurement in the third series of measurements; configured to determine whether a first measurement in the fourth series of measurements is within the predetermined range from a second measurement in the fourth series of measurements; the heater at the location is identified as faulty after determining that the first measurement in the third series of measurements is within the predetermined range from the second measurement in the third series of measurements and the first measurement in the fourth series of measurements is within the predetermined range from the second measurement in the fourth series of measurements.

11. 11. The system of claim 10, The processor, determining whether a third measurement in the third series of measurements is within the predetermined range from a fourth measurement in the third series of measurements; configured to determine whether a third measurement in the fourth series of measurements is within the predetermined range from a fourth measurement in the fourth series of measurements; the heater at the location is identified as faulty after determining that the third measurement in the third series of measurements is within the predetermined range from the fourth measurement in the third series of measurements and the third measurement in the fourth series of measurements is within the predetermined range from the fourth measurement in the fourth series of measurements.

12. 9. The system of claim 8, The heater is connected to a diode.

13. 13. The system of claim 12, The heater is connected in series with the diode.

14. 14. The system of claim 13, the heater is connected to the one of the first plurality of X busses and the diode is connected to the one of the first plurality of Y busses.

15. 1. A system for locating a faulty heater in a heater array of a plasma chamber, comprising:

1. A plasma chamber comprising: a plasma chamber including a heater array having a first plurality of X busses and a first plurality of Y busses, the heater array including a heater at one of the first plurality of X busses and one of the first plurality of Y busses; a processor coupled to the plasma chamber, receiving a first series of current measurements from the first plurality of X buses of the heater array; receiving a second series of measurements of current from the first plurality of Y buses of the heater array; determining whether a first measurement in the first series of measurements is within a predetermined range from a second measurement in the first series of measurements; determining whether a first measurement in the second series of measurements is within a predetermined range from a second measurement in the second series of measurements; a processor configured to identify that the heater at the location is faulty after determining that the first measurement in the first series of measurements is outside the predetermined range from the second measurement in the first series of measurements and the first measurement in the second series of measurements is outside the predetermined range from the second measurement in the second series of measurements; A system comprising:

16. 16. The system of claim 15, The processor, determining whether a third measurement in the first series of measurements is within the predetermined range from a fourth measurement in the first series of measurements; configured to determine whether a third measurement in the second series of measurements is within the predetermined range from a fourth measurement in the second series of measurements; the heater at the location is identified as faulty after determining that the third measurement in the first series of measurements is within the predetermined range from the fourth measurement in the first series of measurements and the third measurement in the second series of measurements is within the predetermined range from the fourth measurement in the second series of measurements.

17. 16. The system of claim 15, the heater array includes a second plurality of X busses and a second plurality of Y busses; The processor, receiving a third series of measurements of current from the second plurality of X buses; receiving a fourth series of measurements of current from the second plurality of Y buses; determining whether a first measurement in the third series of measurements is within the predetermined range from a second measurement in the third series of measurements; configured to determine whether a first measurement in the fourth series of measurements is within the predetermined range from a second measurement in the fourth series of measurements; the heater at the location is identified as faulty after determining that the first measurement in the third series of measurements is within the predetermined range from the second measurement in the third series of measurements and the first measurement in the fourth series of measurements is within the predetermined range from the second measurement in the fourth series of measurements.

18. 20. The system of claim 17, The processor, determining whether a third measurement in the third series of measurements is within the predetermined range from a fourth measurement in the third series of measurements; configured to determine whether a third measurement in the fourth series of measurements is within the predetermined range from a fourth measurement in the fourth series of measurements; the heater at the location is identified as faulty after determining that the third measurement in the third series of measurements is within the predetermined range from the fourth measurement in the third series of measurements and the third measurement in the fourth series of measurements is within the predetermined range from the fourth measurement in the fourth series of measurements.

19. 16. The system of claim 15, The heater is connected to a diode.

20. 20. The system of claim 19, The heater is connected in series with the diode.

21. 21. The system of claim 20, the heater is connected to the one of the first plurality of X busses and the diode is connected to the one of the first plurality of Y busses.

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