Semiconductor device, semiconductor device manufacturing method and manufacturing apparatus, and electronic device

Abstract

The semiconductor device comprises a base substrate (UK), a first light-reflecting portion (RF) positioned above the base substrate (UK), a first mask (6) positioned above the first light-reflecting portion (RF), a base semiconductor portion (8) positioned above the first mask (6), a compound semiconductor portion (9) positioned above the base semiconductor portion (8), and a second light-reflecting portion (RS) positioned above the compound semiconductor portion (9) and the first light-reflecting portion (RF).

Description

[Technical field]

[0001] The present disclosure relates to semiconductor devices and the like. [Background technology]

[0002] In Patent Document 1, a DBR (Distributed Bragg Reflector) layer and a luminescence layer are formed on a GaN substrate. A surface-emitting semiconductor laser element having a photoresist layer is disclosed. The structure using the DBR as a selective growth mask has a problem with heat dissipation. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent No. 6555260 Summary of the Invention

[0004] The semiconductor device according to the present disclosure comprises an underlying substrate including a main substrate, a first optical reflector located above the underlying substrate, a first mask located above the first optical reflector, a base semiconductor portion located above the first mask, a compound semiconductor portion located above the base semiconductor portion, and a second optical reflector located above the compound semiconductor portion and the first optical reflector. [Brief description of the drawings]

[0005] [Figure 1] 1 is a cross-sectional view showing a configuration of a semiconductor device according to an embodiment of the present invention. [Diagram 2] 4 is a cross-sectional view showing another configuration of the semiconductor device according to the embodiment. FIG. [Diagram 3] 4 is a flowchart showing an example of a method for manufacturing a semiconductor device according to the embodiment. [Figure 4] 1 is a block diagram showing an example of a semiconductor device manufacturing apparatus according to an embodiment of the present invention. [Diagram 5]2 is a cross-sectional view taken along the X direction of the semiconductor device according to the first embodiment. FIG. [Figure 6] 4 is a cross-sectional view taken along the Y direction of the semiconductor device according to the first embodiment. FIG. [Figure 7] 1 is a plan view of a semiconductor device according to a first embodiment. [Figure 8] FIG. 2 is a partially enlarged view of the semiconductor device of the first embodiment. [Figure 9] FIG. 2 is a partially enlarged view of the semiconductor device of the first embodiment. [Figure 10] 2 is a cross-sectional view showing an example of the configuration of a base substrate. FIG. [Figure 11] 11 is a cross-sectional view showing another example of the configuration around the first light reflecting portion. FIG. [Figure 12] 11 is a cross-sectional view showing another example of the configuration around the first light reflecting portion. FIG. [Figure 13] 11 is a cross-sectional view showing another example of the configuration around the first light reflecting portion. FIG. [Figure 14] 4 is a flowchart showing an example of a method for manufacturing a semiconductor device according to the first embodiment. [Figure 15] 1A to 1C are cross-sectional views showing steps of an example of a method for manufacturing a semiconductor device according to a first embodiment. [Figure 16] 2 is a cross-sectional view showing an example of lateral growth of a base semiconductor portion 8. FIG. [Figure 17] 4 is a plan view showing another configuration of the semiconductor device of the first embodiment. FIG. [Figure 18] 4 is a cross-sectional view showing another configuration of the semiconductor device of Example 1. FIG. [Figure 19] 4 is a plan view showing another configuration of the semiconductor device of the first embodiment. FIG. [Figure 20] 4 is a cross-sectional view showing another configuration of the semiconductor device according to the first embodiment. FIG. [Figure 21] 4 is a cross-sectional view showing another configuration of the semiconductor device according to the first embodiment. FIG. [Figure 22] 4 is a cross-sectional view showing another configuration of the semiconductor device according to the first embodiment. FIG. [Figure 23] 4 is a cross-sectional view showing another configuration of the semiconductor device according to the first embodiment. FIG. [Figure 24]4 is a cross-sectional view showing another configuration of the semiconductor device according to the first embodiment. FIG. [Diagram 25] 4 is a cross-sectional view showing another configuration of the semiconductor device according to the first embodiment. FIG. [Figure 26] 4 is a cross-sectional view showing another configuration of the semiconductor device according to the first embodiment. FIG. [Figure 27] 4 is a plan view showing another configuration of the semiconductor device in accordance with the first embodiment. FIG. [Figure 28] 4 is a plan view showing another configuration of the semiconductor device in accordance with the first embodiment. FIG. [Figure 29] 4 is a schematic plan view showing another configuration of the semiconductor device according to the first embodiment. FIG. [Diagram 30] 4 is a schematic plan view showing another configuration of the semiconductor device according to the first embodiment. FIG. [Diagram 31] FIG. 11 is a cross-sectional view showing the configuration of a semiconductor device according to a second embodiment. [Diagram 32] FIG. 4 is a cross-sectional view showing the configuration of a base substrate according to Example 2. [Diagram 33] FIG. 4 is a cross-sectional view showing the configuration of a base substrate according to Example 2. [Diagram 34] FIG. 4 is a cross-sectional view showing the configuration of a base substrate according to Example 2. [Diagram 35] FIG. 4 is a cross-sectional view showing the configuration of a base substrate according to Example 2. [Diagram 36] FIG. 11 is a cross-sectional view showing the configuration of a semiconductor device according to a third embodiment. [Figure 37] FIG. 11 is a cross-sectional view showing the configuration of a semiconductor device according to a third embodiment. [Figure 38] 10 is a flowchart showing an example of a method for manufacturing a semiconductor device according to a fourth embodiment. [Figure 39] FIG. 11 is a cross-sectional view showing the configuration of a semiconductor device according to a fourth embodiment. [Diagram 40] FIG. 11 is a cross-sectional view showing the configuration of a semiconductor device according to a fourth embodiment. [Diagram 41] 13 is a flowchart showing another example of the method for manufacturing a semiconductor device according to the fourth embodiment. [Diagram 42] 11 is a cross-sectional view showing another configuration of the semiconductor device according to the fourth embodiment. [Diagram 43] 13 is a cross-sectional view showing another configuration of the semiconductor device according to the eighth embodiment. [Diagram 44] 13 is a cross-sectional view showing another configuration of the semiconductor device according to the eighth embodiment. [Diagram 45] 13 is a cross-sectional view showing another configuration of the semiconductor device according to the ninth embodiment. [Diagram 46] FIG. 23 is a schematic diagram showing the configuration of an electronic device according to a tenth embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0006] [Semiconductor Devices] Fig. 1 is a cross-sectional view showing the configuration of a semiconductor device according to this embodiment. As shown in Fig. 1, a semiconductor device 30 according to this embodiment includes an underlying substrate UK, a first light reflector RF located above the underlying substrate UK, a first mask 6 located above the first light reflector RF, a base semiconductor portion 8 located above the first mask 6, a compound semiconductor portion 9 located above the base semiconductor portion 8, and a second light reflector RS located above the compound semiconductor portion 9 and the first light reflector RF.

[0007] The semiconductor device 30 includes one or more surface-emitting semiconductor laser elements 20 including a base semiconductor portion 8, a compound semiconductor portion 9, a first light reflecting portion RF, and a second light reflecting portion RS. Here, the normal direction of the base substrate UK and the direction from the base substrate UK to the first mask 6 are defined as the upward direction. In the semiconductor device 30, the first mask 6 may be a mask layer 6, the base semiconductor portion 8 may be a base semiconductor layer 8, the compound semiconductor portion 9 may be a compound semiconductor layer 9, the first light reflecting portion RF may be a first light reflecting layer, and the second light reflecting portion RS may be a second light reflecting layer. The first mask 6 may have a mask portion 5 and an opening K. That is, the first mask 6 may be a mask pattern including the mask portion 5 and the opening K.

[0008] A first electrode E1 can be provided on the compound semiconductor portion 9. The first light reflecting portion RF, the base semiconductor portion 8, the compound semiconductor portion 9, the first electrode E1, and the second light reflecting portion RS may overlap with each other in a planar view. Two components overlap with each other in a planar view means that at least a part of one component overlaps with the other component when viewed in the normal direction of the base substrate UK (including perspective viewing).

[0009] In the semiconductor device 30, laser oscillation is possible by light generated in the compound semiconductor portion 9 traveling back and forth between the first and second light reflecting portions RF and RS. In the semiconductor device 30, the first light reflecting portion RF is provided between the base substrate UK and the first mask 6, so that heat dissipation from the first light reflecting portion RF is improved, and the reliability of the surface-emitting semiconductor laser element 20 is enhanced.

[0010] The base semiconductor portion 8 and the compound semiconductor portion 9 may include a nitride semiconductor. The nitride semiconductor may be, for example, Al x Ga y In z N (0≦x≦1; 0≦y≦1; 0≦z≦1; x+y+z=1), and specific examples include GaN-based semiconductors, AlN (aluminum nitride), InAlN (indium aluminum nitride), and InN (indium nitride). A GaN-based semiconductor is a semiconductor that contains gallium atoms (Ga) and nitrogen atoms (N), and typical examples include GaN, AlGaN, AlGaInN, and InGaN. The base semiconductor portion 8 may be of a doped type (e.g., n-type containing a donor). Each of the base semiconductor portion 8 and the compound semiconductor portion 9 may be a nitride semiconductor layer.

[0011] The base semiconductor portion 8 including a nitride semiconductor can be formed by, for example, an ELO (Epitaxial Lateral Overgrowth) method. When the ELO method is used, threading dislocations (defects) in the base semiconductor portion 8 and the compound semiconductor portion 9 on the mask portion 5 are reduced, so that the light emission efficiency (for example, the ratio of the amount of light to the amount of charge injected from the first electrode E1) of the compound semiconductor portion 9 is increased and the amount of heat generated is reduced. This is because threading dislocations are dislocations (defects) that extend from the base semiconductor portion 8 to the compound semiconductor portion 9, and they impede charge transfer and cause heat generation.

[0012] When the base semiconductor portion 8 is formed using the ELO method, a template substrate including an underlying substrate UK, a first light reflecting portion RF, and a mask pattern 6 on the first light reflecting portion RF may be used. The template substrate may have a growth inhibition region (e.g., a region that inhibits crystal growth in the Z direction) corresponding to the mask portion 5, and a seed region corresponding to the opening K. For example, the growth inhibition region and the seed region may be formed in the first light reflecting portion RF, and the base semiconductor portion 8 may be formed on the growth inhibition region and the seed region using the ELO method.

[0013] The first light reflecting portion RF may be an epitaxial DBR (Distributed Bragg Reflector) including a nitride semiconductor. This increases the light reflectance of the first light reflecting portion RF. .

[0014] Fig. 2 is a cross-sectional view showing another configuration of the semiconductor device according to this embodiment. As shown in Fig. 2, the semiconductor device 30 is located on the opposite side of the base substrate UK (above the compound semiconductor portion 9) and can be configured to include a circuit board CB electrically connected to the surface-emitting semiconductor laser element 20.

[0015] [Semiconductor device manufacturing] Fig. 3 is a flow chart showing an example of a method for manufacturing a semiconductor device according to this embodiment. The method for manufacturing a semiconductor device in Fig. 3 includes the steps of preparing a base substrate UK, forming a first light reflecting portion RF, forming a first mask 6, forming a base semiconductor portion 8 by using the ELO method, forming a compound semiconductor portion 9, and forming a second light reflecting portion RS.

[0016] Fig. 4 is a block diagram showing an example of a semiconductor device manufacturing apparatus according to this embodiment. The semiconductor device manufacturing apparatus 70 in Fig. 4 includes a first film formation unit 72 that forms the first light reflecting portion RF, the base semiconductor portion 8, and the compound semiconductor portion 9, a second film formation unit 73 that forms the first mask 6 and the second light reflecting portion RS, and a control unit 74 that controls the first and second film formation units 72 and 73.

[0017] The first film forming section 72 includes an MOCVD (Metal Organic Chemical Vapor Deposition) device. Alternatively, the control unit 74 may include a processor and a memory. The control unit 74 may be configured to control the first and second film forming units 72 and 73 by executing a program stored in, for example, an internal memory, a communication device capable of communication, or an accessible network. The above-mentioned program and a recording medium on which the above-mentioned program is stored are also included in this embodiment.

[0018] Example 1 (Overall composition) FIG. 5 is a cross-sectional view of the semiconductor device according to the first embodiment along the X direction. FIG. 6 is a cross-sectional view of the semiconductor device according to the first embodiment along the Y direction. FIG. 7 is a plan view of the semiconductor device according to the first embodiment. As shown in FIG. 5, FIG. 6, and FIG. 7, the semiconductor device 30 according to the first embodiment includes an undersubstrate UK, a first light reflecting portion RF located on the undersubstrate UK, a seed portion 4 located on the first light reflecting portion RF, a first mask 6 located on the seed portion 4 and including a mask portion 5 and an opening K, a base semiconductor portion 8 located on the first mask 6, a compound semiconductor portion 9 located on the base semiconductor portion 8, an insulating film KF located on the compound semiconductor portion 9, a first electrode E1 located on the compound semiconductor portion 9, a second electrode E2 located on the base semiconductor portion 8, and a second light reflecting portion RS located on the first electrode E1. The base semiconductor portion 8 and the compound semiconductor portion 9 may include a nitride semiconductor (for example, a GaN-based semiconductor). The X direction is the <11-20> direction of the base semiconductor portion 8, the Y direction is the <1-100> direction of the base semiconductor portion 8, and the Z direction is the <11-20> direction of the base semiconductor portion 8. <0001> It is a direction.

[0019] The base semiconductor portion 8 includes a first portion HD and a second portion SD (low defect portion) located on the mask portion 5 and having a threading dislocation density of 1 / 5 or less than that of the first portion HD. 6 / cm 2 or less. The second portion SD overlaps with the compound semiconductor portion 9 in a planar view. The portion of the compound semiconductor portion 9 that overlaps with the second portion SD in a planar view becomes a low-dislocation portion that inherits the low-dislocation property (low defect property) of the base semiconductor portion 8. The first light reflecting portion RF and the second light reflecting portion RS can be configured to overlap with the second portion SD in a planar view. The base semiconductor portion 8 can be configured of an n-type semiconductor (e.g., silicon-doped gallium nitride). For example, when the mask portion 5 contains silicon, the base semiconductor portion 8 can be made into an n-type semiconductor by diffusing a part of the first mask 6 when forming the base semiconductor portion 8 with an unintentional doping.

[0020] 5 and 6, the first electrode E1 is an anode having light-transmitting properties, and the second electrode E2 is a cathode. The first electrode E1 is located above the compound semiconductor portion 9 and overlaps with the second light reflecting portion RF in a planar view. The second electrode E2 is located above the first mask 6 and does not overlap with the second light reflecting portion RS in a planar view. The second electrode E2 is in contact with the base semiconductor portion 8. The compound semiconductor portion 9 is provided on the base semiconductor portion 8, but the compound semiconductor portion 9 is not formed above a portion of the base semiconductor portion 8, and the second electrode E2 is provided so as to be in contact with this portion of the base semiconductor portion 8.

[0021] The semiconductor device 30 includes one or more surface emitting semiconductor laser elements 20 (VCSEL elements: a vertical cavity surface emitting laser element) including a first light reflecting portion RF, a base semiconductor portion 8, a compound semiconductor portion 9, an insulating film KF, first and second electrodes E1·E2, and a second light reflecting portion RS. In the semiconductor laser element 20, light generated in the compound semiconductor 9 by a current between the first and second electrodes E1·E2 oscillates as a laser due to stimulated emission and feedback between the first and second light reflecting portions RF·RS.

[0022] In the semiconductor device 30, the first light reflecting portion RF is provided between the base substrate UK and the first mask 6, which improves heat dissipation from the first light reflecting portion RF and enhances the reliability of the surface-emitting semiconductor laser element 20. In addition, the degree of freedom in designing (materials, structure, etc.) the base substrate UK and the first light reflecting portion RF is increased.

[0023] 8 is a partial enlarged view of the semiconductor device of Example 1. As shown in FIG. 8, the compound semiconductor portion 9 includes, in order from the bottom, an n-type semiconductor layer 9A as a first-type semiconductor layer, an active layer 9K, and a p-type semiconductor layer 9B as a second-type semiconductor layer. The active layer 9K has an MQW (Multi-Quantum Well) structure and includes, for example, at least one of InGaN and GaN. The n-type semiconductor layer 9A is, for example, an n-type AlGaN layer. The p-type semiconductor layer 9B is, for example, a p-type GaN layer. The first electrode E1, which is an anode, is provided so as to be in contact with the p-type semiconductor layer 9B.

[0024] The semiconductor device 30 includes an insulating film KF located on the compound semiconductor portion 9, and the insulating film KF includes an aperture portion AP overlapping with the first electrode E1, the first light reflecting portion RF, the second portion SD, and the second light reflecting portion RS in a plan view. The first electrode E1 is a transparent electrode located between the compound semiconductor portion 9 and the second light reflecting portion RS, and the first electrode E1 is in contact with the upper surface of the insulating film KF. The insulating film KF may be made of SiOx, SiNx, AlOx, or the like.

[0025] In the aperture portion AP, the first electrode E1 and the compound semiconductor portion 9 come into contact. Specifically, the p-type semiconductor layer 9B exposed in the aperture portion AP comes into contact with the center of the first electrode E1. The aperture portion AP is a current confinement portion formed by penetrating the insulating film KF, for example, in a circular shape, and the current path between the first and second electrodes E1 and E2 is constricted on the anode side by the aperture portion AP, thereby improving the light emission efficiency.

[0026] In the first embodiment, the aperture portion AP overlaps with the second light reflecting portion RS, the compound semiconductor portion 9, the second portion SD (low defect portion) of the base semiconductor portion 8, and the first light reflecting portion RF in a plan view. Therefore, a current path from the first electrode E1 in the aperture portion AP through the compound semiconductor portion 9 to the base semiconductor portion 8 is formed in the base semiconductor portion 8 and the low defect portion of the compound semiconductor portion 9. This increases the light emission efficiency in the active layer 9K and suppresses heat generation in the base semiconductor portion 8 and the compound semiconductor portion 9.

[0027] In the semiconductor device 30, a first pad P1 is provided in contact with the first electrode E1, and the first pad P1, the aperture portion AP, and the second electrode E2 are aligned in the Y direction in a plan view. In this way, the second electrode E2 can be formed on the second portion SD (low defect portion) of the base semiconductor portion 8, and the light emission efficiency in the active layer 9K can be improved. The first pad P1 only needs to be in contact with a part of the first electrode E1, but may be shaped so that the first pad P1 is in contact with the periphery of the first electrode E1 (the contact area with the first electrode E1 surrounds the aperture portion AP in a plan view) in order to inject a current more uniformly into the aperture portion AP. The first pad P1 may be circular.

[0028] FIG. 9 is a partial enlarged view of the semiconductor device of Example 1. The first light reflecting portion RF is located on the base substrate UK and can be an epitaxial DBR including a nitride semiconductor. In this case, as shown in FIG. 9, the first light reflecting portion RF has a plurality of pairs PF including a first refraction portion R1 and a second refraction portion R2 having a larger optical refractive index than the first refraction portion R1. The second refraction portion R2 includes a GaN-based semiconductor, and the first refraction portion R1 may include a refractive material (e.g., a nitride semiconductor) having a smaller optical refractive index than the GaN-based semiconductor of the second refraction portion R2. In FIG. 6, a seed portion 4 is provided between the first light reflecting portion RF and the first mask 6. Specifically, the upper surface of the first light reflecting portion RF is included in the first refraction portion R1, and the seed portion 4 including, for example, a GaN-based semiconductor is formed on the first light reflecting portion RF, and the first mask 6 is formed on the seed portion 4. The base semiconductor portion 8 located on the first mask 6 may have a larger optical refractive index than the mask portion 5. The seed portion 4 may have a larger optical refractive index than the mask portion 5 and the first refraction portion R1.

[0029] By forming the first light reflecting portion RF as an epitaxial DBR including a nitride semiconductor, the light reflectance of the first light reflecting portion RF can be increased, and the manufacturing process can be simplified. In addition, the stress (tensile stress at room temperature) of the base semiconductor portion 8 is alleviated.

[0030] The second light reflecting portion RS is located on the first electrode E1 and may be a dielectric DBR including a dielectric. In this case, as shown in Fig. 8, the second light reflecting portion RS has a plurality of pairs PS including a third refraction portion R3 and a fourth refraction portion R4 having a larger optical refractive index than the third refraction portion R3, and each of the third refraction portion R3 and the fourth refraction portion R4 includes a dielectric material.

[0031] The lower surface of the second light reflecting portion RS may be included in the third refraction portion R3, and the upper surface of the second light reflecting portion RS may be included in the fourth refraction portion R4. The third refraction portion R3 may have a smaller optical refractive index than the p-type semiconductor layer 9B. This can increase the optical reflectance of the second light reflecting portion RS. Furthermore, by providing the second light reflecting portion RS in an island shape on the first electrode E1, heat dissipation is improved.

[0032] 5 and 6, the semiconductor device 30 of the first embodiment includes a gap TK in contact with the side surface of the base semiconductor portion 8, the side surface of the compound semiconductor portion 9, and the side surface of the second light reflecting portion RS, and the gap TK overlaps with the center 5C of the mask portion 5 in a plan view. The side surfaces of the base semiconductor portion 8 and the compound semiconductor portion 9 may each be the a-plane or m-plane of a GaN-based semiconductor. Providing the gap TK improves heat dissipation and also relieves stress in the base semiconductor portion 8.

[0033] Fig. 10 is a cross-sectional view showing an example of the configuration of the base substrate. As shown in Fig. 10, the base substrate UK may be composed of a main substrate 1. In this case, for example, a SiC substrate (6H-SiC bulk crystal), a GaN substrate (bulk crystal), or an AlN substrate (bulk crystal) can be used as the main substrate 1. The base substrate UK may also include the main substrate 1 and a base portion 3 located above the main substrate 1. In this case, for example, a SiC substrate may be used for the main substrate 1 and a nitride semiconductor (for example, a GaN-based semiconductor) may be used for the base portion 3, an AlN substrate may be used for the main substrate 1 and a nitride semiconductor (for example, a GaN-based semiconductor) may be used for the base portion 3, a Si substrate (bulk crystal) may be used for the main substrate 1 and aluminum nitride (AlN) or silicon carbide (SiC) may be used for the base portion 3, or a GaN substrate (bulk crystal) may be used for the main substrate 1 and GaN may be used for the base portion 3. Furthermore, the base substrate UK may include a main substrate 1, a buffer portion 2 located above the main substrate 1, and a base portion 3 located above the buffer portion 2. In this case, for example, a SiC substrate or a Si substrate may be used for the main substrate 1, at least one of AlN (aluminum nitride) and SiC (silicon carbide) may be used for the buffer portion 2, and a nitride semiconductor (e.g., a GaN-based semiconductor) may be used for the base portion 3.

[0034] 11 to 13 are cross-sectional views showing another example of the configuration around the first light reflecting portion. In FIG. 11, the upper surface of the first light reflecting portion RF is included in the second refraction portion R2, and the first mask 6 is formed on the first light reflecting portion RF. In this case, the uppermost second refraction portion R2 functions as a seed when the base semiconductor portion 8 grows laterally, and the base semiconductor portion 8 contacts the upper surface of the first light reflecting portion RF at the opening K of the first mask 6. In FIG. 12, the uppermost first refraction portion R1 may be included in the first refraction portion R1, and the first mask 6 may be formed on the first light reflecting portion RF. In this case, the uppermost first refraction portion R1 including, for example, a nitride semiconductor functions as a seed when the base semiconductor portion 8 grows laterally, and the base semiconductor portion 8 contacts the upper surface of the first light reflecting portion RF at the opening K of the first mask 6. In FIG. 13, a seed portion 4 is provided between the first light reflecting portion RF and the first mask 6. Specifically, the upper surface of the first light reflecting portion RF is included in the second refraction portion R2, a seed portion 4 including, for example, a nitride semiconductor is formed on the first light reflecting portion RF, and a first mask 6 is formed on the seed portion 4. In addition, by using the same material (for example, a GaN-based semiconductor) for the top layer or seed portion 4 of the first light reflecting portion RF and the base semiconductor portion 8, the manufacturing process can be simplified.

[0035] (Manufacturing method) Fig. 14 is a flowchart showing an example of a method for manufacturing a semiconductor device according to Example 1. Fig. 15 is a cross-sectional view showing steps of an example of a method for manufacturing a semiconductor device according to Example 1. As shown in Figs. 14 and 15, the method for manufacturing a semiconductor device includes the steps of preparing a base substrate UK, forming a first light reflecting portion RF, forming a seed portion 4, forming a first mask 6, forming a base semiconductor portion 8 by an ELO method, forming a compound semiconductor portion 9, forming an insulating film KF (current confinement layer), forming first and second electrodes E1 and E2, and forming a second light reflecting portion RS.

[0036] (Base substrate) The main substrate 1 of the base substrate UK may be a heterogeneous substrate having a lattice constant different from that of the base semiconductor portion including, for example, a GaN-based semiconductor. Examples of heterogeneous substrates include single crystal silicon (Si) substrates, sapphire (Al2O3) substrates, silicon carbide (SiC) substrates, and aluminum nitride (AlN) substrates. The surface orientation of the main substrate 1 may be, for example, the (111) surface of a silicon substrate, the (0001) surface of a sapphire substrate, or the 6H-SiC (0001) surface of a SiC substrate.

[0037] The main substrate 1 may have a higher thermal conductivity than a GaN bulk substrate. From the viewpoint of having better thermal conductivity and light transmissivity than a GaN substrate, a SiC substrate may be used for the main substrate 1. A GaN substrate (bulk crystal) may also be used for the main substrate 1 (see FIG. 10).

[0038] In the base substrate UK, for example, as shown in FIG. 10, a base portion (base layer) 3 may be provided on a main substrate 1, or a buffer portion 2 (buffer layer) and base portion 3 may be provided on a main substrate 1. When a silicon substrate is used, the base portion 3 or buffer portion 2 including an AlN layer may be provided to prevent the phenomenon in which the silicon substrate and the GaN-based semiconductor melt together at high temperatures. The AlN layer can be formed to a thickness of about 10 nm to about 5 μm using, for example, an MOCVD apparatus. When a silicon substrate is used, the base portion 3 or buffer portion 2 including a SiC layer may also be provided from the viewpoint of excellent thermal conductivity.

[0039] In the case where the main substrate 1 and the base portion 3 do not melt together, it is not necessary to provide the buffer portion 2. In the first embodiment, the main substrate 1 is a SiC substrate, and a GaN layer serving as the base portion 3 is formed on the main substrate 1 by the MOCVD method to have a thickness of 1.0 μm.

[0040] At least one of the buffer portion 2 (e.g., aluminum nitride) and the base portion 3 (e.g., GaN-based semiconductor) can be formed using a sputtering device (PSD: pulse sputter deposition, PLD: pulse laser deposition, etc.). By forming the film using a sputtering device, the efficiency of the manufacturing process can be improved.

[0041] When base semiconductor portion 8 is grown laterally using the ELO method, even if a base with poor crystallinity is used, the low crystallinity is carried over to above opening K (first portion HD) and not to second portion SD that overlaps aperture portion AP and the light emitting region of active layer 9K in plan view (therefore, second portion SD is a low defect portion). Therefore, it is possible to reduce costs while maintaining light emitting characteristics.

[0042] The base portion 3 may have at least one of the effects of preventing the main substrate 1 and the first light reflecting portion RF from melting, the effect of enhancing the crystallinity of the first light reflecting portion RF, the effect of reducing internal stress in the base semiconductor portion 8 (reducing warpage of the semiconductor device 30), and the effect of enhancing heat dissipation. Also, the buffer portion 2 may have at least one of the effects of preventing the main substrate 1 and the base portion 3 from melting, the effect of enhancing the crystallinity of the base portion 3, the effect of reducing internal stress in the base semiconductor portion 8, and the effect of enhancing heat dissipation.

[0043] A GaN substrate (bulk crystal) may also be used for the main substrate 1. In this case, the first light reflecting portion RF (epitaxial DBR) may be formed (directly) on the main substrate 1, or the first light reflecting portion RF (epitaxial DBR) may be formed on the main substrate 1 via an undercoat portion 3 (e.g., a GaN layer). By using a GaN substrate for the main substrate 1, threading dislocations in the first light reflecting portion RF are reduced, and threading dislocations above the opening K in the base semiconductor portion 8 can be reduced.

[0044] Alternatively, a base substrate having a GaN-based semiconductor layer of the (11-22) plane formed on a sapphire substrate, or a base substrate having a GaN-based semiconductor layer of the (20-21) plane formed on a sapphire substrate may be used. Since the semiconductor layer epitaxially formed on these semi-polar base substrates has high crystallinity, these base substrates can also be used in Example 1.

[0045] (1st light reflection section) As shown in FIG. 9, by stacking 20 to 40 pairs of AlN in the first refraction portion R1 and GaN in the second refraction portion R2, an epitaxial DBR with high reflectivity (96% or more) and high thermal conductivity can be formed. In this case, threading dislocations due to lattice mismatch between the main substrate 1, the first refraction portion R1, and the second refraction portion R2 may occur. However, the threading dislocations (defects extending in the Z direction) in the first light reflecting portion RF are stopped by the first mask 6, and are not inherited by the second portion SD of the base semiconductor portion 8 and the compound semiconductor portion 9 thereon (particularly the portion overlapping with the aperture portion AP). This increases the degree of freedom in designing the base substrate UK and the first light reflecting portion RF, and enables design taking into account heat dissipation, crystal quality, power consumption, manufacturing costs, and the like.

[0046] By making the first light reflecting portion RF an epitaxial DBR of AlN (first refraction portion) / GaN (second refraction portion), the thermal conductivity of the first light reflecting portion RF can be increased. In addition, the first mask 6 can reduce stress propagation from the first light reflecting portion RF to the base semiconductor portion 8 and the compound semiconductor portion 9. Of course, the first light reflecting portion RF can also be an epitaxial DBR of a lattice matching system such as AlInN (first refraction portion) / GaN (second refraction portion).

[0047] The epitaxial DBR may be formed by MOCVD, or may be formed by RPCVD (remote plasma chemical vapor deposition) or PSD (pulse sputter deposition), which are capable of low-temperature film formation. This reduces the temperature difference during and after film formation, making it possible to suppress cracks caused by the difference in thermal expansion coefficient between the main substrate 1 and the epitaxial DBR. Alternatively, the epitaxial DBR may be formed by a sputtering method capable of forming a film at a low temperature, and the seed portion 4 may be formed by an MOCVD method.

[0048] In Example 1, 6H- An undoped GaN layer was formed to a thickness of approximately 2 μm on a SiC (0001) substrate as the base portion 3, and 30 pairs of AlN (first refraction portion) / GaN (second refraction portion) were stacked on the base portion 3 at a growth temperature of 1040°C and a growth pressure of 50 Torr to form an epitaxial DBR. The design peak wavelength of the DBR was 400 nm, and the optical film thickness of the AlN in each pair was λ / 4. This enabled the first light reflecting portion RF to have a high light reflectance of approximately 98%.

[0049] As shown in Fig. 9, the uppermost part of the first light reflecting part RF may be a first refraction part (AlN) and a seed part 4 including a GaN-based semiconductor may be provided thereon, or the uppermost part of the first light reflecting part RF may be a second refraction part (GaN) as shown in Fig. 11. By making the layer in contact with the lower surface of the first mask 6 a GaN-based semiconductor layer, it is possible to reduce the possibility of occurrence of a phenomenon in which the semiconductor layer in contact with the lower surface of the first mask 6 re-evaporates due to a temperature rise when growing the base semiconductor part 8 after the formation of the first mask 6.

[0050] The refractive material of the first refraction portion R1 may be AlN, AlInN, or InN. The refractive material of the first refraction portion R1 (e.g., AlN) may have a higher thermal conductivity than the GaN-based semiconductor of the second refraction portion R2 (e.g., GaN). The refractive material of the first refraction portion R1 may have a different lattice constant from the GaN-based semiconductor of the second refraction portion R2. The refractive material of the first refraction portion R1 (e.g., AlN) may have a smaller lattice constant than the GaN-based semiconductor of the second refraction portion R2 (e.g., GaN). Regarding the thermal expansion coefficient, the main material of the main substrate 1 (e.g., SiC, Si) < the GaN-based semiconductor of the second refraction portion R2 (e.g., GaN) < the refractive material of the first refraction portion R1 (e.g., AlN).

[0051] (First mask) The opening K of the first mask 6 exposes the nitride semiconductor functioning as a seed and functions as a growth start hole for starting the growth of the base semiconductor portion 8, and the mask portion 5 functions as a selective growth mask for growing the base semiconductor portion 8 laterally. The mask portion 5 may be, for example, a silicon oxide film (SiO x ), titanium nitride film (TiN, etc.), silicon nitride film (SiN x A single layer film including any one of a silicon oxynitride film (SiON) and a metal film having a high melting point (for example, 1000° C. or higher), or a laminated film including at least two of these can be used.

[0052] For example, a silicon oxide film having a thickness of about 10 nm to about 500 nm is formed over the entire surface by sputtering, and a resist is applied over the entire surface of the silicon oxide film. After that, the resist is patterned by photolithography to form a resist having a plurality of stripe-shaped openings. After that, a portion of the silicon oxide film is removed by a wet etchant such as hydrofluoric acid (HF) or buffered hydrofluoric acid (BHF) to form a plurality of openings K, and the resist is removed by organic cleaning to form the first mask 6. The openings K may be formed by using a general lift-off method.

[0053] The openings K are elongated (slit-shaped) and are periodically arranged in the a-axis direction (X-direction) of the base semiconductor portion 8. The width (opening width) of the openings K can be about 0.1 μm to 20 μm (for example, about 5 μm). The smaller the width of each opening, the smaller the number of threading dislocations propagating from each opening to the base semiconductor portion 8. Also, the second portion (low defect portion) SD can be made larger. Regarding the thickness of the mask portion 5, it is preferable that it is thin from the viewpoint of heat dissipation, but it can be set to 10 nm or more, 20 nm or more, or 40 nm or more in consideration of suppressing mutual reaction between the first mask 6 and the base semiconductor portion 8.

[0054] The width of the mask portion 5 can be set to 10 μm to 200 μm. By increasing the width of the mask portion 5, it is possible to increase the area (effective area) of the second portion SD (low defect portion) of the base semiconductor portion 8. This allows the aperture diameter (diameter of the aperture portion AP) to be increased, thereby achieving a high-output semiconductor laser device.

[0055] A silicon oxide film may decompose and evaporate in small amounts during the formation of the base semiconductor portion 8 and become incorporated into the base semiconductor portion 8, but a silicon nitride film and a silicon oxynitride film have the advantage of being less susceptible to decomposition and evaporation at high temperatures.

[0056] Therefore, the first mask 6 may be a single layer film of a silicon nitride film or a silicon oxynitride film, or may be a laminate film in which a silicon oxide film and a silicon nitride film are formed in this order, or may be a laminate film in which a silicon nitride film and a silicon oxide film are formed in this order, or may be a laminate film in which a silicon nitride film, a silicon oxide film and a silicon nitride film are formed in this order.

[0057] Pinholes and other abnormalities in the mask portion 5 can be eliminated by performing organic cleaning after film formation, and then introducing the mask into the film formation device again to form a film of the same type. A good quality first mask 6 can also be formed by using a general silicon oxide film (single layer) and using such a film formation method again.

[0058] The mask portion 5 may have a smaller optical refractive index than the second refraction portion R2 (e.g., a GaN-based semiconductor). In the first embodiment, since the first mask 6 exists inside the cavity, the first mask 6 can be designed so as to hinder the resonance of light as little as possible. Since the mask portion 5 is a selectively grown film and also a light-transmitting film, it may have high optical transmission characteristics (low optical absorption). When the top part (second refraction portion R2) or the seed portion 4 of the first light reflecting portion RF is a GaN layer, and a single layer of a silicon oxide film or a silicon nitride film, which has a lower refractive index than GaN, is used as the mask material, the optical thickness (physical thickness / refractive index) of the silicon oxide film or the silicon nitride film is defined as λ( By making the wavelength an integer multiple of (lasing wavelength) / 2, the reflectance at the first light reflecting portion RF can be increased. Furthermore, a mask material made of a plurality of film types, each having an optical thickness of an integer multiple of λ / 2, may be used. For example, when the top (second refraction portion R2) of the first light reflecting portion RF or the seed portion 4 is a GaN layer, a silicon oxide film and a silicon nitride film having a higher refractive index than the silicon oxide film may be formed on the GaN layer in this order, both with an optical thickness of λ / 4. By adopting such a pair of a silicon oxide film with an optical thickness of λ / 4 and a silicon nitride film with an optical thickness of λ / 4 as the first mask, the light reflectance can be further increased. Conversely, a design in which the reflectance of the first light reflecting portion RF is reduced by the first mask 6 is also possible.

[0059] (Base semiconductor part) In Example 1, the base semiconductor portion 8 (ELO semiconductor layer) was a GaN layer, and an MOCVD apparatus was used to perform ELO deposition of gallium nitride (GaN) on the above-mentioned template substrate. As an example of ELO deposition conditions, the following can be adopted: substrate temperature: 1120°C, growth pressure: 50 kPa, TMG (trimethylgallium): 22 sccm, NH3: 15 slm, V / III=6000 (ratio of the amount of Group V raw material supplied to the amount of Group III raw material supplied).

[0060] In this case, the base semiconductor portion 8 is selectively grown (vertical growth) on the seed portion 3 (e.g., a GaN layer) exposed in the opening portion K, and then grows laterally on the mask portion 5. Then, before the base semiconductor portions 8 growing laterally on both sides of the mask portion 5 meet, the lateral growth is stopped.

[0061] A single silicon nitride film was used for the mask portion 5, and the optical thickness of the mask portion 5 was set to λ / 4 assuming an emission wavelength of 450 nm. The width of the mask portion 5 was 50 μm, the width of the opening K was 5 μm, the width of the gap TK was 3 μm, the horizontal width of the base semiconductor portion 8 was 52 μm, the width of the low defect portion (size in the X direction) was 23.5 μm, and the layer thickness of the base semiconductor portion 8 was 5 μm. The aspect ratio of the base semiconductor portion 8 was 52 μm / 5 μm=10.4, which is a very high aspect ratio. The width (effective width) of the low defect portion SD may be 10 μm or more, or 20 μm or more.

[0062] In the formation of the base semiconductor portion 8 in Example 1, the lateral film formation rate is increased. The method for increasing the lateral film formation rate is as follows. First, a vertically grown layer growing in the Z direction (c-axis direction) is formed on the seed portion 3 exposed from the opening K, and then a laterally grown layer growing in the X direction (a-axis direction) is formed. At this time, by setting the thickness of the vertically grown layer to 10 μm or less, preferably 5 μm or less, and more preferably 3 μm or less, the thickness of the laterally grown layer can be kept low and the lateral film formation rate can be increased.

[0063] Fig. 16 is a cross-sectional view showing an example of lateral growth of the base semiconductor portion 8. As shown in Fig. 16, an initial growth layer SL is formed on the seed portion 3, and then the base semiconductor portion 8 can be grown laterally from the initial growth layer SL. The initial growth layer SL serves as a starting point for the lateral growth of the base semiconductor portion 8. By appropriately controlling the ELO film formation conditions, it is possible to control the base semiconductor portion 8 to grow in the Z direction (c-axis direction) or the X direction (a-axis direction).

[0064] Here, deposition of the initial growth layer SL may be stopped just before the edge of the initial growth layer SL rises onto the upper surface of the mask portion 5 (at the stage where it is in contact with the upper end of the side surface of the mask portion 5) or just after it rises onto the upper surface of the mask portion 5 (i.e., at this timing, the ELO deposition conditions may be switched from the c-axis direction deposition conditions to the a-axis direction deposition conditions). In this way, lateral deposition is performed from a state in which the initial growth layer SL slightly protrudes from the mask portion 5, so that consumption of material in the growth of the base semiconductor portion 8 in the thickness direction can be reduced, and the base semiconductor portion 8 can be grown laterally at high speed. The initial growth layer SL may be formed to a thickness of, for example, 2.0 μm or more and 3.0 μm or less.

[0065] The deposition temperature of the base semiconductor portion 8 (ELO semiconductor portion) may be high, exceeding 1200°C, but may be 1150°C or lower. The ELO semiconductor portion can also be formed at a low temperature below 1000°C, which is preferable from the viewpoint of reducing mutual reactions. In such low-temperature deposition, it was found that if trimethylgallium (TMG) is used as the gallium source, the source is not sufficiently decomposed, and gallium atoms and carbon atoms are simultaneously incorporated into the ELO semiconductor portion in greater amounts than usual. This is thought to be because, in the ELO method, deposition in the a-axis direction is fast and deposition in the c-axis direction is slow, so that more is incorporated during deposition on the c-plane.

[0066] It was also found that carbon incorporated into the ELO semiconductor portion reduces reaction with the mask portion 5 and reduces adhesion between the mask portion 5 and the ELO semiconductor portion (base semiconductor portion 8). Therefore, in low-temperature deposition of the ELO semiconductor portion, the amount of ammonia supplied is reduced and deposition is performed at a low V / III ratio (<1000), so that carbon elements in the raw material or chamber atmosphere can be incorporated into the ELO semiconductor portion and reaction with the mask portion 5 can be reduced. In this case, the base semiconductor portion 8 is configured to contain carbon.

[0067] Fig. 17 is a plan view showing another configuration of the semiconductor device of Example 1. In Fig. 16, the lateral growth of the base semiconductor portions 8 growing laterally from both sides of the mask portion 5 is stopped before they meet, but this is not limited to the above. As shown in Fig. 17, the lateral growth of the base semiconductor portions 8 growing laterally from both sides of the mask portion 5 may be stopped after they meet. In this case, the base semiconductor portion 8 contains a void VD that overlaps with the center of the mask portion 5 in a plan view, and dislocations (crystal defects) at the meeting portion increase, so that the aperture portion AP of the semiconductor laser element 20 is configured not to overlap with the meeting portion in a plan view.

[0068] (Compound Semiconductor Division) The base semiconductor portion 8 and the compound semiconductor portion 9 may be formed consecutively in the same apparatus (for example, an MOCVD apparatus), or the substrate may be removed from the apparatus once after the base semiconductor portion 8 is formed, and the surface of the base semiconductor portion 8 may be polished before the compound semiconductor portion 9 is formed. In this case, the compound semiconductor portion 9 may be formed after an n-type GaN-based semiconductor layer (for example, with a thickness of about 0.1 μm to about 3 μm) that serves as a buffer during regrowth is formed on the base semiconductor portion 8. In addition to the MOCVD apparatus, a sputtering apparatus, a remote plasma CVD apparatus (RPCVD), a PSD (Pulse Sputter Deposition) apparatus, etc. may be used to form the compound semiconductor portion 9. Remote plasma CVD equipment and PSD equipment do not use hydrogen as a carrier gas, making it possible to form low-resistance p-type GaN-based semiconductor parts.

[0069] The MQW structure of the active layer 9K may be, for example, a 5-6 period structure of InGaN / GaN. The In composition varies depending on the target emission wavelength, and may be about 15-20% In concentration for blue (near 450 nm) and about 30% In concentration for green (near 530 nm). If necessary, an electron blocking layer (for example, an AlGaN layer) may be formed on the active layer 9K. In addition, in order to reduce resistance, the surface (about 10 nm) of the p-type semiconductor layer 9B may be a highly doped p-type layer.

[0070] FIG. 18 is a cross-sectional view showing another configuration of the semiconductor device of the first embodiment. In FIG. 8, the aperture portion AP is provided in the insulating film KF, but the present invention is not limited to this. As shown in FIG. 18, a ring-shaped high resistance portion HR (a region with a low p-type doping concentration) may be provided in the p-type semiconductor layer 9B, and the inside of the high resistance portion HR may be the aperture portion AP (current confinement portion) (the high resistance portion HR surrounds the aperture portion AP). The aperture portion AP may also be formed by implanting Al (aluminum) and Fe (iron). In addition, in order to give the aperture portion AP a light confinement effect due to the refractive index difference, the periphery of the aperture may be dug to generate a refractive index difference between the aperture portion AP and its surroundings (for example, the refractive index of the surroundings may be made smaller than that of the aperture portion AP).

[0071] (First and second electrodes) The first electrode E1 is made of a transparent conductive material having optical transparency, such as indium tin oxide (including crystalline ITO, amorphous ITO, and Sn-doped In2O3), indium zinc oxide (IZO), IFO (F-doped In2O3), tin oxide (including SnO2, Sb-doped SnO2, and F-doped SnO2), and zinc oxide (including ZnO, Al-doped ZnO, and B-doped ZnO).

[0072] The first electrode E1 may include at least one of Ga (gallium) oxide, Ti (titanium) oxide, Nb (niobium) oxide, and Ni (nickel) oxide as a base layer. The aperture diameter of the first electrode E1 (the diameter of the current injection region in contact with the p-type semiconductor portion) may be, for example, 2 μm or more and 100 μm or less.

[0073] The first pad P1 in contact with the first electrode E1 may have a single-layer structure or a multi-layer structure containing at least one of Au, Ag, Pd, Pt, Ni, Ti, V, W, Cr, Al, Cu, Zn, Sn, and In. For the multi-layer structure, for example, with the left side as the lower layer, a configuration such as Ti layer / Au layer, Ti layer / Al layer, Ti layer / Al layer / Au layer, Ti layer / Pt layer / Au layer, Ni layer / Au layer, Ni layer / Au layer / Pt layer, Ni layer / Pt layer, Pd layer / Pt layer, Ag layer / Pd layer, etc. can be adopted.

[0074] (Second light reflection section) The second light reflecting portion RS is, for example, a DBR in which the third refraction portion R3 and the fourth refraction portion R4 are alternately stacked as shown in FIG. 8. The third refraction portion R3 includes, for example, SiO2. The fourth refraction portion R4 is a layer including a material having a higher refractive index than the third refraction portion R3, and includes, for example, Ta2O5, HfO2, ZrO2, TiO2, Al2O3, Nb2O5, ZnO, AlN, SiN, or MgO. Light incident on the interface between the third refraction portion R3 and the fourth refraction portion R4 at an angle equal to or greater than the critical angle is totally reflected at this interface, and thus the second light reflecting portion RS achieves a high light reflectance (for example, 96% or more).

[0075] In FIG. 5, when the main substrate 1 is light-transmitting, the second light reflecting portion RS may have a reflectance of approximately 100%, for example, about 99%, for the emission wavelength of the active layer 9K, and the first light reflecting portion RF may have a reflectance lower than that of the second light reflecting portion RS, for example, about 98%. In this case, the light traveling back and forth between the first light reflecting portion RF and the second light reflecting portion RS is emitted as a laser beam from the lower surface of the first light reflecting portion RF (the portion overlapping with the aperture portion AP in a plan view). Note that the configuration is not limited to one in which the laser beam is emitted from the first light reflecting portion RF side. When the main substrate 1 is not light-transmitting, the laser beam may be emitted from the second light reflecting portion RS side, or may be emitted from each of the first and second light reflecting portions RF and RS.

[0076] (singularization) Fig. 19 is a plan view showing another configuration of the semiconductor device of Example 1. As shown in Fig. 19, the semiconductor device 30 of Fig. 7 may be divided into individual semiconductor devices 30, each of which includes one semiconductor laser element 20.

[0077] (Modification) Fig. 20 is a cross-sectional view showing another configuration of the semiconductor device according to the first embodiment. As shown in Fig. 20, the semiconductor device 30 includes a circuit board CB disposed on the opposite side of the main substrate 1 and electrically connected to the first and second electrodes E1 and E2. Specifically, the first electrode E1 is connected to the circuit board via the first pad P1 and the conductive adhesive A1, and the second electrode E2 is connected to the circuit board CB via the conductive adhesive A2. The circuit board CB may be configured to drive the semiconductor laser element 20.

[0078] 21 and 22 are cross-sectional views showing another configuration of the semiconductor device according to the first embodiment. The semiconductor device 30 shown in FIG. 21 includes a first pad P1 in contact with the first electrode E1 and a second pad P2 in contact with the second electrode E2, and the upper surface levels (height positions) of the first and second pads P1 and P2 are the same, and the upper surfaces of the first and second pads P1 and P2 are located higher than the upper surface of the second light reflecting portion RS. This makes it easy to mount the semiconductor device on the circuit board CB (see FIG. 22). An insulating film DF can be provided between the periphery of the second electrode E2 and the base semiconductor portion 8. By providing the insulating film DF, it is possible to prevent a short circuit between the second electrode E2 and the upper surface (p-type semiconductor layer) of the compound semiconductor portion 9, and the possibility that holes injected from the first electrode E1 into the p-type semiconductor layer will move to the second electrode E2 without passing through the active layer is reduced. The second electrode E2 may have a shape in which the non-peripheral portion EH is recessed from the peripheral portion, and the recessed non-peripheral portion EH may be filled with an insulator DL. The insulator DL ​​can flatten the upper surface of the second pad P2. Also, by bringing the first pad P1 into contact with the upper surface of the second light reflecting portion RS, heat dissipation can be improved.

[0079] 23 and 24 are cross-sectional views showing another configuration of the semiconductor device according to the first embodiment. In FIG. 5 and the like, the seed portion 4 is formed entirely on the first light reflecting portion RF, but this is not limiting. As shown in FIG. 23 and FIG. 24, the seed portion 4 may be provided locally so as to overlap with the opening K of the first mask 6. In FIG. 23, the top of the first light reflecting portion RF is the second refraction portion R2, and in FIG. 24, the top of the first light reflecting portion RF is the first refraction portion R1. This can reduce stress from the seed portion 4. The seed portion 4 may be formed at a low temperature of 800° C. or less.

[0080] 25 and 26 are cross-sectional views showing another configuration of the semiconductor device according to the first embodiment. In FIG. 6, the second electrode E2 is in contact with the base semiconductor portion 8, but this is not limited thereto. As shown in FIG. 25, the second electrode E2 may be in contact with the seed portion 4. In this case, the seed portion 4 may be, for example, an n-type GaN-based semiconductor layer. Also, as shown in FIG. 26, the second electrode E2 may be in contact with the top portion of the first light reflecting portion RF (for example, the second refraction portion R2). In this case, the top portion of the first light reflecting portion RF may be, for example, an n-type GaN-based semiconductor layer.

[0081] Fig. 27 is a plan view showing another configuration of the semiconductor device in accordance with the first embodiment. As shown in Fig. 27, the first and second electrodes E1 and E2 may be arranged in the X direction, and the second electrode E2 may overlap the first portion HD in plan view. Note that the first electrode E1 and the aperture portion AP overlap the second portion SD in plan view.

[0082] Fig. 28 is a plan view showing another configuration of the semiconductor device in accordance with Example 1. The semiconductor device 30 in Fig. 28 has a first region L1 and a second region L2 of the same area that are adjacent to each other in the X direction with a gap TK therebetween, and the shape of the semiconductor laser element 20 differs between the two regions L1 and L2.

[0083] Specifically, in the first region L1, two semiconductor laser elements 20 are aligned in the Y direction, and in the second region L2, six semiconductor laser elements 20 are aligned in the Y direction. The aperture diameter of the semiconductor laser element 20 in the first region L1 is larger than the aperture diameter of the semiconductor laser element 20 in the second region L2.

[0084] In the semiconductor laser element 20 in the first region L1, in a plan view, the aperture portion AP and the first pad P1 are aligned in the Y direction, which is the longitudinal direction, and the second electrode E2 in contact with the base semiconductor portion 8 and the first pad P1 are aligned in the X direction. In the semiconductor laser element 20 in the second region L2, the aperture portion AP and the first pad P1 are aligned in the X direction, which is the longitudinal direction, and the aperture portion AP is located between the second electrode E2 in contact with the base semiconductor portion 8 and the first pad P1.

[0085] Fig. 29 and Fig. 30 are schematic plan views showing another configuration of the semiconductor device in accordance with Example 1. The semiconductor device 30 in Fig. 29 is obtained by mounting a plurality of the semiconductor devices shown in Fig. 19 on a circuit board CB. The semiconductor device 30 in Fig. 30 is obtained by dividing the semiconductor device 30 in Fig. 28 into regions and mounting a plurality of semiconductor devices obtained from the second region L2 on the circuit board CB.

[0086] Example 2 Fig. 31 is a cross-sectional view showing the configuration of a semiconductor device according to Example 2. A semiconductor device 30 of Example 2 includes an underlying substrate UK as shown in Fig. 10, for example, where a first light reflecting portion RF is located on the underlying substrate UK, and the underlying substrate UK has a recess UT opening on its upper surface.

[0087] 32 to 35 are cross-sectional views showing the configuration of the base substrate according to Example 2. In Example 2, as shown in FIG. 32, the main substrate 1 may have a recessed portion corresponding to the recess UT. As shown in FIG. 33, the base substrate UK may include a base portion 3 located above the main substrate 1, and the base portion 3 may be penetrated at a portion corresponding to the recess UT. As shown in FIG. 34, the base substrate UK may include a buffer portion 2 and a base portion 3 located above the main substrate 1, and the base portion 3 may have a recessed portion corresponding to the recess UT. As shown in FIG. 35, the base substrate UK may include a buffer portion 2 and a base portion 3 located above the main substrate 1, and the main substrate 1 may have a recessed portion corresponding to the recess UT, and the buffer portion 2 and the base portion 3 may be penetrated at a portion corresponding to the recess UT. The recess UT is formed in a stripe shape extending in the Y direction, and the width of the recess UT (size in the X direction) is, for example, 3 μm, and the depth of the recess UT (size in the Z direction) is, for example, 5 μm.

[0088] 31, the second light reflecting portion RS does not overlap with the recess UT in a planar view. The first and second refraction portions R1 and R2 of the first light reflecting portion RF have a U-shaped portion UC along the recess UT, and the U-shaped portion UC overlaps with the center of the mask portion 5 in a planar view. The semiconductor device 30 of the second embodiment has a gap TK that contacts the side surfaces of the compound semiconductor portion 9 and the base semiconductor portion 8, and the gap TK overlaps with the recess UT in a planar view.

[0089] The gap TK contacts the side surface 5S of the mask portion 5 and the side surface 4S of the seed portion 4, and the U-shaped portion UC (of the second refraction portion R2) located at the top of the first light reflecting portion RF contacts the gap TK. Note that the U-shaped portion UC (of the first refraction portion R1) located at the top of the first light reflecting portion RF may be configured to contact the gap TK. By providing a recess UT in the base substrate UK and providing a U-shaped portion in the first light reflecting portion RF, which is an epitaxial DBR, the stress of the first light reflecting portion RF is alleviated and the occurrence of cracks is reduced. In addition, the heat dissipation from the first light reflecting portion RF is also improved.

[0090] Example 3 FIG. 36 is a cross-sectional view showing the configuration of a semiconductor device according to Example 3. FIG. 37 is a cross-sectional view showing the configuration of a semiconductor device according to Example 3. In the semiconductor devices of FIG. 36 and FIG. 37, a second electrode E2 is provided on the back surface of the base substrate UK. For example, the base substrate UK can be a main substrate 1 (e.g., a SiC substrate, a Si substrate) that is n-type doped. When the base substrate UK is provided with the base portion 3, the base portion 3 is an n-type semiconductor layer (e.g., a GaN-based semiconductor), and when the buffer portion 2 and the base portion 3 are provided with the base substrate UK, they are n-type semiconductor layers (e.g., a nitride semiconductor). Each epitaxial layer (e.g., a nitride semiconductor) and the seed portion 4 (e.g., a GaN-based semiconductor) of the first light reflecting portion RF are also n-type semiconductor layers.

[0091] Example 4 FIG. 38 is a flow chart showing an example of a method for manufacturing a semiconductor device according to Example 4. FIGS. 39 to 40 are cross-sectional views showing a configuration of a semiconductor device according to Example 4. In Example 4, a base substrate UK has a main substrate 1 and a second mask MS located above the main substrate 1. In FIG. 38, after a step of preparing the main substrate 1, a step of forming a second mask MS and a step of forming an underlying portion 3 by the ELO method are performed. That is, the semiconductor device 30 in FIGS. 39 to 40 has an underlying portion 3 formed by the ELO method. Note that a buffer portion 2 may be provided between the main substrate 1 and the second mask MS.

[0092] 39 to 40, for example, the main substrate 1 can be a SiC substrate, the buffer portion 2 can be a GaN-based semiconductor layer, the second mask MS can be a single layer film or a multilayer film including at least one of a silicon oxide film and a silicon nitride film, and the base portion 3 can be a GaN-based semiconductor layer formed by an ELO method.

[0093] The second mask MS includes a mask portion M and an opening Q, and in Fig. 39, the opening K of the first mask 6 overlaps with the opening Q of the second mask MS in a plan view. As shown in Fig. 40, a configuration may be used in which the gap TK of the base semiconductor portion 8 overlaps with the opening Q of the second mask MS in a plan view.

[0094] Fig. 41 is a flow chart showing another example of the method for manufacturing the semiconductor device according to the fourth embodiment. Fig. 42 is a cross-sectional view showing another configuration of the semiconductor device according to the fourth embodiment. In Fig. 41, after the step of preparing the main substrate 1, the step of forming a second mask MS and the step of forming the lowermost part of the first light reflecting portion RF by the ELO method are performed. Therefore, the semiconductor device 30 in Fig. 42 has the first light reflecting portion RF whose lowermost part is formed by the ELO method.

[0095] In the fourth embodiment, since the undercoat portion 3 or the lowermost portion of the first light reflecting portion RF (epitaxial DBR) is formed by the ELO method, dislocations (defects) in the first light reflecting portion RF are reduced, and the light reflectance can be increased.

[0096] Example 5 In the fifth embodiment, an epitaxial DBR of InAlN (first refraction portion R1) / GaN (second refraction portion R2) is formed. In this case, the base substrate UK is placed in the reaction furnace of the MOCVD apparatus, H2 and NH3 are supplied into the reaction furnace to raise the substrate temperature to 1070°C, and then TMG is supplied to the base substrate UK to epitaxially grow a GaN layer as the buffer portion 2 to a thickness of 100 nm. Next, the substrate temperature is lowered to 930°C (first temperature), and then the supply gas is switched from H2 to N2, and TMI and TMA are supplied to grow a non-doped InAlN layer (first refraction portion R1) to a thickness of 50 nm. Next, TEG and SiH4 are supplied while maintaining the substrate temperature at 930°C to grow a Si-doped GaN layer as the first layer of the second refraction portion R2 to a thickness of 5 nm. Next, the supply gas was switched from N2 to H2, the substrate temperature was raised to 1070°C (second temperature), and TMG was supplied to grow a non-doped GaN layer of 40 nm as the second layer of the second refraction portion R2. The above process was then repeated to form an epitaxial DBR made of 40 pairs of InAlN / GaN. When forming a first light reflecting portion RF made of InAlN / GaN that is lattice-matched with the base semiconductor portion 8 (e.g., a GaN layer), a GaN substrate (bulk crystal) can be used as the base substrate UK. In this case, the threading dislocation density on the opening K of the first mask 6 is set to 5×10 6 cm -2or less, and the aperture portion AP can be formed also above the opening portion K.

[0097] Example 6 In the sixth embodiment, the first light reflecting portion RF (epitaxial DBR) is formed by the PSD method. In the PSD method, all or some of the elements for forming the compound epitaxial layer are intermittently supplied. To form the compound epitaxial layer, it is necessary to supply all of the constituent elements, but there are cases where only some of the elements need to be intermittently supplied. That is, all or some of the raw materials of the constituent elements are intermittently excited. In the case of III-V nitrides, generally, all of the group III elements can be intermittently supplied, but when forming a mixed crystal, some group III elements may be intermittently supplied and other group III elements may be continuously supplied (preferably at a slow supply rate).

[0098] Regarding the group V element, when nitrogen is supplied as a gas, it exists in a gaseous state (molecules, radicals, ions) near the substrate growth surface, so it does not have to be intentionally supplied intermittently. The N element can also be supplied intermittently by intermittently exciting (sputtering) a raw material containing N, for example, a III-V group nitride. The group V element may be supplied by intermittently exciting a raw material, or the group V element raw material may be present in an atmosphere, or another raw material may be intermittently excited and supplied at the same time while the group V element raw material is present in the atmosphere. In addition, when multiple elements are supplied intermittently, the timing at which the multiple elements are supplied may be the same or different.

[0099] Regarding the supply duration, if it is too short, a large amount of energy is instantaneously applied to increase the supply rate during the supply period in order to obtain a practical film formation rate, which results in droplets being more likely to be generated as in the PLD method. On the other hand, if the supply duration is too long, it may not be possible to obtain a supply stop time that allows sufficient migration. Regarding the supply stop time (sec), if it is too short, the migration time will be insufficient and it will be difficult to obtain good crystals, and if it is too long, impurities will be easily incorporated, and depending on the film formation method, it may be difficult to continue film formation.

[0100] In Example 6, Ar gas was introduced at 1.0 sccm and nitrogen gas at 4.0 sccm by a mass flow controller as the atmospheric gas, and the growth pressure was 2×10 -2 Torr. The SiC substrate was grounded, the voltage applied between the SiC substrate and the Ga metal target was -600V, the voltage application time was 5μsec, and the voltage application was paused for 95μsec, and the voltage applied between the SiC substrate and the Ga metal target was -557V, the voltage application time was 5μsec, and the voltage application was paused for 50μsec. The amount of Ar gas introduced into the growth chamber was temporarily increased to start sputtering discharge, and after confirming that the amount of Ar gas and the growth pressure were stabilized to the above-mentioned set values, the shutters were opened to form the GaN layer, which is the second refraction portion R2. The growth temperature was 350°C. If an Al target is used in the same manner, an AlN layer, which is the first refraction portion R1, can be formed. By repeating the above process, an epitaxial DBR consisting of 30 pairs of AlN (first refraction portion R1) / GaN (second refraction portion R2) can be formed.

[0101] Example 7 In the first to sixth embodiments, the base semiconductor portion 8 can be made of GaN, but the base semiconductor portion 8 may be made of InGaN, which is a GaN-based semiconductor. The lateral deposition of InGaN is performed at a low temperature, for example, below 1000° C. This is because at high temperatures, the vapor pressure of indium increases and indium is not effectively incorporated into the film. The low deposition temperature has the effect of reducing the mutual reaction between the mask portion 5 and the base semiconductor portion 8. In addition, InGaN has the effect of being less reactive with the mask portion 5 (silicon oxide film, silicon nitride film, etc.) than GaN. When indium is incorporated into the base semiconductor portion 8 at an In composition level of 1% or more, the reactivity with the mask portion 5 is further reduced. Triethylgallium (TEG) can be used as the gallium source gas.

[0102] Example 8 Fig. 43 and Fig. 44 are cross-sectional views showing another configuration of the semiconductor device according to Example 8. As shown in Fig. 43, a wavelength conversion section HS may be provided below (on the back surface side) of the base substrate UK. For example, by arranging a general YAG phosphor that emits yellow light as the wavelength conversion section HS, white light illumination can be achieved.

[0103] As shown in Figure 44, in a semiconductor device 30 including a plurality of semiconductor laser elements 20, a red-emitting phosphor HR is arranged so as to overlap with the aperture portion AP of the semiconductor laser element 20 for the red sub-pixel in a planar view, a green-emitting phosphor HG is arranged so as to overlap with the aperture portion AP of the semiconductor laser element 20 for the green sub-pixel in a planar view, and a blue-emitting phosphor HB is arranged so as to overlap with the aperture portion AP of the semiconductor laser element 20 for the blue sub-pixel in a planar view, thereby realizing a semiconductor device 30 for a laser display device.

[0104] Example 9 FIG. 45 is a cross-sectional view showing another configuration of the semiconductor device according to the ninth embodiment. In FIG. 45, a photonic crystal layer is used for the first light reflecting portion RF. The first light reflecting portion RF, which is a photonic crystal layer, has a structure in which, for example, a fifth refraction portion R5 and a sixth refraction portion R6 having a higher refractive index than the fifth refraction portion R5 are arranged two-dimensionally (XY plane). The fifth refraction portion R5 may be a hole having a diameter of several tens to several hundreds of nanometers formed in a lattice point shape in the base layer. The base layer may be a nitride semiconductor layer. The lattice pitch may be approximately the emission wavelength (for example, 200 to 400 nm) in the compound semiconductor portion 9. In this case, the first light reflecting portion RF (photonic crystal layer) having a GaN-based semiconductor layer as a base layer may be formed on the base substrate UK (for example, GaN substrate), and the counter substrate SK (for example, GaN substrate) may be disposed on the first light reflecting portion RF, and the first mask 6 may be provided on the counter substrate SK via the seed portion 4. If the counter substrate SK is a GaN substrate, the first mask 6 may be provided on the counter substrate SK. Alternatively, the counter substrate SK may not be provided and the first mask 6 may be provided on the first light reflecting portion RF (photonic crystal layer) via the seed portion 4, or the first mask 6 may be provided on the first light reflecting portion RF (photonic crystal layer). It is known that when a photonic crystal is formed, the crystallinity of the upper layer decreases. In the ninth embodiment, a photonic crystal that realizes high light reflectance is used, while the decrease in the crystallinity of the upper layer is suppressed, and a compound semiconductor portion 9 with high light emission efficiency can be obtained.

[0105] Example 10 Fig. 46 is a schematic diagram showing the configuration of an electronic device according to Example 10. An electronic device 40 in Fig. 46 includes the semiconductor device 30 of Examples 1 to 9 and a control unit 80 including a processor that controls the semiconductor device 30. Examples of the electronic device 40 include a communication device, an optical device, a display device, a lighting device, a sensor device, an information processing device, a medical device, and an electric vehicle (EV).

[0106] The above-described embodiments and examples are intended to be illustrative and explanatory, and are not intended to be limiting. Based on these examples and descriptions, it will be apparent to those skilled in the art that many variations are possible.

[0107] [Additional Notes] The invention according to the present disclosure has been described above based on the drawings and examples. However, the invention according to the present disclosure is not limited to the above-mentioned embodiments. In other words, the invention according to the present disclosure can be modified in various ways within the scope of the present disclosure, and the embodiments obtained by appropriately combining the technical means disclosed in the different embodiments are also included in the technical scope of the invention according to the present disclosure. In other words, it should be noted that a person skilled in the art can easily make various modifications or corrections based on the present disclosure. It should also be noted that these modifications or corrections are included in the scope of the present disclosure. [Explanation of symbols]

[0108] 1 Main Board 2 Buffer section 3. Base 5 Mask section 6 First Mask 8 Base Semiconductor Section 9. Compound Semiconductor Department 20 Semiconductor laser element 30 Semiconductor Devices RF 1st light reflection section RS 2nd light reflection section MS 2nd Mask R1~R4 1st~4th bending section UK base board K opening Q Opening E1 1st electrode E2 2nd electrode CB Circuit Board HD Part 1 SD Part 2

Claims

1. A base substrate including a main substrate; A first light reflecting portion located above the base substrate; a first mask located above the first light reflecting portion; a base semiconductor portion located above the first mask; a compound semiconductor portion located above the base semiconductor portion; a second light reflecting portion located above the compound semiconductor portion and the first light reflecting portion; a first electrode located above the compound semiconductor portion; a second electrode located above the first mask or below the main substrate; the first mask includes a mask portion and an opening, A semiconductor device, wherein in a plan view, a region located between the first electrode and the second electrode does not overlap with the opening.

2. The semiconductor device according to claim 1 , wherein the base semiconductor portion includes a first portion and a second portion located on the mask portion and having a threading dislocation density that is ⅕ or less than that of the first portion.

3. A semiconductor device as described in claim 2, wherein the first electrode overlaps with the second light reflecting portion in a planar view.

4. A semiconductor device as described in claim 3, wherein the second electrode is located above the first mask.

5. A base substrate including a main substrate; A first light reflecting portion located above the base substrate; a first mask located above the first light reflecting portion; a base semiconductor portion located above the first mask; a compound semiconductor portion located above the base semiconductor portion; a second light reflecting portion located above the compound semiconductor portion and the first light reflecting portion; a first electrode located above the compound semiconductor portion and overlapping with the second light reflecting portion in a plan view; a second electrode located above the first mask or below the main substrate; an insulating film located on the compound semiconductor portion, the first mask includes a mask portion and an opening, the base semiconductor portion includes a first portion and a second portion located on the mask portion and having a threading dislocation density that is ⅕ or less than that of the first portion; The insulating film includes an aperture portion that overlaps with the first electrode, the first light reflecting portion, the second portion, and the second light reflecting portion in a planar view.

6. The semiconductor device according to claim 2 , wherein the compound semiconductor portion includes a first type semiconductor layer, an active layer, and a second type semiconductor layer in this order.

7. A base substrate including a main substrate; A first light reflecting portion located above the base substrate; a first mask located above the first light reflecting portion; a base semiconductor portion located above the first mask; a compound semiconductor portion located above the base semiconductor portion; a second light reflecting portion located above the compound semiconductor portion and the first light reflecting portion, the first mask includes a mask portion and an opening, the base semiconductor portion includes a first portion and a second portion located on the mask portion and having a threading dislocation density that is ⅕ or less than that of the first portion; the compound semiconductor portion includes a first type semiconductor layer, an active layer, and a second type semiconductor layer in this order; the second type semiconductor layer includes an aperture portion that overlaps with the first light reflecting portion, the second portion, and the second light reflecting portion in a planar view, and a high resistance portion that surrounds the aperture portion and has a higher current resistance than the aperture portion.

8. The semiconductor device according to claim 5 , wherein the aperture portion does not overlap a center of the mask portion in a plan view.

9. The semiconductor device according to claim 1 , further comprising a void located on the mask portion and in contact with a side surface of the base semiconductor portion and a side surface of the compound semiconductor portion.

10. The semiconductor device according to claim 2 , wherein the second portion overlaps with the first light reflecting portion and the second light reflecting portion in a plan view.

11. A semiconductor device as described in any one of claims 1, 5, or 7, wherein the first optical reflecting portion has a plurality of pairs including a first refractive portion and a second refractive portion having an optical refractive index larger than that of the first refractive portion.

12. the second refractive portion includes a GaN-based semiconductor, The semiconductor device according to claim 11 , wherein the first refractive portion includes a refractive material having an optical refractive index smaller than that of a GaN-based semiconductor of the second refractive portion.

13. The semiconductor device according to claim 12 , wherein the refractive material has a thermal conductivity greater than that of the GaN-based semiconductor of the second refractive portion.

14. The semiconductor device according to claim 12 , wherein the refractive material has a smaller lattice constant than the GaN-based semiconductor of the second refractive portion.

15. The semiconductor device according to claim 12 , wherein the thermal expansion coefficients of the main material of the main substrate are smaller than the GaN-based semiconductor of the second refractive portion, and the refractive material are smaller than the main material of the main substrate.

16. The semiconductor device of claim 12 , wherein the refractive material is a nitride semiconductor.

17. The semiconductor device of claim 12 , wherein the refractive material is AlN or AlInN, or InN.

18. The semiconductor device according to claim 11 , wherein the mask portion has a smaller optical refractive index than the second refractive portion.

19. The semiconductor device of claim 18 , wherein the base semiconductor portion has a higher optical index of refraction than the mask portion.

20. The semiconductor device according to claim 11 , wherein an upper surface of the first light reflecting portion is included in the second refractive portion.

21. The semiconductor device of claim 11 , further comprising a seed portion between the first light reflecting portion and the first mask.

22. The semiconductor device of claim 21 , wherein the seed portion has a greater optical refractive index than the mask portion and the first refractive portion.

23. The semiconductor device according to claim 1 , wherein the base semiconductor portion is in contact with an upper surface of the first light reflecting portion at the opening.

24. the first light reflecting portion is located on the base substrate, The semiconductor device according to claim 11 , wherein the base substrate has a recess that opens onto an upper surface.

25. The semiconductor device according to claim 24 , wherein the main substrate is recessed in a portion corresponding to the recess.

26. the base substrate includes a base portion located above the main substrate, 25. The semiconductor device according to claim 24, wherein the base portion is recessed or penetrated in a portion corresponding to the recess.

27. The semiconductor device according to claim 24 , wherein the second light reflecting portion does not overlap the recess in a plan view.

28. A base substrate including a main substrate; A first light reflecting portion located above the base substrate; a first mask located above the first light reflecting portion; a base semiconductor portion located above the first mask; a compound semiconductor portion located above the base semiconductor portion; a second light reflecting portion located above the compound semiconductor portion and the first light reflecting portion, the first mask includes a mask portion and an opening, the first light reflecting portion includes a plurality of pairs each including a first refraction portion and a second refraction portion having a light refractive index larger than that of the first refraction portion; the first light reflecting portion is located on the base substrate, the base substrate has a recess that opens onto an upper surface thereof; The semiconductor device, wherein the first bending portion and the second bending portion have a U-shaped portion along the recess.

29. a gap in contact with side surfaces of the compound semiconductor portion, the base semiconductor portion, and the mask portion, The semiconductor device according to claim 28 , wherein the void and the recess overlap in a plan view.

30. 30. The semiconductor device of claim 29, wherein a U-shaped portion located at the top of the first light reflecting portion contacts the gap.

31. a base portion located between the main substrate and the first light reflecting portion, The semiconductor device according to claim 1 , 5 , 7 , or 28 , wherein the underlying portion comprises a nitride semiconductor.

32. A buffer portion located on the main substrate; 32. The semiconductor device of claim 31, further comprising: a second mask located between the buffer portion and the undercoat portion.

33. the second mask includes a mask portion and an opening; The semiconductor device according to claim 32 , wherein the openings of the first mask and the openings of the second mask overlap in a plan view.

34. the second mask includes a mask portion and an opening; The semiconductor device according to claim 32 , wherein a center of a mask portion of the first mask overlaps with an opening of the second mask in a plan view.

35. The semiconductor device according to claim 4 , wherein the second electrode does not overlap the second light reflecting portion in a plan view.

36. The semiconductor device of claim 4 , wherein the second electrode contacts the base semiconductor portion.

37. a seed portion between the first light reflecting portion and the first mask; The semiconductor device of claim 4 , wherein the second electrode contacts the seed portion.

38. The semiconductor device according to claim 4 , wherein the second electrode is in contact with an upper surface of the first light reflecting portion.

39. the first electrode is a transparent electrode located between the compound semiconductor portion and the second light reflecting portion, the first electrode is in contact with an upper surface of the insulating film; The semiconductor device according to claim 5 , wherein the first electrode and the compound semiconductor portion are in contact with each other in the aperture portion.

40. The semiconductor device according to claim 5 , wherein the second light reflecting portion is provided in an island shape on the first electrode.

41. The semiconductor device according to claim 5 , wherein the second electrode overlaps with the second portion in a plan view.

42. 30. The semiconductor device of claim 1, 5, 7, or 28, wherein the base semiconductor portion and the compound semiconductor portion each comprise a nitride semiconductor.

43. The semiconductor device of claim 42 , wherein the primary substrate is a heterogeneous substrate having a different lattice constant than that of the base semiconductor portion.

44. The semiconductor device of claim 1 , 5, 7, or 28, wherein the main substrate has a higher thermal conductivity than a bulk GaN substrate.

45. The main substrate is transparent; The semiconductor device according to claim 1 , wherein the first light reflecting portion has a lower light reflectance than the second light reflecting portion.

46. 43. The semiconductor device of claim 42, wherein the primary substrate is a silicon carbide substrate.

47. The semiconductor device according to claim 21 , wherein the seed portion is locally provided so as to overlap the opening.

48. The semiconductor device of claim 42 , further comprising an air gap in contact with a side surface of the base semiconductor portion, a side surface of the compound semiconductor portion, and a side surface of the second light reflecting portion.

49. 49. The semiconductor device of claim 48, wherein a side surface of each of the base semiconductor portion and the compound semiconductor portion is an a-plane or an m-plane of the nitride semiconductor.

50. The semiconductor device according to claim 48 , wherein the gap and a center of the mask portion overlap in a plan view.

51. The semiconductor device according to claim 8 , wherein the base semiconductor portion contains a void that overlaps with a center of the mask portion in a plan view.

52. The threading dislocation density of the second portion is 5×10 ６ / cm ２ 3. The semiconductor device of claim 2, wherein:

53. 30. The semiconductor device of claim 1, 5, 7, or 28, comprising a wavelength converting portion located below the main substrate.

54. The semiconductor device according to claim 6 , wherein the second light reflecting portion includes a plurality of pairs each including a third refraction portion and a fourth refraction portion having a light refractive index larger than that of the third refraction portion.

55. 55. The semiconductor device of claim 54, wherein the third bending portion and the fourth bending portion each comprise a dielectric material.

56. a lower surface of the second light reflecting portion is included in the third refraction portion, an upper surface of the second light reflecting portion is included in the fourth refraction portion; The semiconductor device according to claim 54 , wherein the third refractive portion has an optical refractive index smaller than that of the second type semiconductor layer.

57. The semiconductor device of claim 1 , 5 , 7 , or 28 , wherein the first light reflecting portion is a photonic crystal layer.

58. The semiconductor device of claim 4 , wherein the first electrode is an anode and the second electrode is a cathode.

59. 29. The semiconductor device according to claim 1, comprising at least one surface-emitting semiconductor laser element including the base semiconductor portion, the compound semiconductor portion, and the first light reflecting portion and the second light reflecting portion.

60. 60. The semiconductor device of claim 59 including a circuit board connecting to one or more of said surface emitting semiconductor laser elements.

61. 61. An electronic device comprising the semiconductor device of claim 60.

62. 29. A method for manufacturing a semiconductor device according to claim 1, 5, 7 or 28, comprising the steps of: A method for manufacturing a semiconductor device, comprising forming the base semiconductor portion by an ELO method.

63. The base substrate includes a base portion, The method for manufacturing a semiconductor device according to claim 62, wherein the undercoat portion is formed by an ELO method.

64. 63. The method for manufacturing a semiconductor device according to claim 62, wherein the lowermost portion of the first light reflecting portion is formed by an ELO method.

65. 29. An apparatus for manufacturing a semiconductor device according to claim 1, 5, 7, or 28, comprising: An apparatus for manufacturing a semiconductor device, the apparatus forming the base semiconductor portion by an ELO method.

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