Substrate for electronic device, electronic device, chip resistor, and method for manufacturing electronic device

Abstract

To provide a substrate for an electronic device with a surface sufficiently flattened, which is superior in thermal conductivity and the adhesion between an alumina substrate and a flattened layer.SOLUTION: The substrate for the electronic device includes: an alumina substrate made of sintered body of alumina particles; and multiple flattened layers laminated on an upper surface of the alumina substrate. At least one of the multiple flattened layers is a flattened layer containing alumina as a main component.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present disclosure relates to a substrate for an electronic device, an electronic device, a chip resistor, and a method for manufacturing an electronic device. [Background technology]

[0002] Alumina substrates have good insulation and thermal conductivity, and therefore have been widely used as substrates (insulating substrates) in electronic devices, such as chip resistors. In general, a chip resistor comprises an insulating substrate, a pair of upper electrodes provided at both ends of the upper surface of the insulating substrate, and a resistor provided on the upper surface of the insulating substrate and connected between the pair of upper electrodes.

[0003] The chip resistor further includes a protective film provided to cover at least the resistor body, a pair of end electrodes provided on both end surfaces of the insulating substrate to be electrically connected to the pair of upper electrodes, and a plating layer formed on a portion of the upper electrode and on the surfaces of the pair of end electrodes.

[0004] Typically, when manufacturing the above-mentioned chip resistors, multiple sets of surface electrodes such as upper electrodes and resistors are formed together on a large-sized substrate made of alumina, and the large-sized substrate on which the surface electrodes etc. are formed is then divided (broken) along the primary dividing grooves and secondary dividing grooves that extend in a lattice pattern, or a dicing blade is used instead of the dividing grooves to cut into a lattice pattern, thereby obtaining individual chip elements.

[0005] However, the surface of the alumina substrate is not smooth and has minute irregularities and undulations. Therefore, there is a problem that the shapes of the front electrode and resistor formed on the surface of the alumina substrate are not stable. In particular, when the front electrode and resistor are formed as thin films by photolithography, there is a problem that the front electrode and resistor, which are thin films, are affected by the surface condition of the alumina substrate, and distortion, disconnection, cracks, etc. occur.

[0006] In order to solve the above problems, for example, Patent Document 1 proposes a technology in which a small amount of silica glass is contained in the alumina substrate itself, a glass coating is formed over the entire surface of the alumina substrate, and an upper electrode, resistor, etc. are formed on the glass coating. [Prior art documents] [Patent documents]

[0007] [Patent Document 1] JP 2017-168749 A Summary of the Invention [Problem to be solved by the invention]

[0008] In the technology of Patent Document 1, voids were generated at the interface between the alumina substrate and the glass coat. When voids exist between the alumina substrate and the glass coat, the adhesion between the alumina substrate and the glass coat is poor, and for example, when a functional film such as a resistor formed on the upper surface of the glass coat is subjected to an annealing process or repeated heat load in a post-process of chip resistor manufacturing, defects such as disconnection of the resistor occur, resulting in a problem of a decrease in the yield of the chip resistor. The present disclosure has been made in view of the above circumstances, and its purpose is to provide a substrate for an electronic device that is excellent in planarization, has excellent adhesion between the alumina substrate and the planarization layer, and has excellent thermal conductivity, an electronic device and a chip resistor that include the substrate for an electronic device, and a method for manufacturing an electronic device. [Means for solving the problem]

[0009] The substrate for electronic devices of the present disclosure that can achieve the above object is: an alumina substrate made of a sintered body of alumina particles; a plurality of planarization layers laminated on an upper surface of the alumina substrate; At least one of the plurality of planarizing layers is characterized in that its main component is alumina. Effect of the Invention

[0010] According to the present disclosure, it is possible to provide a substrate for an electronic device which has a sufficiently planarized surface, excellent adhesion between the alumina substrate and the planarization layer which constitute the substrate for an electronic device, and excellent thermal conductivity, an electronic device and a chip resistor which include the substrate for an electronic device, and a manufacturing method for an electronic device. [Brief description of the drawings]

[0011] [Figure 1] FIG. 1 is a schematic cross-sectional view of a substrate for an electronic device according to one embodiment of the present disclosure. [Diagram 2] FIG. 2 is a schematic cross-sectional view for explaining a method for determining the ratio of the length of pores between the alumina substrate and the planarizing layer. [Diagram 3] FIG. 3 is a top view photograph showing an example of the surface properties of a planarizing layer fired at a high temperature. [Figure 4] FIG. 4 is a schematic cross-sectional view of a chip resistor as an electronic device according to an embodiment of the present disclosure. [Diagram 5] FIG. 5 is a diagram showing a scanning electron microscope photograph of a cross section of the electronic device substrate in Example 1. As shown in FIG. [Figure 6] FIG. 6 is a diagram showing a scanning electron microscope photograph of a cross section of the electronic device substrate in Comparative Example 1. [Figure 7] FIG. 7 is a diagram showing a scanning electron microscope photograph of a cross section of the electronic device substrate in Comparative Example 2. As shown in FIG. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0012] As described above, in the technology of Patent Document 1, defects such as disconnection of the resistor in the chip resistor occurred, resulting in variation in resistance value. When the present inventors analyzed the cause, voids were confirmed at the interface between the alumina substrate and the glass coat. It is believed that the adhesiveness between the glass coat and the alumina substrate was low in the part where the voids existed, and the thermal conductivity deteriorated, causing the resistor to melt.

[0013] In view of these circumstances, the present inventors have conducted extensive research to obtain a substrate for electronic devices that has a sufficiently flat surface, excellent adhesion between the alumina substrate and the flattening layer that constitute the substrate for electronic devices, and excellent thermal conductivity. As a result, the inventors have found that the substrate for electronic devices used in electronic devices such as the chip resistors may be formed by laminating a plurality of flattening layers on an alumina substrate, with at least one of the plurality of flattening layers being mainly composed of alumina. Hereinafter, the substrate for electronic devices in the embodiment of the present disclosure will first be described.

[0014] [Substrates for electronic devices] Hereinafter, a substrate for an electronic device according to an embodiment of the present disclosure will be described with reference to Fig. 1. Note that the embodiment of the present disclosure is not limited to the form shown in Fig. 1, and can be appropriately modified within a range that does not impair the effects of the present disclosure.

[0015] FIG. 1 is a schematic cross-sectional view of an electronic device substrate 11 according to an embodiment of the present disclosure. FIG. 1 shows a structure in which a plurality of planarization layers (multi-layer planarization layers) 11b are laminated on the upper surface of an alumina substrate 11a made of a sintered body of alumina particles. FIG. 1 also shows an example in which the plurality of planarization layers 11b are configured by laminating two layers, a first planarization layer 111b and a second planarization layer 112b. The number of planarization layers is not limited to this, and may be three or more layers. In this specification, the "planarization layer in contact with the alumina substrate" refers to the layer closest to the alumina substrate in the cross section of the electronic device substrate, as in the first planarization layer 111b. It is also the layer with the largest area in contact with the alumina substrate 11a. The "topmost planarization layer" refers to the planarization layer furthest from the alumina substrate in the cross section of the electronic device substrate, as in the second planarization layer 112b. Hereinafter, the alumina substrate 11a and the plurality of planarization layers 11b will be described. (Alumina substrate) The alumina substrate 11a used for electronic device substrates is made of a sintered body of alumina particles. The sintered body is preferably made of alumina with a purity of 96% or more, which has excellent heat resistance and insulating properties. Furthermore, the alumina substrate has irregularities on its surface. The irregularities on the surface of this alumina substrate are due to the shape of the alumina particles that make up the sintered body. The irregularities are expressed as a maximum height Rz, which is, for example, about several hundred nm to several thousand nm. The maximum height Rz can be measured, for example, by an AFM (atomic force microscope).

[0016] (multiple planarization layers) The electronic device substrate 11 of the present disclosure has a configuration in which a plurality of planarization layers 11b are laminated. In the embodiment of the present disclosure, by providing a plurality of planarization layers 11b on the alumina substrate 11a, functional films such as electrodes and resistors can be formed without being affected by the surface state of the alumina substrate 11a. In this specification, the term "planarization layer" simply refers to the planarization layer of the electronic device substrate obtained by firing, and is distinguished from the planarization layer before firing.

[0017] (Component composition of planarization layer) At least one of the planarization layers is a planarization layer whose main component is alumina. By making at least one of the planarization layers whose main component is alumina, a difference in thermal expansion coefficient between the planarization layer and the alumina substrate is unlikely to occur when a thermal load is applied. Furthermore, since the planarization layer whose main component is alumina is similar in material to the alumina substrate, it exhibits excellent insulation and thermal conductivity similar to the alumina substrate. As a result, the characteristics of the alumina substrate, such as excellent insulation and thermal conductivity, can be fully exhibited in electronic devices. Here, the "main component" means that, for example, in the case of a planarization layer whose main component is alumina, the proportion of alumina in one planarization layer is 50% by mass or more. The proportion is preferably 80% by mass or more, more preferably 90% by mass or more.

[0018] The planarization layer, whose main component is alumina, contains other materials besides alumina, such as SiO 2 (Silica), ZrO 2(zirconia), TiO 2 , MnO, MgO, CaO, SrO, BaO, Yb 2 O 3 The planarization layer may contain ceramics such as metal oxides, organic or inorganic binders, etc. The planarization layer mainly composed of alumina preferably contains at least one of silica and zirconia in addition to the main component alumina.

[0019] At least one of the multiple planarization layers is a planarization layer whose main component is alumina, but the remaining planarization layers may be planarization layers whose main component is alumina, or may be planarization layers whose main component is ceramics other than alumina. That is, at least one of the multiple planarization layers may be a planarization layer whose main component is ceramics other than alumina. Most preferably, all of the multiple planarization layers are planarization layers whose main component is alumina.

[0020] The planarization layer of a ceramic whose main component is not alumina is not limited to a ceramic whose main component is, for example, SiO 2 , but can ensure the smoothness of the surface of the electronic device substrate, excellent adhesion to the alumina substrate, and excellent thermal conductivity. 2 (Silica), ZrO 2 (zirconia), TiO 2 , MnO, MgO, CaO, SrO, BaO, Yb 2 O 3 The planarizing layer made of a ceramic other than alumina as the main component is preferably made of silica or zirconia as the main component.

[0021] Of the multiple planarization layers, the planarization layer in contact with the alumina substrate is preferably a planarization layer whose main component is alumina. This is preferable because the alumina substrate and the planarization layer are homogeneous and have the same thermal expansion coefficient, resulting in a good interface. Alternatively, of the multiple planarization layers, the topmost planarization layer furthest from the alumina substrate may be a planarization layer whose main component is alumina. This is preferable because heat generated in functional films such as electrodes and resistors is well dissipated to the planarization layer. Both the planarization layer in contact with the alumina substrate and the topmost planarization layer may be planarization layers whose main component is alumina.

[0022] In the electronic device substrate of the present disclosure, a plurality of planarizing layers are laminated to form a multi-layer structure. The term "multi-layer" refers to a structure in which two or more planarizing layers are laminated. There is no particular upper limit on the number of layers, but it is preferably 5 layers or less because the process becomes complicated.

[0023] (Total thickness of multiple planarization layers, thickness of each planarization layer) The thickness of each planarization layer constituting the plurality of planarization layers is not particularly limited as long as the planarization layer can achieve the original purpose of the planarization layer, which is to planarize the surface of the alumina substrate. The maximum height Rz of the surface of a general alumina substrate is in the range of several hundred nm to several thousand nm due to the shape of the alumina particles constituting the sintered body, as described above. Therefore, the total thickness of the plurality of planarization layers is preferably larger than the maximum height Rz. Since the maximum height Rz may be the particle diameter of the alumina particles constituting the sintered body, it can be said that the total thickness of the plurality of planarization layers is preferably, for example, equal to or larger than the average particle diameter of the alumina particles constituting the sintered body. The total thickness of the plurality of planarization layers is preferably, for example, 2.0 μm or more, more preferably 2.5 μm or more, depending on the maximum height Rz and the average particle diameter of the alumina particles constituting the sintered body. The upper limit of the total thickness of the plurality of planarization layers is not particularly limited, and can be, for example, 20 μm or less.

[0024] Of the plurality of planarization layers, the planarization layer in contact with the alumina substrate may have the smallest thickness. From the viewpoint of increasing adhesion with the alumina substrate and suppressing the formation of voids, the thickness of the planarization layer in contact with the alumina substrate is preferably in the range of 10 nm to 1000 nm.

[0025] As an example of the main components of the multiple planarization layers being different, for example, in the case of a two-layer structure, the planarization layer in contact with the alumina substrate is mainly composed of silica, and the planarization layer on the outermost surface is mainly composed of alumina. In addition, for example, in the case of a three-layer structure, the main components of the planarization layers are, in order from the alumina substrate side, a structure such as alumina / silica / alumina. In these structures, compounds are generated between the planarization layers, which is preferable because it improves the binding property. In the case of silica and alumina, mullite is formed. Since silica has a lower thermal conductivity than alumina, the thickness of the planarization layer mainly composed of silica can be set to, for example, 1 μm or less, preferably 500 nm or less, and more preferably 300 nm or less, to suppress the decrease in thermal conductivity.

[0026] The planarization layer may be a continuous surface or may have a discontinuous surface as long as the outermost surface of the electronic device substrate, for example, on which a resistor is disposed, is planarized. When the planarization layer has a discontinuous surface, for example, the planarization layer in contact with the alumina substrate may be located at least in a concave portion of the unevenness of the alumina substrate, and a part of the alumina substrate may be exposed, and may also include a case in which the planarization layer or the alumina substrate is present in a shape of a plurality of islands when the electronic device substrate is viewed from above. It is preferable that the planarization layer covers 50% or more of the area of ​​the alumina substrate or the planarization layer serving as the base directly below it.

[0027] The plurality of planarizing layers are all planarizing layers whose main component is alumina, and at least one of the planarizing layers may have a particle shape different from that of the other planarizing layers. In addition, it is preferable that the particles constituting the planarizing layer in contact with the alumina substrate among the plurality of planarizing layers have a smaller average particle size and a smaller aspect ratio of the long side to the short side than the particles constituting the other planarizing layers.

[0028] In the electronic device substrate of the present embodiment, the ratio of the length of the void between the alumina substrate and the planarization layer to the surface line of the alumina substrate covered with the planarization layer is preferably 50% or less in a cross section in the lamination direction of the planarization layers. FIG. 2 is a cross-sectional schematic diagram for explaining a method for determining the above ratio when the entire surface of the planarization layer-forming side of the alumina substrate 11a is not covered with the planarization layers 11b and has an exposed portion 19 of the alumina substrate, as an example of the electronic device substrate of the present embodiment. In FIG. 2, the ratio is calculated by determining the ratio of the total length of the solid lines P2 to P3 and P6 to P7 that are in contact with the void between the alumina substrate 11a and the planarization layer 11b to the total length of the solid lines P1 to P4 and P5 to P8 representing the surface of the alumina substrate 11a covered with the planarization layer 11b. In FIG. 2, an exposed portion 19 of the alumina substrate, indicated by a dotted line, is not included in the surface line covered by the planarizing layer 11b.

[0029] [Electronic Devices] An embodiment of the present disclosure includes an electronic device comprising the above-mentioned electronic device substrate. The electronic device includes a chip resistor. The chip resistor includes a chip resistor having at least a resistor disposed on the upper surface of the planarization layer of the electronic device substrate. The thermistor includes a thermistor having at least a resistance temperature detector disposed on the upper surface of the planarization layer of the electronic device substrate. The material of the resistor is required to have low reactivity with at least the outermost surface of the planarization layer, but is not otherwise particularly limited, and the materials exemplified below can be used.

[0030] [Electronic device manufacturing method] The method for manufacturing an electronic device according to this embodiment includes applying ceramic particles to the upper surface of an alumina substrate by a method exemplified below, drying the applied particles, and then firing the substrate; more specifically, forming a plurality of planarizing layers by the method of the first or second embodiment below, thereby manufacturing a substrate for an electronic device according to this embodiment.

[0031] (First embodiment) The method for manufacturing an electronic device according to the first embodiment includes the steps of: On the upper surface of an alumina substrate made of a sintered body of alumina particles, Repeating the steps of applying ceramic particles and drying the ceramic particles to obtain a sintering substrate having a plurality of planarizing layers stacked thereon before sintering; The firing substrate is fired at a temperature at which crystallization proceeds, The method includes obtaining a substrate for an electronic device having a plurality of planarization layers formed thereon.

[0032] Second embodiment The method for producing an electronic device according to the second embodiment includes the steps of: On the upper surface of an alumina substrate made of a sintered body of alumina particles, Applying ceramic particles and drying the applied ceramic particles to obtain a substrate to be fired having one pre-fired planarizing layer formed thereon; The firing substrate is repeatedly fired at a temperature at which crystallization proceeds, The method includes obtaining a substrate for an electronic device having a plurality of planarization layers formed thereon.

[0033] First, a method for manufacturing a substrate for an electronic device will be described below, with overlapping parts between the first and second embodiments being described together.

[0034] (Preparation of alumina substrate) An alumina substrate made of a sintered body of alumina particles is prepared as a substrate for constituting an electronic device substrate. The manufacturing method of the alumina substrate 11a is not particularly limited. The alumina substrate is produced by molding and sintering alumina particles. The alumina particles used to manufacture the sintered body constituting the alumina substrate 11a can have different particle sizes or contain additives depending on the desired characteristics.

[0035] (Formation of multiple planarization layers) In the first embodiment, in the step of forming a plurality of planarization layers of a substrate for an electronic device, (1) coating the upper surface of the alumina substrate with ceramic particles; (2) Drying a step of repeatedly carrying out the steps to obtain a substrate to be fired on which a plurality of planarization layers before firing are laminated; At least a step of firing the substrate at a temperature at which crystallization proceeds is carried out.

[0036] In the second embodiment, in the step of forming a plurality of planarization layers of a substrate for an electronic device, [1] A step of applying ceramic particles to an upper surface of the alumina substrate and drying the applied ceramic particles to obtain a substrate to be fired having one pre-fired planarizing layer formed thereon; [2] firing the firing substrate at a temperature at which crystallization proceeds; The method includes at least repeatedly performing the steps.

[0037] The method of applying ceramic particles to form a flattening layer on an alumina substrate is not particularly limited. For example, a sol-gel method can be used. The sol-gel method is one of the ceramic synthesis methods, and can produce a flattening layer at a lower temperature than the conventional melting method or sintering method. In addition, since the raw material is in a solution state, a flattening layer with a thin film thickness can be produced. Alternatively, a particle dispersion liquid can be used. Therefore, particles of different shapes or particles of multiple different components, which will be described later, can be added. Furthermore, additives for controlling the sinterability and the film quality after sintering, such as an organic binder, can be added.

[0038] The ceramic particles for forming the flattening layer may be ceramic particles having the same composition as that of the flattening layer described above.

[0039] Of the multiple planarization layers, the planarization layer in contact with the alumina substrate is preferably formed using ceramic particles that have an aspect ratio of long side to short side of 1 to 5 or are approximately spherical. By using ceramic particles with such a shape, the ceramic particles can easily penetrate into the irregularities of the alumina substrate, suppressing the generation of voids between the alumina substrate and the planarization layer, improving adhesion between the alumina substrate and the planarization layer, and improving the properties of the electronic device substrate and the electronic device, such as thermal conductivity.

[0040] The planarization layer in contact with the alumina substrate is preferably formed using ceramic particles having an average particle diameter of 50 nm or less. In this case, the ceramic particles can easily penetrate the unevenness of the alumina substrate, suppressing the generation of voids between the alumina substrate and the planarization layer, thereby improving the adhesion between the alumina substrate and the planarization layer, and improving the properties of the substrate for electronic devices and the electronic device, such as thermal conductivity. The lower limit of the average particle diameter is not particularly limited from the viewpoint of ensuring the above-mentioned effects, but the lower limit of the average particle diameter (primary particle diameter) is about 5 nm as a particle size that can be currently produced. The average particle diameter can be measured, for example, using a TEM.

[0041] The planarizing layer in contact with the alumina substrate is more preferably formed using alumina particles having an aspect ratio of long side to short side of 1 or more and 5 or less, being approximately spherical, and having an average particle size of 50 nm or less.

[0042] In one embodiment, the thickness of the planarization layer before firing that contacts the alumina substrate is, for example, in the range of 10 nm or more and the maximum height Rz × 1.0 or less. If the thickness of the planarization layer before firing that contacts the alumina substrate is in the above range, it is preferable because voids are unlikely to occur at the interface with the alumina substrate.

[0043] In one embodiment, the planarization layers before firing may all be composed of alumina particles of the same size and shape, and may differ only in thickness.

[0044] In one embodiment, the planarization layers are all formed of ceramic particles (e.g., alumina particles) whose main component is alumina, and the ceramic particles constituting each planarization layer have different shapes. For example, in the case of a planarization layer having a two-layer structure, the planarization layer before firing that contacts the alumina substrate is formed of spherical ceramic particles, and the planarization layer before firing on the outermost surface is formed of plate-like or feather-like ceramic particles. By forming the planarization layers using ceramic particles having different shapes in this way, the planarization layer in contact with the alumina substrate has high adhesion to the alumina substrate, and the outermost surface has excellent smoothness, resulting in a substrate for electronic devices. Furthermore, by using ceramic particles whose main component is alumina, the adhesion between the planarization layers is also good when fired.

[0045] In the following, the sol-gel method will be described as an example of a method for applying ceramic particles to form a planarization layer, but the method for forming the planarization layer in this embodiment is not limited to this and also includes formation by other methods.

[0046] In the sol-gel method, a sol material is applied onto the alumina substrate 11a and dried to form the multi-layer planarization layer 11b. In the case of using a particle dispersion liquid, the particle dispersion liquid is applied onto the alumina substrate 11a and dried to form the multi-layer planarization layer 11b. Various methods of application are possible, such as spin coating, dipping, spraying, transfer coating, die coating, gravure printing, flexographic printing, offset printing, screen printing, and inkjet printing.

[0047] According to the above method, the leveling effect of the coating liquid is exerted when forming the planarization layer, and a planarization layer with a smooth surface can be obtained, even if the thickness of the planarization layer is approximately the same as the maximum height Rz of the alumina substrate, for example.

[0048] In order to efficiently exert the leveling effect, an additive for controlling thickening due to drying can be added to control the time until leveling. In addition, since it is possible to promote leveling by reducing surface tension, an additive for promoting the reduction of surface tension may be added. Addition of additives can also be expected to have a defoaming effect. Specifically, silicone-based additives and fluorine-based additives can be used, but are not limited thereto. In addition, surfactants include cationic (anionic), anionic (cationic), amphoteric, nonionic, etc., but are not particularly limited as long as they do not deteriorate the properties of the coating liquid to which they are added.

[0049] Although the material constituting the multi-layer flattening layer 11b has been described above, it is also possible to perform a treatment on the alumina substrate side. For example, in order to improve wettability, a hydrophilic treatment or an oleophilic treatment can be performed on the surface of the alumina substrate on which the multi-layer flattening layer is to be formed, depending on the characteristics of the material constituting the multi-layer flattening layer. For example, in the case of an aqueous coating liquid, the wettability can be improved by subjecting the alumina substrate 11a to a hydrophilic treatment, specifically a plasma treatment.

[0050] Examples of the alumina sol include sols of boehmite crystals, pseudo-boehmite crystals, γ-alumina, or non-crystalline colloidal alumina particles obtained by various production methods, and sols of colloidal alumina particles having various shapes such as rod-like, fibrous, feathery, and granular shapes.

[0051] A coating solution such as the above-mentioned alumina sol is applied onto the alumina substrate 11a and dried. In this specification, the planarizing layer obtained by forming a layer by one coating or the like and drying before firing or the planarizing layer obtained by firing this is referred to as one layer.

[0052] (Planarization layer before firing) In both the first and second embodiments, the planarization layer before firing has a particle shape derived from the raw material used to form the planarization layer. For example, the planarization layer before firing that contacts the alumina substrate is preferably composed of particles having an aspect ratio of the long side to the short side of 1 to 5 or approximately spherical particles. With this configuration, as described above, the ceramic particles can easily penetrate into the irregularities of the alumina substrate, suppressing the generation of voids between the alumina substrate and the planarization layer, improving the adhesion between the alumina substrate and the planarization layer, and improving the properties of the substrate for electronic devices and the electronic device, such as thermal conductivity.

[0053] The planarization layer before firing, which is in contact with the alumina substrate, is preferably composed of ceramic particles having an average particle size of 50 nm or less. In this case, too, the ceramic particles can easily penetrate the unevenness of the alumina substrate, suppressing the generation of voids between the alumina substrate and the planarization layer, thereby improving the adhesion between the alumina substrate and the planarization layer, and improving the properties of the electronic device substrate and the electronic device, such as thermal conductivity. The lower limit of the average particle size is not particularly limited from the viewpoint of ensuring the above-mentioned effects, but the lower limit of the average particle size (primary particle size) is about 5 nm as a particle size that can be currently manufactured.

[0054] It is more preferable that the planarizing layer before firing that is in contact with the alumina substrate is formed from alumina particles that have an aspect ratio of their long and short sides of 1 or more and 5 or less, are roughly spherical, and have an average particle size of 50 nm or less.

[0055] In one embodiment, the thickness of the planarization layer before firing that contacts the alumina substrate is, for example, in the range of 10 nm or more and the maximum height Rz × 1.0 or less. If the thickness of the planarization layer before firing that contacts the alumina substrate is in the above range, voids are unlikely to occur at the interface with the alumina substrate, which is preferable.

[0056] In one embodiment, the planarization layers before firing may all be composed of alumina particles of the same size and shape, and may differ only in thickness.

[0057] In one embodiment, the planarization layers before firing are all formed of ceramic particles (e.g., alumina particles) whose main component is alumina, and the ceramic particles constituting each planarization layer have different shapes. For example, in the case of a planarization layer having a two-layer structure, the planarization layer before firing that contacts the alumina substrate is formed of spherical ceramic particles, and the planarization layer before firing on the outermost surface is formed of plate-like or feather-like ceramic particles. By forming the planarization layers with ceramic particles having different shapes in this way, the planarization layer that contacts the alumina substrate has high adhesion to the alumina substrate, and the outermost surface has excellent smoothness, thereby obtaining a substrate for electronic devices. Furthermore, by forming the planarization layers each mainly of alumina ceramic particles, the adhesion between the planarization layers is also good when fired.

[0058] (Firing) By carrying out the firing, a denser planarization layer can be realized. The firing is carried out before the formation of the resistors so that the resistors formed on the upper surfaces of the planarization layers are not affected by the volumetric shrinkage caused by the firing. In both the first and second embodiments, the firing is preferably carried out at a temperature equal to or higher than that of the annealing treatment carried out in the subsequent process. When the main component is alumina, for example, firing at a temperature at which crystallization advances may advance to γ-alumina, θ-alumina, and α-alumina, and may be carried out at a temperature in the range of, for example, 600 to 1800°C. The firing time may be, for example, 3 hours, as described in the examples below.

[0059] As in the first embodiment, when multiple planarization layers are formed before firing and then fired, bonding occurs between each layer by firing. If the main components of the planarization layers are the same, bonding is likely to proceed. If the main components of the multiple planarization layers are different from each other, a compound / intermediate composition may be formed.

[0060] As in the second embodiment, ceramic particles may be applied, dried, and fired every time a flattening layer is formed. For example, alumina particles for forming a first flattening layer may be applied to the upper surface of an alumina substrate, dried, and then fired at a high temperature of, for example, 1100°C or higher, for example, 1280°C, for 3 hours or more. As a result, cracks due to shrinkage accompanying the formation of α-alumina may be intentionally generated, as shown in the upper surface photograph of the flattening layer after the high-temperature firing in FIG. 3. FIG. 3 is an electron microscope photograph taken at a magnification of 20,000 times using a scanning electron microscope (product name S-4800) of Hitachi High-Technologies Corporation. After the cracks are formed, for example, a solution containing alumina particles for forming a second flattening layer is applied so as to penetrate into the cracks of the first flattening layer, and then fired, whereby an anchor effect is generated and the adhesion between the first flattening layer and the second flattening layer can be improved.

[0061] (Chip resistors and their manufacturing methods) Hereinafter, a chip resistor will be described as an electronic device having an electronic device substrate according to an embodiment of the present disclosure, with reference to the drawings. Note that the embodiment of the present disclosure is not limited to the form shown in the drawings below, and can be appropriately modified without impairing the effects of the present disclosure. In the following description, the same components are given the same reference numerals, and the description is omitted as appropriate.

[0062] First, a chip resistor including a substrate for electronic devices according to an embodiment of the present disclosure will be described with reference to FIG. 4. The chip resistor 21 according to an embodiment of the present disclosure has a configuration shown in FIG. 4. That is, the chip resistor 21 includes a substrate for electronic devices 11 including an alumina substrate 11a and a multi-layered flattening layer 11b, a pair of upper electrodes 12, a pair of lower electrodes 13, a resistor 14, and a pair of end electrodes 15. The pair of upper electrodes 12 are provided at both ends of one surface (upper surface) of the alumina substrate 11a. As shown in FIG. 4, the pair of lower electrodes 13 may be provided at both ends of the rear surface of the substrate for electronic devices 11. The multi-layered flattening layer 11b is provided over the entire upper surface of the alumina substrate 11a, and the resistor 14 is provided on the upper surface of the multi-layered flattening layer 11b and connected between the pair of upper electrodes 12. The pair of end electrodes 15 are provided on both end surfaces of the substrate for electronic devices 11 so as to be electrically connected to the pair of upper electrodes 12. Although the chip resistor 21 illustrated in FIG. 4 is provided with the lower electrode 13, the chip resistor according to the present disclosure does not necessarily have to be provided with the lower electrode 13.

[0063] As an example of a method for manufacturing an electronic device according to the present embodiment, there is a method for manufacturing a chip resistor. As described above, the method for manufacturing a chip resistor according to a preferred embodiment of the present disclosure includes a step of applying ceramic particles to the upper surface of an alumina substrate by a sol-gel method or a method using a particle dispersion liquid, drying the substrate, and then firing the substrate, specifically, a step of manufacturing a substrate for an electronic device by the method of the first or second embodiment. The method for manufacturing an electronic device according to the present embodiment including a chip resistor is not particularly limited except that the substrate for an electronic device is manufactured by the method of the first or second embodiment.

[0064] On the planarized layer of the electronic device substrate obtained by the above firing, for example, as shown in the following examples, a thin film made of NiCrAlSi alloy is formed by sputtering or the like, and then the thin film is patterned into a meandering shape by photolithography (resist coating, drying, exposure, development, etching, and resist peeling), to form the resistor 14. In addition to the NiCrAlSi alloy, the material constituting the resistor 14 includes pure metals of Pt, Ni, and Cu, and alloys containing 50 mass% or more of each metal, such as Pt-Co alloy. These are materials with a large temperature coefficient of resistance (TCR), and resistors made of these materials can be used as resistors for temperature measurement in addition to functioning as chip resistors.

[0065] 4, the methods of forming the above-mentioned alumina substrate 11a, planarization layer 11b, and resistor 14 are not particularly limited. For example, the upper electrode 12 can be formed by depositing a copper material on the planarization layer 11b by a method such as sputtering. The other electrodes, protective films, and plating layers can also be formed in a manner generally used.

[0066] In the manufacturing process of the chip resistor 21, an annealing treatment may be performed after the resistor 14 is formed and before the upper electrode 12 and the like are formed, or after the resistor 14 and the electrodes 12 and the like are formed. EXAMPLES

[0067] The present disclosure will be described in more detail below with reference to examples. The present disclosure is not limited to the following examples, and may be modified as appropriate within the scope of the above and below-described aims, and all such modifications are within the technical scope of the present disclosure.

[0068] [Example 1] First, a sample was prepared by laminating two planarization layers on an alumina substrate as follows. The alumina substrate was made of alumina with a purity of 96% or more, and had a maximum height Rz of 2.4 μm. In this example, it was determined that smoothness was ensured when the total thickness of the planarization layer formed on the upper surface of the alumina substrate was equal to or greater than the maximum height Rz of the alumina substrate, and that smoothness was not ensured when the total thickness of the planarization layer was smaller than the maximum height Rz of the alumina substrate.

[0069] Alumina sol manufactured by Kawaken Fine Chemical Co., Ltd. (trade name: Alumina Sol-10A, crystal form: pseudo-boehmite, (minor axis x major axis): 10 nm x 50 nm) was applied to the upper surface of the alumina substrate by processing with a spin coater (manufactured by Mikasa Co., Ltd.) at a rotation speed of 3000 rpm for 20 seconds, and dried at room temperature to form a first planarization layer. The thickness of this first planarization layer was about 1.7 μm. Next, alumina sol manufactured by Nissan Chemical Co., Ltd. (trade name: Alumina Sol AS-200, feathery particles, length: 200 nm or more) was applied to the upper surface of the alumina substrate by processing with a spin coater (manufactured by Mikasa Co., Ltd.) at a rotation speed of 1000 rpm for 20 seconds, and dried at room temperature to form a second planarization layer, and a pre-fired sample was obtained. The thickness of the second planarization layer after drying was about 3.7 μm.

[0070] (Confirmation of void state between alumina substrate and planarization layer) In a cross section perpendicular to the surface of the planarization layer of the unfired sample, milling was performed so that the interface between the alumina substrate and the planarization layer could be observed, and the cross section including the interface was observed using a scanning electron microscope (product name S-4800) manufactured by Hitachi High-Technologies Corporation to obtain a cross-sectional SEM image. The result is shown in FIG. 5. In FIG. 5, a multi-layer planarization layer 11c before firing is formed on an alumina substrate 11a, that is, a first planarization layer 111c before firing is formed on the alumina substrate 11a, and a second planarization layer 112c before firing is formed on the first planarization layer 111c. A thin layer is formed on the outermost surface, which is a deposit 16 generated by the milling process.

[0071] [Firing] The above sample was subjected to annealing treatment in an electric drying furnace at 700° C. for 3 hours to obtain a laminated substrate sample.

[0072] (Evaluation of adhesion between planarization layer and alumina substrate) Using the above laminated substrate sample, the adhesion between the planarizing layer and the alumina substrate was evaluated as follows.

[0073] The adhesion between the planarization layer and the alumina substrate was evaluated by the stud pin method, in which a stud pin was fixed to the surface of the second planarization layer of the laminate substrate sample with an epoxy resin adhesive, a load was applied by pulling the stud pin, and the strength (fracture strength) at the time of peeling was measured using a thin film adhesion strength tester (Quad Group, Sebastian). As a reference, the planarization layer was not formed, and the stud pin was fixed to the surface of the alumina substrate with epoxy resin, and the fracture strength was measured when the same test as above was performed. Then, when the fracture strength was equivalent to the fracture strength of this reference, the adhesion between the planarization layer and the alumina substrate was evaluated as excellent, with an "O"; when the fracture strength was lower than the fracture strength of the reference, the adhesion between the planarization layer and the alumina substrate was evaluated as poor, with an "X".

[0074] [Preparation of heat generation test sample (resistor formation)] A resistor was formed on the upper surface of the second planarization layer of the laminated substrate sample as follows. In detail, a thin film made of NiCrAlSi alloy was formed on the second planarization layer by sputtering or the like, and then the thin film was processed into a line shape with a line width of 40 μm by photolithography (resist application, drying, exposure, development, etching, and resist peeling) to form a resistor. In addition, electrodes made of Cu were formed on both ends of the linear resistor to obtain a heat generation test sample. The distance between the electrodes was 1.1 mm. The obtained heat generation test sample was used to perform a heat generation test described in detail below.

[0075] (Heat generation test) Using the above heat generation test samples, the heat generation state when electricity was applied was evaluated to evaluate thermal conductivity. The initial resistance values ​​were measured because they differed, and the heat generation state when electricity was applied so that the input power was constant was measured with a thermograph (Advancedthermo TVS-500EX, Avionics Corporation). The temperature of the place where heat was generated the most was obtained and converted to the case where the input power was 1W. In this heat generation test, it was determined that a sample had good thermal conductivity when the value converted per 1W of input power was equal to or less than the value of the reference (alumina substrate).

[0076] [Comparative Example 1] In Comparative Example 1, a sample was obtained in the same manner as in Example 1, except that a single planarization layer (thickness 1.74 μm) was formed using an alumina sol manufactured by Kawaken Fine Chemical Co., Ltd. (product name: Alumina Sol-10A, crystal form: pseudo-boehmite, (minor axis × major axis): 10 nm × 50 nm) and a spin coating speed of 1000 rpm. Cross-sectional microscopic observation, evaluation of adhesion between the planarization layer and the alumina substrate, and heat generation tests were performed.

[0077] [Comparative Example 2] In Comparative Example 2, a sample was obtained in the same manner as in Example 1, except that a single planarization layer (thickness 3.48 μm) was formed using an alumina sol manufactured by Nissan Chemical Co., Ltd. (product name: Alumina Sol 200 (AS-200), feathery particles, length: 200 nm or more) at a spin coating speed of 1000 rpm, and cross-sectional microscopy observation, evaluation of adhesion between the planarization layer and the alumina substrate, and heat generation tests were performed.

[0078] [Reference] As a reference, only the alumina substrate used in Example 1 was prepared. Using this alumina substrate, the adhesion test was carried out as described above, and a heat generation test sample was formed and a heat generation test was carried out to obtain each measured value as a reference.

[0079] 6 and 7 show cross-sectional microscope photographs of Comparative Example 1 and Comparative Example 2, which were observed and photographed in the same manner as in FIG. 5. As shown in FIG. 6 and FIG. 7, in Comparative Example 1 and Comparative Example 2, a single-layer planarization layer 17 before firing is formed instead of the multi-layer planarization layer 11c before firing. In the cross-sectional microscope photographs of FIG. 5 to FIG. 7, the white line-shaped parts are holes. From these FIG. 5 to FIG. 7, it can be seen that the ratio of the length of the holes between the alumina substrate and the planarization layer to the surface line of the alumina substrate covered with the planarization layer is 50% or less in Example 1 and Comparative Example 1, but exceeds 50% in Comparative Example 2. In this embodiment, the ratio of the length of the holes was evaluated in the sample before sintering, but it has been separately confirmed that the evaluation result is almost the same in the sample after sintering.

[0080] The total thickness of the planarization layer and the evaluation results of the adhesion between the planarization layer and the alumina substrate (referred to as "adhesion test" in Table 1) for Example 1, Comparative Example 1, and Comparative Example 2 are shown in Table 1. Furthermore, the results of the heat generation test for Example 1, Comparative Example 1, Comparative Example 2, and the reference are also shown in Table 1.

[0081] [Table 1]

[0082] As is clear from Table 1, in Example 1, the total thickness of the planarization layer exceeds the maximum height Rz of the alumina substrate (2.4 μm), and it is understood that the smoothness of the surface of the substrate for electronic devices is ensured. Also, as is clear from Figure 5, in Example 1, the voids between the alumina substrate and the first planarization layer are sufficiently suppressed, and as a result, the adhesion between the alumina substrate and the planarization layer is high, and in the heat generation test, the thermal conductivity is also excellent, and is almost the same as that of the reference (only the alumina substrate).

[0083] On the other hand, in Comparative Example 1, as is clear from Fig. 6, the voids between the alumina substrate and the planarization layer were suppressed, and the adhesion between the alumina substrate and the planarization layer was ensured. The results of the heat generation test were also almost the same as those of the reference (alumina substrate only). However, the thickness of the planarization layer was smaller than the maximum height Rz of the alumina substrate, and smoothness could not be ensured.

[0084] In Comparative Example 2, from the results in Table 1, the thickness of the planarization layer exceeds the value of the maximum height Rz of the alumina substrate, and smoothness is ensured. However, as shown in FIG. 7, voids are continuously generated between the alumina substrate and the planarization layer, and the adhesion between the alumina substrate and the planarization layer is poor. In addition, the heat generation test showed poor thermal conductivity. In Comparative Example 2, the reason for poor adhesion and poorer thermal conductivity than the reference (alumina substrate only) is presumably due to the voids between the alumina substrate and the planarization layer. If a large number of voids are present, not only is the adhesion with the alumina substrate poor, but the voids (air layer) function as heat insulation, so only partial thermal conduction is obtained, and it is considered that the thermal conductivity is poor.

[0085] Both Comparative Example 1 and Comparative Example 2 are single-layer planarization layers formed of alumina. However, the particle shapes of the alumina used to form the planarization layers are different, and Comparative Example 1 resulted in greater suppression of voids between the alumina substrate and the planarization layer. From these results, it can be seen that in order to further suppress voids between the alumina substrate and the planarization layer, it is effective to use particles that are close to spherical and have a small particle size, as in the case of the alumina particle shape used to form the planarization layer in Comparative Example 1. [Industrial Applicability]

[0086] The substrate for electronic devices according to the present disclosure has a sufficiently planarized surface, excellent adhesion between the alumina substrate and the planarization layer, and excellent thermal conductivity, and is therefore useful as a substrate part for use in electronic devices that require excellent durability. [Explanation of symbols]

[0087] 11 Substrates for electronic devices 11a Alumina substrate 11b Multilayer planarization layer 111b First planarization layer 112b Second planarization layer 11c Multi-layer planarization layer before firing 111c First planarization layer before firing 112c Second planarization layer before firing 12 Upper electrode 13 Lower electrode 14 Resistor 15 End electrode 21 Chip resistors 16 Sediments 17 Single planarization layer before firing 18 Vacancies 19 Exposed part of alumina substrate

Claims

1. an alumina substrate made of a sintered body of alumina particles; a plurality of planarization layers laminated on an upper surface of the alumina substrate; at least one of the plurality of planarization layers is a planarization layer whose main component is alumina, the planarization layer whose main component is alumina is a planarization layer that is in contact with an alumina substrate, and the planarization layers other than the planarization layer whose main component is alumina are planarization layers made of ceramics whose main component is alumina, silica, or zirconia.

2. The substrate for electronic devices as described in claim 1, wherein the total thickness of the multiple planarization layers is equal to or greater than the maximum height Rz of the alumina substrate.

3. 3. The substrate for electronic devices according to claim 1, wherein among the plurality of planarization layers, the planarization layer in contact with the alumina substrate has the smallest thickness.

4. 4. The substrate for electronic devices according to claim 1, wherein the planarizing layer mainly composed of alumina contains at least one of silica and zirconia in addition to the alumina as the main component.

5. 5. The substrate for electronic devices according to claim 1, wherein at least one of the plurality of planarizing layers is a ceramic planarizing layer whose main component is silica or zirconia.

6. 5. The substrate for electronic devices according to claim 1, wherein the plurality of planarization layers are all planarization layers whose main component is alumina, and at least one planarization layer has a particle shape different from the other planarization layers.

7. The substrate for electronic devices according to any one of claims 1 to 6, wherein, of the plurality of planarization layers, a planarization layer in contact with the alumina substrate has particles constituting the planarization layer that have a smaller average particle diameter and a smaller aspect ratio of long sides to short sides than particles constituting the other planarization layers.

8. In a cross section in a stacking direction of the plurality of planarization layers, The substrate for electronic devices according to any one of claims 1 to 7, wherein a ratio of a length of a hole between the alumina substrate and the planarization layer to a surface line of the alumina substrate covered with the planarization layer is 50% or less.

9. An electronic device comprising the substrate for an electronic device according to any one of claims 1 to 8.

10. 9. A chip resistor, comprising at least a resistor disposed on an upper surface of the planarizing layer of the substrate for electronic devices according to claim 1.

11. 10. The method of claim 9 for producing an electronic device, comprising: On the upper surface of an alumina substrate made of a sintered body of alumina particles, Repeating the steps of applying ceramic particles and drying the ceramic particles to obtain a sintering substrate having a plurality of planarizing layers stacked thereon before sintering; The firing substrate is fired at a temperature at which crystallization proceeds, A method for producing an electronic device, comprising obtaining a substrate for an electronic device having a plurality of planarization layers formed thereon.

12. 10. The method of claim 9 for producing an electronic device, comprising: On the upper surface of an alumina substrate made of a sintered body of alumina particles, A substrate for firing is obtained by applying ceramic particles and drying the applied ceramic particles to form a planarizing layer before firing. The firing substrate is repeatedly fired at a temperature at which crystallization proceeds, A method for producing an electronic device, comprising obtaining a substrate for an electronic device having a plurality of planarization layers formed thereon.

13. 13. The method for manufacturing an electronic device according to claim 11 or 12, wherein, of the plurality of planarization layers, a planarization layer in contact with the alumina substrate is formed using ceramic particles having an aspect ratio of long side to short side of 1 or more and 5 or less, or being approximately spherical.

14. 14. The method for manufacturing an electronic device according to claim 11, wherein, of the plurality of planarization layers, the planarization layer in contact with the alumina substrate is formed using ceramic particles having an average particle size of 50 nm or less.

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