Reference current source

Abstract

To provide a standard current source capable of improving the stability of a reference current.SOLUTION: A standard current source SCS includes: a reference current path P0 including a diode-connected first transistor M1, a diode-connected second transistor M2, and a first resistor R1 connected in series between a first fixed potential VDD and a second fixed potential GND; a first output current path P1 including a third transistor M3 having a gate connected to the gate of the second transistor M2 and forming a current mirror with the second transistor M2, and including a second resistor R2 interposed between the third transistor M3 and the first fixed potential VDD; and a second output current path P2 having a voltage-current conversion circuit 40 through which a reference current Is flows for a given potential of a third node N3 between the third transistor M3 and the second resistor R2 in the first output current path P1.SELECTED DRAWING: Figure 3

Description

[Technical field]

[0001] The present disclosure relates to a reference current source. [Background technology]

[0002] A reference current source is used in an integrated circuit (IC). The reference current source can generate one or more reference currents. The reference currents are supplied to multiple circuits in a semiconductor chip using current mirrors. The reference currents can be used to determine the operating points of each circuit in the IC. The reference current source preferably has a structure that is not susceptible to PVT (process / voltage / temperature) variations / fluctuations.

[0003] Non-Patent Document 1 discloses a band-gap reference (BGR), i.e., a current source that utilizes the energy band gap of a semiconductor. This current source has high resistance to fluctuations such as temperature. In the BGR method, bipolar transistors are used in principle. When a semiconductor chip includes bipolar transistors in addition to a complementary metal-oxide semiconductor (CMOS) circuit, the manufacturing cost of the semiconductor chip increases.

[0004] Non-Patent Document 2 discloses a β-multiplier reference (BMR) circuit. Conventional reference current sources can generate a reference current with practical stability even if the power supply potential fluctuates. However, the BMR cannot compensate for temperature characteristics if it is left as a fundamental circuit.

[0005] Non-Patent Document 3 discloses a Widlar current source (BMR circuit with CMOS circuit) having multiple field effect transistors. A complicated circuit is required to perform temperature compensation.

[0006] Patent Document 1 discloses a reference current source including a current mirror. This reference current source is considered to require a start-up circuit. [Prior art documents] [Patent documents]

[0007] [Patent Document 1] JP 2002-244748 A [Non-patent literature]

[0008] [Non-Patent Document 1] Behzad Razavi, “TheBandgap Reference,” IEEE Solid-State Circuit Magazine, Vol. 8, Issue 3, pp. 9-12, Summer2016. [Non-Patent Document 2] R. Jacob Baker, “CMOSCircuit Design, Layout, and Simulation, Fourth Edition,” John Wiley &Sons, Chapter 23, July 2019. [Non-Patent Document 3] Yen-Ting Wang, Degang Chen, Randall L.Geiger, “A CMOS Supply-Insensitive with 13ppm / °CTemperature Coefficient Current Reference,” 2014 IEEE 57thInternational Midwest Symposium on Circuits and Systems (MWSCAS), pp. 475-478, August 2014. Summary of the Invention [Problem to be solved by the invention]

[0009] However, when semiconductor structures are miniaturized, the power supply rejection ratio (PSRR) of the reference current supplied to the internal circuit decreases. Therefore, a reference current source that can stably supply the reference current with a simple structure is required. [Means for solving the problem]

[0010] the first reference current source comprises: a reference current path including a diode-connected first transistor, a diode-connected second transistor, and a first resistor connected in series between a first fixed potential and a second fixed potential; a first output current path including a third transistor having a gate connected to a gate of the second transistor and constituting a current mirror together with the second transistor, and including a second resistor interposed between the third transistor and the first fixed potential; and a second output current path including a voltage-current conversion circuit through which a reference current flows when a potential of a node between the third transistor and the second resistor in the first output current path is applied. , and the voltage-to-current conversion circuit comprises a fourth transistor having a gate connected to the node, and an output resistor connected between the fourth transistor and the second fixed potential.

[0011] In the second reference current source, the second transistor and the third transistor have the same gate length; The second transistor Gate Width of the third transistor Gate Width Greater than.

[0012] In the third reference current source, the second transistor is a set of N transistors (1≦N). If multiple, they are connected in parallel. The third transistor is a transistor having M pieces (1≦M). If multiple, they are connected in parallel. It consists of: the second transistor and the third transistor have the same gate length; The sum of the gate widths of the N transistors constituting the second transistor is The above The sum of the gate widths of the M transistors that make up the third transistor is K times (1 <K)である。

[0013] As mentioned above, The voltage-current conversion circuit includes a fourth transistor having a gate connected to the node, and an output resistor connected between the fourth transistor and the second fixed potential.

[0014] Fourth In the reference current source of the fourth transistor and the first transistor have the same gate length; The fourth transistor Gate Width is the first transistor Gate Width Greater than.

[0015] Fifth In the reference current source, the gate length of one of the transistors constituting the third transistor is not more than 100 nm and not less than 5 nm. Effect of the Invention

[0016] According to the reference current source of the present invention, the stability of the reference current can be improved. [Brief description of the drawings]

[0017] [Figure 1] FIG. 1 is a circuit diagram of a reference current source according to a comparative example. [Diagram 2] FIG. 2 is a circuit diagram showing a reference current source according to the embodiment. [Diagram 3] FIG. 3 is a circuit diagram of a reference current source SCS in which each of the transistors M2, M4, M5 is constituted by a number of identical transistors connected in parallel. [Figure 4] FIG. 4 is a graph showing the relationship between the first fixed potential VDD (V) and the reference current Is (μA). [Diagram 5] FIG. 5 is a graph showing the relationship between the gate-source voltage Vgs (mV) and the drain current Id (μA) of one transistor. [Figure 6] FIG. 6 is a graph showing the relationship between the first fixed potential VDD (V), the reference current Ia (μA), and the first output current Ib (μA). [Figure 7] FIG. 7 is a conceptual graph showing the relationship between the voltage V and the current I applied to a circuit element. [Figure 8] FIG. 8 is a circuit diagram of an apparatus including a circuit for deriving a reference current Is from a reference current source SCS. [Figure 9] FIG. 9 is a circuit diagram of a reference current source according to another embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0018] Various exemplary embodiments will be described in detail below with reference to the drawings. Note that the same or corresponding parts in each drawing are denoted by the same reference numerals, and duplicated explanations will be omitted.

[0019] FIG. 1 is a circuit diagram of a reference current source according to a comparative example.

[0020] The reference current source shown in Fig. 1 is a beta-multiplier reference (BMR) circuit (Widlar current mirror current source) with a CMOS circuit. The reference current source includes a first upstream transistor M11, a second upstream transistor M12, a first downstream transistor M21, and a second downstream transistor M22. The transistors shown in each drawing are metal-oxide-semiconductor (MOS) field effect transistors.

[0021] The first upstream transistor M11 is a P-type MOS transistor, and its source is connected to a first fixed potential VDD. The first downstream transistor M21 is an N-type MOS transistor, and its drain is connected to the drain of the first upstream transistor M11 and its source is connected to a second fixed potential GND. The first downstream transistor M21 has its gate and drain connected together, that is, it constitutes a diode-connected transistor.

[0022] The second upstream transistor M12 is a P-type MOS transistor, and its source is connected to the first fixed potential VDD. The second downstream transistor M22 is an N-type MOS transistor, and its drain is connected to the drain of the second upstream transistor M12, and its source is connected to the second fixed potential GND via a resistor R. The second upstream transistor M12 has its gate and drain connected together, that is, it constitutes a diode-connected transistor.

[0023] The gate of the first upstream transistor M11 is connected to the gate of the second upstream transistor M12, and this transistor pair constitutes an upper current mirror. The gate of the first downstream transistor M21 is connected to the gate of the second downstream transistor M22, and this transistor pair and the resistor R constitute a lower current mirror. Note that in the Widlar current source, the resistor R is connected to the second downstream transistor M22 that is not diode-connected, not to the first downstream transistor M21.

[0024] Here, the gate width W21 of the first downstream transistor M21 and the gate width W22 of the second downstream transistor M22 have a relationship of W22=K×W21. Note that K>1, and the size of the second downstream transistor M22 is larger than the size of the first downstream transistor M21. The gain coefficient β of the transistor is expressed as follows: β=μ×C OX × (W / L), where μ is the carrier mobility, C OX is the capacitance per unit area of ​​the gate oxide film, W is the gate width, and L is the gate length. If the gate lengths L of the illustrated transistors are all equal, the value of the gain coefficient β or the value of (W / L) is proportional to the gate width W. The second downstream transistor M22 has a gain coefficient β that is K times that of the first downstream transistor M21. The gain coefficient β is proportional to the width of the channel through which carriers flow (gate width W).

[0025] On the other hand, the upstream current mirror passes the first reference current Iref1 and the second reference current Iref2 of the same magnitude through the left and right lines. Therefore, the first reference current Iref1 flowing through the first downstream transistor M21 and the second reference current Iref2 flowing through the second downstream transistor M22 are equal to each other.

[0026] In order to make the drain current Id of the transistor with a large gain coefficient β equal to the drain current Id of the transistor with a small gain coefficient β, the gate-source voltage Vgs of the transistor with the larger gain coefficient β should be made smaller. That is, the gate-source voltage Vgs(M22) of the second downstream transistor M22 with a large gain coefficient β is smaller than the gate-source voltage Vgs(M21) of the first downstream transistor M21 with a small gain coefficient β. If the difference between these gate-source voltages is ΔVgs, then Vgs(M22)+ΔVgs=Vgs(M21) is satisfied.

[0027] In addition, the gate-source voltage Vgs(M21) of the first downstream transistor M21, the gate-source voltage Vgs(M22) of the second downstream transistor M22, and the voltage V(R) across the resistor R satisfy Vgs(M21) - Vgs(M22) - V(R) = 0 according to the voltage law of a closed loop including these circuit elements.

[0028] Therefore, the voltage V(R) applied across the resistor R is Vgs(M21)-Vgs(M22)=δVgs. Thus, the voltage V(R)=δVgs across the resistor R depends on the parameter K indicating the size of the transistor, but does not depend on the first fixed potential VDD. If the resistance value of the resistor R is r, then the second reference current Iref2=V(R) / r=δVgs / r. Thus, according to the reference current source of the comparative example, the second reference current Iref2 does not change even if the first fixed potential VDD changes. However, particularly when the semiconductor structure is miniaturized, there is room for improvement in the reference current source of the comparative example. That is, the BMR circuit cannot compensate for the temperature dependency by itself. Furthermore, miniaturization reduces the Early voltage, and the dependency of the reference current on the power supply voltage (first fixed potential VDD) increases. Furthermore, the PSRR of the reference current supplied to the internal circuit decreases. Therefore, a reference current source that can stably supply the reference current with a simple structure is required when the power supply potential or temperature fluctuates.

[0029] 2 is a circuit diagram of a reference current source according to an embodiment. The reference current source SCS according to the embodiment has the following structure.

[0030] First, in the reference current source SCS, not only is the variation of the reference current Is suppressed in response to the power supply potential variation (or ground potential variation), but the variation of the reference current in response to the temperature variation is small and the structure is simple. The reference current source of the comparative example uses a BMR circuit to suppress the variation of the second reference current Iref2 in response to the power supply potential variation, but the BMR circuit alone has a large temperature dependency. In the reference current source of the comparative example, the second reference current Iref2 varies greatly in response to the temperature variation. In order to reduce the temperature dependency in the reference current source of the comparative example, it was considered necessary to add a temperature compensation circuit having a complex structure. On the other hand, the reference current source SCS of the embodiment can perform temperature compensation with a simple structure.

[0031] Second, the reference current source SCS has a structure that allows it to operate without a startup circuit. That is, in the reference current source of the comparative example, a stable state exists even when the second reference current Iref2=0, and a startup circuit is required to escape from this stable state. On the other hand, the reference current source of the embodiment operates without a startup circuit.

[0032] The reference current source SCS according to the embodiment will be described in detail below.

[0033] The reference current source SCS of the embodiment includes a reference current path P0, a first output current path P1, and a second output current path P2 between a power supply line that provides a first fixed potential VDD and a ground line that provides a second fixed potential GND.

[0034] The reference current path P0 includes a first transistor M1, a second transistor M2, and a first resistor R1 connected in series between a first fixed potential VDD and a second fixed potential GND. The reference current path P0 further includes a third resistor R3 connected between the first fixed potential VDD and the first transistor M1. The positions of the third resistor R3 and the first transistor M1 may be interchanged.

[0035] The third resistor R3 is interposed between the first fixed potential VDD and the drain of the first transistor M1. The first transistor M1 is an N-type MOS transistor, the drain of which is connected to the third resistor R3, and the source of which is connected to the drain of the second transistor M2. The gate of the first transistor M1 is connected to the drain, constituting a diode-connected transistor. The first transistor M1 may be a diode-connected P-type MOS transistor, in which case the source is connected to the third resistor R3. When the positions of the third resistor R3 and the first transistor M1 are interchanged, and the first transistor M1 is a diode-connected P-type MOS transistor, the source of the first transistor M1 is connected to the first fixed potential VDD, and the drain and gate are connected to the third resistor R3.

[0036] The second transistor M2 is an N-type MOS transistor, the drain of which is connected to the source of the first transistor M1, and the source of which is connected to the first resistor R1. The gate of the second transistor M2 is connected to the drain, constituting a diode-connected transistor. The first resistor R1 is connected between the source of the second transistor M2 and a second fixed potential GND.

[0037] The first output current path P1 includes a second resistor R2 and a third transistor M3 connected in series between a first fixed potential VDD and a second fixed potential GND.

[0038] The second resistor R2 is interposed between the first fixed potential VDD and the drain of the third transistor M3. The third transistor M3 has a gate connected to the gate of the second transistor M2 and forms a current mirror together with the second transistor M2. The source of the third transistor M3 is connected to the second fixed potential GND. The reference current source SCS includes an inverse Widlar current source. In the inverse Widlar current source, the first resistor R1 is connected to the diode-connected second transistor M2, not to the third transistor M3 that forms one of the current mirrors.

[0039] The second output current path P2 includes a fifth transistor M5, a fourth transistor M4, and a fourth resistor R4 connected in series between a first fixed potential VDD and a second fixed potential GND. The fifth transistor M5 is not a component of the reference current source SCS, but rather a load of the drain current (reference current) flowing through the fourth transistor M4. In other words, in the second output current path P2, the circuit belonging to the reference current source SCS is the voltage-current conversion circuit 40.

[0040] The fifth transistor M5 is a P-type MOS transistor, the source of which is connected to the first fixed potential VDD and the drain of which is connected to the drain of the fourth transistor M4. The fifth transistor M5 has its gate connected to its drain, constituting a diode-connected transistor. The fourth transistor M4 is an N-type MOS transistor, the drain of which is connected to the drain of the fifth transistor M5 and the source of which is connected to the fourth resistor R4. The gate of the fourth transistor M4 is connected to a third node N3 between the third transistor M3 and the second resistor R2 in the first output current path P1. The fourth resistor R4 (output resistor) is connected between the source of the fourth transistor M4 and the second fixed potential GND.

[0041] The voltage-current conversion circuit 40 is composed of a fourth transistor M4 and a fourth resistor R4. Specifically, the voltage-current conversion circuit 40 includes a fourth transistor M4 having a gate connected to a third node N3, and a fourth resistor R4 connected between the fourth transistor M4 and a second fixed potential GND. The voltage-current conversion circuit 40 is provided with the potential of the third node N3 in the first output current path P1 via the gate of the fourth transistor M4, and a reference current Is flows.

[0042] Here, an example of the relationship of transistor sizes will be described, but the present invention is not limited only to these relationships. The size (gate width W2) of the second transistor M2 is larger than the size (gate width W1) of the first transistor M1. Further, the size (gate width W2) of the second transistor M2 is larger than the size (gate width W3) of the third transistor M3. The size (gate width W4) of the fourth transistor M4 is the same as the size (gate width W2) of the second transistor M2, but is larger than the size (gate width W1) of the first transistor M1. The size (gate width W5) of the fifth transistor M5 as a load is larger than the size (gate width W3) of the third transistor M3. Note that when the gate lengths of the respective transistors are equal, the sizes of the transistors are proportional to the magnitudes of the gate widths.

[0043] In this example, W1 = 1 μm, W2 = 4 μm, W3 = 1 μm, W4 = 4 μm, W5 = 5 μm, and the relationship of W1 = W3 < W2 = W4 < W5 is satisfied. Assuming K = 4, W2 = K × W3 = K × W1, and W4 = K × W3 = K × W1. Among these transistors, the smallest transistor is the first transistor M1 or the third transistor M3. Each of the transistors M1 to M5 may be composed of a plurality of identical transistors. When each of the transistors M1 to M5 is composed of a plurality of identical transistors, the sum of the gate widths of the identical transistors included in each of the transistors M1 to M5 is defined as the gate width of each of the transistors M1 to M5. The gain factor β of each individual transistor also has the same relationship as the gate width.

[0044] The gate length L of one transistor constituting the smallest third transistor M3 is 5 nm or more and 100 nm or less. That is, the miniaturization of the transistor reduces the Early voltage, and the generated reference current Is is significantly affected. When the gate length L is miniaturized to 100 nm or less, particularly when it is miniaturized to 50 nm or less, the generated reference current Is is significantly affected. The reference current source SCS aims to improve the stability of the reference current when miniaturized. Therefore, when the gate length L is 100 nm or less, the effect of improving the PSRR of the reference current is significant. When the gate length L is 50 nm or less, the effect of improving the PSRR of the reference current is even more significant. When the gate length L is 30 nm or less, the effect of improving the PSRR of the reference current is even more significant.

[0045] Generally, transistors with a gate length L of 5 nm or more are known, so this embodiment can be applied to transistors with a gate length L of 5 nm or more. Of course, even when the circuit of this embodiment is applied to a transistor with a gate length L of less than 5 nm, the stability improvement effect of the reference current Is can be expected in principle. When the gate length L is 20 nm or less, it is also possible to adopt a transistor with a FinFET structure. For transistors with a gate length L of 3 nm or less, it is also possible to adopt a transistor with a structure different from the current FinFET structure (improved FinFET, Nanosheet FET, Forksheet FET, CFET, etc.). Note that, as an example, each of the transistors M1 to M5 is used in a saturation region, but may be operated in a non-saturation region as the power supply voltage decreases.

[0046] The parameters of each circuit element were determined by performing optimization using the short channel models disclosed in the above-mentioned non-patent document 2, with the values ​​designed as described below as a guide.

[0047] An example of the parameters of each circuit element is as follows:

[0048] Gate width W1 of the first transistor M1=1 μm Gate length L1 of first transistor M1=100 nm Gate width W2 of second transistor M2=4 μm The gate length L2 of the second transistor M2 is 100 nm. Gate width W3 of the third transistor M3 = 1 μm The gate length of the third transistor M3 is L3=100 nm. Gate width W4 of the fourth transistor M4=4 μm The gate length of the fourth transistor M4 is L4=100 nm. Gate width W5 of the fifth transistor M5=5 μm Gate length L5 of the fifth transistor M5=100 nm Resistance value of the first resistor R1: r1 = 5kΩ The resistance value of the second resistor R2 is r2 = 15kΩ The resistance value of the third resistor R3 is r3 = 15kΩ The resistance value of the fourth resistor R4 is r4 = 17 kΩ First fixed potential VDD=1.2V Second fixed potential GND=0V

[0049] In the above, 1.2V was used as the first fixed potential VDD (power supply voltage), but the reference current Is can also be stabilized by using 1.0V. When setting the parameters, first understand the characteristics of the transistors in that process. Select parameters that will obtain the desired current within a reasonable range of resistance values ​​and transistor mounting area. Note that in actual design, care should be taken to prevent excessive variation in transistor size.

[0050] If the voltage drop in the first transistor M1 is Vf1 and the voltage drop in the second transistor M2 is Vf2, the relationship in the path from the second fixed potential GND to the first fixed potential VDD is 0V+(Ia×r1)+Vf2+Vf1+(Ia×r3)=VDD. That is, by modifying this formula, the reference current Ia is given by Ia=(VDD-Vf1-Vf2) / (r1+r3). Unlike the conventional β-multiplier, the reference current source SCS according to the embodiment does not have a different equilibrium point, so a start-up circuit is not required. The reference current Ia increases monotonically with respect to the first fixed potential VDD, but the voltage drop Vf (=Vf1, Vf2) in each transistor does not change much with respect to the reference current Ia, so the increase rate of the reference current Ia is greater than the increase rate of the first fixed potential VDD.

[0051] As an example, the voltage fluctuation of the first node N1 is designed to be approximately half of the fluctuation of the first fixed potential VDD. For example, the fluctuation of the potential of the first fixed potential VDD is ΔV(VDD)=10mV. In this case, if the reference current Ia does not change, the voltage drop value by the third resistor R3 does not change, so the potential of the first node N1 also increases by 10mV. To make the fluctuation of the potential of the first node N1 half of 10mV (=5mV), the voltage drop by the third resistor R3 needs to be increased by 5mV. At this time, the reference current Ia increases by ΔIa=5mV / 15kΩ=1 / 3μA. Assuming that the reference current Ia is approximately 15μA, the change rate of the reference current Ia is ΔIa / Ia=approximately 2%. When the first fixed potential VDD is 1.2V, the change rate of the first fixed potential VDD is ΔV(VDD) / VDD=10mV / 1.2V=0.8%.

[0052] On the other hand, the current mirror consisting of the second transistor M2 and the third transistor M3 is designed so that the fluctuation of the first output current Ib is twice as large as the fluctuation of the reference current Ia. If the resistance values ​​of the third resistor R3 and the second resistor R2 are made equal (r3=r2), the potential of the third node N3 will not depend on the first fixed potential VDD. For example, as described above, if the first fixed potential VDD rises by 10 mV, the reference current Ia increases, and the voltage drop in the third resistor R3 increases by 5 mV, the potential of the first node N1 rises by 5 mV. On the other hand, since the increase in the first output current Ib is twice the increase in the reference current Ia, the increase in the voltage drop in the second resistor R2 is 10 mV. That is, if the first fixed potential VDD rises by 10 mV, the voltage drop in the second resistor R2 increases by 10 mV, so these voltage changes cancel each other out, and the potential of the third node N3 does not change.

[0053] The above voltage fluctuation compensation conditions can be summarized as follows:

[0054] (Condition 1) The amount of change ΔV(N1) in the potential of the first node N1 at the lower end of the third resistor R3 is preferably set to be half the amount of change ΔV(VDD) in the potential of the first fixed potential VDD (ΔV(N1)=ΔV(VDD) / 2). In this case, the amount of change ΔIa in the reference current Ia is the voltage across the third resistor R3 divided by the resistance value r3, and the following relational expression is established. To satisfy condition 1, the parameters of the circuit elements in the reference current path P0 are adjusted. ΔIa=(ΔV(VDD) / 2)÷r3…(Formula 1)

[0055] (Condition 2) The resistance value r3 of the third resistor R3 and the resistance value r2 of the second resistor R2 are set to be the same. In this case, the following relational expression is established. r2=r3 …(Formula 2)

[0056] (Condition 3) The amount of change ΔIb in the first output current Ib is set to twice the amount of change ΔIa in the reference current Ia. In this case, the following relational expression is established using (Equation 1). ΔIb=2×ΔIa=2×(ΔV(VDD) / 2)÷r3=ΔV(VDD) / r3 …(Formula 3)

[0057] When these (Condition 1) to (Condition 3) are satisfied, the change in potential of the third node N3 is zero. In other words, the change in potential of the third node N3, ΔV(N3), is given by (the increase in the first fixed potential VDD) - (the voltage drop due to the second resistor R2), and is expressed as ΔV(N3) = ΔV(VDD) - (r2 x ΔIb). In this formula, substituting the value of (Formula 3) (ΔIb = ΔV(VDD) / r3) and the value of (Formula 2) (r2 = r3), we obtain ΔV(N3) = ΔV(VDD) - (r3 x ΔV(VDD) / r3) = 0.

[0058] Of course, based on such a design concept, it is preferable to further fine-tune the parameters of each circuit element, and other ratios can also be set for each parameter. In the reference current source SCS of this example, by setting each parameter, it is possible to compensate not only for the fluctuation of the reference current Is caused by the power supply voltage fluctuation, but also for the fluctuation of the reference current Is caused by temperature change. Note that these conditions are one example of a circuit design for stabilizing the reference current Is, and by optimizing using a simulator with parameters that satisfy each condition as a guide, parameters that satisfy conditions slightly different from these conditions can be set.

[0059] In the example shown in Figure 4, the reference current Is is designed to be in the usable range of 25μA or more. The resistance value r1 of the first resistor R1 is set to 5kΩ, the resistance value r2 of the second resistor R2 is set to 15kΩ, and the resistance value r3 of the third resistor R3 is set to 15kΩ, and these values ​​are each set to three times the resistance value r1 of the first resistor R1. The parameter (K ​​times) indicating the size of the second transistor M2 is set to K=4. Although this value deviates from the condition for Ia=Ib, it is possible to suppress the fluctuation of the reference current Is in response to the fluctuation of the first fixed potential VDD.

[0060] FIG. 3 is a circuit diagram of a reference current source SCS formed by a plurality of identical transistors connected in parallel, where each of the transistors M2, M4, and M5 is constituted by such transistors.

[0061] In this example, each of the transistors M1 to M5 shown in FIG. 2 is constituted by one or a plurality of identical transistors connected in parallel. The sizes of the respective transistors are the same. The remaining structure is the same as that shown in FIG. 2. Therefore, the reference current source SCS shown in FIG. 3 is a circuit equivalent to the reference current source SCS shown in FIG. 2.

[0062] When each of the transistors M1 to M5 is composed of one or a plurality of identical transistors, the sum of the gate widths of the identical transistors included in each of the transistors M1 to M5 is defined as the gate width of each of the transistors M1 to M5. By comparing these total gate widths, the sizes of the respective transistors M1 to M5 can be compared. That is, when the second transistor M2 is composed of N (1 ≤ N) transistors and the third transistor M3 is composed of M (1 ≤ M) transistors, the sum of the gate widths of the N identical transistors constituting the second transistor M2 is K times (1 < K) the sum of the gate widths of the M identical transistors constituting the third transistor M3 (N = K × M, and in this example, K = 4). In the figure, the second transistor M2 is composed of four identical transistors, the fourth transistor M4 is composed of four identical transistors, and the fifth transistor M5 is composed of five identical transistors. The gate width of each individual identical transistor is, for example, all 1 μm.

[0063] FIG. 4 is a graph showing the relationship between the first fixed potential VDD (V) and the reference current Is (μA) in the reference current source shown in FIG. 2.

[0064] Let the range of the reference current Is from 25.4 μA to 25.6 μA be the first allowable reference current range ΔIs1. Let the range of the reference current Is from 25.2 μA to 25.6 μA be the second allowable reference current range ΔIs2.

[0065] At 0° C. (solid line), when the first fixed potential VDD varies from 1.14 V to 1.26 V, the reference current Is is within the first allowable reference current range ΔIs1. At 0° C. (solid line), when the first fixed potential VDD varies from 1.11 V to 1.29 V, the reference current Is is within the second allowable reference current range ΔIs2.

[0066] At 50° C. (dash-dotted line), when the first fixed potential VDD varies from 1.17 V to 1.30 V, the reference current Is is within the first allowable reference current range ΔIs1. At 50° C. (dash-dotted line), when the first fixed potential VDD varies from 1.13 V to 1.35 V, the reference current Is is within the second allowable reference current range ΔIs2.

[0067] At 100° C. (dotted line), when the first fixed potential VDD varies from 1.20 V to 1.34 V, the reference current Is is within the first allowable reference current range ΔIs1. At 100° C. (dotted line), even when the first fixed potential VDD varies from 1.16 V to 1.39 V, the reference current Is is within the second allowable reference current range ΔIs2.

[0068] Even when the first fixed potential VDD varies from 1.20V to 1.26V and the temperature varies from 0°C to 100°C, the reference current Is is within the first allowable reference current range ΔIs1. Even when the first fixed potential VDD varies from 1.16V to 1.29V and the temperature varies from 0°C to 100°C, the reference current Is is within the second allowable reference current range ΔIs2. Note that even when the first fixed potential VDD varies from 1.00V to 1.4V within the temperature range of 0°C to 100°C, the reference current Is is within the reference current range of 23.4μA to 25.6μA.

[0069] The results in Figure 4 show that the power supply potential fluctuation is kept within the range of 1.2V×(100-10)%≦VDD≦1.2V×(100+10)%, and the fluctuation of the reference current Is is kept within the range of ±2% within the temperature range of 0°C to 100°C.

[0070] Next, a guideline for the parameters of each circuit element that satisfies the above-mentioned (Condition 1) to (Condition 3) will be described.

[0071] First, the first transistor M1 constituting the reference current path P0 that defines (Condition 1) will be considered.

[0072] Figure 5 is a graph showing the relationship between the gate-source voltage Vgs (mV) and the drain current Id (μA) of a diode-connected transistor. This graph shows data at 0°C (solid line), 50°C (dashed line), and 100°C (dotted line). Although Figure 5 is a graph related to the characteristics of the first transistor M1, it can also be used to consider the characteristics of the third transistor M3.

[0073] When the gate-source voltage Vgs increases, the drain current Id increases. In the reference current source according to the embodiment, the gate-source voltage Vgs is designed to use the reference voltage Vgs0. The fluctuation range of the gate-source voltage Vgs from the reference voltage Vgs0 is |ΔVgs|. A suitable example of the use range of the gate-source voltage Vgs when the transistor is turned on is (|Vgs0|-|ΔVgs|)≦|Vgs|≦(|Vgs0|+|ΔVgs|). For example, when the reference voltage Vgs0 is 440mV and the fluctuation range |ΔVgs| is 120mV, 320mV≦|Vgs|≦560mV is exemplified. For example, when the reference voltage Vgs0 is 400mV, 280mV≦|Vgs|≦520mV is exemplified. These use ranges are only examples, and when the current to be handled is reduced, the reference voltage |Vgs0| and the fluctuation range |ΔVgs| can be further reduced. When the transistor is an N-channel type, the gate-source voltage is positive, and when the transistor is a P-channel type, the gate-source voltage is negative, so the magnitude (absolute value) of the gate-source voltage is set as described above.

[0074] At a gate-source voltage Vgs higher than the gate-source voltage Vgs in the utilization range, there is a fixed point X1 at which the drain current Id does not vary with temperature changes. In other words, in the reference current source SCS according to the embodiment, a gate-source voltage Vgs smaller than the gate-source voltage Vgs that provides the fixed point X1 is used. In this case, the drain current Id varies with temperature changes, but as described above, the reference current source SCS as a whole can suppress changes in the reference current Is.

[0075] The fixed point X1 will now be explained in more detail.

[0076] The drain current Id of a transistor is roughly Id=β / 2×(Vgs-VT) 2 where VT is the threshold voltage of the transistor. It is known that the two constants β and VT become smaller as the temperature increases. As the temperature increases, the rising voltage of the IV curve becomes lower and the slope becomes smaller. Therefore, when the source of the transistor is connected to the second fixed potential GND, when Vgs reaches a certain voltage or higher, the position of the IV curve for each temperature is reversed. The point of reversal is approximately the fixed point X1.

[0077] At a gate-source voltage Vgs below the fixed point X1, the higher the temperature, the greater the drain current Id, and at a gate-source voltage Vgs above the fixed point X1, the higher the temperature, the greater the drain current Id. A circuit that uses the voltage of the fixed point X1 shown in the figure could be considered, but this voltage is too high and difficult to use.

[0078] In the data curve of the current-voltage characteristic shown in FIG. 5, if a tangent line is drawn near Vgs=500mV, the tangent line of the data curve intersects with the horizontal axis at about 350mV, and the slope of the tangent line is about 0.25mS. This can be applied to the current-voltage characteristic of the third transistor M3. In order to set the change amount ΔIb of the first output current Ib to twice the change amount ΔIa of the reference current Ia, it is appropriate to set the resistance value r1 of the first resistor R1 to a value close to the reciprocal of the mutual conductance (the slope of the tangent line (about 0.25mS)) of the third transistor M3 at a specific operating point (e.g., intersection point X0 in FIG. 7). Therefore, the reciprocal of this slope is appropriate as a guide for the resistance value r1 of the first resistor R1, and it is set to about 4kΩ as an initial value for fitting. This value is a guideline value, and is not a final optimized value (e.g., 5kΩ) to obtain the characteristic of FIG. 4, but can be used as a guideline for optimization.

[0079] Next, consider the series combined resistance of the second transistor M2 and the first resistor R1. For example, the series combined resistance (rM2+r1) of the on-resistance rM2 of the second transistor M2 and the resistance value r1 of the first resistor R1 is set to about twice the on-resistance rM1 of the first transistor M1 (rM2+r1=rM1×2=8kΩ). Since the second transistor M2 can pass four times the current of the third transistor M3, the on-resistance rM2 is set to, for example, 1kΩ. These values ​​are only guidelines, and the resistance value r1 of the first resistor R1 actually optimized by a simulator is 5kΩ.

[0080] Next, consider the third resistor R3. If the combined series resistance of the second transistor M2 and the first resistor R1 is 8 kΩ, then the resistance value r3 of the third resistor R3 should be set as follows to satisfy the above-mentioned (Condition 1): r3 = rM1 + rM2 + r1 = 4 kΩ + 8 kΩ = 12 kΩ.

[0081] Next, consider the second resistor R2. According to the above (Condition 2), the resistance value r2 of the second resistor R2 is approximately r2 = r3 = 12 kΩ. These values ​​are only estimates, and the resistance values ​​r2 and r3 actually optimized by the simulator are both 15 kΩ.

[0082] In addition, when these parameters are used as a guideline, if the Vgs of the first transistor M1 and the third transistor M3 are each 0.5V, when VDD=1.2V, 0.2V is applied across the third resistor R3. In this case, the reference current Ia is 16.7μA according to Ohm's law. Referring to Figure 5, this current value is a little smaller than expected. Therefore, using these parameters as a guideline, the parameters of each circuit element are adjusted and matched. In practice, using these values ​​as a guideline, the parameters of each circuit element are optimized using a simulator such as "LTspice" so that the fluctuation of the reference current Is against voltage fluctuation and temperature fluctuation is minimized, and the parameters of each circuit element mentioned above are obtained. When the parameters optimized to obtain the graph of Figure 4 are used, the characteristics of Figure 6 are obtained.

[0083] FIG. 6 is a graph showing the relationship between the first fixed potential VDD (V), the reference current Ia (μA), and the first output current Ib (μA).

[0084] At 0°C (thin solid line), the reference current Ia (μA) increases with an increase in the first fixed potential VDD (V). At 0°C (thick solid line), the first output current Ib (μA) increases at a greater rate than the reference current Ia (μA), and the voltage drop at the second resistor R2 increases. The increase in the first fixed potential VDD and the voltage drop at the second resistor R2 tend to cancel each other out at the third node N3. Therefore, the potential fluctuation at the third node N3 due to the fluctuation in the first fixed potential VDD is suppressed.

[0085] At 50°C (thin dashed line), the reference current Ia (μA) increases with an increase in the first fixed potential VDD (V). At 50°C (thick dashed line), the first output current Ib (μA) increases at a greater rate than the reference current Ia (μA), and the voltage drop across the second resistor R2 increases. Therefore, at 50°C, as at 0°C, the potential fluctuation at the third node N3 due to the fluctuation in the first fixed potential VDD can be suppressed.

[0086] At 100°C (thin dotted line), the reference current Ia (μA) increases with an increase in the first fixed potential VDD (V). At 100°C (thick dotted line), the first output current Ib (μA) increases at a greater rate than the reference current Ia (μA), and the voltage drop across the second resistor R2 increases. Therefore, at 100°C, as at 0°C, the potential fluctuation at the third node N3 due to the fluctuation in the first fixed potential VDD is suppressed.

[0087] When the potential fluctuation of the third node N3 is suppressed, the potential fluctuation applied to the gate of the fourth transistor M4 is suppressed, and therefore the fluctuation of the reference current Is flowing through the fourth transistor M4 is suppressed.

[0088] In the above-mentioned (Condition 3), the change amount ΔIb of the first output current is set to twice the change amount ΔIa of the reference current Ia. To satisfy such a condition, the reference current source of this embodiment uses an inverse Widlar current mirror. In the inverse Widlar current mirror, the first resistor R1 is disposed downstream of the second transistor M2, and the size of the second transistor M2 is different from the size of the third transistor M3. In the example shown in FIG. 2, the size of the third transistor M3 is smaller than that of the second transistor M2, and the change amount of the first output current Ib can be set to approximately twice the change amount of the reference current Ia. Below, a supplementary explanation of the operation of the inverse Widlar current mirror will be given.

[0089] FIG. 7 is a conceptual graph showing the relationship between the voltage V and the current I applied to a circuit element, and is a diagram for explaining an inverse Widlar current mirror.

[0090] The thick solid line (M3) in Fig. 7 shows the characteristics of the drain current Id versus the change in the gate-source voltage Vgs of the third transistor M3. If the size of the second transistor M2 is K times that of the third transistor M3, then the current (second transistor M2) shown by the dotted line in Fig. 7 will be K times the current (third transistor M3) shown by the thick line in Fig. 7. This is shown by the dotted line (M2) in Fig. 7.

[0091] The current I flowing through the first resistor R1 increases linearly in proportion to the voltage V across the resistor (thin solid line (R1) in FIG. 7). When the first resistor R1 and the second transistor M2 are connected in series as in the reference current source SCS, the same current flows through them, so the composite IV characteristic is obtained by adding up the horizontal axis (V) at the same vertical axis (current). This is shown by the dashed line (M2+R1) in FIG. 7. The gate-source voltage Vgs of the third transistor M3 (thick solid line (M3) in FIG. 7) coincides with the voltage between the gate of the second transistor M2 (second node N2 in FIG. 2) and the second fixed potential GND (dashed line (M2+R1) in FIG. 7) at the intersection X0 (voltage V0). That is, at the common gate potential V0, the drain current Id flowing through the second transistor M2 and the drain current Id flowing through the third transistor M3 are equal. When the size of the second transistor M2 is increased (by K times), the position of the intersection point X0 moves to the right on the thick solid line (M3), and the voltage V0 increases.

[0092] Starting from setting the resistance value r1 of the first resistor R1 and the reciprocal rM3 of the mutual conductance of the third transistor M3 to be the same, by adjusting K and r1, the slope of the tangent to the dashed line (M2+R1) at the intersection X0 can be made roughly half the slope of the tangent to the dotted line (M2). In this case, the change in the first output current Ib is roughly twice the change in the reference current Ia.

[0093] In the case where the condition of the intersection point X0 is satisfied, the ratio ka=(ΔIa / ΔV) of the change amount ΔIa of the reference current Ia flowing through the reference current path P0 (second transistor M2) to the voltage change amount ΔV. The ratio kb=(ΔIb / ΔV) of the change amount ΔIb of the first output current Ib flowing through the first output current path P1 (third transistor M3) to the voltage change amount ΔV. As an example, these ratios are set to ka:kb=1:2. In other words, when the first fixed potential VDD (power supply potential) rises and the reference current Ia flowing through the reference current path P0 increases, the first output current Ib tends to increase at twice the reference current Ia. When the first fixed potential VDD rises and the potential of the drain (third node N3 in FIG. 2) of the third transistor M3 tends to rise, the first output current Ib flowing through the third transistor M3 increases, the voltage drop in the second resistor R2 increases, and the potential fluctuation of the third node N3 is suppressed.

[0094] Furthermore, if the voltage drop across one transistor is Vf, then when 2×Vf+α≦first fixed potential VDD (α is the voltage effect due to a resistor or the like) is set, the reference current source operates at this minimum voltage.

[0095] Note that these are merely design guidelines, and in practice, the parameters of the circuit elements are further adjusted using a circuit simulator so as to obtain the graph in Figure 4.

[0096] In the reference current source according to the above-described embodiment, the general operation is as follows: the potential of the first node N1 is increased by 2×Vf from the second fixed potential GND by the second transistor M2 and the first transistor M1, and transferred to the third node N3 located downstream of the second resistor R2 using a current mirror consisting of the second transistor M2, the third transistor M3, and the first resistor R1; the potential of the third node N3 is then reduced by Vf by the fourth transistor M4, and this voltage is applied to the fourth resistor R4 (output resistor).

[0097] This section explains compensation for temperature-related fluctuations in the reference current Is. This reference current source SCS is an excellent circuit that also compensates for fluctuations in the power supply potential, and can perform temperature compensation as described above by fine-tuning the parameters of each circuit element using a simulator.

[0098] The resistors used to obtain the characteristics in Fig. 4 are ideal resistors whose resistance value hardly changes with temperature rise. When various resistors are configured from the on-resistance of transistors, the resistance value increases with temperature rise. However, if the change in resistance value causes a change in the reference current Is, it is sufficient to use a simulator to recalculate and set the parameters of the circuit elements as necessary so that the change in the reference current Is with respect to temperature change is suppressed.

[0099] As described above, the above-mentioned reference current source SCS can suppress the fluctuation of the reference current Is against the power supply potential fluctuation (the fluctuation of the first fixed potential VDD) with a simple structure. In addition, the reference current source SCS can reduce the temperature dependency. That is, the reference current Ia has a temperature characteristic related to the voltage drop of two transistors (2×Vf) in the reference current path P0. The third node N3 has a temperature characteristic related to the voltage drop of one transistor (1×Vf) in the first output current path P1. When the fourth resistor R4 does not have a temperature characteristic, this circuit can eliminate the temperature characteristic of the potential of the source of the fourth transistor M4 and obtain a reference current Is with small temperature dependency. As described above, when the reference current Ia≈the first output current Ib and the resistance value r3 of the third resistor R3=the resistance value r2 of the second resistor R2, the temperature characteristic of the potential of the second node N2 and the temperature characteristic of the potential of the third node N3 become approximately the same. Since this temperature characteristic has voltage fluctuation characteristics equivalent to the Vf of one transistor, when the potential of the fourth transistor M4 is reduced by Vf, the voltage applied across the fourth resistor R4 becomes almost independent of temperature.

[0100] 8 is a circuit diagram of a device including a circuit for extracting a reference current Is from a reference current source SCS. There are numerous ways in which the reference current source SCS can be used, but one example is shown here.

[0101] A differential circuit DIF is provided between a first fixed potential VDD and the fourth transistor M4, instead of the fifth transistor M5 shown in Fig. 2. The differential circuit DIF includes a positive input transistor M51, a negative input transistor M52, a reference transistor M53, and an output transistor M54.

[0102] The positive input transistor M51 is an N-type MOS transistor, the gate of which is supplied with a positive input signal, and the source of which is connected to the drain of the fourth transistor M4. The negative input transistor M52 is an N-type MOS transistor, the gate of which is supplied with a negative input signal, and the source of which is connected to the drain of the fourth transistor M4. The reference transistor M53 is a P-type MOS transistor, the gate of which is connected to the drain and the drain of the positive input transistor M51, and the source of which is connected to the first fixed potential VDD. The output transistor M54 is a P-type MOS transistor, the gate of which is connected to the gate of the reference transistor M53, the source of which is connected to the first fixed potential VDD, and the drain of the negative input transistor M52. The drain of the output transistor M54 is connected to the output terminal Vout, and a capacitor Cout is interposed between the output terminal Vout and the second fixed potential GND.

[0103] The reference current Is flows through the fourth transistor M4 and the fourth resistor R4. The reference current source SCS provides the reference current Is that flows through the differential circuit DIF, and a differential signal is output from the output terminal Vout according to the differential input. The circuit that can be connected to the reference current source SCS is not limited to the differential circuit DIF, and other amplifiers and the like can also be connected.

[0104] FIG. 9 is a circuit diagram of a reference current source according to another embodiment.

[0105] The reference current source SCS shown in Fig. 9 is obtained by replacing the N-type MOS transistor and the P-type MOS transistor in the reference current source SCS shown in Fig. 2 with each other. That is, the first fixed potential VDD shown in Fig. 2 is replaced with a fixed potential GND (ground potential). The second fixed potential GND shown in Fig. 2 is replaced with a fixed potential VDD (power supply potential). The other structure is the same as that shown in Fig. 2. In this way, there are N-channel type (NMOS type) transistors and P-channel type (PMOS type) transistors, and these can operate in the same way even if they are replaced with each other.

[0106] As described above, the reference current source SCS according to the embodiment includes a reference current path P0 including a diode-connected first transistor M1, a diode-connected second transistor M2, and a first resistor R1 connected in series between a first fixed potential VDD and a second fixed potential GND, a first output current path P1 including a third transistor M3 having a gate connected to the gate of the second transistor M2 and constituting a current mirror together with the second transistor M2, and including a second resistor R2 interposed between the third transistor M3 and the first fixed potential VDD (in FIG. 9, the first fixed potential is the ground potential), and a second output current path P2 including a voltage-current conversion circuit 40 to which a potential of a third node N3 between the third transistor M3 and the second resistor R2 in the first output current path P1 is applied and through which a reference current flows.

[0107] According to the reference current source SCS, the stability of the reference current Is can be improved by appropriately setting the parameters of the circuit elements. That is, even if the power supply potential or the ground potential fluctuates or the temperature fluctuates, the potential of the third node N3 is relatively suppressed, and the fluctuation of the reference current Is that depends on the potential of the third node N3 can be suppressed. Also, the reference current source SCS can perform temperature compensation without having a complex temperature compensation circuit, but this does not prevent the provision of a separate temperature compensation circuit.

[0108] In the reference current source SCS according to the embodiment, the size of the second transistor M2 is larger than the size of the third transistor M3. When the first fixed potential VDD fluctuates, the first output current Ib flowing through the third transistor M3 changes more greatly than the reference current Ia flowing through the second transistor M2. Therefore, the voltage drop across the second resistor R2 increases, and the potential fluctuation at the third node N3 is further suppressed. Therefore, the stability of the reference current Is can be improved.

[0109] In the reference current source SCS according to the embodiment, the second transistor M2 is composed of N (1 ≤ N) transistors, the third transistor M3 is composed of M (1 ≤ M) transistors, and the sum of the gate widths of the N transistors constituting the second transistor M2 is K times (1 < K) the sum of the gate widths of the M transistors constituting the third transistor M3. That is, one transistor may be configured by connecting a plurality of sub-transistors in parallel.

[0110] In the reference current source SCS according to the embodiment, the voltage-current conversion circuit 40 includes a fourth transistor M4 having a gate connected to the third node N3, and a fourth resistor (output resistor) connected between the fourth transistor M4 and the second fixed potential GND. As the structure of the voltage-current conversion circuit 40, various structures are known, but this structure has the advantage of being simple.

[0111] In the reference current source SCS according to the embodiment, the size of the fourth transistor M4 is larger than the size of the first transistor M1. When the size of the fourth transistor M4 is made larger than the size of the first transistor M1 and made to be about the same as the size of the second transistor M2, the temperature dependence of the reference current Is tends to decrease. Therefore, the stability of the reference current Is can be improved.

[0112] In the reference current source SCS according to the embodiment, the gate length of one transistor constituting the third transistor M3 is 5 nm or more and not more than 100 nm. That is, when the semiconductor structure is miniaturized, the fluctuation of the reference current Is due to external factors tends to become large, so that the effect of the reference current source SCS according to the embodiment is more remarkable under such conditions.

[0113] As described above, the reference current source according to the embodiment can obtain a reference current that is insensitive to both power supply voltage fluctuations and temperature fluctuations with a simple circuit. The reference current source is composed of only resistors and field effect transistors, and therefore does not require bipolar transistors, which are essential in the BGR circuit. Therefore, the reference current source can be manufactured by a normal CMOS process. The above-mentioned transistors are enhancement type transistors, but depletion type transistors can also be used. The first resistor R1, the second resistor R2, and the third resistor R3 can also be configured using the on-resistance of transistors, etc. The above-mentioned circuit elements are directly electrically connected, but another element may be interposed between the circuit elements if it does not substantially affect the circuit operation. The above-mentioned numerical values ​​have the desired effect even if they include an error of at least ±10%. [Explanation of symbols]

[0114] 40...voltage-current conversion circuit, Cout...capacitor, DIF...differential circuit, M1...first transistor, M2...second transistor, M3...third transistor, M4...fourth transistor, M5...fifth transistor, M11...first upstream transistor, M12...second upstream transistor, M21...first downstream transistor, M22...second downstream transistor, M51...positive input transistor, M52...negative input transistor, M53...reference transistor, M54...output transistor, P0...reference current path, P1...first output current path, P2...second output current path, R1...first resistor, R2...second resistor, R3...third resistor, R4...fourth resistor (output resistor), SCS...reference current source, VDD...first fixed potential, GND...second fixed potential, Vout...output terminal.

Claims

1. a reference current path including a first diode-connected transistor, a second diode-connected transistor, and a first resistor, which are connected in series between a first fixed potential and a second fixed potential; a first output current path including a third transistor having a gate connected to a gate of the second transistor and constituting a current mirror together with the second transistor, the first output current path including a second resistor interposed between the third transistor and the first fixed potential; a second output current path including a voltage-current conversion circuit through which a reference current flows when a potential of a node between the third transistor and the second resistor in the first output current path is applied; Equipped with The voltage-current conversion circuit includes: a fourth transistor having a gate connected to the node; an output resistor connected between the fourth transistor and the second fixed potential; Equipped with Reference current source.

2. The second transistor and the third transistor have equal gate lengths, The gate width of the second transistor is larger than the gate width of the third transistor.

2. The reference current source of claim 1.

3. The second transistor is composed of N transistors (1≦N), and when there are a plurality of transistors, the transistors are connected in parallel, The third transistor is composed of M (1≦M) transistors, and when there are a plurality of transistors, the transistors are connected in parallel, the second transistor and the third transistor have the same gate length; a sum of gate widths of N transistors constituting the second transistor is K times (1<K) a sum of gate widths of M transistors constituting the third transistor; 2. The reference current source of claim 1.

4. The gate lengths of the fourth transistor and the first transistor are equal, The gate width of the fourth transistor is larger than the gate width of the first transistor.

2. The reference current source of claim 1.

5. The gate length of one transistor constituting the third transistor is 5 nm or more and not more than 100 nm. A reference current source according to any one of claims 1 to 4.

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