Isotropic Silicon Nitride Removal

Abstract

An exemplary method for etching silicon-containing materials may include flowing a fluorine-containing precursor into a remote plasma region of a semiconductor processing chamber. The method may include forming a plasma in the remote plasma region to generate plasma effluents of the fluorine-containing precursor. The method may include flowing the plasma effluents into a processing region of the semiconductor processing chamber. A substrate may be disposed in the processing region. The substrate may include a trench formed through stacked layers including alternating layers of silicon nitride and silicon oxide. The method may include isotropically etching the silicon nitride layer while substantially preserving the silicon oxide.

Description

[Technical field]

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application claims the benefit of and priority to U.S. Provisional Application No. 63 / 160,287, entitled "ISOTROPIC SILICON NITRIDE REMOVAL," filed on March 12, 2021, the contents of which are incorporated by reference in their entirety into this specification for all purposes.

[0002]

[0002] The present technology relates to semiconductor processes and equipment. More specifically, the present technology relates to isotropically etching materials relative to other materials. [Background technology]

[0003]

[0003] Integrated circuits are made possible by processes that produce intricately patterned layers of material on a substrate surface. Creating patterned materials on a substrate requires a controlled method for removing exposed material. Chemical etching is used for a variety of purposes, including transferring a pattern of photoresist to an underlying layer, thinning a layer, or narrowing the lateral dimensions of features already present on a surface. It is often desirable to have an etching process that etches some materials faster than others, for example, to facilitate the pattern transfer process. Such an etching process is said to be selective to the first material. Due to the diversity of materials, circuits, and processes, etching processes have been developed that are selective to a variety of materials.

[0004]

[0004] Etching processes can be called wet or dry based on the materials used in the process. Wet HF etching preferentially removes silicon oxide over other dielectrics and materials. However, wet processes have difficulty penetrating some constrained trenches and can sometimes deform the remaining materials. Dry etching is performed in a local plasma formed within the processing area of ​​the substrate, but can penetrate more constrained trenches and causes less deformation of the fragile remaining structures. However, local plasmas can damage the substrate through the generation of electric arcs when they discharge.

[0005]

[0005] Thus, there is a need for improved systems and methods that can be used to manufacture high quality devices and structures. The present technology addresses these and other needs. Summary of the Invention

[0006]

[0006] An exemplary method for etching silicon-containing materials can include flowing a fluorine-containing precursor into a remote plasma region of a semiconductor processing chamber. The fluorine-containing precursor can be XF y and y may be 5 or greater. The method may include forming a plasma in a remote plasma region to generate a plasma effluent of a fluorine-containing precursor. The method may include flowing the plasma effluent into a processing region of a semiconductor processing chamber. A substrate may be disposed within the processing region and may include a trench formed through the trench formed through stacked layers including alternating layers of silicon nitride and silicon oxide. The method may include laterally etching the layer of silicon nitride.

[0007]

[0007] In some embodiments, the method may include stopping the flow of the fluorine-containing precursor after the first period of time. The method may include purging the processing region with a purge precursor. The purge precursor may be or include nitrogen. The method may include flowing an additive precursor with the fluorine-containing precursor. The additive precursor may be or include a halogen other than fluorine. The etch selectivity between silicon nitride and silicon oxide may be about 20:1 or greater. The fluorine-containing precursor may include sulfur, phosphorus, arsenic, silicon, carbon, selenium, or tellurium. The method may be performed at a chamber operating pressure between about 10 mTorr and about 5 Torr. The method may be performed at a chamber temperature of about 20° C. or less. The method may include flowing argon, helium, or nitrogen with the fluorine-containing precursor. The flow ratio of argon, helium, or nitrogen to the fluorine-containing precursor may be about 2:1 or less. The method may include flowing a hydrogen-containing precursor with the fluorine-containing precursor. The method can include forming a passivation layer over the silicon oxide.

[0008]

[0008] Some embodiments of the present technology may include a method of etching a silicon-containing material. The method may include flowing a first halogen-containing precursor and a second halogen-containing precursor into a remote plasma region of a semiconductor processing chamber. The first halogen-containing precursor may include fluorine. The second halogen-containing precursor may include one of chlorine, bromine, or iodine. The method may include forming a plasma in the remote plasma region to generate plasma effluents of the first halogen-containing precursor and the second halogen-containing precursor. The method may include flowing the plasma effluents into a processing region of the semiconductor processing chamber. A substrate may be disposed in the processing region and may include a trench formed through the trench formed through stacked layers including alternating layers of silicon nitride and silicon oxide. The method may include laterally etching the layer of silicon nitride. The method may include stopping the flow of the halogen-containing precursor after the first period of time. The method may include purging the processing region with a purge precursor.

[0009]

[0009] In some embodiments, the method can include forming a passivation layer over the exposed surface of the silicon oxide. The passivation layer can include a polymerized layer of material that includes elements of the second halogen-containing precursor. The first halogen-containing precursor can include sulfur and fluorine. The method can include repeating the method at least 10 cycles. The first period can be about 30 seconds or more. The method can include flowing argon or nitrogen with the halogen-containing precursor. The flow ratio of argon or nitrogen to the halogen-containing precursor can be about 2:1 or less.

[0010]

[0010] Some embodiments of the present technology may include a method of etching a silicon-containing material. The method may include flowing a fluorine-containing precursor into a remote plasma region of a semiconductor processing chamber. The method may include flowing a halogen-containing precursor into a remote plasma region of a semiconductor processing chamber. The halogen-containing precursor may include chlorine, bromine, or iodine. The method may include forming a plasma in the remote plasma region to generate plasma effluents of the fluorine-containing precursor and the halogen-containing precursor. The method may include flowing the plasma effluents into a processing region of the semiconductor processing chamber. A substrate is disposed in the processing region, and the substrate may define a trench formed through stacked layers including alternating layers of silicon nitride and silicon oxide. The method may include isotropically etching the layer of silicon nitride. The method may include stopping the flow of the fluorine-containing precursor and the halogen-containing precursor after a first period of time. The method may include purging the processing region with a purge precursor.

[0011]

[0011] Such techniques may provide many benefits over conventional systems and techniques. For example, the process may selectively isotropically etch silicon nitride within a semiconductor structure. In addition, the process may protect exposed oxide during the etching process. These and other embodiments, along with many of their advantages and features, are described in more detail in conjunction with the following description and accompanying drawings.

[0012]

[0012] A further understanding of the nature and advantages of the disclosed technology may be realized by reference to the remaining portions of the specification and the drawings. [Brief description of the drawings]

[0013] [Figure 1] 1 illustrates a top view of one embodiment of an exemplary processing system in accordance with some embodiments of the present technique. [Figure 2A]

[0014] 1 shows a schematic cross-sectional view of an exemplary processing chamber in accordance with some embodiments of the present technique. [Figure 2B]

[0015] 2B shows a detailed view of a portion of the processing chamber shown in FIG. 2A, in accordance with some embodiments of the present technique. [Diagram 3]

[0016] FIG. 1 illustrates a bottom view of an exemplary showerhead in accordance with some embodiments of the present technique. [Figure 4]

[0017] 1 illustrates exemplary steps of a method according to some embodiments of the present technology. [Diagram 5]

[0018] 1A-C show cross-sectional views of a substrate being processed according to some embodiments of the present technique. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0014]

[0019] Some drawings are included as schematics. It should be understood that the drawings are for illustrative purposes and should not be considered to scale unless expressly stated to be to scale. Furthermore, as schematics, the drawings are provided to aid in understanding and may not include all aspects or information compared to a realistic depiction and may include material that is emphasized for illustrative purposes.

[0015]

[0020] In the accompanying drawings, similar components and / or features may have the same reference numbers. Furthermore, various components of the same type may be distinguished according to the reference numbers, with a letter distinguishing between the similar components. If only a first reference number is used in this specification, the description is applicable to any of the similar components having the same first reference number, regardless of the letter.

[0016]

[0021] In the transition from 2D NAND to 3D NAND, many process operations are changed from vertical to horizontal operations. In addition, as the number of cells formed in a 3D NAND structure increases, the aspect ratio of the memory holes and other structures also increases (sometimes dramatically). During 3D NAND processing, stacks of placeholder layers and dielectric materials may form inter-electrode dielectric layers or IPD layers. A wide variety of operations may be performed on these placeholder layers to position the structure before the material is completely removed and replaced with metal. Metallization may be incorporated on one side of the cell structure, while operations such as forming floating gates or charge trapping layers may be performed earlier on the other side of the structure. These layers may be formed within the memory holes, but crosstalk between vertically separated memory cells may occur. One way to reduce this communication may include etching the placeholder material before forming these layers to allow the dielectric material to further separate individual cell material layers from adjacent cells.

[0017]

[0022] Many conventional techniques utilize wet etching to access each of the cell placeholder materials and perform lateral etching of the placeholders before forming layers such as charge trapping layers. However, wet etching can be more robust than other etching techniques. Wet etching can etch the placeholder materials further than necessary or desired. For example, wet etching can over-etch some features. In addition, wet etching of small form factor structures can cause collapse or deformation of the pattern due to the surface tension of the etchant. The use of wet etchants can also require a subsequent step to remove residues formed in the trenches or holes. Dry etching techniques can also be performed, but many of the dry etchants further etch silicon and silicon oxide, reducing the selectivity of the process.

[0018]

[0023] The present technology overcomes these problems by implementing a dry etching process that can selectively etch silicon nitride laterally while limiting the etching of the oxide. By utilizing a specific precursor combination, the exposed surface of the oxide can be protected during the etching process. In this way, the protective material allows for an etching step to be performed that does not require or only requires minimal removal of the underlying structural material.

[0019]

[0024] While the remainder of the disclosure will routinely identify specific etching processes utilizing the disclosed techniques, it will be readily understood that the systems and methods are equally applicable to deposition and cleaning processes that may occur in the chambers described. Thus, the techniques should not be considered limited to use only with etching processes or chambers. Additionally, while an exemplary chamber is described to provide a foundation for the techniques, it should be understood that the techniques may in fact be applied to any semiconductor processing chamber that may enable the single chamber process described.

[0020]

[0025] FIG. 1 illustrates a top view of one embodiment of a deposition, etch, bake, and cure chamber processing system 100, according to an embodiment. In the figure, a pair of front-opening unified pods 102 deliver substrates of various sizes that are received by a robot arm 104 and placed in a low pressure holding area 106 before being placed in one of the substrate processing chambers 108a-108f, located in tandem sections 109a-109c. A second robot arm 110 may be used to transfer substrate wafers from the holding area 106 to and from the substrate processing chambers 108a-108f. Each substrate processing chamber 108a-f may be equipped to perform several substrate processing steps, including cyclic layer deposition, atomic layer deposition, chemical vapor deposition, physical vapor deposition, etching, pre-cleaning, degassing, orientation, and other substrate processes, as well as dry etching processes as described herein.

[0021]

[0026] The substrate processing chambers 108a-f may include one or more system components for depositing, annealing, curing, and / or etching a dielectric film on a substrate wafer. In one configuration, two pairs of processing chambers (e.g., 108c-d and 108e-f) may be used to deposit a dielectric material on a substrate, and a third pair of processing chambers (e.g., 108a-b) may be used to etch the deposited dielectric. In another configuration, all three pairs of chambers (e.g., 108a-f) may be configured to etch a dielectric film on a substrate. Any one or more of the processes described may be performed in one or more chambers separate from the manufacturing system shown in different embodiments. It will be appreciated that further configurations of deposition, etch, annealing, and curing chambers for the dielectric film are contemplated by the system 100.

[0022]

[0027] 2A shows a cross-sectional view of an exemplary processing chamber system 200 having a plasma generation region partitioned within the processing chamber, which may be configured to perform processes as described further below. During etching of a film (e.g., titanium nitride, tantalum nitride, tungsten, silicon, polysilicon, silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, etc.), process gas may flow through gas injection assembly 205 into first plasma region 215. Remote plasma system 201 may optionally process a first gas included in the system and then travel through gas injection assembly 205. Injection assembly 205 may include two or more separate gas supply channels, where a second channel, if included, may bypass RPS 201.

[0023]

[0028] Cooling plate 203, faceplate 217, ion suppressor 223, showerhead 225, and substrate support 265 with substrate 255 disposed thereon are shown and each may be included according to an embodiment. Pedestal 265 may have heat exchange channels through which heat exchange fluid flows to control the temperature of the substrate. The heat exchange channels may operate to heat and / or cool the substrate or wafer during processing operations. The wafer support platter of pedestal 265, which may comprise aluminum, ceramic, or a combination thereof, may also be resistively heated using embedded resistive heating elements to achieve relatively high temperatures, such as up to about 100° C. or higher, or about 1100° C.

[0024]

[0029] The face plate 217 may be pyramidal, conical, or another similar structure that is narrow at the top and widens toward the bottom. The face plate 217 may also be flat, as shown, or may include multiple through channels used to distribute process gases. Plasma generating gases and / or plasma excited species may pass through multiple holes in the face plate 217 shown in FIG. 2B for more uniform delivery into the first plasma region 215, depending on the RPS 201 used.

[0025]

[0030] An exemplary configuration may include gas inject assembly 205 opening into gas feed region 258 separated from first plasma region 215 by faceplate 217 such that gas / species may flow into first plasma region 215 through holes in faceplate 217. Structural and operational features may be selected to prevent bulk backflow of plasma from first plasma region 215 into feed region 258, gas inject assembly 205, and fluid delivery system 210. Faceplate 217 (or conductive top of the chamber) and showerhead 225 are shown with insulating ring 220 disposed between their features, allowing an AC potential to be applied to faceplate 217 relative to showerhead 225 and / or ion suppressor 223. Insulating ring 220 may be disposed between faceplate 217 and showerhead 225 and / or ion suppressor 223 to allow formation of a capacitively coupled plasma (CCP) in the first plasma region. Additionally, baffles (not shown) may be positioned within first plasma region 215 or otherwise coupled to gas injector assembly 205 to affect the flow of fluid entering this region through gas injector assembly 205. In some embodiments, additional plasma sources may be utilized, including inductively coupled plasma sources extending around the chamber or in fluid communication with the chamber, as well as additional plasma generation systems.

[0026]

[0031] The ion suppressor 223 may include a plate or other geometry that defines a number of apertures throughout the structure. The number of apertures is configured to suppress the movement of ionic charged species out of the first plasma region 215 while allowing uncharged neutral or radical species to pass through the ion suppressor 223 and into the activated gas supply region between the suppressor and the showerhead. In an embodiment, the ion suppressor 223 may comprise a perforated plate having various aperture configurations. These uncharged species may include highly reactive species that are carried with a less reactive carrier gas through the apertures. As discussed above, the movement of ionic species through the apertures may be reduced and in some cases may be completely suppressed. Controlling the amount of ionic species that pass through the ion suppressor 223 may advantageously provide improved control over the gas mixture that is brought into contact with the underlying wafer substrate, thereby providing improved control over the deposition and / or etching characteristics of the gas mixture. For example, adjusting the ion concentration of the gas mixture may significantly change its etch selectivity, e.g., SiNx:SiOx etch ratio, Si:SiOx etch ratio, etc. In alternative embodiments in which deposition is performed, the balance of conformal to flowable deposition for the dielectric material may also be shifted.

[0027]

[0032] The plurality of apertures in the ion suppressor 223 may be configured to control the passage of active gas (i.e., ionic, radical, and / or neutral species) through the ion suppressor 223. For example, the aspect ratio of the apertures (i.e., diameter relative to length of the aperture) and / or the geometry of the apertures may be controlled to reduce the flow rate of ionic charged species in the active gas passing through the ion suppressor 223. The apertures in the ion suppressor 223 may include a tapered section facing the plasma excitation region 215 and a cylindrical section facing the showerhead 225. The cylindrical section may be shaped and dimensioned to control the flow of ionic species passing to the showerhead 225. An adjustable electrical bias may be applied to the ion suppressor 223 as an additional means for controlling the flow of ionic species through the ion suppressor 223.

[0028]

[0033] The ion suppressor 223 may function to reduce or eliminate the amount of ionic charged species that travel from the plasma generating region to the substrate. Uncharged neutral and radical species may further pass through the openings of the ion suppressor to react with the substrate. It should be noted that in embodiments, complete removal of ionic charged species in the reaction region surrounding the substrate may not be performed. In certain cases, ionic species are intended to reach the substrate to perform etching and / or deposition processes. In these cases, the ion suppressor may help control the concentration of ionic species in the reaction region at a process-supporting level.

[0029]

[0034] The showerhead 225, in combination with the ion suppressor 223, may allow the plasma present in the first plasma region 215 to avoid direct excitation of gases in the substrate processing region 233, but still allow excited species to migrate from the chamber plasma region 215 into the substrate processing region 233. In this way, the chamber may be configured to prevent the plasma from contacting the substrate 255 being etched. This advantageously protects various intricate structures and films patterned on the substrate, which may be damaged, displaced, or distorted if the generated plasma comes into direct contact. In addition, when the plasma is allowed to contact the substrate or approach the substrate level, the etch rate of oxide species may increase. Thus, if the exposed area of ​​material is an oxide, this material may be further protected by keeping the plasma away from the substrate.

[0030]

[0035] The processing system may further include a power supply 240 electrically coupled to the processing chamber. The power supply 240 provides power to the face plate 217, the ion suppressor 223, the showerhead 225, and / or the pedestal 265 to generate a plasma in the first plasma region 215 or the processing region 233. The power supply may be configured to provide an adjustable amount of power to the chamber depending on the process being performed. Such a configuration may allow for the use of an adjustable plasma in the process being performed. Unlike remote plasma units that often present an on or off function, an adjustable plasma may be configured to provide a specific amount of power to the plasma region 215. This may allow for the development of specific plasma characteristics that may separate precursors in a specific way and enhance the etch profile produced by these precursors.

[0031]

[0036] A plasma may be ignited in either the chamber plasma region 215 above the showerhead 225 or in the substrate processing region 233 below the showerhead 225. For example, a plasma may exist in the chamber plasma region 215 to generate radical precursors from an inflow of a fluorine-containing precursor or other precursor. To ignite a plasma in the chamber plasma region 215 during deposition, an alternating voltage, typically in the radio frequency (RF) range, may be applied between a conductive top portion of the processing chamber, e.g., faceplate 217, and the showerhead 225 and / or ion suppressor 223. The RF power source may generate a high RF frequency of 13.56 MHz, although other frequencies may be generated alone or in combination with the 13.56 MHz frequency.

[0032]

[0037] FIG. 2B shows a detailed view 253 of features that affect process gas distribution through faceplate 217. As shown in FIGS. 2A and 2B, the intersection of faceplate 217, cooling plate 203, and gas injector assembly 205 defines a gas delivery region 258. Gas delivery region 258 may be supplied with process gas from gas injector assembly 205. Gas may fill gas delivery region 258 and flow through apertures 259 in faceplate 217 to first plasma region 215. Apertures 259 may be configured to direct flow in substantially one direction. This allows process gas to flow into processing region 233 but may be partially or completely prevented from flowing back into gas delivery region 258 after traversing faceplate 217.

[0033]

[0038] A gas distribution assembly such as the showerhead 225 for use in the processing chamber section 200 may be referred to as a dual channel showerhead (DCSH) and is described in further detail in the embodiment depicted in Figure 3. The dual channel showerhead may provide an etching process that allows for separation of etchants outside the processing region 233 and results in limited interaction with the chamber components and each other before being delivered into the processing region.

[0034]

[0039] The showerhead 225 can include an upper plate 214 and a lower plate 216. The plates can be coupled together to define a space 218 between the plates. The plates can be coupled to provide a first fluid channel 219 through the upper and lower plates and a second fluid channel 221 through the lower plate 216. The formed channels can be configured to provide fluid access from the space 218 through the lower plate 216 only via the second fluid channel 221, and the first fluid channel 219 can be fluidly isolated from the space 218 between the plates and the second fluid channel 221. The space 218 can be fluidly accessible through a side of the gas distribution assembly 225.

[0035]

[0040] 3 is a bottom view of a showerhead 325 for use in a processing chamber, according to an embodiment. The showerhead 325 may correspond to the showerhead 225 shown in FIG. 2A. The through-holes 365, which represent the first fluid channels 219, may have a number of shapes and configurations to control and influence the flow of precursors through the showerhead 225. Small holes 375, which represent the second fluid channels 221, may be approximately evenly distributed above the surface of the showerhead, even among the through-holes 365. Compared to other configurations, these small holes 375 may help provide more uniform mixing of the precursors as they flow out of the showerhead.

[0036]

[0041] The aforementioned chambers may be used in performing exemplary methods, including etching methods. Referring to FIG. 4, exemplary steps in a method 400 according to an embodiment of the present technology are shown. Prior to the first step of the method, the substrate may be processed with one or more methods before being placed in a processing region of a chamber in which the method 400 may be performed. For example, an IPD layer may be formed on the substrate, and then one or more memory holes or trenches may be formed through the stacked layers. The IPD layer may include any number of materials and may include alternating layers of placeholder material and dielectric material. In an embodiment, the dielectric material may be or may include silicon oxide. The placeholder material may be or may include silicon nitride. The remaining disclosure discusses silicon nitride and silicon oxide, but any other known materials used for these two layers may be used in place of one or more layers. Some or all of these steps may be performed in a chamber or system tool as described above, or may be performed in different chambers on the same system tool, which may include the chamber in which the steps of the method 400 are performed.

[0037]

[0042] The method 400 may include flowing a fluorine-containing precursor into a remote plasma region of a semiconductor processing chamber at step 405. An exemplary chamber may be the chamber 200 described above, which may include one or both of the RPS unit 201 or the first plasma region 215. Either or both of these regions may be the remote plasma region used in step 405. At step 410, a plasma may be generated in the remote plasma region, and plasma effluents of the fluorine-containing precursor may be generated. At step 415, the plasma effluents may be flowed into a processing region of the chamber. In some embodiments, the plasma effluents may interact with a substrate in the processing region and passivate or protect some portions of the structure at optional step 420. For example, in some embodiments, the plasma effluents may passivate an oxide material. As discussed above, the substrate may include a silicon or silicon-containing substrate or wafer having multiple layers of materials formed thereon, such as alternating layers of silicon oxide and silicon nitride. A memory hole or trench may be formed through the stacked layers extending down to the level of the substrate, providing an exposed portion of the substrate at the bottom of the hole or trench. Thus, within the hole structure, there may be exposed regions of silicon nitride, silicon oxide, and silicon or any silicon-containing material.

[0038]

[0043] The formation of the holes or trenches may have been performed in a different chamber or in some previous process step. If performed in the same chamber as method 400, the exposed portions of the surface of the substrate may be relatively clean or tidy. However, if the process is performed in a different chamber or in a different environment, there may be native oxide formed above the exposed portions of the substrate through the holes or trenches. The native oxide may be different from the oxide formed in the alternating layers of the memory structure. For example, a layer of silicon oxide that may be used to separate memory cells may be a relatively high quality oxide, while the native oxide may be a relatively low quality oxide and relatively porous compared to the layer of silicon oxide.

[0039]

[0044] The etching process for removing silicon nitride may have a relatively high selectivity to silicon oxide, for example, about 100:1 or more. However, in some structures, the amount of silicon nitride removed may be on the order of a few nanometers to a micrometer or more. For example, in some embodiments, the amount of silicon nitride to be recessed may be tens of nanometers to hundreds of nanometers. Such an amount of material may be etched over a relatively long etching period. The selectivity of the nitride removal process to oxide operates in part based on the oxide resistance to the etchant, which may include some fluorine-containing materials. The fluorine will eventually penetrate some of the silicon oxide material, generating volatile material that will be removed as well. However, the process generally includes an incubation period during which the fluorine slowly interacts with the oxide material. The incubation may be performed for 2 minutes, for example, up to 5 minutes, up to 10 minutes, or more, depending on the quality of the oxide, the energy of the fluorine, and other processing conditions. Thus, by forming a silicon oxide passivation, the process may laterally or isotropically etch the silicon nitride in step 425 while the oxide material is affected in a limited manner.

[0040]

[0045] The radical fluorine emissives may contact the semiconductor structure and penetrate into the formed trenches. The silicon nitride may be etched laterally between sections of the silicon oxide, while the exposed surfaces of the silicon oxide are unaffected or minimally affected by the fluorine plasma emissives. Additionally, as described below, in some embodiments, a passivation layer may be formed on the exposed surfaces of the silicon oxide by utilizing certain fluorine-containing precursors, as well as additive precursors, to form a polymerized protective layer over the material.

[0041]

[0046] The extent of this damage or interaction may be related to the power of the plasma used to form the fluorine-containing plasma effluents, as well as the distance traveled by the formed effluents. For example, by utilizing a remote plasma, a relatively low plasma power may be used, such as less than 5 kW, about 3 kW or less, or about 1 kW or less, or about 500 W or less. This may limit the energy of the plasma effluents, as well as the complete dissociation of the precursor material. Additionally, as previously described, by forming a remote plasma, which may include ion filtering before delivery to the substrate, the extent to which the ionic plasma effluents interact with the silicon nitride structure may be limited. For example, a localized plasma may retain enough energy at the wafer level to at least damage the silicon oxide or silicon nitride top layer included in the stack through a bombardment process. Additionally, ionic effluents are often directional, which may provide benefits for anisotropic etching of surfaces perpendicular to the direction of effluent delivery, but may not promote lateral etching. The present technique utilizes neutral or radical species generated in the plasma to generate an isotropic etchant, and silicon nitride may be laterally etched. As the total flow rate is decreased and / or the pressure is increased, as described below, the plasma power may be further decreased to about 400 W or less, about 300 W or less, about 200 W or less, or about 100 W or less, while the plasma is maintained. This may further limit fluorine dissociation and additive precursor dissociation, improving both the selective etching of nitride. This may be more easily accomplished during the initiation period or after saturation, during which oxide etching may occur. Additionally, additive precursors may have reduced dissociation, which may promote the development of a passivation layer in some embodiments.

[0042]

[0047] The etching process may continue for a first period of time in some embodiments. After the first period of time, the flow of the fluorine-containing precursor may be stopped along with the formation of the plasma. A purge may then be performed in optional step 430, which may remove residual etchant material, etch by-products, or other materials from the chamber. The purge may be performed with any number of materials that may be chemically inert, such as nitrogen or a noble gas, that may be used to purge the processing region of the chamber. The purge process may improve etch selectivity and reduce the residence time of these materials in the processing region by facilitating the removal of by-products as well as less beneficial plasma effluents. This may facilitate, for example, lateral etching of silicon nitride while reducing exposure and bombardment to silicon oxide.

[0043]

[0048] The first period of time may be sufficient to produce an etch while limiting residence time that may begin to affect the oxide surface. For example, in some embodiments, the first period of time may be about 5 seconds or more, about 10 seconds or more, about 15 seconds or more, about 20 seconds or more, about 25 seconds or more, about 30 seconds or more, about 35 seconds or more, about 40 seconds or more, about 45 seconds or more, about 50 seconds or more, about 55 seconds or more, about 60 seconds or more, about 2 minutes or more, about 3 minutes or more, about 4 minutes or more, about 5 minutes or more, or more. However, to limit additive effects, in some embodiments, the first period of time may be about 5 minutes or less, about 4 minutes or less, about 3 minutes or less, about 2 minutes or less, or less.

[0044]

[0049] Precursors used in the present technique may include fluorine-containing precursors as well as additional precursors, as described below. An exemplary fluorine-containing precursor is nitrogen trifluoride (NF 3) and may be flowed into a remote plasma region. The remote plasma region may be separate from but fluidly connected to the processing region. Other fluorine sources may be used in conjunction with or as an alternative to nitrogen trifluoride. In general, a fluorine-containing precursor is flowed into the remote plasma region, and the fluorine-containing precursor may include at least one precursor selected from the group consisting of atomic fluorine, diatomic fluorine, nitrogen trifluoride, carbon tetrafluoride, hydrogen fluoride, xenon difluoride, and various other fluorine-containing precursors used or useful in semiconductor processing.

[0045]

[0050] In some embodiments, the fluorine-containing precursor may be characterized by an increase in fluorine content in the molecule of the fluorine-containing precursor. For example, in some embodiments, the fluorine-containing precursor may be characterized by an increase in fluorine content in the molecule of the fluorine-containing precursor. y X can be any number of materials or periodic elements. y can be about 1 or more, about 2 or more, about 3 or more, about 4 or more, about 5 or more, about 6 or more, or more. In some embodiments, fluorine may be replaced with additional halogen elements. The formula designations are merely intended to represent ratios and are not intended to limit the precursor. For example, X 2 F 8 are encompassed by the recited formula, where y would be 4. Further examples encompassed by the formula would be readily apparent as well. The element X can be any of a variety of elements that can form compounds with fluorine or other halides.

[0046]

[0051] For example, non-limiting examples may include any other nonmetal that may combine with a halide, such as sulfur or phosphorus, as well as any other poor metal, transition metal, or other element that may chemically combine with a halogen element. As non-limiting examples, fluorine-containing precursors may include phosphorus pentafluoride, sulfur hexafluoride, and other fluorine or halogen-containing materials. These materials may generate a number of plasma effluent materials that may enhance etching. For example, in the case of sulfur hexafluoride, the precursors may produce S, F, SF, SF, among many other radical and neutral species. 2 ,SCIENCE FICTION 3 ,SCIENCE FICTION 4 ,SCIENCE FICTION5 , F 2 , S 2 F 8 Various elements, including , may be produced to enhance etching.

[0047]

[0052] Any number of halogen-containing precursors, such as fluorine-containing precursors, may be used, but some materials, such as phosphorus and sulfur, may improve selectivity over other materials, such as nitrogen trifluoride, for example, due to the additional effect they may provide with the silicon oxide material. For example, sulfur and phosphorus compounds may create some passivation or protective material on the exposed surface of the silicon oxide. For example, sulfur and phosphorus are elements large enough that some amount of polymerization may occur to create some bridge polymer on the oxide surface. Sulfur may bond with the oxygen surface and be incorporated into the film while maintaining one or more fluorine atoms. This may protect the surface from further fluorination and reaction with the oxygen surface. This may allow etching of the nitride structure while maintaining or limiting any effect on the oxide layer, since there may be no speculative formation on the nitride.

[0048]

[0053] In some embodiments, an additive precursor may be flowed with the silicon-containing precursor. The additive precursor may be or may include a halogen-containing precursor that includes a halogen different from fluorine. For example, the additive precursor may include a precursor that includes any group III, IV, V, or VI element, and any combination of group VII elements or halogens. An exemplary material is represented by the formula X a Y b where X comprises any Group III, IV, V, or VI element, Y comprises chlorine, bromine, or iodine, a is 1, 2, or 3, and b is 3, 4, 5, 6, 7, 8, or 9. The additive precursor formula may also be represented by the formula R 1 R 2 R 3 Precursors characterized by XY, where X is any Group IV element, Y is chlorine, bromine, or iodine, and R 1 ~R3 can be additional group IV elements in any combination, H, methyl, ethyl, or other hydrocarbons, additional halogens, or any other listed materials to extend the chain. For example, without any limitation on the precursors encompassed by the above formula, exemplary precursors can include silicon and chloride in any combination, such as carbon tetrachloride and / or disilicon hexachloride. Similarly, precursors can include carbon and chloride, germanium and chloride, silicon and fluorine, carbon and fluorine, germanium and fluorine, silicon and bromine, carbon and bromine, germanium and bromine, silicon and iodine, carbon and iodine, germanium and iodine, selenium and fluorine, bromine, chlorine or iodine, tellurium and fluorine, bromine, chlorine or iodine, phosphorus and fluorine, bromine, chlorine or iodine, and arsenic and fluorine, bromine, chlorine or iodine. Additionally, the additive precursors may be characterized by one or more methyl groups, such as trimethylsilane.

[0049]

[0054] The additive precursor may act as a passivation precursor as described above. For example, a fluorine-containing precursor may etch materials including silicon nitride as well as silicon oxide after sufficient exposure or without sufficient passivation, while the additive precursor may perform the same passivation step as described above without etching the structure. Other halogen-containing precursors may perform the same function as the fluorine precursors described above, so the same steps may be performed while further controlling the etching step by limiting the additional fluorine content. Any precursor encompassed by the formula above may be used as the additive precursor, but in some embodiments, precursors characterized by silicon-silicon, carbon-carbon, germanium-germanium, or similar atomic bonding structures may be used. This is because the low power plasma may more easily break this bond over the auxiliary portion of the precursor. The additive precursor may also facilitate the repair of etched surfaces. For example, the additive precursor may include silicon as described above. The silicon-containing precursor, once plasma enhanced, may return silicon to silicon oxide when etched. The added silicon may be oxidized when the structure is removed from the processing environment. Water in the atmosphere can react with the silicon to restore the oxidized surface. Thus, the process can limit, prevent, or regenerate silicon oxide and maintain the silicon oxide layer during the etching process. In some embodiments where the additive precursor includes fluorine, the additive precursor can replace the fluorine-containing precursor.

[0050]

[0055] In some embodiments of the present technique, additional precursors may also be provided along with the fluorine-containing precursor. For example, a hydrogen-containing precursor may be provided, or one or more other precursors may be provided, such as argon, nitrogen, helium, an oxygen-containing precursor, or other precursors. Hydrogen and argon are easily ionizable relative to helium, which may facilitate processing in some embodiments. The hydrogen-containing precursor may be or include hydrogen, a hydrocarbon, or any hydrogen-containing precursor. Exemplary oxygen-containing precursors may be or include water vapor, hydrogen peroxide, oxygen, ozone, nitrous oxide, nitric oxide, or excited oxygen-containing materials, although as previously described in some embodiments, the oxygen-containing precursor may not be plasma enhanced to limit interaction with the silicon nitride material through the trench that is subsequently etched. The present technique may further etch silicon. Providing a quantity of an oxygen-containing precursor may facilitate etching.

[0051]

[0056] Without being bound to any particular theory, providing materials such as hydrogen or argon, among other precursors, may facilitate the etching process by providing additional electrons to the process. Fluorine may be a pseudo scavenger of electrons in the plasma, but the additional precursor may donate additional electrons, increasing the electron density in the plasma and improving the etching process and selectivity to nitrides. Thus, in some embodiments, a flow ratio of the fluorine-containing precursor to the additional precursor may be maintained. For example, the flow ratio of the additive precursor and / or additional precursor, such as hydrogen or argon, is maintained at least about 1:2 relative to the fluorine-containing precursor, and may be maintained at about 1:1 or more, about 1.5:1 or more, about 2.0:1 or more, about 2.5:1 or more, about 3.0:1 or more, about 3.5:1 or more, about 4.0:1 or more, or higher. However, the flow ratio may be maintained to limit dilution, which may inhibit additional etching if it becomes high enough. Thus, in some embodiments, the flow ratio of the additional precursor to the fluorine-containing precursor may be maintained at about 10.0:1 or less, about 9.0:1 or less, about 8.0:1 or less, about 7.0:1 or less, about 6.0:1 or less, about 5.0:1 or less, about 4.0:1 or less, about 3.0:1 or less, about 2.0:1 or less, about 1.0:1 or less, or less. For example, an additional precursor such as argon may be included to facilitate plasma formation and provide electrons. However, argon may be removed from the plasma precursor to enhance selectivity if the added precursor is characterized by a lower ionization energy than argon.

[0052]

[0057] Process conditions may also affect the steps performed in method 400. While each of the steps of method 400 may be performed during a constant temperature in embodiments, in some embodiments, the temperature may be adjusted during different steps. The temperature may be maintained in any range, but at higher temperatures, more dissociation of fluorine-containing materials may occur, generating more fluorine radicals. As the amount of fluorine radicals increases, oxides may begin to etch more easily and selectivity may decrease. Thus, in some embodiments, the temperature may be maintained at about 700° C. or less, about 650° C. or less, about 600° C. or less, about 550° C. or less, about 500° C. or less, or less. In some embodiments, the substrate, pedestal, or chamber temperature during the nitride or silicon etch is maintained at a temperature of about 400° C. or less, and in some embodiments the temperature may be maintained at about 350° C. or less, about 300° C. or less, about 250° C. or less, about 200° C. or less, or about 150° C. or less, about 100° C. or less, or about 50° C. or less, about 25° C. or less, about 10° C. or less, about 0° C. or less, about −10° C. or less, about −20° C. or less, or about −30° C. or less, or lower.

[0053]

[0058] At lower process temperatures, the choice of precursors may be increased to reduce or limit free hydrogen. For example, methyl groups may still beneficially passivate exposed oxide surfaces. On the other hand, when temperatures drop below about 20° C., free hydrogen may generate ammonia or fluorimides, which may also etch oxides by generating ammonium fluorosilicate as a by-product. Thus, in some embodiments, hydrogen concentration may be limited to less than 1:1 with any other element of the precursor, and based on the plasma power, limited to methyl groups, which may perform passivation on exposed oxide surfaces during nitride etching.

[0054]

[0059] In some embodiments, the process may be carried out at a variety of pressures to facilitate processing in any of a number of processing chambers. For example, the process may be carried out in a chamber capable of providing a pressure of about 10 mTorr or less, such as with a turbomolecular pump. Additionally, the pressure in the chamber may be maintained at a higher pressure to increase the associated etch rate. The pressure in the processing chamber may be maintained at about 1 Torr or greater, about 2 Torr or greater, about 5 Torr or greater, about 10 Torr or greater, about 50 Torr or greater, about 100 Torr or greater, about 200 Torr or greater, or higher.

[0055]

[0060] The precursor and total flow rate may also facilitate improved silicon nitride etching. For example, argon, helium, nitrogen, or other plasma stabilizing precursor may be provided or maintained at a flow rate of about 100 sccm or less, or may be maintained at a flow rate of about 90 sccm or less, about 80 sccm or less, about 70 sccm or less, about 60 sccm or less, about 50 sccm or less, about 40 sccm or less, about 30 sccm or less, about 20 sccm or less, about 10 sccm or less, or less. By lowering the flow of the plasma stabilizing precursor, dissociation is reduced and lower plasma power can be used to generate the plasma. Etching can be controlled to increase nitride etching. Nitride etching can be more easily performed relative to oxide etching. The flow of the additive precursor, the first halogen-containing precursor, the second halogen-containing precursor, or all precursors may be maintained at or near any of the flow rates described to further control dissociation and improve selectivity of the nitride etch relative to the oxide etch.

[0056]

[0061] By performing an amount of etching followed by an amount of purging, a controlled lateral or isotropic etch of silicon nitride may be performed. To further facilitate the etching, the technique may be performed in several cycles to refresh the silicon oxide, allow removal of etching by-products, and facilitate delivery of etchant into the lateral recesses of the silicon nitride. In some embodiments, the process, including optional purging, may be performed for about 2 or more cycles, about 3 or more cycles, about 4 or more cycles, about 5 or more cycles, about 10 or more cycles, about 20 or more cycles, about 50 or more cycles, about 100 or more cycles, about 200 or more cycles, or more, depending on factors such as the extent of silicon nitride etching performed or other effects of the process.

[0057]

[0062] The benefits of performing additional cycles may include that when hydrogen is combined with the etchant precursor, the hydrogen plasma effluents may beneficially interact with the silicon oxide layer of the stack to extract fluorine that may interact with the layer during each cycle. As previously mentioned, the silicon oxide may eventually react to the process to remove the silicon nitride after an incubation period during which the fluorine interacts with and begins to extend into the oxide structure. However, the hydrogen effluents may not react with the silicon oxide itself, or may only interact minimally, but the effluent energy may be sufficient to draw off fluorine that has begun to interact with the silicon oxide, removing fluorine from the layer when the plasma effluents contact the exposed surface of the silicon oxide layer. By performing a purge as described above, the removed fluorine and reacted hydrogen may be evacuated from the chamber. This may increase the overall selectivity of the silicon nitride etching process to silicon oxide, at least to some extent, by refreshing the incubation period and removing residual etchant from the silicon oxide with each cycle. By carrying out the process as described above, the etch selectivity of silicon nitride to silicon oxide is maintained at about 10:1 or greater, and may produce selectivities of about 15:1 or greater, about 20:1 or greater, about 30:1 or greater, about 50:1 or greater, about 70:1 or greater, about 100:1 or greater, or greater.

[0058]

[0063] 5A-5C, cross-sectional views of a structure 500 being processed according to some embodiments of the present technology are shown. As shown in FIG. 5A, a substrate 505 may have multiple stacked layers overlying the substrate, which may be silicon, silicon germanium, or other substrate material. The layers may include an IPD layer including a dielectric material 510, which may be silicon oxide, in alternating layers with a placeholder material 520, which may be silicon nitride. The placeholder material 520 may be or may include a material that will be removed in subsequent operations to create individual memory cells. Although shown with only seven layers of material, the exemplary structure may include any of the number of layers discussed above. It should be understood that the figures are merely schematic to illustrate aspects of the present technology. A trench 530, which may be a memory hole, may be defined through the stacked structure to the level of the substrate 505. The trench 530 may be defined by sidewalls 532, which may be composed of alternating layers of dielectric material 510 and placeholder material 520.

[0059]

[0064] 5B shows the structure after a method according to the present technique has begun to be performed, as described with respect to FIG. 4 above. A remote plasma of a fluorine-containing precursor, which may include additional precursors, may be formed to generate plasma effluents. The plasma effluents may be delivered to a substrate processing region, where they may interact with the substrate and exposed materials. As described above, while etching silicon nitride or placeholder material 520, plasma effluents of some precursors according to embodiments of the present technique may passivate silicon oxide or generate a protective layer 540 on exposed regions.

[0060]

[0065] 5C shows the structure after further methods or operations according to the present technique have been performed, as described with respect to FIG. 4 above. For example, as the etching process continues, additional passivation or protective material 540 may extend over further exposed surfaces of the dielectric material 510, which may continue to protect the material from vertical etching as the silicon nitride continues to recess during cycles of the process. By utilizing and processing precursors as discussed throughout the present technique, the silicon nitride may be isotropically or laterally etched from between sections of the silicon oxide, while limiting damage or removal of the silicon oxide.

[0061]

[0066] In the preceding description, for purposes of explanation, numerous details have been set forth in order to provide an understanding of various embodiments of the present technology. However, it will be apparent to one skilled in the art that particular embodiments may be practiced without some of these details or with additional details.

[0062]

[0067] Although several embodiments have been disclosed, those skilled in the art will recognize that various modifications, alternative structures, and equivalents may be used without departing from the spirit of the embodiments. Moreover, some well-known processes and elements have not been described to avoid unnecessarily obscuring the present technology. Thus, the above description should not be construed as limiting the scope of the present technology. In addition, although a method or process may be described in a sequence or steps, it should be understood that the steps may be performed simultaneously or in a different order than listed.

[0063]

[0068] Where a range of values ​​is given, each intervening value between the upper and lower limit of that range is specifically disclosed to the smallest unit of the lower limit, unless the context clearly indicates otherwise. Any narrower ranges between any stated or unstated intervening value in a stated range, as well as any other stated or intervening value in that stated range, are also encompassed. The upper and lower limits of these smaller ranges may be individually included or excluded from the range, and each range in which either, neither or both limits are included in the smaller ranges is also encompassed within the scope of this technology, subject to any specifically excluded limits in the stated range. Where a stated range includes one or both of the limits, ranges excluding either or both of those included limits are also included.

[0064]

[0069] As used in this specification and the appended claims, the singular forms "a," "an," and "the" include plural referents unless the context clearly dictates otherwise. Thus, for example, a reference to "a precursor" includes a plurality of such precursors, a reference to "the layer" includes a reference to one or more layers and equivalents thereof known to those skilled in the art, and so forth.

[0065]

[0070] Additionally, the terms "comprise(s)", "comprising", "contain(s)", "containing", "include(s)", and "including", when used in this specification and claims, are intended to specify the presence of stated features, integers, components, or steps, but do not exclude the presence or addition of one or more other features, integers, components, steps, operations, or groups.

Claims

1. 1. A method for etching a silicon-containing material, comprising: flowing a fluorine-containing precursor that includes phosphorus into a remote plasma region of a semiconductor processing chamber; forming a plasma in the remote plasma region to produce a plasma effluent of the fluorine-containing precursor; flowing the plasma effluents into a processing region of the semiconductor processing chamber, the processing region having a substrate disposed therein, the substrate including a trench formed through stacked layers including alternating layers of silicon nitride and silicon oxide; isotropically etching said layer of silicon nitride while substantially preserving said silicon oxide; A method comprising:

2. stopping the flow of the fluorine-containing precursor after a first period of time; purging the processing area with a purge precursor; 10. The method of claim 1 further comprising:

3. 3. The method of etching silicon-containing materials of claim 2, wherein the purge precursor comprises nitrogen.

4. 10. The method of claim 1 further comprising flowing an additive precursor with said fluorine-containing precursor, said additive precursor comprising a halogen other than fluorine.

5. 10. The method of claim 1, wherein the etch selectivity between silicon nitride and silicon oxide is 20:1 or greater.

6. 10. The method of etching silicon-containing materials of claim 1, wherein the method is carried out at a chamber operating pressure between 10 mTorr and 5 Torr.

7. 10. The method of etching silicon-containing materials of claim 1, wherein the method is carried out at a chamber temperature of 20° C. or less.

8. 10. The method of etching silicon-containing materials of claim 1, further comprising flowing argon, helium, or nitrogen with the fluorine-containing precursor.

9. 9. The method of claim 8, wherein a flow ratio of the argon, helium, or nitrogen to the fluorine-containing precursor is 2:1 or less.

10. 10. The method of etching silicon-containing materials of claim 1, further comprising flowing a hydrogen-containing precursor along with the fluorine-containing precursor.

11. 10. The method of etching silicon-containing materials of claim 1 further comprising forming a passivation layer over said silicon oxide.

12. 1. A method for etching a silicon-containing material, comprising: flowing a first halogen-containing precursor and a second halogen-containing precursor into a remote plasma region of a semiconductor processing chamber, the first halogen-containing precursor comprising fluorine and the second halogen-containing precursor comprising one of chlorine, bromine, or iodine; forming a plasma in the remote plasma region to produce plasma effluents of the first halogen-containing precursor and the second halogen-containing precursor; flowing the plasma effluents into a processing region of the semiconductor processing chamber, the processing region having a substrate disposed therein, the substrate including a trench formed through stacked layers including alternating layers of silicon nitride and silicon oxide; allowing fluorine contained in the first halogen-containing precursor to lie dormant above an exposed surface of the silicon oxide for an incubation period to form a passivation layer above the silicon oxide; laterally etching the layer of silicon nitride for a first period of time after the incubation period; stopping the flows of the first halogen-containing precursor and the second halogen-containing precursor after the first period of time; purging the processing area with a purge precursor; A method comprising:

13. 13. The method of etching silicon-containing materials of claim 12, wherein the passivation layer comprises a polymerized layer of a material containing an element of the second halogen-containing precursor.

14. 13. The method of etching silicon-containing materials of claim 12, wherein the first halogen-containing precursor comprises sulfur and fluorine.

15. 13. The method of etching silicon-containing materials of claim 12, further comprising repeating said method for at least 10 cycles.

16. 13. The method of etching silicon-containing materials of claim 12, wherein the first period of time is 30 seconds or longer.

17. 13. The method of etching silicon-containing materials of claim 12, further comprising flowing argon or nitrogen with the first halogen-containing precursor and the second halogen-containing precursor.

18. 20. The method of claim 17, wherein a flow ratio of the argon or nitrogen to the first halogen-containing precursor and the second halogen-containing precursor is 2:1 or less.

19. 1. A method for etching a silicon-containing material, comprising: flowing a fluorine-containing precursor into a remote plasma region of a semiconductor processing chamber; flowing a halogen-containing precursor, including chlorine, bromine, or iodine, into a remote plasma region of a semiconductor processing chamber; forming a plasma in the remote plasma region to produce plasma effluents of the fluorine-containing precursor and the halogen-containing precursor; flowing the plasma effluents into a processing region of the semiconductor processing chamber, a substrate being disposed within the processing region, the substrate defining a trench through stacked layers including alternating layers of silicon nitride and silicon oxide; allowing fluorine contained in the fluorine-containing precursor to lie over the exposed surface of the silicon oxide for an incubation period of at least 2 minutes to form a passivation layer over the silicon oxide; after the incubation period, isotropically etching the layer of silicon nitride for a first period of time of 5 minutes or less; stopping the flows of the fluorine-containing precursor and the halogen-containing precursor after the first period of time; purging the processing area with a purge precursor; A method comprising:

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