Edge ring temperature and bias control

Abstract

To provide a method and a device, used for controlling a processing result profile at a proximal portion of a peripheral edge of a substrate in a plasma assisted processing of the substrate.SOLUTION: In a processing chamber 100 of a substrate 117, a substrate support assembly 115 includes: a first base plate 120; and a second base plate 121 circumscribing the first base plate. The first base plate and the second base plate each include one or more respective first cooling channels 129 and second cooling channels 131 disposed therein. The substrate support assembly further includes: a substrate support body 119 that is arranged on the first base plate and is thermally connected to the first base plate; and a bias ring 122 that is arranged on the second base plate and is thermally couped to the second base plate.SELECTED DRAWING: Figure 1

Description

[Background technology]

[0001] Technical Field

[0001] The embodiments described herein relate generally to semiconductor device manufacturing, and more particularly to methods and apparatus used to control a process profile at and near the peripheral edge of a substrate during plasma processing of the substrate.

[0002] 2. Description of Related Art

[0002] Plasma-assisted etching processes are well known and are commonly used processes of record (POR) in the manufacture of high density integrated circuits to pattern a material layer of a substrate by forming openings in such a material layer. In a typical plasma-assisted etching process, a substrate is positioned on a substrate support disposed in a processing chamber, and a plasma is formed above the substrate. Ions from the plasma are then accelerated toward the substrate and toward openings formed in a mask layer disposed on the substrate to etch openings in a material layer disposed below the mask surface that correspond to the openings in the mask layer.

[0003]

[0003] In many cases, the substrate support is part of a substrate support assembly that further includes an annular ring (herein referred to as an edge ring) located proximate the periphery on the substrate support. The edge ring circumscribes the substrate and protects the dielectric material of the substrate support from erosion that would otherwise be caused by the plasma. Unfortunately, electrical and thermal discontinuities between the substrate edge and a portion of the edge ring located proximate the substrate edge can cause undesirable process result variations at the substrate edge. In plasma-assisted etching processes, undesirable process result variations include non-uniformity (i.e., differences between) the opening profile of an opening etched at the edge or edge of the substrate compared to the profile of an opening etched at a substrate region located radially inward from the edge or edge of the substrate. Excessive process result variations across the surface of the substrate edge can adversely affect and reduce device yield (the percentage of devices that meet performance specifications out of the total number of devices fabricated on the substrate).

[0004] Therefore, there is a need in the art for an apparatus and method for controlling variations in process results at the edge of a substrate during plasma-assisted processing of the substrate. Summary of the Invention

[0005]

[0005] The embodiments described herein provide methods and apparatus used to control a process result profile proximate a peripheral edge of a substrate during plasma-assisted processing of the substrate.

[0006] In one embodiment, the substrate support assembly is characterized by a first base plate and a second base plate circumscribing the first base plate. The first base plate and the second base plate each have one or more first and second cooling channels disposed therein, respectively. The substrate support assembly further features a substrate support disposed on the first base plate and thermally coupled to the first base plate, and a bias ring disposed on the second base plate and thermally coupled to the second base plate, wherein the substrate support and the bias ring are each formed of a dielectric material. The substrate support assembly further includes an edge ring bias electrode embedded in the dielectric material of the bias ring, and an edge ring disposed on the bias ring.

[0007] In another embodiment, a method for processing a substrate includes heating a substrate support of a substrate support assembly to a first temperature, heating an edge ring circumscribing the substrate support to a second temperature, and positioning a substrate on the substrate support, where the substrate support assembly is disposed within a processing volume of a processing chamber and is characterized by a first base plate and a second base plate circumscribing the first base plate. The first base plate and the second base plate each have one or more first and second cooling channels disposed therein, respectively. The substrate support assembly further includes a substrate support disposed on and thermally coupled to the first base plate, and a bias ring disposed on and thermally coupled to the second base plate. The substrate support and the bias ring are each formed of a dielectric material. The substrate support assembly further includes an edge ring bias electrode embedded in the dielectric material of the bias ring, and an edge ring disposed on the bias ring. The method further includes flowing a processing gas into the processing space, igniting and maintaining a plasma of the processing gas, biasing the substrate using a first bias voltage, and biasing the edge ring using a second bias voltage.

[0008] In another embodiment, a processing chamber includes a substrate support assembly disposed within a processing volume of the processing chamber and a computer-readable medium having instructions stored thereon, when executed by a processor, for performing a method of processing a substrate. Here, the substrate support assembly includes a first base plate and a second base plate circumscribing the first base plate. The first base plate and the second base plate each have one or more first and second cooling channels disposed therein, respectively. The substrate support assembly further includes a substrate support disposed on the first base plate and thermally coupled to the first base plate, and a bias ring disposed on the second base plate and thermally coupled to the second base plate. Here, the substrate support and the bias ring are each formed of a dielectric material. The substrate support assembly further includes an edge ring bias electrode embedded in the dielectric material of the bias ring, and an edge ring disposed on the bias ring. A method for processing a substrate includes heating a substrate support to a first temperature, heating an edge ring circumscribing the substrate to a second temperature, and positioning the substrate on the substrate support, the method further including flowing a process gas into a processing space, igniting and maintaining a plasma of the process gas, biasing the substrate using a first bias voltage, and biasing the edge ring using a second bias voltage.

[0009]

[0009] In order that the above-mentioned features of the present disclosure may be understood in detail, a more particular description of the present disclosure briefly summarized above may be obtained by reference to embodiments, some of which are illustrated in the accompanying drawings. It should be noted, however, that the present disclosure may admit of other equally effective embodiments, and therefore, that the accompanying drawings illustrate only typical embodiments of the present disclosure, and therefore, should not be considered as limiting the scope of the present disclosure. [Brief description of the drawings]

[0010] [Figure 1]1 is a schematic cross-sectional view of a processing chamber featuring a substrate support assembly configured to perform the methods described herein, according to one embodiment. [Figure 2A]

[0011] 2 is a schematic cross-sectional view of a portion of a substrate support assembly according to another embodiment that may be used in the plasma processing chamber described in FIG. 1. [Figure 2B] 2 is a schematic cross-sectional view of a portion of a substrate support assembly according to another embodiment that may be used in the plasma processing chamber described in FIG. 1. [Figure 2C] 2 is a schematic cross-sectional view of a portion of a substrate support assembly according to another embodiment that may be used in the plasma processing chamber described in FIG. 1. [Figure 3A]

[0012] 2 is a schematic cross-sectional view of a portion of a substrate support assembly according to another embodiment that may be used in the processing chamber described in FIG. 1. [Figure 3B] 2 is a schematic cross-sectional view of a portion of a substrate support assembly according to another embodiment that may be used in the processing chamber described in FIG. 1. [Figure 4A]

[0013] 2 is an enlarged view of a portion of FIG. 1, illustrating generally the plasma sheath profile formed using the methods described herein. [Figure 4B] 2 is an enlarged view of a portion of FIG. 1, illustrating generally the plasma sheath profile formed using the methods described herein. [Figure 4C] 2 is an enlarged view of a portion of FIG. 1, illustrating generally the plasma sheath profile formed using the methods described herein. [Figure 4D]

[0014] 2 is an enlarged view of a portion of FIG. 1, illustrating generally the effect of varying edge ring temperature using the methods described herein. [Figure 4E] 2 is an enlarged view of a portion of FIG. 1, illustrating generally the effect of varying edge ring temperature using the methods described herein. [Figure 5A]

[0015] 2 is a schematic cross-sectional view of a portion of a substrate support assembly according to another embodiment that may be used in the processing chamber described in FIG. 1. [Figure 5B]

[0016] 2 is a schematic cross-sectional view of a portion of a substrate support assembly according to another embodiment that may be used in the processing chamber described in FIG. 1. [Figure 6A]

[0017] 1 shows comparative measurements of normalized critical dimension (CD) shrinkage near the edge of substrates processed using embodiments of the methods described herein. [Figure 6B] 1 shows comparative measurements of normalized critical dimension (CD) shrinkage near the edge of substrates processed using embodiments of the methods described herein. [Figure 7A]

[0018] 6B shows comparative measurements of normalized etch rates proximate the edge of substrates processed using the same processing conditions described in FIG. 6A. [Figure 7B] 6B. Comparative measurements of normalized etch rates proximate the edge of substrates processed using the same processing conditions described in FIG. 6B. [Figure 8]

[0019] 1 is a flow diagram describing a method of processing a substrate according to embodiments described herein. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011]

[0020] For ease of understanding, the same reference numerals have been used, where possible, to designate identical elements that are common to the figures. It is contemplated that elements and features disclosed in one embodiment may be beneficially incorporated in other embodiments even if such elements and features are not specifically recited.

[0012]

[0021] The embodiments described herein provide methods and apparatus used to control a process result profile proximate a peripheral edge of a substrate during plasma-assisted processing of the substrate. In particular, the methods and apparatus described herein provide for selectively electrically biasing and temperature controlling an annular ring (herein, an edge ring) disposed along the periphery of a surface of a substrate support assembly on which an unprocessed substrate is supported. The biasing and temperature controlling of the edge ring is performed independently of the biasing and temperature controlling of the substrate support on which the unprocessed substrate is disposed.

[0013]

[0022] Independent biasing and temperature control, as occurs between the substrate support and the edge ring, allows fine tuning of the process result profile proximate the edge of the substrate. For example, in a plasma-assisted etch process, the process results on a substrate proximate the substrate edge (e.g., within 15 mm of the edge) are often different from the process results on a substrate at a location radially inward from the substrate edge. This non-uniformity in process results can often be attributed to corresponding discontinuities or changes in the characteristics of the plasma used to perform the process on the substrate, which is formed above the substrate (where the plane of the major surface of the substrate is processed in a horizontal position). Discontinuities or changes in the characteristics of the process plasma include changes in the shape of the plasma region above the substrate and changes in the degree of ionization of the process gas forming the plasma throughout the plasma. Typically, such discontinuities or changes in the process plasma are more pronounced in the edge region of the substrate and in the region disposed above the edge ring proximate the edge region, compared to the region above the substrate inward from the edge of the substrate. Thus, the apparatus and methods presented herein allow fine control of both the edge ring bias and the edge ring temperature, improving upon the differences discussed above.

[0014]

[0023] In many cases, existing substrate processing steps, such as material deposition steps (such as CVD, PVD, and ALD processes) or material removal steps (such as chemical mechanical polishing (CMP) and wet or dry etching processes), can cause feature profile variations or material thickness variations between center and edge regions of a substrate. In such situations, the fine control of both edge ring biasing and edge ring temperature enabled by the embodiments described herein can be used to compensate for center-to-edge non-uniformities due to existing substrate processing steps.

[0015]

[0024] Biasing the edge ring, as shown and described in Figures 1 and 4A-4C, facilitates tuning the shape of the plasma in a region disposed proximate to and above the substrate edge by controlling the shape of the plasma sheath. When the plasma sheath is curved, the trajectory of ions drawn toward the biased substrate differs from the trajectory of ions drawn from the plasma toward the substrate when the sheath is parallel to the substrate surface. Controlling the edge ring temperature affects the concentration of reactive neutral species (e.g., radicals and activated molecules) in the process gas, which in turn tunes the chemical reactions involving reactive neutrals in a region disposed proximate to and above the substrate edge.

[0016]

[0025] FIG. 1 is a schematic cross-sectional view of a plasma processing chamber configured to practice the methods described herein, according to one embodiment. In this embodiment, the processing chamber is a plasma etch processing chamber (such as a reactive ion etch (RIE) plasma chamber). In other embodiments, the processing chamber is a plasma deposition chamber (e.g., a plasma enhanced chemical vapor deposition (PECVD) chamber, a plasma enhanced physical vapor deposition (PEPVD) chamber, or a plasma enhanced atomic layer deposition (PEALD) chamber). In other embodiments, the processing chamber is a plasma processing chamber or a plasma-based ion implantation chamber (e.g., a plasma enhanced doping (PLAD) chamber or a physical vapor deposition (PVD) chamber). In this document, the processing chamber includes an inductively coupled plasma (ICP) source electrically coupled to a radio frequency (RF) power source. In other embodiments, the plasma source is a capacitively coupled plasma (CCP) source (e.g., a plasma electrode disposed in the processing space), where the plasma electrode is electrically coupled to an RF power source and capacitively couples energy and power into a plasma in the chamber.

[0017]

[0026] The processing chamber 100 features a chamber body 101 including a chamber lid 102, one or more sidewalls 103, and a chamber base 104 that collectively define a processing space 105. The processing space 105 is fluidly connected to a processing gas source 106 that supplies processing gas into the processing space 105. The processing chamber 100 further includes a plasma generator 107 configured to ignite and maintain a plasma 108 of processing gas(es) introduced into the processing space through the processing gas source. The plasma generator 107 includes one or more inductive coils 109 disposed proximate the chamber lid 102 at a location outside the processing space 105. The one or more inductive coils 109 are electrically coupled to an RF power source 110. The plasma generator 107 is used to ignite and maintain the plasma 108 by inductively coupling energy from the inductive coil 109, powered by the RF power source 110, to the processing gas(es). Here, the process space 105 is fluidly connected to a vacuum source (such as one or more dedicated vacuum pumps) to maintain the process space 105 at a sub-atmospheric pressure and to evacuate process gases and other gases from the process space 105. Typically, the process chamber includes a system controller 111 that controls the operation of the process chamber and is used to implement the methods described herein.

[0018]

[0027] Herein, the system controller 111 includes a programmable central processing unit (herein, CPU 112) operable with memory 113 (e.g., non-volatile memory) and support circuits 114. The support circuits 114 conventionally include cache, clock circuits, input / output subsystems, power supplies, etc. (and combinations thereof) coupled to the CPU 112 and coupled to various components of the process chamber 100 to facilitate control thereof. The CPU 112 is one of any form of general-purpose computer processor used in industrial environments (e.g., a programmable logic controller (PLC)) to control the various components and sub-processors of the process chamber 100. The memory 113 coupled to the CPU 112 is non-transitory and is typically one or more of readily available memory such as random access memory (RAM), read-only memory (ROM), a floppy disk drive, a hard disk, or any other form of local or remote digital storage.

[0019]

[0028] Typically, the memory 113 is in the form of a computer-readable storage medium (e.g., non-volatile memory) containing instructions that, when executed by the CPU 112, facilitate operation of the process chamber 100. The instructions in the memory 113 are in the form of a program product (e.g., a program implementing the methods of the present disclosure). The program code may conform to any of a number of different programming languages. In one example, the present disclosure may be implemented as a program product stored on a computer-readable storage medium for use with a computer system. The program(s) of the program product define the functions of the embodiments (including the methods described herein).

[0020]

[0029] Exemplary computer-readable storage media include (i) non-writable storage media that permanently store information (e.g., a read-only memory device in a computer, such as a CD-ROM disk readable by a CD-ROM drive, a flash memory, a ROM chip, or any type of solid-state non-volatile semiconductor memory), and (ii) writable storage media that store information that can be changed (e.g., a floppy disk in a diskette drive or hard disk drive, or any type of solid-state random access semiconductor memory). Such computer-readable storage media, when carrying computer-readable instructions that direct the functions of the methods described herein, are embodiments of the present disclosure. In some embodiments, the methods described herein, or portions thereof, are performed by one or more application specific integrated circuits (ASICs), field programmable gate arrays (FPGAs), or other types of hardware implementations. In some other embodiments, the processes described herein are performed by a combination of software routines, ASIC(s), FPGAs, and / or other types of hardware implementations.

[0021]

[0030] The processing chamber 100 further includes a substrate support assembly 115 disposed within the processing space 105. The substrate support assembly 115 is disposed on a support shaft 116 that extends sealingly (e.g., surrounded by a bellows (not shown)) through the chamber base 104 in an area below the chamber base 104 or between the substrate support assembly 115 and the chamber base 104. Typically, a substrate 117 is loaded into the processing space 105 through an opening (not shown) in one of the side walls 103 or more, which is conventionally sealed by a door or valve (not shown) during substrate processing. A number of lift pins 118 movably disposed through the substrate support assembly 115 facilitate the transfer of the substrate 117 to and from the substrate support assembly 115. In a raised position, the lift pins 118 extend above a surface of the substrate support assembly 115 to raise the substrate 117 from the surface and allow access to the substrate 117 by a robotic handler (not shown). In the lowered position, the upper surfaces (not shown) of the lift pins 118 are flush with or below the surface of the substrate support assembly 115 and the substrate 117 rests on the surface of the substrate support assembly 115 .

[0022]

[0031] Here, the substrate support assembly 115 includes a substrate support 119 disposed on and thermally coupled to a first base plate 120, and a second base plate 121 circumscribing the first base plate 120. The substrate support 119 is formed of a dielectric material (e.g., a bulk sintered ceramic material such as silicon carbide (SiC) or a metal oxide or metal nitride ceramic material such as aluminum oxide (Al2O3), aluminum nitride (AlN), titanium oxide (TiO), titanium nitride (TiN), yttrium oxide (Y2O3), mixtures thereof, and combinations thereof). The substrate support 119 is thermally coupled to the first base plate 120 by a thermally conductive adhesive or mechanical means including a thermally conductive material (e.g., a thermally conductive and physically compatible gasket or other electrically conductive material) disposed between the first base plate 120 and the substrate support 119. In some embodiments, one or both of the first base plate 120 and the second base plate 121 are formed of a corrosion-resistant, thermally conductive material (e.g., a corrosion-resistant ceramic or metal, such as aluminum, an aluminum alloy, stainless steel, or aluminum nitride (AlN)).

[0023]

[0032] The substrate support assembly 115 further includes a bias ring 122 disposed on the second base plate 121 and an edge ring 123 disposed on the bias ring 122. The bias ring 122 is typically made of a dielectric material with electrodes embedded therein. The dielectric material may be one of the ceramic materials or a combination of such ceramic materials that may be used to form the substrate support 119, as described above. Typically, the edge ring 123 is formed of a thermally conductive and electrically conductive material (e.g., silicon, graphite, silicon carbide, or a combination thereof). In some embodiments, the edge ring 123 is thermally coupled to the bias ring 122 by a thermally conductive material 124 (such as a silicone gasket) interposed between the edge ring 123 and the bias ring 122. In other embodiments, the thermally conductive material 124 includes a silicone-based or acrylic-based tape or paste.

[0024]

[0033] In some embodiments, guard rings 125a-b are disposed on the inner and outer periphery of the thermally conductive material 124 between the edge ring 123 and the bias ring 122 to protect the thermally conductive material 124 from corrosion caused by the process gases and plasma by preventing exposure to the thermally conductive material 124. The first guard ring 125a circumscribes the thermally conductive material 124 and is therefore disposed proximal and radially outward of the thermally conductive material 124. The second guard ring 125b is disposed proximal and radially inward of the thermally conductive material 124. Here, the guard rings 125a-b are formed of a polymer that is resistant to the process gases and plasma. Examples of suitable polymers include one or more fluorine-containing polymers (fluoropolymers) (e.g., perfluoroalkoxy (PFA), fluorinated ethylene propylene (FEP), polytetrafluoroethylene (PTFE), available commercially from DuPont as TEFLON®, or combinations thereof).

[0025]

[0034] In other embodiments, the edge ring 123 is disposed directly above and in direct contact with the bias ring 122. Typically, in such embodiments, one or both of the interfaces of the edge ring 123 and the bias ring 122 are polished during fabrication. The polished interface between the edge ring 123 and the bias ring 122 increases the contact surface area compared to an unpolished surface, and therefore increases the heat transfer rate between the edge ring 123 and the bias ring 122 as desired. In some embodiments, the DC power source 141 is electrically coupled to an electrode embedded in the bias ring 122, such as the edge ring bias electrode 136 or a second electrode (not shown). In such embodiments, the edge ring bias electrode 136 or the second electrode is used to ensure intimate contact between the bias ring 122 and the edge ring 123 by providing an electric potential between the edge ring 123 and the edge ring bias electrode 136 or the second electrode, thereby creating an electrostatic (ESC) attractive force between them, thereby ensuring a high heat transfer rate.

[0026]

[0035] Here, the substrate support 119 includes one or more chuck electrodes 126 embedded within its dielectric material. The one or more chuck electrodes 126 are used to secure the substrate 117 to the substrate support 119 by providing an electrical potential between the substrate 117 and the chuck electrode(s) 126, thereby creating an attractive electrostatic (ESC) force therebetween. Here, the one or more chuck electrodes 126 are coupled to a chuck power supply 127 (such as a DC power supply) that provides a chucking voltage to the chuck electrode(s) 126.

[0027]

[0036] The substrate support assembly 115 is further configured to bias one or both of the edge ring 123 and the substrate 117 with respect to the plasma 108 formed thereover. Typically, the substrate 117 is biased through capacitive coupling with an electrode to which a substrate bias voltage is applied. The electrode used to provide the bias may be disposed within or beneath the dielectric material of the substrate support 119. In some embodiments, biasing the substrate 117 includes applying a substrate bias voltage to a chuck electrode 126 disposed within the dielectric material of the substrate support 119. In such embodiments, the chuck electrode 126 is electrically coupled to both a chuck power supply 127 and a bias power supply 134 (the electrical coupling between the bias power supply 134 and the chuck electrode 126 is shown in phantom). In such embodiments, the chuck electrode 126 is used to provide both the substrate bias and a DC chucking potential. In some embodiments, biasing the substrate 117 includes applying a substrate bias voltage from a bias power supply 134 to a first base plate 120, which is electrically coupled to the bias power supply 134. In another embodiment, biasing the substrate 117 includes applying a bias voltage to a substrate bias electrode (not shown) embedded in a dielectric material of the substrate support 119. The substrate bias electrode, if used, is typically electrically isolated from the chuck electrode 126 by the dielectric material of the substrate support 119 disposed between the substrate bias electrode and the chuck electrode 126. Typically, the bias power supply 134 provides one or a combination of continuous wave (CW) RF power, pulsed RF power, CW DC power, or pulsed DC power.

[0028]

[0037] Biasing the edge ring 123 includes applying an edge ring bias voltage to the edge ring bias electrode 136, independent of biasing the substrate 117. Here, the edge ring bias electrode 136 is embedded within the dielectric material of the bias ring 122 and is electrically coupled to the bias power supply 134 through a tuning circuit 137 disposed between the edge ring bias electrode 136 and the bias power supply 134. In other embodiments, the edge ring bias electrode 136 is electrically coupled to a second bias power supply 140 that is different from the bias power supply 134 (the electrical connection between the edge ring bias electrode 136 and the second bias power supply 140 is shown in phantom). The independence of biasing the edge ring 123 and biasing the substrate 117 allows fine control of the shape of the plasma sheath 138a proximate the peripheral edge of the substrate 117. Plasma sheath 138a typically defines a dark-space boundary region disposed between the bulk of plasma 108 and the surfaces of substrate 117 and edge ring 123 facing plasma 108. Controlling the shape of plasma sheath 138a is discussed below in the discussion associated with Figures 4A-4C.

[0029]

[0038] In some embodiments, one or both of the first base plate 120 and the second base plate 121 are formed of a thermally conductive, electrically insulating material, such as a metal nitride ceramic material (e.g., aluminum nitride (AlN)). By forming one or both of the first base plate 120 and the second base plate 121 of a thermally conductive, electrically insulating material, cross-talk between the edge ring bias electrode 136 and an electrode used to provide bias power to the substrate (e.g., a substrate bias electrode, described above but not shown) or the chuck electrode 126, as desired, is prevented or substantially eliminated (even though the bias power supply 134 is electrically coupled thereto). As used herein, "cross-talk" refers to undesirable electrical interference between the power provided to each electrode, which can undesirably interfere with the ability to independently control the bias power to each electrode. Typically, cross-talk occurs due to capacitive coupling between the electrodes and the electrically conductive base plate or plates (e.g., aluminum base plates) through the relatively thin dielectric material of the substrate support or bias ring disposed therebetween.

[0030]

[0039] Here, the substrate support assembly 115 further includes one or more first heating elements 128 embedded in the dielectric material of the substrate support 119 and one or more first cooling channels 129 disposed in the first base plate 120. The one or more first heating elements 128 are used to heat the substrate support 119, and thus the substrate 117 disposed thereon, to a desired temperature prior to processing and to maintain the substrate 117 at a desired temperature during processing. The one or more first cooling channels 129 are fluidly coupled to and in fluid communication with a coolant source (not shown), such as a refrigerant or a source of modified water having a relatively high electrical resistance. The first base plate 120 is used to regulate the temperature of the substrate support 119, and thus the substrate 117 disposed thereon, during substrate processing. To facilitate fine control of the temperature of the substrate support 119, and thus the substrate 117 disposed thereon, the first heating element(s) 128 and the flow of coolant through the first cooling channel 129 may be used alone or in combination.

[0031]

[0040] The temperature of the edge ring 123 is maintained and controlled independent of the temperature of the substrate 117 using one or both of the second heating element 130 and the second cooling channel 131. In this embodiment, the second heating element 130 comprises a resistive heating element embedded within the dielectric material of the bias ring 122. The second heating element 130, in combination with a coolant flowing through the second cooling channel 131, is used to heat the bias ring 122, and thus the edge ring 123, which is thermally coupled to the bias ring 122, to a desired temperature prior to substrate processing and to maintain the edge ring at a desired temperature during substrate processing. Here, the bias ring 122 is thermally insulated from the substrate support 119 by a first insulator ring 132 interposed between the bias ring 122 and the substrate support 119.

[0032]

[0041] Here, the second cooling channel 131 disposed in the second baseplate 121 is fluidly coupled and in fluid communication with a coolant source (not shown), which may be the same as or different from the coolant source used to supply cooling fluid to the first cooling channel(s). In embodiments where the same coolant source is used, the flow rate of the coolant through the first cooling channel and the flow rate of the coolant through the second cooling channel are independently controlled to facilitate independent temperature control of each of the first baseplate 120 and the second baseplate 121. Typically, the second baseplate 121 is thermally insulated from the first baseplate 120 by a second insulator ring 133 interposed between the second baseplate 121 and the first baseplate 120. The first insulator ring 132 and the second insulator ring 133 are typically formed of a material suitable for inhibiting heat transfer between the substrate support 119 and the bias ring 122, and between the first baseplate 120 and the second baseplate 121, respectively. Examples of suitable materials that may be suitable for the insulator rings 132, 133 include PTFE, quartz, silicone, and combinations thereof. In some embodiments, no insulator rings are used and the first and second base plates are spaced and insulated from each other by a vacuum placed in the space between them.

[0033]

[0042] Here, the substrate support assembly 115 further includes one or more temperature sensors (e.g., thermocouple 135) disposed within or proximate to the dielectric material of the bias ring 122. The thermocouple 135 is used to monitor the temperature of the bias ring 122 and, therefore, the edge ring 123 thermally coupled thereto. In some other embodiments, one or both of the substrate support 119 and edge ring 123 are heated using their own dedicated heaters disposed below them, as shown in FIG. 2A. In some other embodiments, both the substrate support 119 and edge ring 123 are disposed on a common base plate, as shown in FIG. 3.

[0034]

[0043] 2A is a schematic cross-sectional view of a portion of a substrate support assembly 200a according to an embodiment that may be used in place of the substrate support assembly 115 in the processing chamber 100 depicted in FIG. 1. Here, a first heater (e.g., first heating plate 201) is interposed between the substrate support 119 and the first base plate 120, and a second heater (e.g., second heating plate 202) is interposed between the bias ring 122 and the second base plate 121. The first heating plate 201 is insulated from the second heating plate 202 by a first insulator ring 132 disposed between the first heating plate 201 and the second heating plate 202. The second base plate 121 is insulated from the first base plate 120 by a second insulator ring 133 interposed between the second base plate 121 and the first base plate 120.

[0035]

[0044] 2B is a schematic cross-sectional view of a portion of a substrate support assembly 200b according to an embodiment that may be used in place of the substrate support assembly 115 in the processing chamber 100 depicted in FIG. 1. Here, the substrate support assembly 200b is similar to the substrate support assembly 115 depicted in FIG. 1, but further includes a first electrically insulating plate 203 and a second electrically insulating plate 204. The first electrically insulating plate 203 is interposed between the substrate support 119 and the first base plate 120. The second electrically insulating plate 204 is interposed between the bias ring 122 and the second base plate 121. Here, the second electrically insulating plate 204 circumscribes the first electrically insulating plate 203 and is thermally insulated from the first electrically insulating plate 203 by the first insulator ring 132 and / or the second insulator ring 133 interposed therebetween.

[0036]

[0045] Typically, one or both of the first and second electrically insulating plates 203 and 204 are formed of a thermally conductive and electrically insulating material, such as a metal nitride ceramic material (e.g., aluminum nitride (AlN)). The electrically insulating plates 203 and 204 prevent or substantially eliminate crosstalk between the edge ring bias electrode 136 and an electrode used to provide bias power to the substrate (e.g., a substrate bias electrode, described above but not shown) or the chuck electrode 126, as desired (even though the bias power supply 134 is electrically coupled thereto). In some embodiments, one or both of the electrically insulating plates 203 and 204 have a thickness sufficient to substantially eliminate or significantly reduce capacitive coupling between the respective electrodes disposed thereon and the respective base plates disposed thereunder. For example, in some embodiments, one or both of the electrically insulating plates 203 and 204 have a thickness greater than about 5 mm (e.g., greater than about 10 mm), or, for example, between about 5 mm and about 50 mm.

[0037]

[0046] FIG. 2C is a schematic cross-sectional view of a portion of a substrate support assembly 200c according to an embodiment that may be used in place of the substrate support assembly 115 in the processing chamber 100 described in FIG. 1. Here, the substrate support assembly 200c is similar to the substrate support assembly 115 described in FIG. 1, but further includes an electrically insulating plate 204 interposed between the second base plate 121 and the bias ring 122. The substrate support assembly 200c does not include the electrically insulating plate 203 described in FIG. 2B, and the first base plate 120 is supported by at least a portion of the facility plate 205. The facility plate 205 provides structural support to the substrate support assembly 200c and may be used with one or any combination of the embodiments described herein. In other embodiments, the substrate support assembly may include the electrically insulating plate 203 and not include the electrically insulating plate 204. Including one electrically insulating plate but not the other further reduces or substantially eliminates crosstalk between the bias electrodes and reduces the manufacturing cost of the substrate support assembly.

[0038]

[0047] 3A is a schematic cross-sectional view of a portion of a substrate support assembly 300b according to another embodiment that may be used in place of the substrate support assembly 115 in the processing chamber 100 described in FIG. 1. Here, both the substrate support 119 and the bias ring 122 are disposed on a common base plate 301. The temperature of the base plate 301 is adjusted using one or more cooling channels 302 disposed therein. The one or more cooling channels 302 are fluidly coupled to and in fluid communication with a coolant source (not shown), such as a coolant or a source of modified water having a relatively high electrical resistance. The base plate 301 is used to adjust the temperature of the substrate support 119 and the bias ring 122 during substrate processing, and thus the temperature of the substrate 117 and the edge ring 123 disposed on the substrate support 119 and the bias ring 122, respectively. Here, the substrate support 119 and the bias ring 122 are insulated from each other by an insulator ring 303 interposed therebetween. In this embodiment, the substrate support 119 and bias ring 122 each include a corresponding heating element 128, 130 embedded within their dielectric material. In other embodiments, the substrate support 119 and bias ring 122 are heated using a heating plate (e.g., heating plates 201, 202 shown in FIG. 2).

[0039]

[0048] Typically, the bias ring 122, and thus the edge ring 123 disposed thereon, is maintained at a desired temperature or within a desired temperature range using measurements provided by one or more thermocouples 135. The measured temperature(s) are communicated to the system controller 111, which compares the measured temperature(s) with a desired temperature setpoint or desired temperature range. If the measured temperature is below the desired temperature setpoint or below the desired temperature range, the system controller 111 increases the heat flow to the edge ring 123. Typically, the heat flow to the edge ring 123 is increased by applying power to or increasing the power provided to the second heating element 130 shown in Figures 1 and 3, or the second heating plate 202 shown in Figure 2. If the measured temperature is above the desired temperature setpoint or above the desired temperature range, the system controller 111 removes heat from the edge ring 123. Typically, heat is removed from the edge ring 123 by turning off or reducing the power applied to the bias ring 122, varying the coolant flow rate to the second base plate 121 shown in Figures 1 and 2 or the integrated base plate shown in Figure 3A, or a combination thereof. In some embodiments, the substrate support assembly 300a further includes one or both of a first electrically insulating plate 203 and a second electrically insulating plate 204 (see Figure 2B) interposed between the base plate 301 and the substrate support 119 or between the base plate 301 and the bias ring 122, respectively.

[0040]

[0049] Figure 3B is a schematic cross-sectional view of a portion of a substrate support assembly 300b according to an embodiment that may be used in place of the substrate support assembly 115 in the processing chamber 100 depicted in Figure 1. Here, the substrate support assembly 300b further includes a common electrically insulating plate 304 interposed between the common base plate 301 and the substrate support 119 and bias ring 122. The electrically insulating plate 304 may be formed of the same materials and have the same thickness as described above in connection with the first and second electrically insulating plates 203 and 204.

[0041]

[0050] 4A-4C are schematic cross-sectional views of a portion of the processing chamber 100 shown in FIG. 1, illustrating the shape of plasma sheaths 138a-c, respectively, proximate the edge of the substrate 117. Here, the shape of the plasma sheaths 138a-c is controlled by adjusting the ratio of the bias voltage applied to the substrate 117 and the bias voltage applied to the edge ring 123, using methods described herein. Typically, increasing the bias voltage provided to the edge ring 123 results in a relatively thicker plasma sheath 138b above the edge ring 123, as compared to when a lower or no bias voltage is applied to the edge ring 123.

[0042]

[0051] 4A , plasma sheath 138a has a uniform thickness across a region disposed above substrate 117 and across a region disposed above a portion of edge ring 123 proximal to substrate 117. The uniform thickness of plasma sheath 138a promotes acceleration of ions from plasma 108 toward the surface of substrate 117 on trajectories 401 that are substantially uniform and perpendicular to the surface of substrate 117 even proximate the edge of substrate 117.

[0043]

[0052] In Figure 4B, the plasma sheath 138b is thicker in the region disposed above the edge ring 123 than in the region disposed above the substrate 117. As shown in Figure 4B, the plasma sheath 138b curves away from the edge of the substrate 117 in the region disposed above the edge of the substrate 117. Here, the ion trajectories 401 from the plasma 108 to the underlying edge of the substrate 117 are tilted toward the edge ring 123. Thus, the ion trajectories 401 near the edge of the substrate in Figure 4B are less focused than those in Figures 4A and 4C, resulting in a relatively slower etch rate near the edge of the substrate.

[0044]

[0053] In FIG. 4C, the plasma sheath 138c is thinner in the region disposed above the edge ring 123 than in the region disposed above the substrate 117. As shown in FIG. 4C, the plasma sheath bends toward the edge of the substrate 117 in the region disposed above the edge of the substrate 117. Here, the ion trajectories 401 from the plasma 108 toward the substrate 117 are angled away from the edge ring 123 around the periphery of the substrate 117. Thus, the ion trajectories 401 near the edge of the substrate in FIG. 4C are more focused than those in FIGS. 4A and 4B, resulting in a relatively increased concentration of ions bombarding the substrate, and therefore an etch rate near the edge of the substrate. By decreasing or increasing the focusing of the ion trajectories 401 near the edge of the substrate 117, the etch rate at the edge can be tuned to be slower or faster, respectively, compared to the remainder of the substrate disposed radially inward from the edge.

[0045]

[0054] In addition to increasing or decreasing the focusing of ions bombarding the substrate surface proximate the substrate edge, tuning the curvature of the plasma sheath changes the orientation of the aperture etched into the material layer(s) of the substrate. For example, in FIG. 4A, the trajectories 401 of ions impacting the substrate surface proximate the substrate edge are substantially perpendicular to the substrate surface, and the apertures (not shown) formed in the substrate surface are also substantially perpendicular to the substrate surface. In FIGS. 4B and 4C, the ion trajectories 401 are tilted away from or towards the center of the substrate 117, respectively, and the resulting apertures are tilted according to the tilt of the ion trajectories 401. Thus, the angle of the etched aperture can be tuned by the edge ring bias power to compensate for the effects of other chamber components causing tilt of features at the edge of the substrate (e.g., non-uniform plasma distribution due to the plasma source or bias, or wear of the edge ring over the useful manufacturing life of the substrate support).

[0046]

[0055] 4D and 4E show schematic diagrams of the effect of edge ring temperature on neutral reactant concentration near and above the edge of a substrate, where the edge ring 123 of FIG. 4D is maintained at a lower temperature than the edge ring 123 of FIG. 4E. The etch rate profile and polymer deposition profile from a location at the edge of the substrate to a location located radially inward from the edge of the substrate are represented diagrammatically by arrows 405 and 407, respectively. When the edge ring temperature is relatively low (FIG. 4D), more polymerizing species 403 tends to be deposited on the edge ring 123, resulting in a lower concentration of polymerizing species above the edge ring 123 near the substrate edge. Thus, relatively less polymer is deposited on the substrate edge, resulting in an edge-high etch rate profile (i.e., a higher etch rate at the edge of the substrate compared to a region located radially inward from the edge of the substrate). On the other hand, when the edge ring temperature is relatively high (FIG. 4E), less polymer deposition occurs on the edge ring 123 and the concentration of polymerizing species is high near the edge of the substrate. Thus, more polymer is deposited on the edge of the substrate, resulting in an edge-slowing etch rate profile (i.e., the etch rate is slower at the edge of the substrate compared to regions located radially inward from the edge of the substrate).

[0047]

[0056] In other embodiments, a large bias power applied to the edge ring can serve, in part, to increase the edge ring temperature to reduce polymer deposition on the edge ring and thus increase the concentration of polymerized species above the substrate edge, hi other embodiments, the bias power applied to the edge ring can be a tuning knob to increase or decrease the process sensitivity near the substrate edge to the edge ring temperature.

[0048]

[0057] 5A and 5B are schematic cross-sectional views of a portion of a substrate support assembly according to some embodiments, which may be combined with one of the other embodiments of the substrate support assembly described herein or a combination of such other embodiments. In FIG. 5A, the substrate support assembly 500a may be any of the substrate support assemblies shown in FIGS. 1 to 4 or described in the description of such figures, and further includes an electrical insulator ring 502 made of a dielectric material (such as quartz or metal oxide ceramic) disposed on the edge ring 123. Typically, the plasma-facing surface of the electrical insulator ring 502 has a lower etch rate than the plasma-facing surface of the edge ring 123 (when the electrical insulator ring 502 is not disposed thereon), and thus the substrate processing life of the substrate support assembly 500a is extended as desired. In other embodiments, the electrical insulator ring 502 is formed of a material that is less likely to generate particles in the chamber for defect control.

[0049]

[0058] FIG. 5B is a schematic cross-sectional view of a portion of a substrate support assembly according to another embodiment that may be used in the processing chamber described in FIG. 1. In FIG. 5B, the substrate support assembly 500b may be any of the substrate support assemblies shown and described in FIGS. 1 to 3, or may include any combination of features of such substrate support assemblies. Here, the edge ring 123 extends above the plane of the plasma-facing surface of the substrate by a height H. (i.e., the plasma-facing surface of the edge ring 123 is higher than the plasma-facing surface of the substrate 117.) Typically, when the processing and bias conditions are the same, the thickness of the sheath disposed above the edge ring is the same. Given the processing and bias conditions shown in FIG. 4A, extending the plasma-facing surface of the edge ring 123 above the plane of the plasma-facing surface of the substrate 117 pushes up the sheath to generate a plasma profile similar to that of FIG. 4B. Thus, extending the plasma-facing surface of edge ring 123 above the plane of the plasma-facing surface of substrate 117 allows for the formation of the plasma profile of Figure 4B at a relatively lower edge bias power compared to configurations in which the bias ring and substrate surface are coplanar. In other embodiments, edge ring 123 is recessed below the plane of the substrate surface, and the same processing conditions as described in Figure 4A result in a plasma profile more similar to that of Figure 4C.

[0050]

[0059] Graphs 600a-b in Figures 6A-6B, respectively, show comparative measurements of normalized critical dimension (CD) shrinkage proximate the edge of substrates processed using method embodiments described herein, and graphs 700a-b in Figures 7A-7B, respectively, show comparative measurements of normalized etch rate proximate the edge of substrates processed using the same processing conditions described in Figures 6A-6B, respectively.

[0051]

[0060] CD shrink allows for the patterning of openings in the surface of the substrate, where the openings have dimensions below a lithography defined dimension in a photoresist layer disposed above it. Typically, the photoresist layer is formed on a multi-layer mask disposed on the surface of the unprocessed substrate to be etched. The openings in the photoresist layer and the multi-layer mask are formed by forming a plasma of a process gas that includes an etchant and a polymerizing gas, and exposing the substrate on which the multi-layer mask and the photoresist layer are formed to the plasma. As features are formed in the multi-layer stack, the polymerizing gas forms a polymerizing passivation layer on the sidewalls of the openings etched in the multi-layer stack to reduce the CD of the etched features. Thus, the dimensions of the openings formed in the surface of the substrate are reduced, or shrink, compared to the lithography defined dimensions patterned in the photoresist layer. Typically, the polymerizing passivation layer forms faster on a relatively cool surface than on a warm surface. This is because the sticking coefficient, and therefore the absorption, of the polymerizing species is higher on the cool surface.

[0052]

[0061] In Figures 6A-6B and 7A-7B, each substrate was processed by forming a plasma of an etchant gas and a polymerizing gas, biasing the substrate, and exposing the substrate to the plasma, where the etchant and polymerizing gas included flow rates of 100 sccm CHF3, 50 sccm CF4, 100 sccm N2, and 100 sccm Ar. The substrates were subjected to a 0.14 W / cm2 charge relative to the substrate surface area. 2 The wafers were biased using a bias power of 100 W and the edge ring bias was varied between about 10 W and about 60 W. The radius of each substrate processed was 150 mm. The CD shrinkage shown in FIGS. 6A-6B was measured at multiple radial locations located between about 105 mm and about 145 mm from the center of the substrate. The example etch rate shown in FIGS. 7A-7B was measured at multiple radial locations located between about 100 mm and about 150 mm from the center of the substrate.

[0053]

[0062] The edge ring was biased in FIG. 6A using a lower bias voltage than the bias voltage applied to the edge ring in FIG. 6B. In FIGS. 6A and 6B, substrates 601a-b, 602a-b, and 603a-b, respectively, were processed using edge rings maintained at three different temperatures relative to the temperature of the substrate support on which the substrates were placed. For substrates 601a,b, the temperature of the edge ring was maintained at about 30° C. lower than the temperature of the substrate support to provide a temperature difference of Δ−30° C. between the edge ring and the substrate support. For substrates 602a,b, the temperature of the edge ring was maintained at about 40° C. higher than the temperature of the substrate support to provide a temperature difference of Δ+40° C. between the edge ring and the substrate support. For substrates 603a,b, the temperature of the edge ring was maintained at approximately the same temperature as the substrate support to provide a temperature difference of Δ0° C. between the edge ring and the substrate support.

[0054]

[0063] In both Figures 6A and 6B, decreasing the temperature of the edge ring relative to the substrate 601a,b decreases the CD shrinkage at the edge of the substrate compared to the CD shrinkage measured at a location located radially inward from the edge of the substrate. In both Figures 6A and 6B, increasing the temperature of the edge ring relative to the substrate 602a,b increases the CD shrinkage at the edge of the substrate compared to the CD shrinkage measured at a location located radially inward from the edge of the substrate. As shown in Figures 6A and 6B, tuning the edge ring temperature provides an effective tuning knob for tuning the CD profile at the edge of the substrate.

[0055]

[0064] It is noted that the effect of edge ring temperature variations on both decreasing and increasing CD shrink at the edge of the substrate is more pronounced when the edge ring is biased using a relatively low bias voltage (see FIG. 6A) than when the edge ring is biased using a high edge ring bias voltage (see FIG. 6B). This suggests that the effect of edge ring temperature tuning can be magnified or reduced by controlling the edge ring biasing and, therefore, the thickness of the plasma sheath formed above the edge ring.

[0056]

[0065] 7A-7B show comparative measurements of example etch rates proximate the edge of substrates processed using embodiments of the methods described herein. In FIG. 7A, the edge ring was biased using a lower bias voltage than the bias voltage applied to the edge ring in FIG. 7B. Here, substrates 701a-b, 702a-b, and 703a-b were processed using the same process conditions as described for substrates 601a-b, 602a-b, and 603a-b in FIGS. 6A and 6B, respectively. For substrates 701a,b, the temperature of the edge ring was maintained at about 30° C. lower than the temperature of the substrate support to provide a temperature difference of Δ−30° C. between the edge ring and the substrate support. For substrates 702a,b, the temperature of the edge ring was maintained at about 40° C. higher than the temperature of the substrate support to provide a temperature difference of Δ+40° C. between the edge ring and the substrate support. For substrates 703a,b, the temperature of the edge ring was maintained at approximately the same temperature as the substrate support to provide a Δ0° C. temperature difference between the edge ring and the substrate support.

[0057]

[0066] In both Figures 7A and 7B, decreasing the temperature of the edge ring relative to the temperature of the substrates 601a,b generally increases the etch rate measured at the edge of the substrate compared to the etch rate measured radially inward from the edge of the substrate. In both Figures 7A and 7B, increasing the temperature of the edge ring relative to the temperature of the substrates 702a,b generally decreases the etch rate measured at the edge of the substrate compared to the etch rate measured radially inward from the edge of the substrate.

[0058]

[0067] Similar to the CD shrink measurements described in Figures 6A and 6B, the effect of edge ring temperature variations in both decreasing and increasing the etch rate toward the edge of the substrate is more pronounced when the edge ring is biased using a relatively low bias voltage (see Figure 7A) than when the edge ring is biased using a high edge ring bias voltage (see Figure 7B). As above, this suggests that the effect of edge ring temperature tuning can be magnified or reduced by controlling the biasing of the edge ring, thereby controlling the thickness of the plasma sheath that forms above the edge ring.

[0059]

[0068] FIG. 8 is a flow diagram describing a method 800 of processing a substrate using a substrate support assembly configured according to embodiments described herein. In activity 801, the method includes positioning a substrate on a substrate support assembly disposed within a processing space of a processing chamber (such as the processing chamber described in FIG. 1). Here, the substrate support assembly is characterized by a first base plate and a second base plate circumscribing the first base plate. Each of the first base plate and the second base plate includes one or more first and second channels disposed therein, respectively. The substrate support assembly further includes a substrate support disposed on the first base plate and thermally coupled to the first base plate, and a bias ring disposed on the second base plate and thermally coupled to the second base plate. Here, the substrate support and the bias ring are each formed of a dielectric material. The bias ring further includes an edge ring bias electrode embedded in the dielectric material of the bias ring and an edge ring disposed on the bias ring.

[0060]

[0069] The method 800 includes, at activities 802 and 803, respectively, heating the substrate to a first temperature and heating an edge ring circumscribing the substrate to a second temperature. Typically, the substrate support, and thus the substrate disposed thereon, are heated to the first temperature using a first heater disposed between the substrate support and a first base plate or embedded in the dielectric material of the substrate support. The bias ring, and thus the edge ring disposed thereon, are heated to the second temperature using a second heater disposed between the bias ring and a second base plate or embedded in the dielectric material of the bias ring. In some embodiments, the method 800 further includes maintaining the substrate at or within a desired temperature range and maintaining the edge ring at or within a desired temperature range. Here, the temperature of the edge ring and the temperature of the substrate support are controlled independently of each other. Controlling the edge ring temperature allows tuning the concentration of polymerizable species in the plasma near the edge ring and proximate the edge of the substrate, and thus tuning the process profile.

[0061]

[0070] At activities 804 and 805, the method 800 includes flowing a process gas into a process space of a process chamber and igniting and maintaining a plasma of the process gas, respectively.

[0062]

[0071] At activities 806 and 807, the method 800 includes biasing the substrate using a first bias voltage; and biasing the edge ring using a second bias voltage, where biasing the substrate includes applying a first bias voltage to one of the first base plate, a chuck electrode embedded in the dielectric material of the substrate support, or a bias electrode embedded in the dielectric material of the substrate support, and biasing the edge ring includes applying a second bias voltage to an edge ring bias electrode embedded in the dielectric material of the bias ring.

[0063]

[0072] At activity 808, the method 800 includes determining a ratio between the first bias voltage and the second bias voltage. At activity 809, the method 800 includes adjusting the second bias voltage to achieve the target voltage ratio. In some embodiments, the first bias voltage is maintained at a constant voltage while the second bias voltage is adjusted to achieve the target voltage ratio.

[0064]

[0073] The methods described herein advantageously enable fine control and tuning of plasma characteristics in a region located proximate to and above the edge of a substrate being processed. Fine control and tuning of the plasma characteristics enables fine control and tuning of the process result profile at the substrate edge. Advantages of the embodiments herein further include eliminating or substantially reducing substrate-to-substrate process variations that may result from an edge ring that does not have temperature control continuing to increase in temperature after the processing chamber reaches an idle state (e.g., the first wafer effect).

[0065]

[0074] While the above is directed to embodiments of the disclosure, other and further embodiments of the disclosure may be devised without departing from the basic scope thereof, the scope of which is determined by the following claims.

Claims

1. 1. A substrate processing system comprising a substrate support assembly, the substrate support assembly comprising: A base plate; a first bias electrode disposed over the base plate and spaced from the base plate by a first portion of a dielectric material; a second portion of dielectric material disposed over the first bias electrode and forming a substrate support surface; a second bias electrode disposed a distance from a center of the substrate support surface and spaced from the first bias electrode by a third portion of dielectric material; an insulator ring disposed between the first portion of dielectric material and the third portion of dielectric material; a pulsed DC bias system configured to supply a first pulsed DC voltage to the first bias electrode and a second pulsed DC voltage to the second bias electrode, the pulsed DC bias system including a first pulsed DC power supply electrically coupled to the first bias electrode; a chuck power supply electrically coupled to the first bias electrode, the chuck power supply configured to provide a DC chucking voltage to electrically clamp a substrate to the substrate support surface; A substrate processing system comprising:

2. 2. The substrate processing system of claim 1 , wherein the second bias electrode is spaced from the plasma-facing surface by a fourth portion of dielectric material disposed between the second bias electrode and the plasma-facing surface of the substrate support assembly.

3. The substrate processing system of claim 1 , wherein the second bias electrode is electrically coupled to a second pulsed DC power supply.

4. The substrate processing system of claim 1 , further comprising an edge ring disposed above the second bias electrode and surrounding the substrate support surface.

5. The substrate processing system of claim 1 , wherein the second bias electrode is electrically coupled to the first pulsed DC power supply.

6. 6. The substrate processing system of claim 5, further comprising a tuning circuit configured to adjust the second pulsed DC voltage relative to the first pulsed DC voltage.

7. The method further comprises a non-transitory computer readable medium having instructions stored thereon for performing a method for processing a substrate, the method comprising: (a) igniting and maintaining a plasma in a process volume of a processing chamber, the process volume having the substrate support assembly disposed therein; (b) applying a chucking voltage to the first bias electrode to electrically clamp the substrate to the substrate support surface; (c) applying the first pulsed DC voltage to the first bias electrode; (d) applying the second pulsed DC voltage to the second bias electrode; The substrate processing system of claim 1 .

8. The method further comprising: (e) adjusting the second pulse DC voltage based on the first pulse DC voltage. The substrate processing system of claim 7 further comprising:

9. 8. The substrate processing system of claim 7, further comprising a chamber lid, one or more chamber walls, and a chamber base that collectively define the processing space, wherein a plurality of electrodes are disposed in the processing space, the plurality of electrodes including the base plate, the first bias electrode, and the second bias electrode.

10. 1. A substrate processing system, comprising: a chamber lid, one or more chamber walls, and a chamber base that collectively define a processing space; a plurality of electrodes disposed in the processing space, the plurality of electrodes including a base plate, a first bias electrode, and a second bias electrode; 1. A substrate support assembly comprising: The base plate; the first bias electrode disposed on the base plate and spaced from the base plate by a first portion of a dielectric material; a second portion of dielectric material disposed over the first bias electrode and forming a substrate support surface; the second bias electrode disposed a distance from a center of the substrate support surface and spaced from the first bias electrode by a third portion of dielectric material; a conductive edge ring disposed on the second bias electrode so as to surround the substrate support surface; a substrate support assembly comprising: A non-transitory computer readable medium having instructions stored thereon that, when executed by a processor, perform a method for processing a substrate. Equipped with The method further comprising: (a) igniting and maintaining a plasma in the processing space; (b) applying a chucking voltage to the first bias electrode to electrically clamp the substrate to the substrate support surface; (c) applying a first pulsed DC voltage to the first bias electrode; (d) applying a second pulsed DC voltage to the second bias electrode; (e) adjusting the second pulse DC voltage based on the first pulse DC voltage; A substrate processing system comprising:

11. 11. The substrate processing system of claim 10, wherein the first bias electrode is electrically coupled to a first pulsed DC power supply, and the second bias electrode is electrically coupled to the first pulsed DC power supply via a tuning circuit configured to adjust the second pulsed DC voltage with respect to the first pulsed DC voltage.

12. the first bias electrode is electrically coupled to a first pulsed DC power source; the second bias electrode is electrically coupled to a second DC electrode; the second DC electrode is operable independently from the first pulsed DC power source; The substrate processing system of claim 10.

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