MEMORY CONTROLLER AND METHODS EMBODIED THEREIN - Patent application

Abstract

To reduce or eliminate the influence of a comparatively long penalty that accompanies the issuance of a write command for writing, into a DRAM, data having a length which is less than a predetermined length.SOLUTION: A memory controller 1 is configured to issue a first write command for writing data of a predetermined length into a DRAM and a second write command for writing data which is less than the predetermined length in the DRAM, the memory controller including: storage means 12 storing a request 101 to the DRAM; deciding means 13 which decides the order of issuing requests; and issuing means 14 which issues DRAM commands based on the decided issuing order. In a period from the issuance of a preceding DRAM command until a second write command targeting the same bank as the preceding DRAM command is issued, if another DRAM command targeting a bank different from the bank targeted by the preceding DRAM command can be issued, the deciding means decides the issuing order so that the other DRAM command that can be issued may be issued before the second write command.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] The present invention relates to a memory controller and a method implemented in a memory controller. [Background technology]

[0002] There are many types of memory devices used in the memory systems of information processing devices, including dynamic random access memories (DRAMs). Of these memory devices, DRAMs are the most widely used.

[0003] DRAM has a larger memory capacity per chip than other memory devices. It is also cheaper than other memory devices when compared for the same capacity. Therefore, it is possible to build a large-capacity memory system at low cost. For this reason, it is widely used in building memory systems.

[0004] The recently established DRAM standard LPDDR4 introduced the Masked Write command (MWR command) as a DRAM command for writing data. Conventional Write commands (WR commands) controlled data masking operations on a byte-by-byte basis, but this MWR command controls data masking operations on a burst-write basis. In this way, burst-write-by-burst control simplifies the implementation of data masking operations, enabling miniaturization and low power consumption.

[0005] Upon receiving the MWR command, the DRAM performs the following three steps, each of which is executed consecutively: (1) Data is read from a DRAM cell in units of one access. (2) Update the read data with the write data based on the data mask signal. (3) Write the updated data

[0006] In the LPDDR4 standard, the parameter tCCDMW defines the minimum interval that must be left to issue an MWR command or a WR command to the same bank following the MWR command or a WR command. Similarly, the parameter tCCD defines the minimum interval that must be left to issue a WR command to the same bank following the MWR command or a WR command. The units of both tCCDMW and tCCD are DRAM operating clock cycles (hereafter referred to as cycles).

[0007] As mentioned above, the MWR command is executed in three steps. Therefore, the value of tCCDMW is larger than the value of tCCD. For example, the values ​​of tCCDMW and tCCD for burst lengths of 16 and 32 are shown in Table 1. As shown in Table 1, the value of tCCDMW is four times the value of tCCD. Therefore, when issuing an MWR command to the same bank following an MWR command or a WR command, the interval must be four times longer than when issuing a WR command. In other words, issuing an MWR command involves a larger penalty.

[0008] [Table 1]

[0009] Patent Document 1 discloses a method for suppressing the issuance of an MWR command. In the method disclosed in Patent Document 1, when the length of write data is less than one access unit, dummy data is added to make it one access unit, and then writing is performed with a WR command. [Prior art documents] [Patent documents]

[0010] [Patent Document 1] JP 2005-182538 A Summary of the Invention [Problem to be solved by the invention]

[0011] However, the method disclosed in Patent Document 1 has a problem that data may be unintentionally overwritten or the amount of written data may increase because dummy data is added. Also, the method disclosed in Patent Document 1 cannot be applied to partial write, which is a write that rewrites only a part of an area within one access unit.

[0012] The present invention has been made in consideration of these problems, and its purpose is to provide a technology that can reduce or eliminate the effect of the relatively long penalty that accompanies issuing a write command to write data that does not meet the specified length to DRAM. [Means for solving the problem]

[0013] One aspect of the present invention relates to a memory controller. The memory controller is configured to be able to issue a first write command for writing data of a specified length to a DRAM and a second write command for writing data of less than the specified length to the DRAM, and includes a storage means for storing requests to the DRAM, a determination means for determining an issue order of the requests stored in the storage means according to a predetermined criterion, and an issue means for issuing DRAM commands based on the issue order determined by the determination means. When a second write command targeting the same bank as the DRAM command is issued after a preceding DRAM command is issued according to the predetermined criterion, if another DRAM command targeting a bank different from the bank targeted by the DRAM command can be issued during the period until the second write command is issued, the determination means determines the issue order so that the other DRAM command that can be issued is issued within the period, and issues the other DRAM command within the period. Before If the specified DRAM command cannot be issued, the second write command is After the aforementioned period has elapsed The order of issuance is determined so that the Effect of the Invention

[0014] According to the present invention, it is possible to reduce or eliminate the effect of the relatively long penalty that accompanies the issuance of a write command for writing data that does not satisfy a prescribed length to a DRAM. [Brief description of the drawings]

[0015] [Figure 1] 1 is a diagram showing a hardware configuration of an image processing device including a memory controller according to a first embodiment. [Diagram 2] FIG. 2 is a block diagram showing the function and configuration of the memory controller of FIG. 1. [Diagram 3] 4A and 4B are diagrams for explaining an embodiment of entries in a DRAM request storage unit according to the first embodiment; [Figure 4] FIG. 2 is a diagram showing an embodiment of a DRAM request issue order determination unit. [Diagram 5] FIG. 13 is a diagram showing an embodiment of a storage unit control signal. [Figure 6] FIG. 11 is a block diagram showing the function and configuration of a memory controller according to a second embodiment. [Figure 7] 11 is a flowchart showing the flow of a series of determination processes in a presence / absence determining unit. [Figure 8] FIG. 13 is a diagram showing one entry of a DRAM request storage unit according to the second embodiment. [Figure 9] FIG. 13 is a diagram showing an example of a storage unit control signal according to the second embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0016] Hereinafter, the embodiments will be described in detail with reference to the attached drawings. Note that the following embodiments do not limit the invention according to the claims. Although the embodiments describe a number of features, not all of these features are essential to the invention, and the features may be combined in any manner. In addition, the embodiments described below may be implemented in hardware or software, unless otherwise specified. Furthermore, in the attached drawings, the same reference numbers are used for the same or similar configurations, and duplicated descriptions are omitted.

[0017] In the first and second embodiments, a memory controller that controls a DRAM determines the order of processing DRAM requests stored in a buffer so that an RD command, a WR command, or an MWR command to another bank is issued within the penalty period of an MWR command, thereby improving the transfer efficiency of DRAM access.

[0018] (First embodiment) 1 is a diagram showing a hardware configuration of an image processing device 200 including a memory controller 1 according to a first embodiment. The image processing device 200 is, for example, a small electronic device such as a smartphone. The image processing device 200 has a function of capturing an image of a subject and displaying the image on a monitor in real time. In the following, a case where the memory controller 1 according to the first embodiment is mounted on the image processing device 200 will be described. However, it will be clear to those skilled in the art who have read this specification that the memory controller 1 can be widely mounted on electronic devices in general, such as digital cameras.

[0019] The image processing device 200 includes at least an imaging unit 201 , a DRAM 203 , an image processing unit 202 , a system bus 204 , and a memory controller 1 .

[0020] The imaging unit 201 captures an image of a subject by capturing the image of the subject. The imaging unit 201 in this embodiment can capture not only still images but also moving images, and outputs each frame image constituting the moving image at a predetermined capturing timing. The image processing unit 202 performs desired image processing on the image captured by the imaging unit 201. The image processing is general, such as brightness correction and gamma correction, and a detailed description thereof will be omitted.

[0021] The DRAM 203 is a synchronous memory used as a work memory for temporarily storing captured images acquired by the imaging unit 201 and captured images processed by the image processing unit 202. The memory controller 1 is an interface for controlling access to the DRAM 203. The configuration and operation of the memory controller 1 will be described later.

[0022] The display unit 205 is a monitor that displays the image processed by the image processing unit 202 at a predetermined display timing. Data between the above processing units is transmitted and received via a system bus 204. The memory controller 1 controls access to the DRAM 203 so that the captured image obtained by the imaging unit 201 at a predetermined imaging timing is processed by the image processing unit 202 and displayed on the display unit 205 at a predetermined display timing.

[0023] Fig. 2 is a block diagram showing the function and configuration of the memory controller 1 in Fig. 1. The memory controller 1 is electrically connected to the DRAM 203. The memory controller 1 and the DRAM 203 may be provided on separate semiconductor chips, or may be provided on a single semiconductor chip. Alternatively, the DRAM 203 may be a plurality of memory devices each provided on a separate semiconductor chip.

[0024] The DRAM 203 includes multiple banks, various decoders, input / output sense amplifiers, and data bus buffers. In each bank, DRAM cells, which are storage elements, are arranged in a matrix. The DRAM 203 is a DRAM memory device having a first write command for writing data of a predetermined length and a second write command for writing data that does not meet the predetermined length. In this embodiment, the DRAM 203 is configured to comply with LPDDR4.

[0025] The memory controller 1 controls the DRAM 203 by providing commands (DRAM commands) and addresses to the DRAM 203. The memory controller 1 transmits data to be written to the DRAM 203 and receives data read from the DRAM 203. The memory controller 1 and the DRAM 203 operate in synchronization with a common clock signal supplied from a system bus 208. In the following, for the sake of simplicity, the description will be centered on the function of the memory controller 1 relating to issuing commands, and other functions of the memory controller 1, such as control of data lines (DQ), will be omitted.

[0026] Regarding commands for writing data to the DRAM 203, the memory controller 1 is configured to be able to issue a first write command for writing data of a specified length to the DRAM 203, and a second write command for writing data that does not satisfy the specified length.

[0027] The first write command is, for example, a WR command (Write command) defined in LPDDR4. The specified length is a unit of access to the DRAM 203, and is determined by at least one of the data width (or bit width) and the DRAM burst length of the DRAM 203, and is particularly the data width x the DRAM burst length. The minimum interval between commands (tCCD: minimum Column to Column command Delay) set for the DRAM 203 is indicated by the number of DRAM clock cycles that must be waited from a write or read command until the next write or read command. For example, tCCD is set to half the DRAM burst length. The minimum interval between any command and the next WR command (hereinafter also referred to as the penalty of the WR command) is tCCD.

[0028] The second write command is, for example, an MWR command (Masked Write command) defined in LPDDR4. The minimum value of the length of the period that must be waited after issuing a preceding WR command or MWR command to a bank before issuing an MWR command to the same bank (or the minimum interval between a WR command / MWR command and an MWR command to the same bank) is called the MWR command penalty tCCDMWR. The MWR command penalty tCCDMWR ​​is set to be longer than tCCD. For example, in accordance with LPDDR4, the MWR command penalty tCCDMWR ​​is set to twice the DRAM burst length, that is, four times tCCD. Alternatively, the MWR command penalty tCCDMWR ​​may be set to twice, three times, five times, or more generally, N times tCCD (N is a natural number equal to or greater than 2). In this case, the period that must be waited after issuing a preceding WR command or MWR command to a bank before issuing an MWR command to the same bank is longer than the minimum issuance interval (=tCCD) of DRAM commands defined in the DRAM specifications.

[0029] The memory controller 1 includes a DRAM request storage unit 12, a DRAM request issue order determination unit 13, and a DRAM command issue unit 14. In the first embodiment, one DRAM request is executed by one DRAM command. Therefore, one DRAM request corresponds to one DRAM command.

[0030] First, the function of the DRAM request storage unit 12 will be described. The DRAM request storage unit 12 is a buffer that holds requests to the DRAM 203 (hereinafter referred to as DRAM requests 101). The DRAM request storage unit 12 is configured with m entries (m is an integer equal to or greater than 2), and each entry is assigned an entry number from 0 to m-1. Note that this embodiment is not limited to a specific value of m.

[0031] Next, Fig. 3 is a diagram for explaining an embodiment of the entries of the DRAM request storage unit 12 in the first embodiment. Fig. 3 shows one entry 31 of the DRAM request storage unit 12. Therefore, in the first embodiment, the DRAM request storage unit 12 has m entries 31 shown in Fig. 3.

[0032] 3, the entry 31 of the DRAM request storage unit 12 has fields for a request type, a target bank, a target page, and MWRF. The information stored in each field is as follows: (a) Request type field This indicates the type of the DRAM request 101 stored in the entry 31. Examples of types WRITE DRAM request 101 is a write (write data) READ DRAM request 101 is a read (read of data) (b) Target bank field The bank number targeted by the DRAM request 101 stored in the entry 31 (c) Target page field The page number of the DRAM request 101 stored in the entry 31 (d) MWRF field A flag indicating whether the DRAM request 101 stored in the entry 31 uses an MWR command. 1'b1: Use MWR command, 1'b0: Do not use MWR command

[0033] When a new DRAM request 101 is stored in the DRAM request storage unit 12, it is stored in the entry 31 following the end of the already stored DRAM request 101. When a DRAM request 101 is read from the DRAM request storage unit 12, the DRAM request storage unit 12 is configured to be able to read from any entry 31.

[0034] Table 2 is a table for explaining the operation of the DRAM request storage unit 12. In Table 2, REQ00, REQ01, REQ02, and REQ03 are IDs that uniquely identify the DRAM requests 101 stored in the DRAM request storage unit 12. Assume that the state of the DRAM request storage unit 12 is the state shown in the column "Current State" in Table 2. That is, REQ00, REQ01, and REQ02 are stored in entries 0 to 2 of the DRAM request storage unit 12, respectively. On the other hand, entries 3 to the last entry m-1 do not store any DRAM requests 101 and are free.

[0035] [Table 2]

[0036] Here, the operation of storing REQ03, which is a new DRAM request 101, will be described. The entry in which the new DRAM request 101 is stored is the entry following the end of the DRAM request 101 stored in the DRAM request storage unit 12. Therefore, when REQ03 is added and stored in the state shown in the column "Current state" in Table 2, it is stored in entry 3. The state after storing REQ03 is shown in the column "After storing DRAM request" in Table 2. After storing REQ03, the DRAM request 101 is stored in each entry from entry 0 to entry 3, as shown in the column "After storing DRAM request" in Table 2.

[0037] Next, the entry purge operation will be described. The DRAM request storage unit 12 purges the entry specified by the storage unit control signal 112, and at the same time moves the DRAM requests 101 stored in the subsequent entries one by one to the vacant entry. Suppose that the DRAM request 101 (REQ01) in entry 1 is purged from the state shown in the column "After DRAM request storage" in Table 2. After the purge, the DRAM requests 101 stored in the entries from entry 2 onwards are moved one by one to younger entries. The state after the DRAM request 101 (REQ01) in entry 1 is purged is shown in the column "After entry purge" in Table 2.

[0038] 2, the operation of referring to each entry will be described. The DRAM request issue order determination unit 13 can refer to all of the stored DRAM requests 104 stored in the DRAM request storage unit 12.

[0039] The operation of the DRAM request issue order determination unit 13 will be described. The DRAM request issue order determination unit 13 determines the issue order of the stored DRAM requests 104 based on the DRAM state. In particular, if another DRAM command targeting a bank different from the bank targeted by the preceding DRAM command can be issued during the penalty period from when the preceding DRAM command is issued until when the MWR command targeting the same bank as the preceding DRAM command is issued, the DRAM request issue order determination unit 13 determines the issue order so that the other DRAM command that can be issued is issued before the preceding MWR command. The determination may further be based on the priority of the DRAM requests 101. Then, the DRAM request 101 to be issued first after the issue order is determined is output as the DRAM request 105 to be issued next.

[0040] The inputs of the DRAM request issue order determination unit 13 are the stored DRAM requests 104 stored in the DRAM request storage unit 12, and a DRAM command issuance status signal 111 which is the output of the DRAM command issue unit 14. Here, the issuance status signal 111 is a signal indicating the issued DRAM command and information related to the DRAM command, and includes at least signals indicating the following states: (a)cmd DRAM command issued (b)bank The target bank of the issued DRAM command (c) page Target page of the issued DRAM command

[0041] On the other hand, the outputs of the DRAM request issue order determination unit 13 are the next DRAM request 105 to be issued and a storage unit control signal 112. The next DRAM request 105 to be issued is the first DRAM request to be issued among the stored DRAM requests 104. The storage unit control signal 112 is a control signal that instructs the DRAM request storage unit 12 to purge an entry.

[0042] The operation of the DRAM request issue order determination unit 13 will be described in more detail with reference to Fig. 4. Fig. 4 is a diagram showing one embodiment of the DRAM request issue order determination unit 13. In the embodiment shown in Fig. 4, the DRAM request issue order determination unit 13 includes a DRAM status management unit 21 and an issue order determination unit 22.

[0043] The DRAM status management unit 21 manages the DRAM status 121 based on the value of the issuance status signal 111. The DRAM status 121 managed by the DRAM status management unit 21 includes at least the following states. In this specification, all-bank refresh and per-bank refresh are collectively referred to as refresh, unless there is any risk of misunderstanding. Therefore, whether "during refresh operation" means "during all-bank refresh operation", "during per-bank refresh operation", or whether it can be either depends on the context. (a) ref(k) indicates whether bank k is in a refresh operation. 1'b1: Refresh operation in progress 1'b0: Non-refresh operation (b) pcmd: Type of DRAM command issued immediately before to the DRAM 203 The WRITE DRAM command writes data. The READ DRAM command reads data. (c) padd(k) is the page address where bank k is open. (d) bst(k) indicates the state of bank k 1'b1: Bank k has a page open 1'b0: Bank k has a closed page (e) cnt(k) is the number of cycles until the next MWR command can be issued to bank k.

[0044] The operation of the DRAM status management unit 21 will be described in more detail. First, the operation of ref(k) will be described. When the DRAM command issue unit 14 issues a REF (REFRESH) command to bank k, the DRAM status management unit 21 sets ref(k) to 1'b1. Then, after the refresh operation time has elapsed, the DRAM status management unit 21 sets the value of ref(k) to 1'b0. For example, suppose that the DRAM command issue unit 14 issues a REF command to bank 0. At this time, the value of the issue status signal 111 is (cmd,bank,page)==(REF,0,-) Here, "-" indicates don't care. Based on this change, the DRAM state management unit 21 recognizes the start of a refresh operation for bank 0. By recognizing the start of the refresh operation, ref(0) is set to 1'b1.

[0045] pcmd holds the type of the DRAM command issued immediately before. For example, assume that the DRAM command issuing unit 14 issues a WR command to bank 0, page 0. At this time, the issuing status signal 111 is (cmd,bank,page)==(WR,0,0) Due to this change, the DRAM status management unit 21 recognizes the issuance of a WR command and sets pcmd to WRITE, which is the type of the WR command.

[0046] padd(k) and bst(k) indicate the state of bank k. When the DRAM command issuing unit 14 issues an ACT (ACTIVATE) command to page p of bank k, the DRAM state management unit 21 recognizes that page p of bank k has entered an open state. Then, it performs the following operation. (a) Set padd(k) to p (b) Set bst(k) to 1'b1 (valid)

[0047] On the other hand, when the DRAM command issuing unit 14 issues a PRE (PRECHARGE) command to page p of bank k, the DRAM status managing unit 21 recognizes that bank k has entered a closed state, and then performs the following operation. (a) Set bst(k) to 1'b0 Note that the value of padd(k) does not change.

[0048] For example, suppose that the DRAM command issuing unit 14 issues an ACT command to bank 0, page 5. At this time, the issuance status signal 111 is (cmd,bank,page)==(ACT,0,5) Based on this change, the DRAM state management unit 21 performs the following operation. (a) Set padd(0) to 5 (b) Set bst(0) to 1'b1

[0049] On the other hand, suppose that the DRAM command issuing unit 14 issues a PRE command to bank 0, page 5. At this time, the issuing state signal 111 is (cmd,bank,page)==(PRE,0,5) Based on this change, the DRAM state management unit 21 performs the following operation. (a) Set bst(0) to 1'b0

[0050] cnt(k) indicates the number of cycles until the next MWR command can be issued for bank k. The value of cnt(k) changes under the following conditions: (a) Issue a WR command or MWR command to bank k. Set the value of the parameter tCCDMWR ​​to cnt(k). (b) The WR command and the MWR command are not issued, and cnt(k) is not 0. Subtract 1 from the value of cnt(k) {cnt(k)=cnt(k)-1} (c) The WR command and the MWR command are not issued, and cnt(k) is 0. cnt(k) holds the value

[0051] The storage unit control signal 112 will now be described. Fig. 5 is a diagram showing one embodiment of the storage unit control signal 112. The storage unit control signal 112 shown in Fig. 5 includes an entry number field and a purge field. The operation of each field will be described below. (a) Entry number field The entry in the DRAM request storage unit 12 to be controlled is shown. (b) Purge field This indicates that the entry in the DRAM request storage unit 12 indicated by the entry number field is to be purged. 1'b1: Purge, 1'b0: No purge operation

[0052] 4, the operation of the issue order determination unit 22 will be described. In the following description, the bank targeted by the stored DRAM request 104 will be abbreviated as the target bank, and the page targeted by the stored DRAM request 104 will be abbreviated as the target page.

[0053] The issue order determination unit 22 determines the issue order of the stored DRAM requests 104 according to the following criteria, and outputs the DRAM request 105 to be issued next. (A) Whether or not the target bank of the stored DRAM request 104 to be determined is undergoing a refresh operation. (B) Whether the type of the DRAM command corresponding to the stored DRAM request 104 to be determined is the same as the type of the DRAM command issued immediately before. (C) Whether the target page of the stored DRAM request 104 being determined is open or not. (D) If the DRAM command corresponding to the stored DRAM request 104 to be determined is an MWR command, whether the value of cnt(k) is 0 {cnt(k)==0} or not.

[0054] When determining the issue order of the stored DRAM requests 104, the above-mentioned criterion (D) is a mandatory criterion that must be applied. However, the criteria (A) to (C) other than the criterion (D) may be applied individually, or multiple criteria may be applied simultaneously. Furthermore, in this embodiment, when multiple stored DRAM requests 104 satisfy the criteria, the DRAM request 101 with the smallest entry number among the stored DRAM requests 104 that satisfy the criteria is selected. Furthermore, when all the stored DRAM requests 104 do not satisfy the criteria, the DRAM request 101 with the smallest entry number among the stored DRAM requests 104 is selected.

[0055] The operation of determining the issue order of stored DRAM requests 104 will be described in detail with four examples of conditions A to D. In the description, Tables 3 and 4 showing the states of the DRAM request storage unit 12 will be used. Here, Tables 3 and 4 show the values ​​that each field of the DRAM request storage unit entry 31 shown in FIG. 3 takes for each DRAM request 101.

[0056] [Table 3]

[0057] [Table 4]

[0058] Here, the MWRF column in Tables 3 and 4 will be explained. The MWRF column in Tables 3 and 4 indicates the value of the MWRF field of entry 31 that stores a DRAM request. In the first embodiment, one DRAM request is implemented by one DRAM command, so the MWRF column in Tables 3 and 4 indicates whether the DRAM command corresponding to the DRAM request is an MWR command or not. Therefore, when the value of the MWRF column in Tables 3 and 4 is 1'b1, the corresponding DRAM command is an MWR command. The DRAM command corresponding to a DRAM request becomes an MWR command when all of the following conditions are satisfied. (a) The request type of the DRAM request is WRITE. (b) There are invalid bytes in the write data.

[0059] Furthermore, invalid bytes exist in the write data when any one of the following conditions is satisfied: (a) The start address of the area to which data is to be written does not match the boundary of the write block. (b) The end address of the area to which data is to be written does not match the boundary of the write block. (c) The strobe information of the write data is invalid.

[0060] It is assumed that there is no dependency between the DRAM requests 101 listed in Tables 3 and 4. Therefore, the execution order of the DRAM requests 101 listed in Tables 3 and 4 can be changed arbitrarily.

[0061] Condition A is shown below. Note that only the DRAM state information necessary for explanation is listed. (Condition A) Selection Criteria Criterion (A) The target bank is not in a refresh operation. For the standard (D) MWR command, the value of cnt(k) is 0. Status of DRAM request storage unit 12 Table 3 DRAM Status (a)ref(0)==1'b1 Bank 0 is in refresh mode ref(1)==1'b0 Bank 1 is not in refresh operation ref(2)==1'b0 Bank 2 is not in refresh operation (e)cnt(1)==4 4 cycles until MWR command can be issued to bank 1 cnt(2) == 0 0 cycles until MWR command can be issued to bank 2

[0062] In Table 3, the entries that satisfy criterion (A) are entries 3 to 8, which have bank 1, which is not in a refresh operation, and bank 2 as the target banks. Among them, the entries that also satisfy criterion (D) are entries 4, 6, 7, and 8. When there are multiple candidates, the DRAM request 101 with the smallest entry number is selected to determine the order of issuance, and therefore the DRAM request of entry 4, which has the smallest entry number, is determined to be the request to be issued next. Therefore, the DRAM request 105 to be issued next is the DRAM request 101 of entry 4.

[0063] As described above, under condition A, the DRAM request 101 of entry 4 is issued prior to the DRAM request 101 of entry 3. The DRAM request 101 of entry 3 has a value of 1'b1 in the MWRF column, and issues an MWR command. However, as shown in the above-mentioned DRAM state, the cnt value of bank 1, which is the target bank of entry 3, i.e., cnt(0), is 4. Therefore, four cycles of elapsed time are required before the MWR command can be issued. If the DRAM request 101 of entry 3 is determined as the request to be issued next, these four extra cycles of elapsed time are required before the DRAM request 101 is issued, which results in a penalty. However, the memory controller 1 according to the present embodiment can suppress the occurrence of this penalty by issuing entry 4 in advance.

[0064] An example of operation under condition B will be described. In condition B, the value of the DRAM state (e)cnt(1) is 0, which is different from condition A. The other DRAM states, selection criteria, and the state of the DRAM request storage unit 12 are the same as those in condition A. (Condition B) Selection Criteria Criterion (A) The target bank is not in a refresh operation. For the standard (D) MWR command, the value of cnt(k) is 0. Status of DRAM request storage unit 12 Table 3 DRAM Status (a)ref(0)==1'b1 Bank 0 is in refresh mode ref(1)==1'b0 Bank 1 is not in refresh operation ref(2)==1'b0 Bank 2 is not in refresh operation (e) cnt(1) == 0 0 cycles until MWR command can be issued to bank 1 cnt(2) == 0 0 cycles until MWR command can be issued to bank 2 In Table 3, the entries that satisfy criterion (A) are entry 3 to entry 8. Entries 3 to 8 also satisfy criterion (D). Therefore, the DRAM request 101 stored in entry 3, which has the smallest entry number, is determined to be the next request to be issued. The next DRAM request 105 to be issued is the DRAM request 101 in entry 3.

[0065] As explained above, under condition B, the DRAM request 101 of entry 3 is issued. As explained under condition A, entry 3 issues an MWR command, but cnt(0) is 0, and no penalty occurs until the MWR command can be issued. Since no penalty occurs, the DRAM request 101 of entry 3 can be issued.

[0066] An example of operation under condition C will be described. Condition C has selection criteria as criteria (A), (B), (C), and (D), and the DRAM state as shown below. The type of the DRAM command issued immediately before is WRITE. The state of the DRAM request storage unit 12 is as shown in Table 4. (Condition C) Selection Criteria Criterion (A) The target bank is not in a refresh operation. Criterion (B): The type of the DRAM command issued is the same as the type of the DRAM command issued immediately before. Criterion (C) The target page is open For the standard (D) MWR command, the value of cnt(k) is 0. Status of DRAM request storage unit 12 Table 4 DRAM Status (a)ref(0)==1'b1 Bank 0 is in refresh mode ref(1)==1'b0 Bank 1 is not in refresh operation ref(2)==1'b0 Bank 2 is not in refresh operation (b)pcmd==WRITE The last DRAM command issued was WRITE (c) padd(1) == 0 Bank 1 is page 0 padd(2)==1 Bank 2 is page 1 (d) bst(1) == 1 Bank 1 page 0 is open bst(2) == 1 Bank 2 page 1 is open (e)cnt(1)==4 4 cycles until MWR command can be issued to bank 1 cnt(2) == 0 0 cycles until MWR command can be issued to bank 2

[0067] In Table 4, the entries that satisfy all of criteria (A) to (C) are entry 0, entry 5, and entry 8. However, entry 5 does not satisfy criterion (D). On the other hand, entry 0 and entry 8 also satisfy criterion (D). Therefore, DRAM request 101 stored in entry 0 is determined as the next request to be issued. The next DRAM request 105 to be issued will be DRAM request 101 of entry 0.

[0068] As described above, under condition C, the DRAM request 101 stored in entry 0 is issued next. The DRAM request 101 in entry 5 issues an MWR command, but since cnt(0) is 4, a penalty of 4 cycles is required before the MWR command is issued. However, the memory controller 1 according to this embodiment issues entry 0, which was stored in advance in the DRAM request storage unit 12 but has not been issued due to the implementation of reordering, prior to entry 5, thereby preventing the occurrence of this penalty.

[0069] A procedure for the issue order determination unit 22 to generate a storage unit control signal 112 for purging an entry in the DRAM request storage unit 12 will be described. In the first embodiment, one DRAM request is executed by one DRAM command. Therefore, when the DRAM command issue unit 14 issues a DRAM command, the operation of the corresponding DRAM request 101 is completed. Therefore, when the issue status signal 111 indicates the issuance of a DRAM command, the issue order determination unit 22 generates and outputs a storage unit control signal 112 to purge the corresponding DRAM request 101.

[0070] For example, assume that the state of the DRAM request storage unit 12 is as shown in Table 3. At this time, as a result of determining the order of issuing the DRAM requests 101, the next DRAM request 105 to be issued is the DRAM request 101 of entry 7. When the DRAM command issuing unit 14 issues a WR command, which is a DRAM command corresponding to the DRAM request 101 of entry 7, the value of the issue state signal 111 becomes (cmd,bank,page)==(WR,1,0) Upon detecting this change, the issue order determination unit 22 determines that the issuance of the corresponding DRAM command has been completed, generates a storage unit control signal 112 for purging the entry 7, and outputs it to the DRAM request storage unit 12. At this time, the fields of the generated storage unit control signal 112 have the following values. (a) Entry Number Field 7 (b) Purge field 1'b1

[0071] Returning to Fig. 2, the function of the DRAM command issuing unit 14 will be described. The DRAM command issuing unit 14 issues DRAM commands based on the issue order determined by the DRAM request issue order determining unit 13. The DRAM command issuing unit 14 generates a DRAM command to be output next to the DRAM 203 from information on the DRAM request 105 to be issued next, and issues it to the DRAM 203. At the same time, the DRAM command issuing unit 14 outputs an issue status signal 111 to the DRAM request issue order determining unit 13.

[0072] According to the memory controller 1 of the present embodiment, the order of issuing DRAM commands is determined based on the presence or absence of an MWR command for writing data of an amount less than the specified length of the DRAM 203 to the DRAM 203. Therefore, it is possible to reduce the effect of the penalty when writing data of an amount less than the specified length, and suppress a decrease in memory access efficiency or increase the efficiency.

[0073] In the memory controller 1 according to the present embodiment, even when an MWR command occurs in conjunction with the execution of a partial write, the penalty caused by the MWR command can be reduced and a decrease in efficiency of data writing can be suppressed or eliminated.

[0074] In the first embodiment, the issue order of the DRAM requests 101 stored in the DRAM request storage unit 12 is determined based on the DRAM state, but this is not limiting. For example, in addition to the criterion (D) related to the DRAM state, the issue order may be determined based on a criterion other than the criteria (A) to (C), such as the priority order of the DRAM requests 101.

[0075] Second Embodiment 6 is a block diagram showing the function and configuration of a memory controller 5 according to the second embodiment. The memory controller 5 according to this embodiment includes a presence / absence determination unit 11 in addition to the memory controller 1 according to the first embodiment. Similarly to the first embodiment, a first write command for writing data of a specified length to the DRAM 203 is a WR command, and a second write command for writing data that does not satisfy the specified length is an MWR command.

[0076] In the first embodiment, one DRAM request 101 is implemented by one DRAM command, but in the second embodiment, one DRAM request 101 may be implemented by a DRAM command string consisting of multiple DRAM commands.

[0077] The memory controller 5 according to the present embodiment will be described in detail with reference to FIG. 6. In describing the second embodiment, the functions newly added in the second embodiment and the functions different from the first embodiment will be mainly described. Meanwhile, the description of the same functions as the first embodiment will be omitted.

[0078] The presence / absence determination unit 11 determines whether a write request to the DRAM 203 requires an MWR command based on (1) the start address and burst length of the write request, or (2) strobe information of the data related to the write request. The presence / absence determination unit 11 determines whether each DRAM command in a DRAM command string generated from the DRAM request 101 is an MWR command, and substitutes the determination result into MWRF103, which is a variable-length flag variable. MWRF103 is identification information for identifying whether each of a plurality of DRAM commands corresponding to the DRAM request 101 is an MWR command. Here, the determination result of the nth DRAM command in the DRAM command string is substituted into the nth bit of MWRF103. For example, the value of MWRF(0) indicates the result of determining the 0th DRAM command in the DRAM command string, i.e., the first DRAM command.

[0079] In the second embodiment, the bit values ​​of the MWRF 103 are defined as follows. (a) The corresponding DRAM command is MWR command 1'b1 (valid) (b) The corresponding DRAM command is not an MWR command: 1'b0 (invalid)

[0080] For example, consider the following DRAM command string consisting of four DRAM commands: DRAM Command(0) MWR Command DRAM Command (1) WR Command DRAM Command (2) MWR Command DRAM Command (3) MWR Command At this time, the value of MWRF103 is as follows for each bit: MWRF(0) == 1'b1: DRAM command(0) is MWR command MWRF(1) == 1'b0: DRAM command (1) is a WR command MWRF(2)==1'b1: DRAM command (2) is an MWR command MWRF(3) == 1'b1: DRAM command (3) is an MWR command Therefore, the value of MWRF103 becomes 4'b1101.

[0081] The operation of the presence / absence determination unit 11 will be described in detail with reference to Fig. 7. Fig. 7 is a flowchart showing the flow of a series of determination processes in the presence / absence determination unit 11. This determination process includes determining whether each DRAM command in a series of DRAM command strings generated from the DRAM request 101 is an MWR command or not, and substituting the determination result into the MWRF 103.

[0082] In S001, 1'b0 is substituted into MWRF(0) for initialization. In S002, if the type of DRAM request is WRITE, the process branches to S003, otherwise the generation of MWRF 103 is terminated. In S003, the number of DRAM commands included in the DRAM command sequence corresponding to DRAM request 101 is calculated. The calculated result is represented by variable b.

[0083] From the result of S003, the number of DRAM commands included in the DRAM command string is b. Therefore, in S004, the loop from S004 to S007 is repeated b times from 0 to b-1. In S005, it is determined whether or not all of the strobe information of the write data corresponding to the j-th DRAM command is valid. If all of the strobe information of the write data is valid, the process branches to S007. Conversely, if there is invalid strobe information of the write data, the process branches to S006. In S006, from the result of S005, there is an invalid byte in the data written by the j-th DRAM command. Therefore, the j-th DRAM command is not a WR command but an MWR command. Since the MWR command is used, 1'b1 is substituted for MWRF(j). In S007, from the result of S005, there is no invalid byte in the data written by the j-th DRAM command. Therefore, the j-th DRAM command is a WR command. Since the WR command is used, 1'b0 is substituted into MWRF(j).

[0084] In S008, if the start address of the data written by the DRAM request 101 does not match the start of the burst write block, the MWR command is used instead of the WR command. Therefore, in S008, it is determined whether the start address of the data written by the DRAM request 101 matches the start of the burst write block. If they match, the process branches to S010. If they do not match, the process branches to S009.

[0085] The operation of S008 will be explained using an example. In the explanation, the burst length and data width are set to the following values. (a) Burst length 16 (b) Data width: 32 bits (4 bytes) Under the above conditions, Burst write block == 16*32bit / 8=64byte Therefore, to determine whether the starting address matches the start of the burst write block, the lowest 6 bits of the starting address can be compared with the constant 6'b000000. If they match, the starting address matches the start of the burst write block. Conversely, if they do not match, the starting address is not the start of the burst write block. Therefore, writing will start halfway through the burst write block, and the MWR command must be used.

[0086] In S009, since the start address does not match the start of the burst write block, the 0th DRAM command uses the MWR command, and therefore bit 0 of MWRF103 is set to 1'b1.

[0087] In S010, it is determined whether the final address (end address) of the data written by the DRAM request 101 matches the rear end of the burst write block. If they match, the generation of the MWRF 103 ends. If they do not match, the process branches to S011.

[0088] The operation of S010 will be explained using an example. The specifications of the burst write block are the same as those applied to the explanation of S008. Therefore, the size of the burst write block is 16*32bit / 8=64bytes. Therefore, in this example, the last address of the burst write block has the lowest 6 bits of 6'b111111. Therefore, to determine whether the end address matches the end of the burst write block, the lowest 6 bits of the end address can be compared with the constant 6'b111111. If they match, the end address matches the end of the burst write block. Conversely, if they do not match, the end address is not the end of the burst write block. Therefore, writing ends in the middle of the burst write block, and the MWR command must be used.

[0089] In S011, since the end address does not match the rear end of the burst write block, the (b-1)th DRAM command uses the MWR command, and therefore bit (b-1) of MWRF 103 is set to 1'b1.

[0090] The operation of the DRAM request storage unit 12 in the second embodiment will be described. Fig. 8 is a diagram showing one entry 32 of the DRAM request storage unit 12 in the second embodiment. As shown in Fig. 8, the entry 32 of the DRAM request storage unit 12 has fields for a request type, a target bank, a target page, an MWRF vector, a number of DRAM commands, and an index. Of these, the fields for the request type, the target bank, and the target page are the same as those of the entry 31 of the DRAM request storage unit in the first embodiment shown in Fig. 3. Therefore, the operation of the MWRF vector field, the number of DRAM commands field, and the index field, which are different from those in the first embodiment, will be described.

[0091] (a) MWRF vector field This indicates the usage status of the MWR command of the DRAM request 101 stored in the entry 32. In the second embodiment, one DRAM request 101 is implemented by a DRAM command string consisting of a plurality of DRAM commands. Therefore, the flag indicating whether or not to use the MWR command is also shown in the form of a vector, with each bit corresponding to a DRAM command. The value indicated by each bit is the same as in the first embodiment, and is defined as follows: 1'b1: Use MWR command, 1'b0: Do not use MWR command (b) DRAM Command Count Field It indicates the number of DRAM commands contained in the DRAM command sequence that implements (or corresponds to) the DRAM request 101 stored in the entry 32. (c) Index Field This indicates the position of the next DRAM command to be issued in the DRAM command string corresponding to the DRAM request 101 stored in the entry 32.

[0092] The operation of storing the new DRAM request 101 in the DRAM request storage unit 12 is the same as that in the first embodiment. That is, the new DRAM request 101 is stored in the entry following the last entry of the DRAM request 101 stored in the DRAM request storage unit 12.

[0093] The storage unit control signal 112 in the second embodiment will be described. Fig. 9 is a diagram showing an example of the storage unit control signal 112 in the second embodiment. The storage unit control signal 112 shown in Fig. 9 includes an entry number field, a purge field, and an update field. Of these, the entry number field and the purge field are the same as the storage unit control signal 112 in the first embodiment shown in Fig. 5. The operation of the update field will now be described.

[0094] (c) Update Field This indicates that the index field is to be updated for the entry in the DRAM request storage unit 12 indicated by the entry number field. 1'b1: Increment the value of the index field by 1, 1'b0: No update operation

[0095] The entry purge operation in the second embodiment will be described. In the second embodiment, one DRAM request 101 is implemented by a DRAM command string consisting of a plurality of DRAM commands. Therefore, after all the DRAM commands constituting the DRAM command string are executed, the entry in the DRAM request storage unit 12 is purged. The operation of moving the DRAM requests 101 stored in the subsequent entries one by one to the entry that becomes free after the purge is the same as in the first embodiment.

[0096] The operation of the DRAM request issue order determination unit 13 in the second embodiment will be described. The DRAM request issue order determination unit 13 in the second embodiment includes a DRAM status management unit 21 and an issue order determination unit 22, as in the first embodiment. Here, the operation of the DRAM status management unit 21 in the second embodiment is similar to that in the first embodiment. On the other hand, the operation of the issue order determination unit 22 in the second embodiment differs from that of the issue order determination unit 22 in the first embodiment. Therefore, the following description will focus on the operation of the issue order determination unit 22 in the second embodiment that differs from that of the issue order determination unit 22 in the first embodiment.

[0097] In explaining the operation of the issue order determination unit 22 in the second embodiment, Table 5 showing the state of the DRAM request storage unit 12 will be used. The "index" column in Table 5 indicates the position of the next DRAM command to be issued in the DRAM command sequence for implementing the DRAM request 101 stored in the entry. For example, if the value in the "index" column in Table 5 is 0, the 0th DRAM command, i.e., the first DRAM command, is the next DRAM command to be issued.

[0098] [Table 5]

[0099] Among the criteria by which the issue order determination unit 22 in the second embodiment determines the issue order, criteria (A) to (C) are the same as those in the first embodiment. However, the precondition of criterion (D) is different from that in the first embodiment because one DRAM request 101 is executed by a DRAM command string composed of a plurality of DRAM commands. That is, the target for determining whether or not it is an MWR command is the next DRAM command to be issued, which is indicated by the index field of the entry 32. Therefore, the criterion (D) for determining the issue order in the second embodiment is as follows: If the next DRAM command to be issued, as indicated by the index field of reference (D) entry 32, is an MWR command, the value of cnt(k) is 0.

[0100] The operation of the issue order determination unit 22 in the second embodiment to determine the issue order of the stored DRAM requests 104 by applying the criteria (A) to (D) is the same as that in the first embodiment. Also, the operation of the issue order determination unit 22 in the second embodiment to output the DRAM request 101 to be issued first after determining the issue order as the DRAM request 105 to be issued next is also the same as that in the first embodiment.

[0101] The procedure for generating the storage unit control signal 112 by the issue order determination unit 22 will be described. In the second embodiment, one DRAM request is implemented by a DRAM command string consisting of a plurality of DRAM commands. The position of the next DRAM command to be issued in the DRAM command string is indicated by the index field of the entry 32. Therefore, the issue order determination unit 22 generates a signal to purge the entry 32, as well as a signal to update the index field of the entry 32.

[0102] The issuance of the last DRAM command constituting the DRAM command string completes the operation of the corresponding DRAM request 101. Therefore, the purge field of the storage control signal 112, which is a signal for purging the entry 32, becomes valid under the following conditions. (a) Issuance status signal 111 indicates issuance of a DRAM command (b) Last DRAM command

[0103] On the other hand, the index field is updated when a DRAM command constituting a DRAM command string is issued. However, when the last DRAM command is issued, there is no need to update the index field. Therefore, the update field of the storage control signal 112 is valid under the following conditions: (a) Issuance status signal 111 indicates issuance of a DRAM command (b) Not the last DRAM command

[0104] The fact that it is the last DRAM command in the DRAM command string can be determined from the value of the DRAM command count field and the value of the index field of entry 32. Here, if the value of the DRAM command count field is c and the value of the index field is idx, then idx==c-1 In this case, it indicates that the next DRAM command to be issued is the last DRAM command constituting the DRAM command string. Therefore, when the issuance status signal 111 indicates the issuance of a DRAM command and (idx==c-1), the issue order determination unit 22 generates and outputs the storage unit control signal 112 to purge the corresponding DRAM request 101.

[0105] For example, assume that the state of the DRAM request storage unit 12 is as shown in Table 5. At this time, assume that as a result of determining the order of issuing the DRAM requests 101, the DRAM request 105 to be issued next is the DRAM request 101 of entry 4.

[0106] When the DRAM command issuing unit 14 issues a WR command, which is a DRAM command corresponding to the DRAM request 101 of entry 4, the value of the issuance status signal 111 becomes (cmd,bank,page)==(WR,1,0) At this time, the value of the index column is 3 and the value of the DRAM command count field is 4, so idx==c-1 3==4-1=3 is established. Therefore, the issue order determination unit 22 determines that the issuance of all the DRAM commands constituting the DRAM command string has been completed, generates the storage unit control signal 112 for purging the entry 4, and outputs it to the DRAM request storage unit 12. At this time, the fields of the generated storage unit control signal 112 have the following values. (a) Entry Number Field 4 (b) Purge field 1'b1 (c) Update field 1'b0

[0107] Then, when the issuance status signal 111 indicates the issuance of a DRAM command and (idx!=c-1), the issue order determination unit 22 generates and outputs a storage unit control signal 112 to update the index field of the corresponding DRAM request 101. At this time, the fields of the generated storage unit control signal 112 have the following values. (a) Entry Number Field 4 (b) Purge field 1'b0 (c) Update field 1'b1

[0108] The following describes the function of the DRAM command issuing unit 14 in the second embodiment. The operation of the DRAM command issuing unit 14 in the second embodiment is similar to that in the first embodiment.

[0109] The memory controller 5 according to the second embodiment provides the same advantageous effects as those provided by the memory controller 1 according to the first embodiment.

[0110] In the second embodiment, the issue order of the DRAM requests 101 stored in the DRAM request storage unit 12 is determined based on the DRAM state, but this is not limiting. For example, in addition to the criterion (D) related to the DRAM state, the issue order may be determined based on a criterion other than the criteria (A) to (C), such as the priority order of the DRAM requests 101.

[0111] (simulation) A simulation result showing the effect of the memory controller 5 according to the second embodiment will be described below. The simulation was performed under the following conditions. -Compliant with LPDDR4, 3200Mbps. ·WL(Write Latency)=14 cycles BL(Burst Length)=16 cycles DRAM203 Data Width = 32 bits DRAM203 Page = 4 kilobytes (KByte) Penalties -PageMiss(WR->*)=110 cycles -MaskedWrite penalty = 32 cycles

[0112] Under the above assumptions, we simulated a case in which two modules competed to write 4000 x 2000 pixel image data for each horizontal line. The data volume for one pixel was 4.5 bytes. There was no page dependency between the two modules.

[0113] (1) When the start address of each line is aligned to the DRAM command unit (64 bytes) In this case, only the final DRAM command in the line is an MWR command. According to the conventional method, the transfer efficiency is 79.5%. According to the method according to the second embodiment, the transfer efficiency is 80.4%, which is an increase of 0.9%.

[0114] (2) When the start address of each line is not aligned to the DRAM command unit (64 bytes) In this case, both the first DRAM command and the last DRAM command of the line are MWR commands. Therefore, unless some special ingenuity is used, a lower transfer efficiency is expected than in the case of (1), and in fact, the transfer efficiency is 78.6% according to the conventional method, which is 0.9% worse than the case of (1). In contrast, the transfer efficiency is 80.4% according to the method of the second embodiment, which is the same as the case of (1). Compared to the conventional method, the transfer efficiency is increased by 1.8%.

[0115] The configuration and operation of the memory controller according to the embodiment have been described above. These embodiments are merely examples, and it will be understood by those skilled in the art that various modifications are possible in the combination of each component and each process, and that such modifications are also within the scope of the present invention.

[0116] In the first and second embodiments, the memory controller has storage and decision functions, but this is not limited to this. For example, a pre-stage circuit having these functions may be provided in front of a conventional memory controller.

[0117] The invention is not limited to the above-described embodiment, and various changes and modifications can be made without departing from the spirit and scope of the invention. Accordingly, the following claims are appended to apprise the public of the scope of the invention. [Explanation of symbols]

[0118] 1 memory controller, 12 DRAM request storage unit, 13 DRAM request issue order determination unit, 14 DRAM command issue unit.

Claims

1. A memory controller configured to be capable of issuing a first write command for writing data of a specified length to a DRAM, and a second write command for writing data of less than the specified length to the DRAM, a storage means for storing requests for the DRAM; a determination means for determining an issuance order of the requests stored in the storage means in accordance with a predetermined criterion; an issuing means for issuing DRAM commands based on the issuing order determined by the determining means; the determining means determines the issuance order so that, when a preceding DRAM command is issued according to the predetermined criterion and then a second write command targeting the same bank as the preceding DRAM command is issued, if it is possible to issue another DRAM command targeting a bank different from the bank targeted by the preceding DRAM command during the period up to the issuance of the second write command, the other DRAM command that can be issued is issued within the period, and if it is not possible to issue the other DRAM command within the period, the determining means determines the issuance order so that the second write command is issued after the period has elapsed.

2. 2. The memory controller according to claim 1, wherein the specified length is determined by at least one of a data width and a burst length of a DRAM.

3. 3. The memory controller according to claim 1, wherein the period is longer than a minimum issuance interval of a DRAM command defined in a DRAM specification.

4. The determination means further determines, for the request to be determined, (1) Whether the type of the DRAM command corresponding to the request to be determined is the same as or different from the type of the DRAM command issued immediately before; (2) Whether the bank targeted by the request to be determined is in a per-bank refresh operation; (3) whether the page to which the request is addressed is open; The memory controller according to claim 1 , wherein the issue order is determined according to at least one of the following:

5. 5. The memory controller of claim 1, further comprising a determination means for determining whether a write request to a DRAM requires a second write command based on (1) a starting address and a burst length of the write request, or (2) strobe information of the data related to the write request.

6. the determining means generates, for each of a plurality of DRAM commands corresponding to a write request to the DRAM, identification information for identifying whether the DRAM command is a second write command; The memory controller according to claim 5 , wherein the determining means refers to generated identification information.

7. the storage means includes a plurality of entries, each configured to store a request; 7. The memory controller according to claim 1, wherein the storage means is configured to be able to read a request from any entry.

8. 8. The memory controller according to claim 1, wherein the determination means determines the issue order further based on the priority of the requests.

9. The memory controller according to claim 1 , wherein the second write command is a masked write command.

10. A method implemented by a memory controller configured to be able to issue a first write command for writing data of a specified length to a DRAM and a second write command for writing data of less than the specified length to the DRAM, the memory controller comprising a storage means for storing a request to the DRAM, the method comprising: determining an issuance order of the requests stored in said storage means in accordance with a predetermined criterion; issuing DRAM commands based on the determined issuing order; The determining includes the steps of: when a preceding DRAM command is issued according to the predetermined criterion and then a second write command targeting the same bank as the preceding DRAM command is issued, if another DRAM command targeting a bank different from the bank targeted by the preceding DRAM command can be issued during the period until the second write command is issued, determining the issuance order such that the other DRAM command that can be issued is issued within the period; and if the other DRAM command cannot be issued within the period, determining the issuance order such that the second write command is issued after the period has elapsed.

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