Designed board construction for power and RF applications

Abstract

To provide a method and system for providing a substrate structure suitable for epitaxial growth to provide a substrate characterized by a coefficient of thermal expansion (CTE) that is substantially matched to epitaxial layers grown thereon.SOLUTION: A substrate 100 includes a support structure comprising: a core 110 containing a polycrystalline ceramic material; a first adhesion layer 112 coupled to the core; a conductive layer 114 coupled to the first adhesion layer; a second adhesion layer 116 coupled to the conductive layer; and a barrier layer 118 coupled to the second adhesion layer. The substrate also includes: a bonding layer 120 coupled to the support structure; a substantially single crystal layer 122 coupled to the bonding layer and containing at least one of silicon carbide, sapphire and gallium nitride; and an epitaxial material 130 coupled to the substantially single crystal layer.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application claims priority to U.S. Provisional Patent Application No. 62 / 350,084, filed June 14, 2016, and entitled "ENGINEERED SUBSTRATE STRUCTURE FOR POWER AND RF APPLICATIONS," and to U.S. Provisional Patent Application No. 62 / 350,077, filed June 14, 2016, and entitled "ENGINEERED SUBSTRATE STRUCTURE AND METHOD OF MANUFACTURE," the disclosures of which are incorporated herein by reference in their entireties for all purposes.

[0002] The following two US patent applications are being filed concurrently with the present application, and the disclosures of these two applications are incorporated herein by reference in their entireties for all purposes:

[0003]

[0003] Application No. 15 / 621,335, entitled “ENGINEERED SUBSTRATE STRUCTURE FOR POWER AND RF APPLICATIONS,” filed on June 13, 2017 (Attorney Docket No. 098825-1049529-001110US).

[0004]

[0004] Application Serial No. 15 / 621,338, entitled "ENGINEERED SUBSTRATE STRUCTURE AND METHOD OF MANUFACTURE," filed June 13, 2017 (Attorney Docket No. 098825-1049532-001610US). [Background technology]

[0005]

[0005] Light emitting diode (LED) structures are typically epitaxially grown on sapphire substrates. Many products now use LED devices, including lighting, computer monitors, and other display devices.

[0006]

[0006] The growth of gallium nitride based LED structures on sapphire substrates is a heteroepitaxial growth process since the substrate and epitaxial layers are composed of different materials. Due to the heteroepitaxial growth process, the epitaxially grown materials can exhibit various adverse effects including reduced uniformity and reduced metrics related to the electronic / optical properties of the epitaxial layers. Therefore, there is a need in the art for improved methods and systems related to epitaxial growth processes and substrate structures. Summary of the Invention

[0007]

[0007] The present invention relates generally to engineered substrate structures. More specifically, the present invention relates to methods and systems suitable for use in epitaxial growth processes. By way of example only, the present invention finds application in methods and systems for providing a substrate structure suitable for epitaxial growth, the structure being characterized by a coefficient of thermal expansion (CTE) that is substantially matched to the epitaxial layer grown thereon. The methods and techniques can be applied to a variety of semiconductor processing operations.

[0008] According to one embodiment of the present invention, a substrate is provided. The substrate includes a support structure comprising a polycrystalline ceramic core, a first adhesive layer bonded to the polycrystalline ceramic core, a conductive layer bonded to the first adhesive layer, a second adhesive layer bonded to the conductive layer, and a barrier layer bonded to the second adhesive layer. The substrate also includes a silicon oxide layer bonded to the support structure, and a barrier layer bonded to the silicon oxide layer. a substantially monocrystalline silicon layer coupled to the silicon layer, and an epitaxial III-V layer coupled to the substantially monocrystalline silicon layer.

[0009]

[0009] According to another embodiment of the present invention, there is provided a method of manufacturing a substrate, the method including forming a support structure by providing a polycrystalline ceramic core, encapsulating the polycrystalline ceramic core in a first adhesive shell, encapsulating the first adhesive shell in a conductive shell, encapsulating the conductive shell in a second adhesive shell, and encapsulating the second adhesive shell in a barrier shell. The method also includes bonding a bonding layer to the support structure, bonding a substantially single crystalline silicon layer to the bonding layer, epitaxially growing an epitaxial silicon layer on the substantially single crystalline silicon layer, and epitaxially growing an epitaxial III-V layer on the epitaxial silicon layer.

[0010]

[0010] In accordance with certain embodiments of the present invention, an engineered substrate structure is provided. The engineered substrate structure includes a support structure, a bonding layer coupled to the support structure, a substantially single crystalline silicon layer coupled to the bonding layer, and an epitaxial single crystalline silicon layer coupled to the substantially single crystalline silicon layer. The support structure includes a polycrystalline ceramic core, a first adhesion layer coupled to the polycrystalline ceramic core, a conductive layer coupled to the first adhesion layer, a second adhesion layer coupled to the conductive layer, and a barrier shell coupled to the second adhesion layer.

[0011]

[0011] Many advantages are achieved by the present invention over the prior art. For example, embodiments of the present invention provide engineered substrate structures that are CTE matched to gallium nitride based epitaxial layers suitable for use in optical, electronic, and optoelectronic applications. The encapsulation layer utilized as a component of the engineered substrate structure prevents diffusion of impurities present in the central portion of the substrate from reaching the semiconductor processing environment in which the engineered substrate is utilized. Critical properties associated with the substrate material, including coefficient of thermal expansion, lattice mismatch, thermal stability, and shape control, are uniquely engineered for improved (e.g., optimized) matching with gallium nitride based epitaxial layers and device layers, as well as various device architectures and performance targets. Process integration is simplified because the substrate material layers are integrated together in conventional semiconductor manufacturing processes. These and other embodiments of the present invention, along with many of its advantages and features, are described in more detail in the following text and in conjunction with the accompanying drawings. [Brief description of the drawings]

[0012] [Figure 1] FIG. 1 is a simplified schematic diagram illustrating a designed substrate structure according to one embodiment of the present invention. [Figure 2A] 1 is a SIMS profile showing species concentration as a function of depth for a designed structure according to an embodiment of the present invention. [Figure 2B] 11 is a SIMS profile showing species concentration as a function of depth for a designed structure after annealing according to an embodiment of the present invention. [Figure 2C] 11 is a SIMS profile showing species concentration as a function of depth for a designed structure having a silicon nitride layer after annealing in accordance with an embodiment of the present invention. [Diagram 3] FIG. 1 is a simplified schematic diagram illustrating a designed substrate structure according to another embodiment of the present invention. [Figure 4] FIG. 13 is a simplified schematic diagram illustrating a designed substrate structure according to yet another embodiment of the present invention. [Diagram 5]1 is a simplified flowchart illustrating a method for manufacturing a designed substrate according to an embodiment of the present invention. [Figure 6] FIG. 2 is a simplified schematic diagram illustrating an epitaxial / engineered substrate structure for RF and power applications according to one embodiment of the present invention. [Figure 7] FIG. 2 is a simplified schematic diagram illustrating III-V epitaxial layers on a designed substrate structure according to one embodiment of the present invention. [Figure 8] 4 is a simplified flowchart illustrating a method for manufacturing a designed substrate according to another embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0013]

[0022] Embodiments of the present invention relate to engineered substrate structures. More specifically, the present invention relates to methods and systems suitable for use in epitaxial growth processes. By way of example only, the present invention is applied to methods and systems that provide substrate structures suitable for epitaxial growth, characterized by a coefficient of thermal expansion (CTE) that is substantially matched to the epitaxial layers grown thereon. The methods and techniques can be applied to a variety of semiconductor processing operations.

[0014]

[0023] FIG. 1 is a simplified schematic diagram illustrating an engineered substrate structure according to one embodiment of the present invention. The engineered substrate 100 shown in FIG. 1 is suitable for a variety of electronic and optical applications. The engineered substrate includes a core 110 that can have a coefficient of thermal expansion (CTE) that substantially matches the CTE of an epitaxial material to be grown on the engineered substrate 100. An epitaxial material 130 is not required as an element of the engineered substrate, but is shown as optional since it is typically grown on the engineered substrate.

[0015]

[0024] For applications involving the growth of gallium nitride (GaN) based materials (epitaxial layers including GaN based layers), the core 110 may be a polycrystalline ceramic material, for example, polycrystalline aluminum nitride (AlN), which may include a binder material such as yttrium oxide. Other materials may be utilized for the core 110, including polycrystalline gallium nitride (GaN), polycrystalline aluminum gallium nitride (AlGaN), polycrystalline silicon carbide (SiC), polycrystalline zinc oxide (ZnO), polycrystalline gallium trioxide (Ga2O3), and the like.

[0016]

[0025] The thickness of the core can be on the order of 100-1500 μm, for example 725 μm. The core 110 is encapsulated in a first adhesion layer 112, which can be referred to as a shell or encapsulation shell. In one embodiment, the first adhesion layer 112 comprises a tetraethyl orthosilicate (TEOS) layer having a thickness on the order of 1,000 Å. In other embodiments, the thickness of the first adhesion layer varies, for example, from 100 Å to 2,000 Å. Although TEOS is utilized in some embodiments for the adhesion layer, other materials (e.g., ceramics, particularly polycrystalline ceramics) that provide adhesion between a subsequently deposited layer and the layer or material below it can also be utilized in accordance with embodiments of the present invention. For example, SiO2 or other silicon oxides (Si x O y ) adheres well to ceramic materials and provides a suitable surface for subsequent deposition of, for example, conductive materials. In some embodiments, the first adhesion layer 112 completely surrounds the core 110 to form a completely encapsulated core, and may be formed using an LPCVD process. The first adhesion layer 112 provides a surface onto which subsequent layers are adhered to form elements of a designed substrate structure.

[0017]

[0026] In addition to using LPCVD processes, furnace-based processes, and the like, to form the first encapsulating adhesion layer, other semiconductor processes, including CVD processes or similar deposition processes, can be utilized in accordance with embodiments of the present invention. As an example, a deposition process can be utilized to coat a portion of the core, the core can be turned over, and the deposition process can be repeated to coat additional portions of the core. Thus, while in some embodiments, LPCVD techniques are utilized to provide a fully encapsulated structure, other deposition techniques can be utilized depending on the particular application.

[0018]

[0027] A conductive layer 114 is formed around the adhesion layer 112. In one embodiment, the conductive layer 114 is formed as a shell of polysilicon (i.e., polycrystalline silicon) around the first adhesion layer 112 because polysilicon has poor adhesion to ceramic materials. In embodiments where the conductive layer is polysilicon, the thickness of the polysilicon layer may be on the order of 500-5,000 Å, for example 2,500 Å. In some embodiments, the polysilicon layer may be formed as a shell to completely surround the first adhesion layer 112 (e.g., a TEOS layer), thereby forming a completely encapsulated first adhesion layer, and may be formed using an LPCVD process. In other embodiments, as described below, the conductive material may be formed on a portion of the adhesion layer, for example, on the bottom half of the substrate structure. In some embodiments, the conductive material may be formed as a completely encapsulating layer and subsequently removed on one side of the substrate structure.

[0019]

[0028] In one embodiment, the conductive layer 114 may be a polysilicon layer that is doped to provide a highly conductive material, such as a polysilicon layer doped with boron to provide a p-type polysilicon layer. In some embodiments, the doping with boron is 1×10 19 cm -3 From 1×10 20 cm -3 The level of other dopants at different dopant concentrations (e.g., 1×1016 cm -3 From 5×10 18 cm -3 Dopant concentrations ranging from 0.1 to 100% can be used to provide either n-type or p-type semiconductor materials suitable for use in the conductive layer. One of ordinary skill in the art would recognize many variations, modifications, and alternatives.

[0020]

[0029] The presence of the conductive layer 114 is useful in electrostatically chucking the designed substrate to a semiconductor processing tool, such as a tool having an electrostatic chuck (ESC). The conductive layer 114 allows for rapid dechucking after processing in the semiconductor processing tool. Thus, embodiments of the present invention provide a substrate structure that can be processed in a manner utilized with conventional silicon wafers. One of ordinary skill in the art would recognize many variations, modifications, and alternatives.

[0021]

[0030] A second adhesion layer 116 (e.g., a TEOS layer having a thickness on the order of 1,000 Å) is formed surrounding the conductive layer 114. In some embodiments, the second adhesion layer 116 completely surrounds the conductive layer 114 to form a complete encapsulation structure, and may be formed using an LPCVD process, a CVD process, or any other suitable deposition process, including the deposition of a spin-on dielectric.

[0022]

[0031] A barrier layer 118, for example a silicon nitride layer, is formed to surround the second adhesive layer 116. In one embodiment, the barrier layer 118 is a silicon nitride layer 118 having a thickness of about 2,000 Å to 5,000 Å. The barrier layer 118 completely surrounds the second adhesive layer 116 to form a complete encapsulation structure in some embodiments and can be formed using an LPCVD process. In addition to silicon nitride layers, amorphous materials including SiCN, SiON, AlN, SiC, etc. can be utilized as the barrier layer. In some implementations, the barrier layer 118 includes several sub-layers constructed to form the barrier layer. Thus, the term barrier layer is not intended to mean a single layer or material, but rather to encompass one or more materials stacked together in a composite manner. One skilled in the art would recognize many variations, modifications, and alternatives.

[0023]

[0032] In some embodiments, the barrier layer 118, e.g., a silicon nitride layer, prevents elements present within the core 110, such as yttrium oxide (i.e., yttria), oxygen, metallic impurities, other trace elements, etc., from diffusing and / or outgassing into the environment of a semiconductor processing chamber in which the engineered substrate may reside, e.g., during a high temperature (e.g., 1,000° C.) epitaxial growth process. Utilizing the encapsulation layers described herein, ceramic materials including polycrystalline AlN designed for non-cleanroom environments can be utilized in semiconductor process flows and cleanroom environments.

[0024]

[0033] FIG. 2A is a secondary ion mass spectrometry (SIMS) profile showing species concentration as a function of depth for a designed structure according to one embodiment of the present invention. The structure did not include a barrier layer 118. Referring to Figure 2A, some species present in the ceramic core (e.g., yttrium, calcium, and aluminum) are reduced to negligible concentrations in the engineered layers 120 / 122. The concentrations of calcium, yttrium, and aluminum are reduced by 3, 4, and 6 orders of magnitude, respectively.

[0025]

[0034] 2B is a SIMS profile showing species concentration as a function of depth for a designed structure without a barrier layer after annealing according to an embodiment of the present invention. As mentioned above, during semiconductor processing operations, the designed substrate structure provided by an embodiment of the present invention may be exposed to high temperatures (about 1100° C.) for several hours, for example during epitaxial growth of GaN-based layers.

[0026]

[0035] For the profile shown in Figure 2B, the designed substrate structure was annealed at 1100 °C for 4 hours. As shown in Figure 2B, calcium, yttrium, and aluminum, which were originally present in low concentrations in the as-deposited sample, diffused into the designed layer and reached similar concentrations to the other elements.

[0027]

[0036] FIG. 2C is a SIMS profile showing species concentration as a function of depth for a designed structure with a barrier layer after annealing according to an embodiment of the present invention. The integration of a diffusion barrier layer 118 (e.g., a silicon nitride layer) into the designed substrate structure prevents calcium, yttrium, and aluminum from diffusing into the designed layer during the annealing process that would have occurred in the absence of the diffusion barrier layer. As shown in FIG. 2C, calcium, yttrium, and aluminum present in the ceramic core remain at low concentrations in the designed layer after annealing. Thus, the use of a barrier layer 118 (e.g., a silicon nitride layer) prevents these elements from diffusing through the diffusion barrier, thereby preventing their release into the environment surrounding the designed substrate. Similarly, any other impurities contained within the bulk ceramic material are also contained by the barrier layer.

[0028]

[0037] Typically, the ceramic material utilized to form the core 110 is fired at a temperature in the range of 1,800°C. This process is expected to remove a significant amount of impurities present in the ceramic material. These impurities may include yttrium, calcium, and other elements and compounds resulting from the use of yttria as a sintering agent. Subsequent diffusion of these impurities would be expected to be insignificant during the epitaxial growth process, which is carried out at much lower temperatures in the range of 800°C to 1100°C. However, contrary to conventional expectations, the inventors have determined that significant diffusion of elements can occur through the layers of the engineered substrate even during the epitaxial growth process at temperatures much lower than the firing temperature of the ceramic material. Thus, embodiments of the present invention integrate a barrier layer 118 (e.g., a silicon nitride layer) to prevent outdiffusion of background elements into epitaxial layers such as the engineered layers 120 / 122 from polycrystalline ceramic materials (e.g., AlN) as well as any GaN layer 130. The silicon nitride layer 118 encapsulates the underlying layers and materials and provides the desired barrier layer function.

[0029]

[0038] As shown in Figure 2B, elements originally present in the core 110, including yttrium, diffuse into and through the first TEOS layer 112, the polysilicon layer 114, and the second TEOS layer 116. However, the presence of the silicon nitride layer 118 prevents these elements from diffusing through the silicon nitride layer, thereby preventing their release into the environment surrounding the engineered substrate, as shown in Figure 2C.

[0030]

[0039] 1, a bonding layer 120 (e.g., a silicon oxide layer) is deposited on a portion of the barrier layer 118, e.g., on top of the barrier layer, and is then used during bonding of the substantially single crystalline silicon layer 122. The bonding layer 120 may be about 1.5 μm thick in some embodiments.

[0031]

[0040] The substantially single crystalline layer 122 is suitable for use as a growth layer during an epitaxial growth process to form the epitaxial material 130. In some embodiments, the epitaxial material 130 comprises a GaN layer having a thickness of 2 μm to 10 μm, which may be utilized as one of multiple layers utilized in optoelectronic, RF, power devices, etc. In one embodiment, the substantially single crystalline layer 122 comprises a substantially single crystalline silicon layer that is attached to the silicon oxide layer 118 using a layer transfer process.

[0032]

[0041] FIG. 3 is a simplified schematic diagram illustrating an engineered substrate structure according to one embodiment of the present invention. The engineered substrate 300 shown in FIG. 3 is suitable for a variety of electronic and optical applications. The engineered substrate includes a core 110 that can have a coefficient of thermal expansion (CTE) that substantially matches the CTE of an epitaxial material 130 to be grown on the engineered substrate 300. The epitaxial material 130 is not required as an element of the engineered substrate structure, but is shown as optional since it is typically grown on the engineered substrate structure.

[0033]

[0042] For applications involving the growth of gallium nitride (GaN) based materials (epitaxial layers including GaN based layers), the core 110 can be a polycrystalline ceramic material, such as polycrystalline aluminum nitride (AlN). The thickness of the core can be on the order of 100-1500 μm, for example 725 μm. The core 110 is encapsulated in a first adhesion layer 112, which can be referred to as a shell or encapsulation shell. In this embodiment, the first adhesion layer 112 completely encapsulates the core, although this is not required by the present invention, as will be discussed in more detail with respect to FIG. 4.

[0034]

[0043] In one embodiment, the first adhesion layer 112 comprises a tetraethylorthosilicate (TEOS) layer having a thickness on the order of 1,000 Å. In other embodiments, the thickness of the first adhesion layer varies, for example, from 100 Å to 2,000 Å. Although TEOS is utilized for the adhesion layer in some embodiments, other materials that provide adhesion between a subsequently deposited layer and the layer or material below may also be utilized in accordance with embodiments of the present invention. For example, SiO2, SiON, etc., adhere well to ceramic materials and provide a suitable surface for subsequent deposition of, for example, conductive materials. In some embodiments, the first adhesion layer 112 completely surrounds the core 110 to form a fully encapsulated core and may be formed using an LPCVD process. The adhesion layer provides a surface onto which subsequent layers are adhered to form elements of the designed substrate structure.

[0035]

[0044] In addition to using LPCVD processes, furnace-based processes, and the like to form the encapsulating adhesion layer, other semiconductor processes can be utilized in accordance with embodiments of the present invention. As an example, a deposition process, e.g., CVD, PECVD, etc., can be utilized that coats a portion of the core, the core can be turned over, and the deposition process can be repeated to coat additional portions of the core.

[0036]

[0045] A conductive layer 314 is formed on at least a portion of the first adhesion layer 112. In one embodiment, the conductive layer 314 comprises polysilicon (i.e., polycrystalline silicon) formed by a deposition process on the bottom (e.g., bottom half or back side) of the core / adhesion layer structure. In embodiments in which the conductive layer is polysilicon, the polysilicon layer may have a thickness on the order of several thousand angstroms, e.g., 3,000 Å. In some embodiments, the polysilicon layer may be formed using an LPCVD process.

[0037]

[0046] In one embodiment, the conductive layer 314 may be a polysilicon layer that is doped to provide a highly conductive material, for example, the conductive layer 314 may be doped with boron to provide a p-type polysilicon layer. Doping with boron is about 1×10 19 cm -3 From 1×10 20 cm -3 The conductive layer is at a level ranging from 0.01 to 0.01 mm. The presence of the conductive layer is useful in electrostatically chucking the designed substrate to a semiconductor processing tool, such as a tool having an electrostatic chuck (ESC). The conductive layer 314 allows for rapid dechucking after processing. Thus, embodiments of the present invention provide a substrate structure that can be processed in a manner utilized with conventional silicon wafers. One of ordinary skill in the art would recognize many variations, modifications, and alternatives.

[0038]

[0047] A second adhesion layer 316 (e.g., a second TEOS layer) is formed to surround the conductive layer 314 (e.g., a polysilicon layer). The second adhesion layer 316 has a thickness on the order of 1,000 Å. In some embodiments, the second adhesion layer 316 completely surrounds the conductive layer 314 and the first adhesion layer 112 to form a complete encapsulation structure and may be formed using an LPCVD process. In other embodiments, the second adhesion layer 316 only partially surrounds the conductive layer 314, for example, terminating at a location indicated by a plane 317 that may be aligned with a top surface of the conductive layer 314. In this example, the top surface of the conductive layer 314 will be in contact with a portion of the barrier layer 118. One of ordinary skill in the art would recognize many variations, modifications, and alternatives.

[0039]

[0048] A barrier layer 118 (e.g., a silicon nitride layer) is formed surrounding the second adhesion layer 316. In some embodiments, the barrier layer 118 has a thickness of about 4,000 Å to 5,000 Å. In some embodiments, the barrier layer 118 completely surrounds the second adhesion layer 316 to form a complete encapsulation structure, and may be formed using an LPCVD process.

[0040]

[0049] In some embodiments, the use of a silicon nitride barrier layer prevents elements present within the core 110, such as yttrium oxide (i.e., yttria), oxygen, metallic impurities, other trace elements, etc., from diffusing and / or outgassing into the environment of a semiconductor processing chamber in which the engineered substrate may reside, for example, during a high temperature (e.g., 1,000° C.) epitaxial growth process. Utilizing the encapsulation layers described herein, ceramic materials including polycrystalline AlN designed for non-cleanroom environments can be utilized in semiconductor process flows and cleanroom environments.

[0041]

[0050] FIG. 4 is a simplified schematic diagram illustrating a designed substrate structure according to another embodiment of the present invention. In the embodiment shown in FIG. 4, a first adhesive layer 412 is formed over at least a portion of the core 110, but does not encapsulate the core 110. In this embodiment, the first adhesive layer 412 is formed on the underside of the core 110 (the backside of the core 110) to enhance adhesion of a subsequently formed conductive layer 414, as described more fully below. Although the adhesive layer 412 is shown only on the underside of the core 110 in FIG. 4, it will be understood that deposition of adhesive layer material on other portions of the core does not adversely affect the performance of the designed substrate structure, and such material can be present in various embodiments. Those skilled in the art will recognize many variations, modifications, and alternatives.

[0042]

[0051] The conductive layer 414 does not encapsulate the first adhesive layer 412 and the core 110, but is substantially aligned with the first adhesive layer 412. Although the conductive layer 414 is shown extending along the bottom or back surface of the first adhesive layer 412 and extending up along a portion of the side, extension along a vertical surface is not required by the present invention. Thus, the embodiment may utilize deposition on one side of the substrate structure, masking of one side of the substrate structure, etc. The conductive layer 414 may be formed on one side of the first adhesive layer 412, e.g., a portion of the bottom / back surface. The conductive layer 414 provides electrical conduction to one side of the designed substrate structure, which may be advantageous in RF and high power applications. The conductive layer may include doped polysilicon as described with respect to the conductive layer 114 of FIG. 1.

[0043]

[0052] A portion of the core 110, a portion of the first adhesive layer 412, and the conductive layer 414 are covered with a second adhesive layer 416 to enhance adhesion of the barrier layer 418 to the underlying material. The barrier layer 418 forms an encapsulation structure to prevent diffusion from the underlying layers, as described above.

[0044]

[0053] In addition to semiconductor-based conductive layers, in other embodiments, conductive layer 414 is a metal layer, such as 500 Å of titanium.

[0045]

[0054] Referring again to FIG. 4, depending on the embodiment, one or more layers may be removed. For example, layers 412 and 414 may be removed leaving only a single adhesive shell 416 and barrier layer 418. In another embodiment, only layer 414 may be removed. In this embodiment, layer 412 may also balance the stress and wafer bow caused by layer 120 deposited on top of layer 418. The configuration of the substrate structure with an insulating layer on top of core 110 (e.g., having only an insulating layer between core 110 and layer 120) benefits power / RF applications where a highly insulating substrate is desired.

[0046]

[0055] In another embodiment, the barrier layer 418 may directly encapsulate the core 110, followed by the conductive layer 414 and then the adhesive layer 416. In this embodiment, the layer 120 may be deposited directly onto the adhesive layer 416 from the top. In yet another embodiment, the adhesive layer 416 may be deposited onto the core 110, followed by the barrier layer 418, then the conductive layer 414, and then another adhesive layer 412.

[0047]

[0056] Although some embodiments have been discussed in terms of layers, it should be understood that the term layer can include several sub-layers that are constructed to form the layer of interest. Thus, the term layer does not mean a single layer of a single material, but is intended to encompass one or more materials that are compositely layered to form a desired structure. One of ordinary skill in the art would recognize many variations, modifications, and alternatives.

[0048]

[0057] FIG. 5 is a simplified flow chart illustrating a method for fabricating an engineered substrate according to an embodiment of the present invention. The method can be utilized to fabricate a substrate that is CTE matched to one or more epitaxial layers grown on the substrate. The method 500 includes forming a support structure by providing a polycrystalline ceramic core (510), encapsulating the polycrystalline ceramic core in a first adhesion layer (e.g., a tetraethylorthosilicate (TEOS) shell) that forms a shell (512), and encapsulating the first adhesion layer in a conductive shell (514) (e.g., a polysilicon shell). The first adhesion layer can be formed as a single layer of TEOS. The conductive shell can be formed as a single layer of polysilicon.

[0049]

[0058] The method also includes encapsulating the conductive shell in a second adhesion layer (516) (e.g., a second TEOS shell) and encapsulating the second adhesion layer in a barrier layer shell (518). The second adhesion layer can be formed as a single layer of TEOS. The barrier layer shell can be formed as a single layer of silicon nitride.

[0050]

[0059] Once the support structure is formed by processes 510-518, the method further includes bonding a bonding layer (e.g., a silicon oxide layer) to the support structure (520) and bonding a substantially single crystalline layer, e.g., a substantially single crystalline silicon layer, to the silicon oxide layer (522). Other substantially single crystalline layers can be used according to embodiments of the invention, including SiC, sapphire, GaN, AlN, SiGe, Ge, diamond, Ga2O3, ZnO, etc. Bonding the bonding layer can include deposition of a bonding material followed by a planarization process as described herein. In embodiments described below, a substantially single crystalline layer (e.g., a substantially single crystalline silicon layer) can be bonded to the silicon oxide layer (522). Bonding the silicon layer (layer) to the bonding layer utilizes a layer transfer process in which the layer is a single crystal silicon layer that is transferred from a silicon wafer.

[0051]

[0060] With reference to FIG. 1, the bonding layer 120 may be formed by deposition of a thick (e.g., 4 μm thick) oxide layer followed by a chemical mechanical polishing (CMP) process that thins the oxide to a thickness of about 1.5 μm. The thick initial oxide serves to fill voids and surface features present on the support structure that may be present after fabrication of the polycrystalline core and may continue to be present when the encapsulation layer shown in FIG. 1 is formed. The CMP process provides a substantially flat surface free of voids, particles, or other features that may then be used during a wafer transfer process to bond the substantially single crystal layer 122 (e.g., a substantially single crystal silicon layer) to the bonding layer 120. The bonding layer 120 need not be characterized by an atomically flat surface, but should provide a substantially flat surface that supports bonding of the substantially single crystal layer (e.g., a substantially single crystal silicon layer) with the desired reliability.

[0052]

[0061] A layer transfer process can be used to bond the substantially single crystalline silicon layer 122 to the bonding layer 120. In some embodiments, a silicon wafer (e.g., a silicon (111) wafer) is implanted to form a cleavage plane. After wafer bonding, the silicon substrate can be removed along with a portion of the single crystalline silicon layer below the cleavage plane, resulting in the exfoliated single crystalline silicon layer 122 shown in FIG. 1. The thickness of the substantially single crystalline layer 122 can be varied to meet various application specifications. Additionally, the crystal orientation of the substantially single crystalline layer 122 can be varied to meet application specifications. Additionally, the doping level and profile in the substantially single crystalline layer 122 can be varied to meet a particular application specification.

[0053]

[0062] The method shown in FIG. 5 may also include smoothing the substantially single crystalline layer (524). In some embodiments, the thickness and surface roughness of the substantially single crystalline layer 122 may be modified for high quality epitaxial growth. Different device applications may have slightly different specifications for the thickness and surface smoothness of the substantially single crystalline layer 122. The cleaving process releases the substantially single crystalline layer 122 from the bulk single crystalline silicon wafer at the peak of the implanted ion profile. After cleaving, the substantially single crystalline layer 122 may be conditioned or modified in several ways before being utilized as a growth surface for epitaxial growth of other materials, such as gallium nitride.

[0054]

[0063] First, the transferred substantially single crystalline layer 122 may contain a small residual hydrogen concentration and may have some crystal damage from the implant. Therefore, it may be beneficial to remove a thin portion of the transferred substantially single crystalline layer 122 where the crystal lattice is damaged. In some embodiments, the depth of the implantation may be adjusted to be greater than the desired final thickness of the substantially single crystalline layer 122. The additional thickness allows for removal of the thin portion of the transferred substantially single crystalline layer that is damaged, leaving an undamaged portion of the desired final thickness.

[0055]

[0064] Second, it may be desirable to tailor the overall thickness of the substantially monocrystalline layer 122. In general, it is desirable for the substantially monocrystalline layer 122 to be thick enough to provide a high quality lattice template for the subsequent growth of one or more epitaxial layers, yet thin enough to be highly conformal. The substantially monocrystalline layer 122 is said to be "conformal" when it is relatively thin so that its physical properties can mimic those of the material surrounding it with less constraints and less tendency to develop crystalline defects. The conformance of the substantially monocrystalline layer 122 may be inversely proportional to the thickness of the substantially monocrystalline layer 122. The higher the conformance, the lower the defect density of the epitaxial layer grown on the template, allowing for the growth of a thicker epitaxial layer. In some embodiments, the thickness of the substantially monocrystalline layer 122 may be increased by epitaxially growing silicon on an exfoliated silicon layer. Cut.

[0056]

[0065] Third, it may be beneficial to improve the smoothness of the substantially single crystalline layer 122. The smoothness of the layer may be related to the total hydrogen dose, the presence of any co-implanted species, and the annealing conditions used to form the hydrogen-based cleaved surface. As described below, the initial roughness resulting from the layer transfer (i.e., cleaving process) may be mitigated by thermal oxidation and oxide stripping.

[0057]

[0066] In some embodiments, removal of the damaged layer and adjustment of the final thickness of the substantially single-crystalline layer 122 can be achieved by thermal oxidation of the top of the exfoliated silicon layer, followed by oxide layer stripping with hydrofluoric (HF) acid. For example, an exfoliated silicon layer with an initial thickness of 0.5 μm can be thermally oxidized to form a silicon dioxide layer with a thickness of about 420 nm. After removing the grown thermal oxide, the remaining silicon thickness in the transfer layer can be about 53 nm. During thermal oxidation, the implanted hydrogen can migrate toward the surface. Thus, the subsequent oxide layer stripping can remove some of the damage. Also, thermal oxidation is typically performed at a temperature of 1000° C. or higher. The high temperature can also repair lattice damage.

[0058]

[0067] The silicon oxide layer formed on top of the substantially single crystalline layer during thermal oxidation can be stripped using HF acid etching. The etch selectivity between silicon oxide and silicon (SiO2:Si) by HF acid can be adjusted by adjusting the temperature and concentration of the HF solution as well as the stoichiometry and density of the silicon oxide. Etch selectivity refers to the etch rate of one material over another. The selectivity of the HF solution can range from about 10:1 to about 100:1 for (SiO2:Si). High etch selectivity can reduce the surface roughness by a similar factor from the initial surface roughness. However, the surface roughness of the resulting substantially single crystalline layer 122 can still be greater than desired. For example, a bulk Si(111) surface can have a root mean square (RMS) surface roughness of less than 0.1 nm as determined by a 2 μm×2 μm atomic force microscope (AFM) scan before additional processing. In some embodiments, a desired surface roughness for epitaxial growth of gallium nitride material on Si(111) may be, for example, less than 1 nm, less than 0.5 nm, or less than 0.2 nm over a 30 μm×30 μm AFM scan area.

[0059]

[0068] If the surface roughness of the substantially single crystalline layer 122 after thermal oxidation and oxide layer stripping exceeds the desired surface roughness, additional surface smoothing can be performed. There are several methods to smooth the silicon surface. These methods may include hydrogen annealing, laser trimming, plasma smoothing, and touch polishing (e.g., chemical mechanical polishing or CMP). These methods may include preferential attack of high aspect ratio surface peaks. Thus, high aspect ratio features on the surface can be removed more quickly than low aspect ratio features, thus resulting in a smoother surface.

[0060]

[0069] It should be understood that the particular steps illustrated in FIG. 5 provide a particular method of manufacturing a designed substrate according to one embodiment of the present invention. Other sequences of steps may be performed according to different embodiments. For example, alternative embodiments of the present invention may perform the steps outlined above in a different order. Furthermore, each step illustrated in FIG. 5 may include multiple sub-steps that may be performed in various orders as appropriate for the individual step. Furthermore, additional steps may be added or removed depending on the particular application. Those skilled in the art will recognize numerous variations, modifications, and alternatives.

[0061]

[0070] FIG. 6 is a simplified schematic diagram showing an epitaxial / engineered substrate structure for RF and power applications according to one embodiment of the present invention. In some LED applications, the engineered substrate structure provides a growth substrate that allows for the growth of high quality GaN layers and is a highly efficient, high performance, low cost, and cost effective, low cost ... The board structure is then removed. However, for RF and power device applications, the designed substrate structure forms part of the completed device, and as a result, the electrical, thermal, and other properties of the designed substrate structure, or elements of the designed substrate structure, are important to the particular application.

[0062]

[0071] Referring to FIG. 1, the single crystal silicon layer 122 is typically a release layer split from a silicon donor wafer using implantation and release techniques. Typical implants are hydrogen and boron. For power and RF device applications, the electrical properties of the layers and materials in the designed substrate structure are important. For example, some device architectures are 10 3Highly insulating silicon layers with resistivity exceeding Ωcm are utilized to reduce or eliminate leakage through the substrate and interface layers. Other applications have utilized designs that include conductive silicon layers of a given thickness (e.g., 1 μm) to connect the device's sources to other elements. Therefore, in these applications, it is desirable to control the dimensions and properties of the single crystal silicon layer. In designs where implantation and peeling techniques are used during layer transfer, residual implant atoms, e.g., hydrogen or boron, are present in the silicon layer, thereby changing its electrical properties. Furthermore, it can be difficult to control the thickness, conductivity, and other properties of the thin silicon layer, for example, using adjustments to the implant dose, surface roughness, and cleavage plane position accuracy, which can affect the conductivity as well as the full width at half maximum (FWHM) of the implant profile, as well as implant depth, which can affect the layer thickness.

[0063]

[0072] According to an embodiment of the present invention, silicon epitaxy on a designed substrate structure is utilized to achieve desired properties of a single crystal silicon layer suited to a particular device design.

[0064]

[0073] Referring to FIG. 6, an epitaxial / designed substrate structure 600 includes a designed substrate structure 610 and a silicon epitaxial layer 620 formed thereon. The designed substrate structure 610 can be similar to the designed substrate structures shown in FIG. 1, FIG. 3, and FIG. 4. Typically, the substantially single crystalline silicon layer 122 is on the order of 0.5 μm after layer transfer. Using a surface conditioning process, the thickness of the single crystalline silicon layer 122 can be reduced to about 0.3 μm in some processes. To increase the thickness of the single crystalline silicon layer to about 1 μm for use in forming a reliable ohmic contact, an epitaxial single crystalline silicon layer 620 is grown on the substantially single crystalline silicon layer 122 formed by the layer transfer process, for example, using an epitaxial process. The epitaxial single crystalline silicon layer 620 can be grown using a variety of epitaxial growth processes, including CVD, ALD, MBE, and the like. The thickness of the epitaxial single crystal silicon layer 620 may be in the range of about 0.1 μm to about 20 μm, for example, between 0.1 μm and 10 μm.

[0065]

[0074] FIG. 7 is a simplified schematic diagram illustrating III-V epitaxial layers on a designed substrate structure according to one embodiment of the present invention. The structure shown in FIG. 7 can be referred to as a double epitaxial structure, as described below. As shown in FIG. 7, a designed substrate structure 710 including an epitaxial single crystal silicon layer 620 has a III-V epitaxial layer 720 formed thereon. In one embodiment, the III-V epitaxial layer includes gallium nitride (GaN).

[0066]

[0075] The desired thickness of the III-V epitaxial layer 720 may vary substantially depending on the desired function. In some embodiments, the thickness of the III-V epitaxial layer 720 may vary between 0.5 μm and 100 μm, such as greater than 5 μm. The resulting breakdown voltage of a device fabricated on the III-V epitaxial layer 720 may vary depending on the thickness of the III-V epitaxial layer 720. Some embodiments provide a breakdown voltage of at least 100V, 300V, 600V, 1.2kV, 1.7kV, 3.3kV, 5.5kV, 13kV, or 20kV.

[0067]

[0076] To provide electrical conductivity between portions of the III-V epitaxial layer 720, which may include multiple sublayers, a set of vias 724 are formed, in this example passing from the top surface of the III-V epitaxial layer 720 to the epitaxial single crystal silicon layer 620. The vias 724 may be lined with an insulating layer (not shown) such that they are insulated from the III-V epitaxial layer 720. As an example, these vias may be used to connect an electrode of a diode or transistor to the underlying silicon layer by providing an ohmic contact through the vias, thereby relieving charge build-up in the device.

[0068]

[0077] If III-V epitaxial layers were grown on the single crystal silicon layer 122, it would be difficult to form such ohmic contacts through the vias because it would be difficult to terminate the via etch in the single crystal silicon layer 122, e.g., etch down to 5 μm of GaN and reliably terminate the etch at 0.3 μm of silicon layer across the entire wafer. Utilizing embodiments of the present invention, it is possible to provide single crystal silicon layers that are several microns thick, which is difficult to do using implant and lift processes due to the high implant energies required to achieve large implant depths. Instead, thick silicon layers enable applications such as the illustrated vias that enable a variety of device designs.

[0069]

[0078] In addition to increasing the thickness of the silicon "layer" by epitaxially growing the single crystal silicon layer 620 on the single crystal silicon layer 122, other adjustments can be made to the original properties of the single crystal silicon layer 122, including modifying the conductivity, crystallinity, etc. For example, if a silicon layer on the order of 10 μm is desired prior to additional epitaxial growth of III-V layers or other materials, such a thick layer can be grown according to embodiments of the present invention.

[0070]

[0079] Because the implantation process may affect the properties of the single crystal silicon layer 122, e.g., residual boron / hydrogen atoms may affect the electrical properties of the silicon, embodiments of the invention remove a portion of the single crystal silicon layer 122 prior to epitaxial growth of the single crystal silicon layer 620. For example, the single crystal silicon layer 122 may be thinned to form a layer 0.1 μm thick or less to remove most or all of the residual boron / hydrogen atoms. The subsequent growth of the single crystal silicon layer 620 is used to provide a single crystal material having electrical and / or other properties that are substantially independent of the corresponding properties of a layer formed using a layer transfer process.

[0071]

[0080] In addition to increasing the thickness of the single crystal silicon material bonded to the designed substrate structure, the electrical properties, including conductivity, of the epitaxial single crystal silicon layer 620 may be different from that of the single crystal silicon layer 122. Doping of the epitaxial single crystal silicon layer 620 during growth may produce p-type silicon by doping with boron and n-type silicon by doping with phosphorus. Undoped silicon may be grown to provide high resistivity silicon for use in devices with insulating regions. The insulating layer may be particularly useful in RF devices.

[0072]

[0081] The lattice constant of the epitaxial single crystal silicon layer 620 can be tailored during growth to be different from the lattice constant of the single crystal silicon layer 122 to produce a strained epitaxial material. In addition to silicon, other elements can be epitaxially grown to provide layers including strained layers, layers including silicon germanium, etc. For example, buffer layers can be grown on the single crystal silicon layer 122, on the epitaxial single crystal silicon layer 620, or between layers to enhance subsequent epitaxial growth. These buffer layers can include strained III-V layers, silicon germanium strained layers, etc. Additionally, the buffer layers and other epitaxial layers can be varied in mole fraction, dopant, polarity, etc. One of ordinary skill in the art would recognize many variations, modifications, and alternatives.

[0073]

[0082] In some embodiments, strain present in the single crystal silicon layer 122 or the epitaxial single crystal silicon layer 620 may be relieved during growth of subsequent epitaxial layers, including III-V epitaxial layers.

[0074]

[0083] 8 is a simplified flow chart illustrating a method of manufacturing an engineered substrate according to another embodiment of the present invention. The method includes forming a support structure by providing a polycrystalline ceramic core (810), forming a first adhesion layer bonded to at least a portion of the polycrystalline ceramic core (812). The first adhesion layer can include a tetraethylorthosilicate (TEOS) layer. The method also includes forming a conductive layer bonded to the first adhesion layer (814). The conductive layer can be a polysilicon layer. The first adhesion layer can be formed as a single layer of TEOS. The conductive layer can be formed as a single layer of polysilicon.

[0075]

[0084] The method also includes forming a second adhesion layer bonded to at least a portion of the conductive layer (816) and forming a barrier shell (818). The second adhesion layer can be formed as a single layer of TEOS. The barrier shell can be formed as a single layer of silicon nitride or a series of sublayers that form the barrier shell.

[0076]

[0085] Once the support structure is formed by processes 810-818, the method further includes bonding a bonding layer (e.g., a silicon oxide layer) to the support structure (820) and bonding the substantially single crystalline silicon layer or the substantially single crystalline layer to the silicon oxide layer (822). Bonding the bonding layer can include deposition of a bonding material followed by a planarization process as described herein.

[0077]

[0086] A layer transfer process can be used to bond the substantially single crystalline silicon layer 122 to the bonding layer 120. In some embodiments, a silicon wafer (e.g., a silicon (111) wafer) is implanted to form a cleavage plane. After wafer bonding, the silicon substrate can be removed along with a portion of the single crystalline silicon layer below the cleavage plane, resulting in the exfoliated single crystalline silicon layer 122 shown in FIG. 1. The thickness of the substantially single crystalline silicon layer 122 can be varied to meet various application specifications. Additionally, the crystal orientation of the substantially single crystalline layer 122 can be varied to meet application specifications. Additionally, the doping level and profile in the substantially single crystalline layer 122 can be varied to meet a particular application specification. In some embodiments, the substantially single crystalline silicon layer 122 can be smoothed as described above.

[0078]

[0087] 8 also includes epitaxially growing an epitaxial silicon layer on the substantially monocrystalline silicon layer 824, and epitaxially growing an epitaxial III-V layer on the epitaxial silicon layer 826. In some embodiments, the epitaxial III-V layer may include gallium nitride (GaN).

[0079]

[0088] It should be understood that the specific steps illustrated in FIG. 8 provide a particular method of manufacturing a designed substrate according to another embodiment of the present invention. Other sequences of steps may be performed according to another embodiment. For example, alternative embodiments of the present invention may perform the steps outlined above in a different order. Furthermore, each step illustrated in FIG. 8 may include multiple sub-steps that may be performed in various orders as appropriate for the individual step. Furthermore, additional steps may be added or removed depending on the particular application. Those skilled in the art will recognize numerous variations, modifications, and alternatives.

[0080]

[0089] It is also understood that the examples and embodiments described herein are for illustrative purposes only, and that various modifications or changes in light thereof will be suggested to those skilled in the art and are to be included within the spirit and scope of this application and the appended claims.

Claims

1. 1. A support structure comprising: A polycrystalline ceramic core; a first adhesive layer bonded to the polycrystalline ceramic core; a conductive layer bonded to the first adhesive layer; a second adhesive layer coupled to the conductive layer; a barrier layer bonded to the second adhesive layer; a support structure including: a bonding layer coupled to the support structure; a substantially monocrystalline layer comprising at least one of silicon carbide, sapphire, or gallium nitride bonded to the bonding layer; an epitaxial semiconductor layer bonded to the substantially monocrystalline layer; A substrate comprising:

2. The substrate of claim 1 , wherein the polycrystalline ceramic core comprises aluminum nitride.

3. The substrate of claim 1 , wherein the bonding layer comprises silicon oxide.

4. The substrate of claim 1 , wherein the epitaxial semiconductor layer comprises an epitaxial III-V layer.

5. The substrate of claim 4, wherein the epitaxial III-V layer comprises an epitaxial gallium nitride layer having a thickness of about 5 μm or greater.

6. The substrate of claim 4 further comprising a plurality of vias extending from the epitaxial III-V layer to the epitaxial semiconductor layer.

7. The substrate of claim 1 , wherein the epitaxial semiconductor layer comprises an epitaxial single crystal silicon layer, and the substrate further comprises an epitaxial III-V layer bonded to the epitaxial single crystal silicon layer.

8. the first adhesive layer encapsulating the polycrystalline ceramic core; the conductive layer encapsulates the first adhesive layer; The substrate of claim 1 , wherein the second adhesive layer encapsulates the conductive layer.

9. The substrate of claim 1 , further comprising an epitaxial silicon layer formed on said substantially monocrystalline layer.

10. the first adhesion layer comprises a first tetraethylorthosilicate (TEOS) layer encapsulating the polycrystalline ceramic core; the conductive layer includes a polysilicon layer encapsulating the first TEOS layer; the second adhesion layer includes a second TEOS layer encapsulating the polysilicon layer; The substrate of claim 1 , wherein the barrier layer comprises a silicon nitride layer encapsulating the second TEOS layer.

11. 1. A method of manufacturing a substrate, the method comprising: Provides a polycrystalline ceramic core, forming a first adhesive layer bonded to the polycrystalline ceramic core; forming a conductive layer coupled to the first adhesive layer; forming a second adhesive layer coupled to the conductive layer; forming a barrier layer bonded to the second adhesive layer to form a support structure; forming a bonding layer coupled to the support structure; bonding a substantially single crystalline layer to the bonding layer, the substantially single crystalline layer comprising at least one of silicon carbide, sapphire, or gallium nitride; forming one or more epitaxial III-V layers coupled to the substantially single crystalline layer; A method comprising:

12. the first adhesive layer encapsulating the polycrystalline ceramic core; the conductive layer encapsulates the first adhesive layer; the second adhesive layer encapsulates the conductive layer; The method of claim 11 , wherein the barrier layer encapsulates the second adhesive layer.

13. The method of claim 11 , further comprising forming an epitaxial silicon layer on the substantially monocrystalline layer.

14. The method of claim 11 , wherein the polycrystalline ceramic core comprises aluminum nitride and the one or more epitaxial III-V layers comprise an epitaxial gallium nitride layer.

15. The method of claim 14, wherein the epitaxial gallium nitride layer has a thickness of about 5 μm or greater.

16. 12. The method of claim 11 , further comprising forming a strained epitaxial silicon layer bonded to the substantially single crystalline layer prior to forming the one or more epitaxial III-V layers, the one or more epitaxial III-V layers being bonded to the strained epitaxial silicon layer.

17. The method of claim 11 , further comprising forming a plurality of vias extending from the one or more epitaxial III-V layers to the substantially single crystalline layer.

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