Silicon Carbide Epitaxial Substrate

Abstract

To provide a method for manufacturing a silicon carbide single crystal that can grow a high-quality silicon carbide single crystal at high speed.SOLUTION: A silicon carbide epitaxial substrate 10 includes: a silicon carbide substrate 20 having a first surface and a silicon carbide epitaxial layer 30 positioned at the first surface. The first surface 20a is a (000-1) C surface and has a linear surface defect density of less than 1.0 cm-2 at a top surface 30a of the silicon carbide epitaxial layer. A ratio of the linear surface defect density to a basal surface dislocation density is less than 0.04% at the first surface of the silicon carbide substrate. A diameter of the silicon carbide substrate is equal to or greater than 100 mm.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present application relates to a silicon carbide epitaxial substrate and a method for producing the same. [Background technology]

[0002] Silicon carbide (SiC) semiconductors have a higher dielectric breakdown field strength, electron saturation drift velocity, and thermal conductivity than silicon semiconductors. For this reason, silicon carbide semiconductors can realize power devices that can operate at higher temperatures, higher speeds, and higher currents than conventional silicon devices, and are attracting attention as semiconductors for realizing switching elements that drive motors used in electric vehicles, hybrid cars, etc. with high efficiency.

[0003] Silicon carbide semiconductors have the same chemical composition, but the stacking direction ( <0001> There are multiple polytypes in which the arrangement of carbon atoms and silicon atoms differs in the direction of the crystal. Furthermore, because the internal energy difference between these polytypes is small, different polytypes are easily generated in a single crystal, and the different polytypes that are generated become dislocations and stacking faults (SFs). Generally, silicon carbide substrates contain more dislocations and stacking faults than silicon substrates. For this reason, when manufacturing semiconductor devices such as switching elements using silicon carbide semiconductors, a silicon carbide epitaxial layer with fewer defects is formed on the silicon carbide substrate, and the main structure of the semiconductor device is formed in the silicon carbide epitaxial layer.

[0004] However, dislocations and stacking faults are extended defects, and dislocations and stacking faults occurring near the surface of a silicon carbide substrate propagate to the silicon carbide epitaxial layer during epitaxial growth, and tend to degrade the crystal quality of the silicon carbide epitaxial layer. For this reason, the development of technology to improve the crystal quality of the silicon carbide substrate itself and technology to form a high-quality silicon carbide epitaxial layer is important for the widespread use of silicon carbide semiconductor devices.

[0005] Stacking faults are planar defects and are typical defects that occur in silicon carbide epitaxial layers. In addition, when a bipolar device using a silicon carbide semiconductor contains basal plane dislocations (abbreviated as BPD), the basal plane dislocations expand and stacking faults are formed when the bipolar device is forward biased. Since stacking faults have high resistance, when stacking faults increase, the internal resistance of the device also increases, and the heat generated by the power loss in the device increases, which may result in the device being destroyed. Such changes in device characteristics are known as bipolar degradation phenomena (Non-Patent Document 1). For this reason, from the viewpoint of long-term reliability of electronic devices, it is necessary to suppress the occurrence of basal plane dislocations in silicon carbide epitaxial growth films and also to suppress the occurrence of stacking faults that become high resistance layers.

[0006] Linear surface defects appear on the surface of a silicon carbide epitaxial layer. Surface linear defects may be accompanied by stacking faults, and it is therefore preferable to suppress the occurrence of linear surface defects in an epitaxially grown film. [Prior art documents] [Patent documents]

[0007] [Patent Document 1] Patent No. 6295969 specification [Patent Document 2] Patent No. 4539140 specification [Non-patent literature]

[0008] [Non-Patent Document 1] Noboru Otani, "Current status of development of low resistivity SiC single crystals for power devices", Journal of the Japanese Society for Crystal Growth, Vol. 45, No. 3 (2018) 45-3-01 [Non-Patent Document 2] Yuuki Ishida, "Current status of high-speed SiC epitaxial growth technology by chemical vapor deposition," J.Vac.Soc.Jpn., Vol.54, No.6, 2011 [Non-Patent Document 3] Shunichi Nakamura and 2 others, "Homoepitaxial growth on 4H-SiC {0001}-near faces," Materials, J. Soc. Mat. Sci., Japan, Vol. 53, No. 12, pp. 1323-1327, Dec. 2004 Summary of the Invention [Problem to be solved by the invention]

[0009] The present application provides a silicon carbide epitaxial substrate having a silicon carbide epitaxial layer with reduced defects, and a method for producing the same. [Means for solving the problem]

[0010] A silicon carbide epitaxial substrate according to one embodiment of the present disclosure comprises a silicon carbide substrate having a first surface, and a silicon carbide epitaxial layer located on the first surface, the first surface being a (000-1) C surface, and a linear surface defect density of 1.0 cm on an upper surface of the silicon carbide epitaxial layer. -2 and the stacking fault density is less than 1.2 cm -2 is less than.

[0011] The linear surface defect density is 0.5 cm -2 It may be less than.

[0012] The linear surface defect density is 0.35 cm -2 It may be less than.

[0013] The stacking fault density is 1.0 cm -2 It may be less than.

[0014] The stacking fault density is 0.35 cm -2 It may be less than.

[0015] the first surface of the silicon carbide substrate has a basal plane dislocation density of 3000 cm -2 It may be less than.

[0016] a basal plane dislocation density of 2000 cm -2 It may be less than.

[0017] The first surface of the silicon carbide substrate may have a ratio of the linear surface defect density to the basal plane dislocation density of less than 0.04%.

[0018] The first surface of the silicon carbide substrate may have a stacking fault density relative to a basal plane dislocation density of less than 0.05%.

[0019] The first surface may have an off angle of 4° or less.

[0020] The first surface may have a surface roughness Ra of 1 nm or less.

[0021] A method for producing a silicon carbide epitaxial substrate according to an embodiment of the present disclosure includes the steps of preparing a silicon carbide substrate having a first surface which is a (000-1) C-plane, holding the silicon carbide substrate in a growth chamber, introducing a gas containing carbon and silicon in a C / Si ratio of 1 or more and 1.6 or less into the growth chamber, and growing a silicon carbide epitaxial layer on the first surface.

[0022] the first surface of the silicon carbide substrate has a basal plane dislocation density of 3000 cm -2 It may be less than.

[0023] a basal plane dislocation density of 2000 cm -2 It may be less than.

[0024] The first surface may have an off angle of 4° or less.

[0025] The first surface may have a surface roughness Ra of 1 nm or less. Effect of the Invention

[0026] According to embodiments of the present disclosure, a silicon carbide epitaxial substrate having a silicon carbide epitaxial layer with reduced defects and a method for manufacturing the same are provided. [Brief description of the drawings]

[0027] [Figure 1] FIG. 1 is a schematic cross-sectional view of a silicon carbide epitaxial substrate of the present embodiment. [Diagram 2] FIG. 2 is a schematic diagram showing the crystal orientation of a silicon carbide substrate used in the silicon carbide epitaxial substrate of this embodiment. [Diagram 3] FIG. 3 is a diagram showing the relationship between the basal plane dislocation density and the linear surface defect density in the substrates of the examples and the comparative examples. [Figure 4] FIG. 4 is a graph showing the relationship between the basal plane dislocation density and the stacking fault density in the substrates of the examples and the comparative examples. [Diagram 5] FIG. 5 is a diagram showing the relationship between the basal plane dislocation density in the substrates of the examples and the comparative examples and the ratio of the linear surface defect density to the basal plane dislocation density in the substrate. [Figure 6] FIG. 6 is a graph showing the relationship between the basal plane dislocation density in the substrates of the examples and the comparative examples and the ratio of the stacking fault density to the basal plane dislocation density in the substrate. [Figure 7] FIG. 7 shows examples of differential interference contrast optical microscope images of linear surface defects observed in the silicon carbide epitaxial substrates of the example and comparative example. [Figure 8] FIG. 8 shows an example of a PL image taken with a near-ultraviolet filter of stacking faults observed in the silicon carbide epitaxial substrates of the example and the comparative example. [Figure 9] FIG. 9 shows examples of PL images taken with a visible light filter of stacking faults observed in silicon carbide epitaxial substrates of the example and comparative example. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0028] (Structure of silicon carbide epitaxial substrate 10) 1 is a schematic cross-sectional view of a silicon carbide epitaxial substrate 10 of this embodiment. The silicon carbide epitaxial substrate 10 includes a silicon carbide substrate 20 and a silicon carbide epitaxial layer 30.

[0029] The silicon carbide substrate 20 has a first surface 20a and a second surface 20b located on the opposite side to the first surface 20a, and a silicon carbide epitaxial layer 30 is located on the first surface 20a. The silicon carbide substrate 20 is made of silicon carbide single crystal. The polytype is preferably 4H. There is no particular limit to the size of the silicon carbide substrate 20. However, from the viewpoint of mass productivity of semiconductor devices fabricated using the silicon carbide epitaxial substrate 10, the silicon carbide substrate 20 preferably has a diameter of 100 mm or more, and more preferably has a diameter of 150 mm. The silicon carbide substrate 20 has a thickness determined according to the diameter according to the standard. For example, when the diameter is 100 mm or 150 mm, the thickness of the silicon carbide substrate 20 is 350 μm ± 25 μm or 500 μm ± 25 μm.

[0030] 2 is a schematic diagram showing the crystal orientation of the silicon carbide substrate used in the silicon carbide epitaxial substrate of this embodiment. The first surface 20a has the following plane orientation.

[0031]

number

[0032] Here, C represents carbon, and indicates that the outermost surface of the first surface 20a is a carbon surface where carbon is exposed.

[0033] Hereinafter, for the sake of simplicity in the description, this will be referred to as the (000-1) C-plane. On the other hand, the second surface 20b is a (0001) Si-plane, and the outermost surface of the second surface 20b is a silicon surface with exposed silicon.

[0034] It is known that silicon carbide substrates have a carbon surface and a silicon surface, but conventionally, silicon carbide epitaxial layers are formed on the silicon surface of silicon carbide substrates. This is because it is easier to control the growth of a silicon carbide epitaxial layer on a silicon surface, and it is easier to control doping. For this reason, when patent documents and non-patent documents do not mention whether the top surface of a silicon carbide substrate is a carbon surface or a silicon surface, it is considered that the silicon surface of the silicon carbide substrate is used.

[0035] The present inventors have conducted detailed studies on techniques for suppressing linear surface defects and stacking faults, which are major defects in silicon carbide semiconductors, and have found that, as described below, it is possible to suppress linear surface defects and stacking faults by epitaxially growing a silicon carbide epitaxial layer on a carbon surface.

[0036] The silicon carbide substrate 20 is preferably an off-substrate. FIG. 2 is a schematic diagram of a cross section of the silicon carbide substrate 20. The silicon carbide substrate 20 is preferably an off-substrate having an off-angle θ. Specifically, the first surface 20a, or the normal 20n of the first surface 20a, is preferably inclined by θ from the [000-1] direction to the

[1120] direction. The off-angle θ is preferably 0.5° or more and 8° or less, and more preferably 0.5° or more and 5° or less.

[0037] The characteristics of the first surface 20a of the silicon carbide substrate 20 will be described in detail. The first surface 20a is preferably subjected to CMP (chemical mechanical polishing). Specifically, it is preferable that the first surface 20a is polished by CMP until the surface roughness Ra of the first surface 20a is 1 nm or less. More preferably, the Ra of the first surface 20a is 0.2 nm or less. Ra can be measured, for example, by a white light interference microscope. For example, it is a value obtained by measuring the first surface 20a at three points with a length of 100 μm and calculating the average. Ideally, Ra can be 0 nm, but in reality, Ra will never be 0 nm. For this reason, the lower limit of the preferable range of Ra is greater than 0.

[0038] In addition, the BPD density on the first surface 20a is 3000 particles / cm 2 Below (3000cm -2 (less than 2000 cm -2 More preferably, it is 1000 cm or less. -2 The BPD density can be measured, for example, by etching the first surface 20a with molten KOH and measuring the number of BPDs that appear as etch pits using an optical microscope. As with Ra, the lower limit of the preferred range of the BPD density is 0 cm -2 Greater than.

[0039] The silicon carbide epitaxial layer 30 is formed by epitaxial growth on the first surface 20a of the silicon carbide substrate 20. The thickness of the silicon carbide epitaxial layer 30 can be set arbitrarily depending on the performance required of a semiconductor device fabricated using the silicon carbide epitaxial substrate 10. For example, the thickness of the silicon carbide epitaxial layer 30 is approximately 1 μm or more and 100 μm or less.

[0040] On the upper surface 30a of the silicon carbide epitaxial layer 30, the linear surface defect density is 1.0 cm -2 The linear surface defect density is preferably less than 0.5 cm -2 More preferably, it is less than 0.35 cm -2 More preferably, it is less than 0.1 cm -2 It is more preferable that the stacking fault density is less than 1.2 cm on the upper surface 30a of the silicon carbide epitaxial layer 30. -2 The stacking fault density is preferably less than 1.0 cm -2 More preferably, it is less than 0.35 cm -2 More preferably, it is less than 0.1 cm -2 Similar to Ra, the lower limit of the preferred range of the linear surface defect density and the stacking fault density is 0 cm 2 Greater than.

[0041] In this embodiment, when the upper surface 30a of the silicon carbide epitaxial layer 30 is viewed from a direction perpendicular thereto, the linear surface defect has an uneven surface with respect to the upper surface 30a, and has a long and thin linear shape. The longitudinal direction (extending direction) of the linear surface defect may be aligned with the step-flow growth direction (direction of the off-angle), may be inclined at about ±5° to 60° with respect to the step-flow growth direction, or may extend in two directions in a V-shape with respect to the step-flow growth direction. In this embodiment, the linear surface defect originates from a defect or scratch on the first surface 20a of the silicon carbide substrate 20. Therefore, the longitudinal length L of the linear surface defect depends on the thickness d of the silicon carbide epitaxial layer 30 and the off-angle θ of the silicon carbide substrate 20, and has a relationship of L=d / tan θ. The linear surface defect is also called a carrot defect.

[0042] The density of linear surface defects can be measured, for example, by a wafer inspection device / review device capable of acquiring differential interference contrast optical microscope images. Such a wafer inspection device / review device can acquire the positions and number of linearly appearing brightness change areas in the acquired differential interference contrast optical microscope images, and calculate the density of linear surface defects.

[0043] The stacking faults are planar defects that start from defects or scratches on the first surface 20a of the silicon carbide substrate 20 or from defects inside the silicon carbide epitaxial layer 30, and extend in a triangular shape toward the upper surface 30a of the silicon carbide epitaxial layer 30, reaching the upper surface 30a. Most of the stacking faults are located in the silicon carbide epitaxial layer 30. The stacking fault density can be measured, for example, by a wafer inspection device / review device that is equipped with a 355 nm excitation light source and a near-ultraviolet filter and can acquire photoluminescence images. Such a wafer inspection device / review device can acquire the positions and number of areas of triangular brightness changes in the acquired photoluminescence image, and calculate the density of stacking faults.

[0044] (Method of Manufacturing Silicon Carbide Epitaxial Substrate 10) Hereinafter, a method for manufacturing the silicon carbide epitaxial substrate 10 of this embodiment will be described. First, a silicon carbide substrate 20 is prepared. The silicon carbide substrate 20 has the first surface 20a with the above-mentioned plane orientation and off-angle. The first surface 20a is prepared by CMP to have a surface roughness Ra of 1 nm or less. The smaller the surface roughness Ra, the more preferable it is. For this reason, for example, a commercially available silicon carbide substrate 20 may be obtained, and the first surface 20a may be subjected to CMP. For example, the first surface 20a may be subjected to CMP using the method described in Japanese Patent No. 6295969. In addition to the step of performing CMP, a step of wet etching the first surface 20a and a step of oxidizing the first surface 20a with a gas may be performed, and these three steps may be appropriately combined and performed two or more times.

[0045] Next, a silicon carbide epitaxial layer 30 is formed. Any method may be used as long as the device is capable of epitaxially growing the silicon carbide epitaxial layer 30. From the viewpoint of being able to form a silicon carbide epitaxial layer 30 with uniform characteristics on a silicon carbide substrate 20 having a large diameter, it is preferable to form the silicon carbide epitaxial layer 30 using a CVD device using a chemical vapor deposition method.

[0046] For example, a silicon carbide substrate 20 is introduced into a growth chamber of a CVD apparatus and placed on a holder with the first surface 20a, which is the (000-1) C surface, facing up. The silicon carbide substrate 20 is heated to a temperature of 1500° C. to 1800° C., and a carrier gas, a gas serving as a carbon source, a gas serving as a silicon source, and a gas serving as a dopant are introduced into the growth chamber to grow a silicon carbide epitaxial layer 30. For example, hydrogen (H2) or the like can be used as the carrier gas. Propane (C3H8) or the like can be used as the carbon source gas in the raw material gas. Silane (SiH4) or the like can be used as the silicon source gas in the raw material gas. Nitrogen (N2) or the like can be used as the dopant gas. Before growing the silicon carbide epitaxial layer 30, only the carrier gas may be introduced into the growth chamber and the first surface 20a of the silicon carbide substrate 20 may be cleaned.

[0047] The ratio C / Si of carbon in the carbon source gas to silicon in the silicon source gas to be introduced is preferably 1 or more. Specifically, C / Si is preferably 1 or more and 1.6 or less. As described later, when C / Si exceeds 1.6, the linear surface defect density increases on the first surface 20a of the growing silicon carbide epitaxial layer 30. In addition, as described in the non-patent document "Current Status of SiC High-Speed ​​Epitaxial Growth Technology by Chemical Vapor Phase Method (J.Vac.Soc.Jpn., Vol.54, No.6,2011)", when C / Si is less than 1 and silane (SiH4) is excessively supplied, Si droplets of Si aggregate on the surface of the epitaxial layer are generated during the epitaxial growth process. This is not preferable because defects caused by Si droplets are generated.

[0048] The pressure in the growth chamber during the growth of the silicon carbide epitaxial layer 30 is preferably 10 kPa or more and 50 kPa or less.

[0049] As will be described in detail in the following examples, according to the method for producing the silicon carbide epitaxial substrate 10 of this embodiment, the silicon carbide epitaxial layer 30 is grown on the (000-1) C face of the silicon carbide substrate 20, and the generation of linear surface defects and stacking faults in the silicon carbide epitaxial layer 30 starting from linear surface defects, stacking faults or scratches on the first face 20a of the silicon carbide substrate 20 can be suppressed. In particular, the stacking fault density can be reduced. In addition, by setting the C / Si in the raw material gas to 1 or more and 1.6 or less during the growth of the silicon carbide epitaxial layer 30, the linear surface defect density in the silicon carbide epitaxial layer 30 can be reduced. C / Si is more preferably 1.5 or less, more preferably 1.4 or less, and even more preferably 1.3 or less. Furthermore, by subjecting the first surface 20a, which is the (000-1)C surface, to CMP and setting the surface roughness Ra of the first surface 20a to 1 nm or less, the propagation of linear surface defects and stacking faults from the silicon carbide substrate 20 to the silicon carbide epitaxial layer 30 can be suppressed.

[0050] (Example) <Sample preparation> Hereinafter, a silicon carbide epitaxial substrate 10 was produced using the method for producing a silicon carbide epitaxial substrate according to this embodiment, and the linear surface defect density and stacking fault density were measured. The results will be described below.

[0051] (Examples 1 to 6) A silicon carbide substrate 20 having a diameter of 150 mm and a first surface 20a that is a (000-1) C surface and an off angle θ of 4° was prepared. CMP was applied to the first surface 20a until the surface roughness Ra was 1 nm or less. CMP was performed using a slurry containing colloidal silica as a main component and an oxidizing agent added thereto, and a polishing pad. Thereafter, a silicon carbide epitaxial layer 30 was grown on the first surface 20a of the silicon carbide substrate 20. The growth temperature was set to 1600° C., the growth rate was set to 40 μm / h, and the pressure in the growth chamber during growth was set to 30 kPa. As shown in Table 1, the C / Si ratio in the source gas was set to 1.25 or 1.4. Hydrogen was used as the carrier gas, and propane and silane were used as the source gas. Nitrogen was used as the dopant source. Each of Examples 1 to 6 was produced using one silicon carbide substrate 20.

[0052] (Reference examples 1~3) The C / Si ratio in the source gas was set to 1.7, and the other conditions were the same as in Examples 1 to 6, to produce a silicon carbide epitaxial substrate of Reference Example 1.

[0053] A silicon carbide substrate having a first surface that was not subjected to CMP and a surface roughness Ra of about 10 nm was prepared, and the other conditions were the same as in Examples 3 to 5 to produce a silicon carbide epitaxial substrate of Reference Example 2.

[0054] A silicon carbide substrate having a first surface of a (0001) Si surface was prepared, and the other conditions were the same as those of Examples 3 to 5 to produce a silicon carbide epitaxial substrate of Reference Example 3.

[0055] Reference Examples 1 and 2 were each produced using one silicon carbide substrate, and Reference Example 3 was produced using 33 silicon carbide substrates of various grades.

[0056] <Measurement> The basal plane dislocation density of the first surface of the silicon carbide substrate was based on the values ​​disclosed by the substrate manufacturer. The linear surface defect density was measured on the top surface of the silicon carbide epitaxial layer of the silicon carbide epitaxial substrate that was fabricated. The equipment and conditions used for the measurement are as follows. The measurement was performed excluding the region from the outer periphery of the substrate to 3 mm inward. Measurement device name: SICA88 manufactured by Lasertec Corporation Measurement conditions: Optical inspection using a light source with a wavelength of 532 nm

[0057] The acquired differential interference contrast optical microscope images were analyzed using the image analysis software provided with the instrument. Since linear surface defects have unevenness relative to the surface, they appear in the image with a different brightness than normal crystal parts, which are flat. Figure 7 shows an example of a differential interference contrast optical microscope image of a linear surface defect. The number of linear surface defects was determined as the total number of linear surface defects parallel to the step-flow growth direction, linear surface defects extending at an angle to the step-flow growth direction, and V-shaped linear surface defects extending in an open manner relative to the step-flow growth direction.

[0058] The stacking fault density on the upper surface of the silicon carbide epitaxial layer of the fabricated silicon carbide epitaxial substrate was measured. The measurement was performed using the following equipment and conditions. The measurement was performed excluding the region from the outer periphery of the substrate to 3 mm inward. Measurement device name: KLA TENCOR Candela CS920 Measurement conditions: Photoluminescence (PL) inspection using an excitation light wavelength of 355 nm. Near ultraviolet and visible light filters were used.

[0059] Figure 8 shows a PL image of a stacking fault taken with a near-ultraviolet filter, and Figure 9 shows a PL image of a stacking fault taken with a visible light filter.

[0060] <Results and Discussion> Here, the basal plane dislocation density of the first surface of the silicon carbide substrate is used as an index of the crystal quality grade of the silicon carbide substrate. Table 1 shows the basal plane dislocation density of the first surface of the silicon carbide substrate of Examples 1 to 6 and Reference Examples 1 to 3, and the linear surface defect density and stacking fault density on the upper surface of the silicon carbide epitaxial layer. FIG. 3 shows the relationship between the basal plane dislocation density and the linear surface defect density of these samples. FIG. 4 shows the relationship between the basal plane dislocation density and the stacking fault density of these samples. FIG. 5 shows the relationship between the basal plane dislocation density of these samples and the ratio of the linear surface defect density to the basal plane dislocation density. FIG. 6 shows the relationship between the basal plane dislocation density of these samples and the ratio of the stacking fault density to the basal plane dislocation density.

[0061] [Table 1]

[0062] A comparison between Examples 1 to 6 and Reference Examples 1 and 3 reveals that the stacking fault density and linear surface defect density in the upper surface of the silicon carbide epitaxial layer formed on the (000-1)C face are significantly smaller than the stacking fault density and linear surface defect density in the upper surface of the silicon carbide epitaxial layer formed on the (0001)Si face. In particular, the stacking fault density was 1.2 cm in Examples 1 to 6. -2 It can be seen that the linear defect density is suppressed to less than 0.16 cm 2 in Examples 1, 4, and 6, and that the basal plane dislocations on the first surface of the silicon carbide substrate are effectively suppressed from propagating to the silicon carbide epitaxial layer and becoming stacking faults. -2 In Examples 1, 3, 4, and 6, the stacking fault density was suppressed to 0.24 cm -2 According to the inventor's study, by performing the CMP described in Patent No. 6295969 and the polishing method including oxidation and etching, and by keeping the basal plane dislocation density of the substrate below 500 cm -2 By using silicon carbide substrates with a linear defect density of 0.1 cm -2It was also found that it was possible to reduce the basal plane dislocation density of the substrate to less than 500 cm by performing the polishing method described in Japanese Patent No. 6295969, which includes CMP and oxidation and etching. -2 By using silicon carbide substrates with a stacking fault density of 0.1 cm -2 It was found that it was possible to suppress the defects to less than 3000 cm. From FIG. 6, it can be seen that this defect suppression effect is roughly constant regardless of the basal plane dislocation density of the first surface of the silicon carbide substrate. Specifically, at least when the basal plane dislocation density of the first surface of the silicon carbide substrate is 3000 cm -2 In the following range, the ratio of stacking fault density to basal plane dislocation density in the first surface of the silicon carbide substrate is less than 0.05%.

[0063] In addition, a comparison between Examples 1 to 6 and Reference Example 1 shows that by setting the C / Si ratio in the source gas to a range of 1 to 1.6, the linear surface defect density can be reduced to 1.0 cm -2 It can be seen that the linear surface defect density can be suppressed to less than 1.6. Conversely, it can be seen that when the C / Si ratio in the source gas is greater than 1.6, the linear surface defect density on the upper surface of the formed silicon carbide epitaxial layer becomes significantly large. The linear surface defect density of the sample of Reference Example 1 exceeds 12, and is therefore not shown in FIG. 3.

[0064] From Figure 5, it can be seen that the basal plane dislocation density of the first surface of the silicon carbide substrate is 3000 cm -2 In the following range, the ratio of the linear surface defect density to the basal plane dislocation density in the first surface of the silicon carbide substrate is less than 0.04%.

[0065] In other words, these results show that by forming a silicon carbide epitaxial layer on the (000-1)C plane and setting the C / Si in the source gas to be 1 or more and 1.6 or less, the effects of basal plane dislocations in the silicon carbide substrate can be effectively suppressed and linear surface defects and stacking faults on the upper surface of the silicon carbide epitaxial layer can be reduced.

[0066] Furthermore, a comparison between Examples 1 to 6 and Reference Example 2 shows that in order to reduce linear surface defects and stacking faults on the upper surface of the silicon carbide epitaxial layer, it is important to smooth the first surface of the silicon carbide substrate by CMP or to remove a process-affected layer by mechanical polishing or the like using CMP.

[0067] In addition, Japanese Patent No. 4539140 discloses that by using the (000-1)C plane of a silicon carbide substrate for growing a silicon carbide epitaxial layer, a silicon carbide semiconductor layer can be epitaxially grown on a silicon carbide substrate with a low off-angle of less than 1°, and that by using a substrate with a low off-angle, the occurrence of step bunching can be reduced. However, according to this patent document, the surface defect density of the obtained silicon carbide epitaxial layer is 100 cm -2 which is considerably larger than the linear surface defect density and stacking fault density in the samples of Examples 1 to 6 and Reference Examples 1 to 3 described above.

[0068] Also, for example, the non-patent document "Homoepitaxial growth on 4H-SiC {0001} near surface ("Materials" (J. Soc. Mat. Sci., Japan), Vol. 53, No. 12, pp. 1323-1327, December 2004)" describes surface defects in a homoepitaxially grown film on a near (000-1)C surface. This non-patent document reports that the surface defect density was reduced by forming a thermal oxide film before epitaxial growth, but does not provide any specific numerical values ​​for the density. The surface defect density can be roughly estimated from Fig. 4 "Surface observation image of homoepitaxially grown film on near (000-1)C surface" to be 100 cm -2 Degree (6mm 2 (6 surface defects in total).

[0069] From these facts, it can be seen that in a silicon carbide epitaxial substrate produced by the manufacturing method for silicon carbide epitaxial substrate 10 of the present embodiment, the linear surface defect density and stacking fault density on the upper surface of the silicon carbide epitaxial layer are significantly smaller than those in the conventional case, and it is possible to realize a silicon carbide epitaxial substrate having a high-quality silicon carbide epitaxial layer. [Industrial Applicability]

[0070] The silicon carbide epitaxial substrate of the present disclosure is a high-quality silicon carbide epitaxial substrate that can be used for a variety of applications, and is particularly suitable for use in the manufacture of semiconductor devices such as power devices. [Explanation of symbols]

[0071] 10 Silicon carbide epitaxial substrate 20 Silicon carbide substrate 20a Page 1 20b 2nd side 20n normal 30 Silicon carbide epitaxial layer 30a top surface

Claims

1. a silicon carbide substrate having a first surface; and a silicon carbide epitaxial layer located on the first surface; the first surface is a (000-1) C surface, The silicon carbide epitaxial layer has an upper surface with a linear surface defect density of 1.0 cm －２ is less than a ratio of the linear surface defect density to the basal plane dislocation density in the first surface of the silicon carbide substrate is less than 0.04%; The silicon carbide epitaxial substrate has a diameter of 100 mm or more.

2. The polytype of the silicon carbide substrate is 4H; 2. The silicon carbide epitaxial substrate of claim 1, wherein the density of the linear surface defects grown on the first surface is less than 1.0 cm −2 by introducing a source gas having a carbon to silicon ratio, C / Si, set in the range of 1.25 to 1.

4.

3. The linear surface defect density is 0.5 cm －２ 2. The silicon carbide epitaxial substrate of claim 1 , wherein the thickness of the silicon carbide epitaxial substrate is less than 100 nm.

4. The linear surface defect density is 0.35 cm －２ 2. The silicon carbide epitaxial substrate of claim 1 , wherein the thickness of the silicon carbide epitaxial substrate is less than 100 nm.

5. The first surface of the silicon carbide substrate has a basal plane dislocation density of 3000 cm －２ 5. The silicon carbide epitaxial substrate of claim 1 , wherein the thickness of the silicon carbide epitaxial substrate is less than 100 nm.

6. a basal plane dislocation density of 2000 cm －２ 5. The silicon carbide epitaxial substrate of claim 1 , wherein the thickness of the silicon carbide epitaxial substrate is less than 100 nm.

7. The silicon carbide epitaxial substrate according to claim 1 , wherein the first surface has an off-angle of 4° or less.

8. The silicon carbide epitaxial substrate according to claim 1 , wherein the first surface has a surface roughness Ra of 1 nm or less.

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