Semiconductor Processing Equipment

Abstract

The present disclosure discloses a semiconductor processing apparatus configured to perform processing on wafers. The disclosed semiconductor processing apparatus includes a vacuum interlock chamber and a plurality of apparatus bodies, each of which includes a transport platform, at least two reaction chambers arranged along the circumferential direction of the transport platform, and a temporary storage channel, with two adjacent apparatus bodies communicating with each other via the temporary storage channel, configured to temporarily store wafers. One of the plurality of apparatus bodies is connected to the vacuum interlock chamber. The transport platform is configured to transport wafers between the vacuum interlock chamber and the reaction chambers, between the temporary storage channel and the vacuum interlock chamber, and between the temporary storage channel and the reaction chambers. The above solution solves the problem of low productivity in semiconductor processing apparatuses.

Description

[Technical field]

[0001] The present disclosure relates generally to the field of semiconductor manufacturing, and more particularly, to semiconductor processing equipment. [Background technology]

[0002] Atomic layer deposition (ALD) process and chemical vapor deposition (CVD) process are widely used in semiconductor processing field. However, when the semiconductor processing equipment used in ALD process and CVD process processes the wafer on the difficult structure of holes and grooves, or performs the same processing with a long processing time, for example, when it is necessary to deposit a thick film (thickness larger than 100 Å), the processing time is relatively long and the productivity is relatively low. Summary of the Invention [Problem to be solved by the invention]

[0003] The present disclosure discloses a semiconductor processing apparatus capable of solving the problem of low productivity of the semiconductor processing apparatus. [Means for solving the problem]

[0004] To solve the above problems, the present disclosure uses the following technical solutions:

[0005] An embodiment of the present disclosure discloses a semiconductor processing apparatus configured to perform processing on a wafer. The semiconductor processing apparatus includes: a vacuum interlock chamber; and a plurality of apparatus bodies, each of which includes a carrier table, and at least two reaction chambers are arranged along a circumferential direction of the carrier table. The semiconductor processing apparatus further includes: a temporary storage channel is provided, any two adjacent ones of the apparatus bodies are communicated with each other via the temporary storage channel, and the temporary storage channel is configured to temporarily store the wafer; One of the multiple apparatus bodies is connected to the vacuum interlock chamber, and the transport table transports the wafer between the vacuum interlock chamber and the reaction chamber, between the temporary storage channel and the vacuum interlock chamber, and between the temporary storage channel and the reaction chamber.

[0006] The technical solutions adopted in the present disclosure can achieve the following beneficial effects:

[0007] In the semiconductor processing apparatus disclosed in the embodiment of the present disclosure, multiple apparatus bodies can be stacked and combined by adjusting the layout of the semiconductor processing apparatus. That is, two adjacent apparatus bodies can be communicated with each other using a temporary storage channel. Each apparatus body can include at least two reaction chambers. Compared with the existing apparatus in which the processing modules can only be arranged around a single carrier, the semiconductor processing apparatus having such a layout can effectively increase the number of reaction chambers, which can improve the productivity of the semiconductor processing apparatus and improve the product competitiveness of the semiconductor processing apparatus. [Brief description of the drawings]

[0008] In order to more clearly describe the embodiments of the present disclosure or the technical solutions of the background art, the accompanying drawings that need to be used in the embodiments of the background art are briefly introduced below. It is obvious that a person skilled in the art can obtain other accompanying drawings according to these accompanying drawings without creative efforts.

[0009] [Figure 1] 1 is a schematic diagram of a semiconductor processing apparatus according to an embodiment of the present disclosure. [Diagram 2] 2 is a schematic diagram of a semiconductor processing apparatus according to some other embodiments of the present disclosure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] In order to make the objectives, technical solutions and advantages of the present disclosure clearer, the technical solutions of the present disclosure are described below clearly and completely with reference to certain embodiments of the present disclosure and corresponding drawings. It is clear that the described embodiments are only a part of the embodiments of the present disclosure, and are not all of the embodiments. Based on the embodiments of the present disclosure, all other embodiments obtained by those skilled in the art without creative efforts shall be within the scope of the present disclosure.

[0011] The technical solutions disclosed in various embodiments of the present disclosure are described in detail below with reference to the accompanying drawings.

[0012] 1 and 2, an embodiment of the present disclosure discloses a semiconductor processing apparatus. The semiconductor processing apparatus can be configured to process wafers. The disclosed semiconductor processing apparatus includes a vacuum interlock chamber 100, a plurality of apparatus bodies 200, and a temporary storage channel 300.

[0013] The vacuum interlock chamber (load lock chamber) 100 can realize the transition between the vacuum state and the atmospheric state. When the vacuum interlock chamber 100 is converted to the vacuum state, the wafer can be loaded / transferred to the semiconductor processing equipment in the vacuum state. That is, the vacuum interlock chamber 100 can be used as a transition chamber to realize the temporary storage and transportation of the wafer, which facilitates the loading and unloading operations by the semiconductor processing equipment.

[0014] The temporary storage channel 300 may also be configured to temporarily store wafers. The temporary storage channel 300 may be disposed between any two adjacent apparatus bodies 200. The temporary storage channel 300 may communicate with two adjacent apparatus bodies 200 to make the vacuum degree of the temporary storage channel 300 match the vacuum degree inside the apparatus body 200. The wafers temporarily stored in the temporary storage channel 300 may be unprocessed wafers or processed wafers. That is, the vacuum interlock chamber 100 and the temporary storage channel 300 may be transition modules for loading and unloading the semiconductor processing equipment, so that the semiconductor processing equipment can easily perform loading and unloading operations.

[0015] The apparatus body 200 may include a carrier 210. At least two reaction chambers 220 may be arranged in the circumferential direction of the carrier 210. Specifically, the carrier 210 may be configured to transport a wafer and complete the loading and unloading of the semiconductor processing apparatus. Specifically, the carrier 210 may have various methods for realizing the transportation of the workpiece to be processed. For example, the carrier 210 may be provided with a transportation device such as a manipulator. For example, each of the carriers 210 (plural) shown in FIG. 1 includes a manipulator 230. The manipulator 230 may realize the transportation of the workpiece to be processed in a gripping manner. In addition, as another example, the carrier 210 may realize the transportation of the workpiece to be processed using an adsorption method (e.g., vacuum adsorption, magnetic adsorption, etc.). In a specific processing process, the wafer may be processed in the reaction chamber 220.

[0016] The multiple apparatus bodies 200 may include a first apparatus body and a second apparatus body. The first apparatus body may include a first carrier. The first carrier may be connected to the vacuum interlock chamber 100. At least two first reaction chambers may be arranged in a circumferential direction of the first carrier. The second apparatus body may include a second carrier. The second carrier may be in communication with the first carrier via a temporary storage channel 300. At least two second reaction chambers may be arranged in a circumferential direction of the second carrier. The first carrier connected to the vacuum interlock chamber 100 may transport wafers between the vacuum interlock chamber 100 and the reaction chamber 220, between the temporary storage channel 300 and the vacuum interlock chamber 100, and between the temporary storage channel 300 and the reaction chamber 220. The second carrier not connected to the vacuum interlock chamber 100 may transport wafers between the temporary storage channel 300 and the reaction chamber 220. In this manner, a load cycle and an unload cycle of the semiconductor processing apparatus may be performed.

[0017] The first reaction chamber and the second reaction chamber may be the core components for processing the wafer. The wafer may be processed in either the first reaction chamber or the second reaction chamber. It should be noted that the structure and processing principle of the first reaction chamber and the second reaction chamber are known in the art and will not be repeated here for the sake of brevity of the specification.

[0018] Generally, two or four first reaction chambers may form a first processing module, i.e., one first processing module may generally include an even number of first reaction chambers. Of course, two or four second reaction chambers may form a second processing module, i.e., one second processing module may generally include an even number of second reaction chambers.

[0019] In the embodiment of the present disclosure, the first reaction chamber and the second reaction chamber may be the same wafer processing apparatus, both of which are the reaction chamber 220 described above. That is, the first reaction chamber and the second reaction chamber may have the same structure and processing principle, and perform the same processing on the workpiece to be processed. In addition, in combination with the above, the first processing module and the second processing module may be the same processing module. In the process of designing the semiconductor processing apparatus, it is not necessary to design multiple different processing modules, but only to repeatedly combine the processing modules. In this way, a modular design of the semiconductor processing apparatus can be realized, which makes the design work of the designer easier, simplifies the design burden, and improves the design efficiency of the semiconductor processing apparatus. Of course, the first reaction chamber and the second reaction chamber may be different wafer processing apparatus, which is not limited by the embodiment of the present disclosure. It should be noted that the first carrier and the second carrier may both be the carrier 210 described above.

[0020] Similarly, it can be seen that the first device body and the second device body can be the same device body, and both of them can be the device body 200 described above. In the process of designing a semiconductor processing device, there is no need to design multiple different device bodies, and the device bodies can be repeatedly combined and communicated with each other through a temporary storage channel. In this way, the modular design degree of the semiconductor processing device can be further improved, which can further facilitate the design work of the designer, simplify the design burden, and improve the design efficiency of the semiconductor processing device. Of course, according to the actual working conditions and on-site constraints, the first device body and the second device body can be designed as different device bodies to meet actual needs, which is not limited in the embodiments of the present disclosure.

[0021] Specifically, one of the multiple apparatus bodies 200 can be connected to the vacuum interlock chamber 100. That is, a first apparatus body can be connected to the vacuum interlock chamber 100. A wafer outside the semiconductor processing apparatus can be entered into the apparatus body 200 through the vacuum interlock chamber 100 for processing, or a wafer processed in the apparatus body 200 can be transported to the outside of the semiconductor processing apparatus through the vacuum interlock chamber 100, thus realizing a load cycle and an unload cycle of the semiconductor processing apparatus.

[0022] Any two adjacent apparatus bodies 200 may be communicated with each other through the temporary storage channel 300. The transport platform 210 may be configured to transport a wafer between the vacuum interlock chamber 100 and the reaction chamber 220, between the temporary storage channel 300 and the vacuum interlock chamber 100, and between the temporary storage channel 300 and the reaction chamber 220. Thus, it is possible to transport a wafer to the reaction chamber 220 for processing, or to transport a processed wafer to the outside of the reaction chamber 220. That is, the temporary storage channel 300 may be disposed between the first apparatus body and the second apparatus body. The first transport platform may be configured to transport a wafer between the vacuum interlock chamber 100 and the first reaction chamber, and between the temporary storage channel 300 and the vacuum interlock chamber 100. The second transport platform may be configured to transport a wafer between the temporary storage channel 300 and the second reaction chamber.

[0023] In a specific processing process of a wafer by the semiconductor processing equipment, the first transfer stage transfers an unprocessed wafer placed in the vacuum interlock chamber 100 to the first reaction chamber, and the first reaction chamber completes the processing of the wafer. At the same time, the first transfer stage can also transfer the processed wafer in the first reaction chamber to the vacuum interlock chamber 100 to complete the processing flow of one wafer.

[0024] Alternatively, the first transport stage may be configured to transport an unprocessed wafer in the vacuum interlock chamber 100 to the temporary storage channel 300. The unprocessed wafer in the temporary storage channel 300 may then be transported via the second transport stage to a second reaction chamber for processing the wafer in the second reaction chamber. The second transport stage may then transport a processed wafer in the second reaction chamber to the temporary storage channel 300. The first transport stage may then transport the processed wafer in the temporary storage channel 300 to the vacuum interlock chamber 100, thereby completing the processing flow of one wafer.

[0025] In the embodiment of the present disclosure, the number of the first device body may be multiple, or the number of the second device body may also be multiple. Of course, the number of the first device body and the number of the second device body may be multiple at the same time, which is not limited by the embodiment of the present disclosure. A plurality of first device bodies may be stacked and combined, or a plurality of second device bodies may be stacked and combined. Of course, a plurality of first device bodies and a plurality of second device bodies may be mixed and stacked. In this way, the semiconductor processing apparatus may include a large number of first reaction chambers or second reaction chambers, which allows the semiconductor processing apparatus to process multiple wafers simultaneously, which further increases the productivity of the semiconductor processing apparatus.

[0026] In the semiconductor processing apparatus disclosed in the embodiment of the present disclosure, a plurality of apparatus bodies 200 can be stacked and combined by adjusting the layout of the semiconductor processing apparatus. That is, two adjacent apparatus bodies can be communicated with each other using a temporary storage channel. Each apparatus body can include at least two reaction chambers. Compared with the existing apparatus in which the processing modules can only be arranged around a single carrier, the semiconductor processing apparatus having such a layout can effectively increase the number of reaction chambers, improve the productivity of the semiconductor processing apparatus, and improve the product competitiveness of the semiconductor processing apparatus.

[0027] Typically, other processing steps may need to be performed on the wafer before it is processed by the semiconductor processing equipment. After the other processing steps are completed, it may be impossible or difficult to directly place the wafer into the vacuum interlock chamber 100. Based on this, in an optional embodiment, the semiconductor processing equipment may further include a semiconductor equipment front-end module 400 and a wafer load port 500. The semiconductor equipment front-end module 400 may include a conventional semiconductor equipment front-end module (EFEM) currently available on the market. The semiconductor equipment front-end module 400 may be configured to efficiently transport and position the wafer before the semiconductor processing equipment processes the wafer. The wafer load port 500 may also include a conventional load port device currently available on the market. The specific structures and principles of the semiconductor equipment front-end module 400 and the wafer load port 500 are known in the art and will not be repeated here for the sake of brevity.

[0028] Specifically, the semiconductor device front-end module 400 may include a wafer transport manipulator. The wafer transport manipulator may be configured to transport a wafer between the vacuum interlock chamber 100 and the wafer load port 500. After the wafer is processed by other processing processes, the wafer may be placed in the wafer load port 500. The wafer transport manipulator may then be configured to accurately transport the wafer in the wafer load port 500 to the vacuum interlock chamber 100. The combined solution of the semiconductor device front-end module 400 and the wafer load port 500 may realize automatic loading and unloading of wafers, and may ensure the accuracy of wafer loading and unloading and the speed of wafer loading and unloading to ensure reliable and stable operation of the semiconductor processing equipment.

[0029] It may be necessary to complete the processing of the wafer in a vacuum environment. In order to allow the semiconductor processing equipment to have a good vacuum environment, in an optional embodiment, a temporary storage table 110 may be placed in the vacuum interlock chamber 100. The temporary storage table 110 may be configured to temporarily store the wafer. One side of the vacuum interlock chamber 100 may be connected to the equipment body 200. A first gate valve may be placed at the connection between the vacuum interlock chamber 100 and the equipment body 200. The other side of the vacuum interlock chamber 100 may be connected to an external device (e.g., the semiconductor device front-end module 400). A second gate valve may be placed at the connection between the vacuum interlock chamber and the external device. It should be noted that the "external device" described herein may refer to an external device related to the equipment body 200. That is, the external device described herein may be a component of the semiconductor processing equipment.

[0030] During a specific loading process of a wafer, the first gate valve may be opened first. Then, the wafer transport manipulator may transport the wafer in the wafer load port 500 to the temporary storage table 110. Then, the first gate valve may be closed. A vacuum pumping operation may be performed in the vacuum interlock chamber 100. The second gate valve may be opened when the vacuum interlock chamber 100 is in a vacuum environment. Then, the transport platform 210 may transport the unprocessed wafer in the vacuum interlock chamber 100 to the reaction chamber 220 or the temporary storage channel 300 to realize the wafer loading operation. During a specific unloading process of a wafer, a vacuum pumping operation may be performed in the vacuum interlock chamber 100 first. The second gate valve may be opened when the vacuum interlock chamber 100 is in a vacuum environment. Then, the transport platform 210 may transport the processed wafer in the reaction chamber 220 or the temporary storage channel 300 to the temporary storage table 110. Then, the second gate valve may be closed and the first gate valve may be opened. In this manner, the wafer transport manipulator can transport the wafer on the temporary storage table 110 to the wafer load port 500 and unload the wafer.

[0031] In the load operation and the unload operation, the first gate valve and the second gate valve can isolate the apparatus body 200 from an external device to prevent the vacuum environment in the apparatus body 200 from being affected. In this way, the semiconductor processing apparatus can provide a better vacuum environment for wafer processing, and further improve the reliability of the semiconductor processing apparatus.

[0032] Since any two adjacent apparatus bodies 200 can be connected to each other via the temporary storage channel 300 (i.e., both sides of the temporary storage channel 300 can be connected to the first apparatus body and the second apparatus body, respectively), and since both the first apparatus body and the second apparatus body are in a vacuum environment, it is not necessary to place gate valves on both sides of the temporary storage channel 300. In this way, the temporary storage channel 300 can be a communicating structure, which can shorten the time required to open and close the gate valve, thereby shortening the time required to load and unload the wafer, which can have a positive effect on improving the productivity of the semiconductor processing apparatus.

[0033] Since the semiconductor processing equipment may process a large number of wafers simultaneously, it may be necessary to quickly perform the loading and unloading of the wafer, or to realize the simultaneous loading and unloading of multiple wafers. Meanwhile, the loading and unloading of the wafers may be performed simultaneously on the temporary storage table 110. Based on this, in an optional embodiment, the number of the temporary storage tables 110 may be multiple. If multiple temporary storage tables 110 are used, the speed of the loading and unloading of the wafers will definitely be faster, and the loading and unloading of multiple wafers may be realized simultaneously to increase the loading and unloading speed of the semiconductor processing equipment. Meanwhile, a part of the temporary storage table 110 may be used for loading, and the remaining part may be used for unloading, thereby preventing the problem of interference or unavailability of the temporary storage table 110 for placing the wafer when the loading and unloading of the wafers are performed simultaneously on the temporary storage table 110. In this way, the semiconductor processing equipment may perform the loading and unloading stably and orderly.

[0034] In an optional embodiment, the device body 200 may further include a transport mechanism 230. The transport mechanism 230 may be disposed on the carrier 210. The transport mechanism 230 may be configured to transport a wafer. Specifically, the transport mechanism 230 may be a manipulator. In order to further improve the loading and unloading speed of the semiconductor processing device, in an optional embodiment, the manipulator may include at least two wafer grabbing devices. The at least two wafer grabbing devices may be configured to transport at least two wafers simultaneously, thereby certainly achieving the above-mentioned effects.

[0035] In addition, the temporary storage channel 300 may include multiple wafer placement tables 310. The wafer placement tables 310 may be configured to temporarily store wafers. The speed of wafer loading and unloading operations is definitely increased by the multiple wafer placement tables 310, and simultaneous loading and unloading of multiple wafers can be realized, so that the loading and unloading speed of the semiconductor processing equipment is increased. Meanwhile, some of the multiple wafer placement tables 310 may be configured to load wafers, and the remaining ones may be configured to unload wafers, so as to prevent interference when simultaneously loading and unloading wafers on the wafer placement tables 310, or the problem of no available wafer placement tables 310 to place wafers on. In this way, the semiconductor processing equipment may perform loading and unloading stably and orderly.

[0036] It should be noted that increasing the loading and unloading speed of a semiconductor processing device can have a positive impact on increasing the productivity of the semiconductor processing device. Thus, increasing the loading and unloading speed of a semiconductor processing device can also increase the productivity of the semiconductor processing device.

[0037] Optionally, the carrier 210 may be a polygonal carrier. The transport mechanism 230 may be disposed on the polygonal carrier. At least two reaction chambers 220 may be disposed in a circumferential direction of the polygonal carrier. In this manner, the reaction chambers 220 may be regularly disposed on the polygonal carrier. The reaction chambers 220 may be regularly disposed around the carrier 210, which facilitates design by a designer.

[0038] Specifically, the shape of the carrier 210 may be a square, a pentagon, or a hexagon. According to the optimization calculation and the constraints of the site layout space, the carrier 210 of these shapes can provide a compact layout for the semiconductor processing apparatus. In this way, the structure of the semiconductor processing apparatus can be made compact, which reduces the volume of the semiconductor processing apparatus, which can facilitate the layout and setup at the installation site, and can improve the utilization efficiency of the site layout space. Furthermore, the shape of the carrier 210 may be a regular square, a regular pentagon, or a regular hexagon. In this way, the apparatus body 200 can be made relatively symmetrical, and the structure of the semiconductor processing apparatus can be made compact.

[0039] To further improve the regular arrangement of the reaction chambers 220, in an optional embodiment, at least two reaction chambers 220 are arranged on at least one side of the transport platform 210, so that the reaction chambers 220 can be arranged more regularly.

[0040] In an embodiment of the present disclosure, the multiple apparatus bodies 200 may include a first apparatus body and a second apparatus body. The first apparatus body may be connected to the vacuum interlock chamber 100. The shape of the carrier 210 of the first apparatus body may be a regular square, and the shape of the carrier 210 of the second apparatus body may be a regular pentagon. This layout allows the semiconductor processing apparatus to be arranged more compactly. In this way, the structure of the semiconductor processing apparatus can be made more compact, and the volume of the semiconductor processing apparatus can be further reduced, which makes it easier to layout and set up at the installation site, and further improves the utilization efficiency of the on-site layout space.

[0041] Furthermore, with respect to the above-mentioned first apparatus body, when the shape of the transport platform 210 is a polygon having an even number of sides, such as a rectangle or a hexagon, the vacuum interlock chamber 100 and the temporary storage channel 300 can be connected to the transport platform 210 at positions corresponding to two opposing sides of the transport platform 210, respectively. In this manner, the vacuum interlock chamber 100 and the temporary storage channel 300 can be disposed on opposing sides of the first apparatus body. Therefore, the reaction chambers 220 can be disposed symmetrically. It can be easily realized that the transport paths of the wafers to the symmetrically disposed reaction chambers are the same.

[0042] As described above, the wafer may be processed in the reaction chamber 220. Specifically, the reaction chamber 220 may be an atomic layer deposition (ALD) process chamber or a chemical vapor deposition (CVD) process chamber. The ALD process may have the advantages of high film purity and better coverage since it has the advantages of low temperature deposition. The CVD process may have the advantages of a simple process, improved environmental performance, no pollution, less consumables, uniform and dense film formation, etc. The type of process for processing the wafer is not limited by the embodiments of the present disclosure.

[0043] The above-mentioned embodiments of the present disclosure mainly describe the differences between various embodiments, and different optimization features of various embodiments can be combined to form better embodiments as long as they are not contradictory, which will not be repeated here for the sake of brevity of the specification.

[0044] The above description is merely an embodiment of the present disclosure and is not used to limit the present disclosure. Those skilled in the art may make various modifications and changes to the present disclosure. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present disclosure shall be included in the scope of the claims of this application.

Claims

1. 1. A semiconductor processing apparatus configured to process a wafer, the semiconductor processing apparatus comprising: a vacuum interlock chamber; and a plurality of apparatus bodies, each of which includes a transport platform, and at least two reaction chambers are arranged along a circumferential direction of the transport platform, and the semiconductor processing apparatus further includes: a temporary storage channel is provided, and two adjacent apparatus bodies are communicated with each other via the temporary storage channel, and the temporary storage channel is configured to temporarily store the wafer; One of the plurality of apparatus bodies is connected to the vacuum interlock chamber, and the transport stage transports the wafer between the vacuum interlock chamber and the reaction chamber, between the temporary storage channel and the vacuum interlock chamber, and between the temporary storage channel and the reaction chamber; a plurality of temporary storage tables are arranged in the vacuum interlock chamber, the plurality of temporary storage tables are configured to temporarily store the wafer, a portion of the plurality of temporary storage tables is used for loading, and the remaining portions of the plurality of temporary storage tables other than the portion of the temporary storage tables are used for unloading; the temporary storage channel includes a plurality of wafer loading tables, the plurality of wafer loading tables being configured to temporarily store a plurality of wafers, some of the plurality of wafer loading tables being configured to load a plurality of wafers, and the plurality of wafer loading tables other than the some of the wafer loading tables being configured to unload a plurality of wafers; A semiconductor processing apparatus, wherein the plurality of apparatus bodies include a first apparatus body and a second apparatus body, the first apparatus body is connected to the vacuum interlock chamber, the transport table of the first apparatus body has a shape of a regular square, and the transport table of the second apparatus body has a shape of a regular pentagon.

2. 2. The semiconductor processing apparatus of claim 1, wherein one side of the vacuum interlock chamber is connected to the apparatus main body, a first gate valve is disposed at a connection between the vacuum interlock chamber and the apparatus main body, the other side of the vacuum interlock chamber is connected to an external device, and a second gate valve is disposed at a connection between the vacuum interlock chamber and the external device.

3. The semiconductor processing apparatus according to claim 1 , wherein at least two of the reaction chambers are disposed on at least one side of the transport platform.

4. The semiconductor processing apparatus of claim 1, wherein the vacuum interlock chamber and the temporary storage channel are each connected to the transport table at positions corresponding to two opposing sides of the transport table.

5. The semiconductor processing apparatus according to claim 1 , wherein the apparatus body further includes a transport mechanism, the transport mechanism being disposed on the transfer table.

6. The semiconductor processing system of claim 5 , wherein said transport mechanism is a manipulator, said manipulator including at least two wafer grippers.

7. The semiconductor processing apparatus of claim 1 , wherein the reaction chamber comprises an atomic layer deposition (ALD) process chamber or a chemical vapor deposition (CVD) process chamber.

Images