Blanking aperture array system, charged particle beam writing apparatus, and method for inspecting blanking aperture array system

Abstract

In the present invention, a substrate comprises a shift resistor which includes a plurality of flip-flops. A control device: supplies the shift resistor with control data such that the value held by the flip-flops at a first voltage in a period of a beam irradiation operation is one; supplies the shift resistor with control data such that the value held by the flip-flops at a second voltage lower than the first voltage outside the period of the beam irradiation operation is one; and determines whether the flip-flops are operating normally by determining whether the control data supplied to the shift resistor matches control data output from one flip-flop, or by determining whether the state of blanking by a first electrode that has been connected to a first flip-flop in accordance with the control data supplied to the shift resistor matches the state of blanking by the first electrode that has been connected to the first flip-flop in accordance with the control data supplied to the shift resistor.

Description

[Technical field]

[0001] SUMMARY OF THE DISCLOSURE Embodiments generally relate to blanking aperture array systems, charged particle beam writing apparatus, and methods for inspecting blanking aperture array systems. [Background technology]

[0002] Masks are used in the manufacture of semiconductor devices. To form fine elements, the mask pattern is also required to be fine. To form a mask having a fine pattern, the pattern is written on the mask material using an electron beam. To efficiently form the mask, a writing method using multiple electron beams (multi-beam writing method) may be used.

[0003] In the multi-beam writing method, an electron beam is passed through a mask (shaping aperture array plate) with multiple apertures to form multiple beams. The multiple beams are directed to a blanking aperture array mechanism with multiple apertures. Each beam is individually deflected by the blanking aperture array mechanism, and the deflected beams do not reach the mask because they hit a shield.

[0004] The blanking aperture array arrangement includes a mechanism around each aperture for modifying the beam passing through that aperture, the mechanism including electrodes and elements of an electronic circuit for applying voltages to the electrodes. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Japanese Patent Publication No. 2008-235571 Summary of the Invention [Problem to be solved by the invention]

[0006] Irradiation of the electron beam for drawing may damage elements of the electronic circuit in the blanking aperture array mechanism. Accumulation of damage may deteriorate the characteristics of the elements. If the deterioration of the characteristics exceeds a certain critical point, the elements of the electronic circuit may fail, in which case the blanking aperture array mechanism cannot operate correctly. To avoid this, the blanking aperture array mechanism may be diagnosed before drawing. If a failure is found at the time of diagnosis, it is possible to deal with it before drawing. Such a failure diagnosis can only identify elements that are determined to be failed at the time of diagnosis. For this reason, it is not possible to identify elements that will fail during the next drawing even if they have deteriorated and are not failed at the time of diagnosis.

[0007] On the other hand, drawing takes time. During drawing, parts of the drawing device cannot be replaced. Therefore, if an element that is diagnosed as normal but may fail in the near future breaks down during drawing, it may be necessary to replace the blanking aperture array mechanism and redo the drawing. This can seriously disrupt mask production plans.

[0008] Based on this current situation, there is a need for a blanking aperture array system, a charged particle beam device, and an inspection method for a blanking aperture array system that can identify elements that may fail in the near future even if they are not found to be faulty in a prior diagnosis. [Means for solving the problem]

[0009] A blanking aperture array system for use in a multi-charged particle beam irradiation device according to one embodiment includes a blanking aperture array substrate and a controller.

[0010] The blanking aperture array substrate includes a shift register including a plurality of flip-flops connected in series and transferring control data used for beam irradiation, a first electrode connected to each of the plurality of flip-flops and formed on the substrate, and a second electrode sandwiching one of a plurality of apertures that allow the beam to pass between the first electrode and the second electrode and connected to ground. The control device supplies to the shift register the control data during beam irradiation operation, such that the value held by the flip-flop is 1 at a first voltage, which is a voltage used during beam irradiation operation, and supplies to the shift register the control data during non-beam irradiation operation, such that the value held by the flip-flop is 1 at a second voltage lower than the first voltage, and determines whether the control data supplied to the shift register is transferred through the shift register and matches the control data output from one of the flip-flops of the shift register, or determines whether the blanking state when blanking is performed by the first electrode connected to the first flip-flop of the shift register in accordance with the control data supplied to the shift register matches the blanking state performed by the first electrode connected to the first flip-flop in accordance with the control data supplied to the shift register, thereby determining whether the plurality of flip-flops are operating normally. Effect of the Invention

[0011] Provided are a blanking aperture array system, a charged particle beam device, and a method for inspecting the blanking aperture array system that enable failures to be addressed before writing and suppress unexpected failure of the blanking aperture array mechanism during writing. [Brief description of the drawings]

[0012] [Figure 1] FIG. 1 shows elements of a rendering device according to a first embodiment. [Diagram 2] FIG. 2 shows a hardware configuration of the control device of the first embodiment. [Diagram 3]FIG. 3 shows the structure of the shaping aperture array plate of the first embodiment along the xy plane. [Figure 4] FIG. 4 shows the structure of the blanking aperture array mechanism of the first embodiment along the xz plane. [Diagram 5] FIG. 5 shows the structure of the blanking aperture array mechanism of the first embodiment along the xy plane. [Figure 6] FIG. 6 shows the circuitry and related elements of the blanking aperture array mechanism of the first embodiment. [Figure 7] FIG. 7 shows some elements and connections of the shift register of the first embodiment and related elements. [Figure 8] FIG. 8 shows a shift register and associated elements of the first embodiment. [Figure 9] FIG. 9 shows an example of elements and connections of a D-type flip-flop of the first embodiment. [Figure 10] FIG. 10 shows an example of elements and connections of a NAND gate in the first embodiment. [Figure 11] FIG. 11 shows an example of elements and connections of the inverter of the first embodiment. [Figure 12] FIG. 12 shows functional blocks of the control device of the first embodiment. [Figure 13] FIG. 13 shows a flow of operations performed by the rendering device of the first embodiment. [Figure 14] FIG. 14 shows the characteristics of the transistor TN of the first embodiment. [Figure 15] FIG. 15 shows an example of the characteristics and applied voltages of the transistor TN of the first embodiment. [Figure 16] FIG. 16 shows the relationship between the deterioration of the transistor TN of the first embodiment and the usage time. [Figure 17] FIG. 17 shows a flow of a writing and inspection method according to a modified example of the first embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0013] Hereinafter, embodiments will be described with reference to the drawings. In the following description, components having substantially the same functions and configurations are given the same reference numerals, and repeated explanations may be omitted. In order to distinguish a plurality of components having substantially the same functions and configurations from one another, additional numbers or letters may be added to the end of the reference numerals.

[0014] All descriptions of one embodiment may also apply to descriptions of another embodiment unless explicitly or obviously excluded. In addition, each functional block can be realized as either hardware or computer software, or a combination of both. It is not essential that each functional block is distinguished as in the following examples. For example, some functions may be performed by a functional block other than the illustrated functional block. Furthermore, the illustrated functional block may be divided into smaller functional subblocks.

[0015] Additionally, any steps in the method flows of the embodiments are not limited to the order illustrated and may occur in an order different from the order illustrated and / or in parallel with other steps, unless otherwise indicated.

[0016] In this specification and claims, when a first element is "connected" to another second element, it includes the first element being connected to the second element directly or via an element that is constantly or selectively conductive.

[0017] Hereinafter, the embodiment will be described using an xyz Cartesian coordinate system.

[0018] 1. First embodiment 1.1.Structure (composition) 1 shows elements (configuration) of a drawing apparatus according to a first embodiment. The drawing apparatus 1 is, for example, a multi-charged particle beam drawing apparatus. Some of the elements will be described in detail later.

[0019] The drawing apparatus 1 includes a control circuitry 2 and a drawing mechanism 3. The drawing mechanism 3 generates a charged particle beam and draws a pattern on the sample 6 by irradiating the sample 6 with the generated charged particle beam. Examples of the sample 6 include a mask coated with a resist or a reticle. The control circuitry 2 controls the operation of the drawing mechanism 3. The drawing apparatus 1 includes a blanking aperture array system, i.e., at least a part of the control circuitry 2 and at least a part of the drawing mechanism 3 constitute a blanking aperture array system.

[0020] The drawing mechanism 3 includes a vacuum chamber 31. The inside of the vacuum chamber 31 is maintained, for example, at a vacuum while drawing is performed on the sample 6 by the drawing apparatus 1. The vacuum chamber 31 is composed of a writing chamber 31a and an optical column 31b.

[0021] The writing chamber 31a has, for example, a rectangular parallelepiped shape and has a space inside. The writing chamber 31a accommodates the sample 6. The writing chamber 31a has an opening on the upper surface, and the opening is connected to the internal space of the lens barrel 31b.

[0022] The imaging apparatus 1 also includes a stage 310 in the writing chamber 31a. On the upper surface of the stage 310, a sample 6 is placed during imaging. The stage 310 can move along the x-axis and the y-axis while holding the sample 6 substantially horizontally. On the upper surface of the stage 310, a mirror 312x and a mirror 312y are provided. The mirror 312x extends along the y-axis, and the mirror 312y extends along the x-axis. The mirrors 312x and 312y are used as references for detecting the position of the stage 310.

[0023] The lens barrel 31b has a cylindrical shape extending along the z-axis and is made of, for example, stainless steel. The lower end of the lens barrel 31b is located inside the writing chamber 31a. The drawing device 1 further includes, in the lens barrel 31b, an electron gun 320, an illumination lens 330, a reduction lens 331, an objective lens 332, a shaping aperture array plate 340, a limiting aperture array plate 341, a blanking aperture array mechanism (blanking aperture array substrate) 350, and deflectors 360 and 361.

[0024] The electron gun 320 is located at the top inside the electron tube 31b. The electron gun 320 is, for example, a hot cathode type electron gun. The electron gun 320 includes elements such as a cathode, a Wehnelt electrode, and an anode. The Wehnelt electrode surrounds the cathode. When the electron gun 320 receives a voltage, it emits an electron beam EB downward along the z axis (in the -z direction). The electron beam EB spreads along the xy plane as it travels along the z axis.

[0025] The illumination lens 330 is an annular electromagnetic lens, and is located below the electron gun 320 along the z-axis. The illumination lens 330 shapes the electron beam EB, which has spread in the xy plane and reaches the illumination lens 330, so that the electron beam EB travels parallel to the z-axis.

[0026] The shaping aperture array plate 340 is located below the illumination lens 330 along the z-axis. The shaping aperture array plate 340 has a plurality of apertures, and causes a portion of the electron beam EB incident on the shaping aperture array plate 340 to pass through the plurality of apertures and branch into a plurality of electron beams EBm.

[0027] The blanking aperture array mechanism 350 is located below the shaping aperture array plate 340 along the z-axis (in the -z direction). The blanking aperture array mechanism 350 blanks the multiple electron beams EBm individually. The blanking aperture array mechanism 350 has multiple apertures, each of which is located below the opening of the shaping aperture array plate 340 along the z-axis (in the -z direction), and blankers provided around each aperture. Each blanker blanks the electron beam EBm that is incident on the aperture for which the blanker is provided.

[0028] The reduction lens 331 is an annular electromagnetic lens, and is located below (in the −z direction) along the z-axis of the blanking aperture array mechanism 350. The reduction lens 331 focuses the multiple electron beams EBm that are parallel to each other and have passed through the blanking aperture array mechanism 350, onto the center of the aperture of the limiting aperture array plate 341.

[0029] The limiting aperture array plate 341 has a plate-like shape extending along the xy plane, and has an aperture in the center of the xy plane. The aperture is located near the focal point (crossover point) of the multiple electron beams EBm that have passed through the reduction lens 331. The beam deflected by the blanker provided in the blanking aperture array mechanism 350 cannot pass through the aperture provided in the center of this limiting aperture array plate 341, and hits the limiting aperture array plate 341, resulting in blanking.

[0030] In addition, the limiting aperture array plate 341 shapes the shape of the electron beam EBm along the xy plane by making the multiple electron beams EBm pass through an aperture. The multiple shaped electron beams EBm form shots of a selected shape.

[0031] The deflector 360 is located below (in the -z direction) the limiting aperture array plate 341 along the z-axis. A shot-shaped electron beam EBm emitted from the limiting aperture array plate 341 is incident on the deflector 360. The deflector 360 includes multiple pairs of electrodes. In FIG. 1, only one pair of electrodes is shown to avoid unnecessary cluttering of the figure. The two electrodes constituting each pair are opposed to each other. Each electrode receives a voltage, and the deflector 360 deflects the incident electron beam EBm along the x-axis and / or the y-axis in response to the application of voltages to the multiple electrodes.

[0032] The objective lens 332 is an annular electromagnetic lens and surrounds the deflector 360. The objective lens 332 cooperates with the deflector 360 to focus the electron beam EBm onto a specific position on the sample 6.

[0033] The deflector 361 is located below the deflector 360 along the z-axis (in the -z direction). The electron beam EBm that has passed through the deflector 360 is incident on the deflector 361. The deflector 360 includes multiple pairs of electrodes. In FIG. 1, only one pair of electrodes is shown to avoid unnecessary cluttering of the figure. The two electrodes that make up each pair face each other. Each electrode receives a voltage, and the deflector 360 deflects the incident electron beam EBm along the x-axis and / or the y-axis in response to the application of voltages to the multiple electrodes.

[0034] The control circuit system 2 includes a control device 21, a power supply device 22, a lens driving device 23, a BAA control unit 24, an irradiation amount control unit 25, a deflector amplifier 27, and a stage driving device .

[0035] The control device 21 controls the power supply device 22, the lens driving device 23, the BAA control unit 24, the irradiation amount control unit 25, the deflector amplifier 27, and the stage driving device 28. The control device 21 receives, for example, an input from a user of the drawing apparatus 1, and controls the power supply device 22, the lens driving device 23, the BAA control unit 24, the irradiation amount control unit 25, the deflector amplifier 27, and the stage driving device 28 based on the received input.

[0036] The power supply unit 22 receives control data from the control unit 21, and applies a voltage to the electron gun 320 based on the received control data.

[0037] The lens driving device 23 receives control data from the control device 21, and controls the illumination lens 330 based on the received control data. Specifically, the lens driving device 23 controls the intensity of the illumination lens 330 with respect to the electron beam EB, i.e., the intensity at which the electron beam EB is refracted. The lens driving device 23 controls the intensity of the illumination lens 330 so as to shape the electron beam EB, which is incident on the illumination lens 330 from above the z axis of the illumination lens 330 and spreads along the xy plane as it travels, into an electron beam substantially parallel to the z axis.

[0038] The lens driving device 23 also receives control data from the control device 21, and controls the strength of the reduction lens 331 based on the received control data. The lens driving device 23 controls the strength of the reduction lens 331 so that the electron beam EBm incident on the reduction lens 331 from above the z-axis of the reduction lens 331 without being blanked by the blanker of the blanking aperture array mechanism 350 is focused onto the center of the aperture of the limiting aperture array plate 341.

[0039] The lens driving device 23 further receives control data from the control device 21, and controls the intensity of the objective lens 332 based on the received control data. The lens driving device 23 controls the intensity of the objective lens 332 so that the electron beam BM incident on the objective lens 332 from above the z-axis of the objective lens 332 is focused on the upper surface of the sample 6. The lens driving device 23 may reduce the electron beam BM.

[0040] The BAA control unit 24 receives BAA control data from the control device 21, and controls the blanking aperture array mechanism 350 based on the received control data.

[0041] The irradiation dose control unit 25 receives control data from the control device 21, and generates irradiation dose control data based on the received control data. The irradiation dose control unit 25 supplies the generated irradiation dose control data to the BAA control unit 24, and controls the irradiation dose of the electron beam BM to the sample 6 via the BAA control unit 24.

[0042] The deflector amplifier 27 receives control data from the controller 21 and generates control signals for controlling each of the deflectors 360 and 361 based on the received control data. The generated control signals are supplied to the deflectors 360 and 361, respectively. The signal for the deflector 360 specifies the potential difference between the two electrodes of each pair of the deflector 360. Similarly, the signal for the deflector 361 specifies the potential difference between the two electrodes of each pair of the deflector 361. The deflector amplifier 27 generates a signal for the deflector 360 so that the deflector 360 receives a voltage that deflects the electron beam EBm by an amount and / or a direction specified by the controller 21. Similarly, the deflector amplifier 27 generates a signal for the deflector 361 so that the deflector 360 receives a voltage that deflects the electron beam EBm by an amount and / or a direction specified by the controller 21.

[0043] The stage driving device 28 measures the positions of the mirrors 312x and 312y using means such as a laser sensor (not shown), and detects the position of the stage 310 based on the measured positions. The stage driving device 28 also receives control data from the control device 21, and drives the stage 310 based on the received control data. By driving the stage 310, the sample 6 moves to a desired position.

[0044] 2 shows the configuration of the control device 21 of the first embodiment, in particular the hardware configuration. As shown in FIG. 2, the control device 21 includes a processor 211, a ROM (read only memory) 212, a storage device 213, an input device 214, an output device 215, an interface 216, and a communication device 217.

[0045] The ROM 212 stores a program for controlling the processor in a non-volatile manner. The storage device 213 includes a volatile or non-volatile memory and / or a hard disk, and holds data. The processor 211 is, for example, a CPU (central processing unit), and performs various operations by executing a program stored in the ROM 212 and loaded into the storage device 213. The processor 211 controls the storage device 213, the input device 214, the output device 215, the interface 216, and the communication device 217 in accordance with the program. The program is configured to cause the control device 21, particularly the processor 211, to perform operations described below as operations by various functional blocks.

[0046] The input device 214 includes one or more of a keyboard, a mouse, and a touch panel, and enables a user of the drawing device 1 to input instructions and / or parameters. The output device 215 includes a display, and presents various information to the user of the drawing device 1. The interface 216 manages communication between the control device 21 and the power supply device 22, the lens driving device 23, the BAA control unit 24, the irradiation dose control unit 25, the deflector amplifier 27, and the stage driving device 28.

[0047] The communication device 217 is configured to be able to communicate with a device external to the drawing device 1. For example, the communication device 217 is connected to the device external to the drawing device 1 wirelessly and / or via a wire, and is able to transmit and receive data to and from the device external to the drawing device 1.

[0048] FIG. 3 shows the structure of the shaping aperture array plate 340 of the first embodiment along the xy plane. As shown in FIG. 3, the shaping aperture array plate 340 extends along the xy plane and has, for example, a rectangular shape. The shaping aperture array plate 340 has, for example, silicon as a base, and the surface of the base is covered with a thin film. The thin film is, for example, chromium, and can be formed by plating or sputtering. The shaping aperture array plate 340 has a plurality of apertures 340a. The apertures 340a penetrate two surfaces, i.e., the top surface and the bottom surface, that face each other along the z axis of the shaping aperture array plate 340. The apertures 340a are arranged, for example, in a matrix along the x axis and the y axis. The apertures 340a are, for example, square, and have substantially the same shape as each other.

[0049] The electron beam EB emitted from the electron gun 320 is shaped by the illumination lens 330 to be parallel along the z-axis, and is incident on the upper surface of the shaping aperture array plate 340. A portion of the incident electron beam EB is blocked by the shaping aperture array plate 340, and the remainder passes through the aperture 340a. By such selective blocking and passing of the electron beam EB, the electron beam EB is split (multiplexed) into a plurality of electron beams EBm traveling downward along the z-axis.

[0050] Fig. 4 shows the structure of the blanking aperture array mechanism 350 of the first embodiment along the xz plane. As shown in Fig. 4, the blanking aperture array mechanism 350 includes a base 351. The base 351 extends along the xy plane.

[0051] A substrate 352 is provided on the upper surface of the base 351. The substrate 352 is made of a semiconductor such as silicon. The edge of the bottom surface of the substrate 352 is located on the upper surface of the substrate 352, and the central portion 352a is thinner than the edge. The substrate 352 includes a plurality of apertures 353 in the central portion 352a. Each aperture 353 spans the upper surface and the bottom surface of the substrate 352. The apertures 353 are arranged in the xy plane. Each aperture 353 is located below the aperture 340a of the shaping aperture array plate 340 along the z axis, and has a shape in the xy plane similar to the shape of the aperture 340a in the xy plane, for example, and is slightly larger than the shape of the aperture 340a in the xy plane. The center of each aperture 353 substantially coincides with the center of the aperture 340a of the shaping aperture array plate 340 on the xy plane. The aperture 353 allows the electron beam EBm that has passed through the aperture 340 a of the shaping aperture array plate 340 to pass therethrough.

[0052] The blanking aperture array arrangement 350 also includes a number of electrode pairs 354. Each electrode pair 354 is provided for one aperture 340a, includes electrodes 355 and 356, and functions as a blanker. The electrodes 355 and 356 include or consist of copper, for example. The electrodes 355 and 356 of each electrode pair 354 are spaced apart from each other and sandwich one aperture 353 for which the electrode pair 354 is provided.

[0053] Resistors 357 are provided in portions of the substrate 352 between adjacent electrode pairs 354 (between electrode 355 of a certain electrode pair 354 and electrode 356 of the adjacent electrode pair 354). Each resistor 357 is provided for one electrode pair 354. Each resistor 357 receives various control signals, holds the received control signals, and applies a voltage to one electrode pair 354 for which the resistor 357 is provided, based on the control signals. Each resistor 357 includes elements such as a plurality of transistors and resistors formed on the substrate 352.

[0054] Serial-parallel conversion circuits (S / P conversion circuits) 359 are provided at an end of center portion 352a of substrate 352. Each S / P conversion circuit 359 receives control data DLS serially from BAA control unit 24, divides the received control data DLS into a plurality of parts, and outputs the resulting plurality of control data DL in parallel. S / P conversion circuit 359 includes elements such as a plurality of transistors and resistors formed on substrate 352.

[0055] Fig. 5 shows the structure of the blanking aperture array mechanism 350 of the first embodiment along the xy plane. As shown in Fig. 5, each electrode 356 has a shape in which one side is removed from a rectangle. The three sides of the electrode 356 extend along the three sides of the aperture 353 surrounded by the electrode 356. Fig. 5 shows, as an example, a structure in which each electrode 356 extends along two sides of the aperture 353 parallel to the x axis and the left side of the two sides parallel to the y axis.

[0056] Each electrode 355 extends along one side of the corresponding aperture 353 that is not extended by the electrode 356 that constitutes the electrode pair 354 with that electrode 355. Fig. 5 shows a structure in which each electrode 355 extends along the right side of the two sides parallel to the y-axis.

[0057] The electrodes 356 are grounded (connected to ground). Each electrode 355 is electrically connected to one resistor 357 corresponding to that electrode 355.

[0058] As described above, each register 357 receives various control signals. The control signals include a clock signal and control data DL. The control signals are provided from the BAA control unit 24. The register 357 is also connected to a node of the internal power supply potential VCC (e.g., 5V).

[0059] Each electrode 356 is connected to a node at a common (ground) potential VSS (eg, 0 V).

[0060] 6 is a circuit diagram of the blanking aperture array mechanism 350 of the first embodiment, and further shows related elements. FIG 6 shows only one S / P conversion circuit 359 and related elements as a representative.

[0061] 6, the S / P conversion circuit 359 is connected to the BAA control unit 24 and receives the control data DLS and the high-speed clock (high-speed clock signal) from the BAA control unit 24. The control data DLS is transferred from the BAA control unit 24 to the S / P conversion circuit 359 via a signal line with a width of 1 bit.

[0062] As described above, the S / P conversion circuit 359 is a serial-parallel conversion circuit that divides the received control data DLS into a plurality of parts and outputs a plurality of control data DL consisting of the divided parts in parallel. Fig. 6 shows an example in which the S / P conversion circuit 359 outputs a total of 4 bits of parallel control data DL. For example, the S / P conversion circuit 359 outputs the first bit of the four consecutive bits in the control data DLS as control data DLa, the second bit as control data DLb, the third bit as control data DLc, and the fourth bit as control data DLd. In this way, a total of 4 bits of control data DLa, DLbDLc, and DLd are output in sequence for each consecutive 4 bits.

[0063] The S / P conversion circuit 359 transfers the control data DL to each register 357 .

[0064] One of the registers 357 receives the control data DLa from the S / P conversion circuit 359 at its input. The register 357 that receives the control data DLa from the S / P conversion circuit 359 is called the register 357a. The register 357a is connected at its output to the input of another register 357. Similarly, the output of each register 357a is connected to the input of another register 357a. The register 357a receives a low-speed clock (low-speed clock signal) SCLK from the BAA control unit 24. The low-speed clock SCLK has a period longer than that of the high-speed clock. The low-speed clock CLK and the period during which each piece of serial data transferred by the control data DL lasts are synchronized. The period during which each piece of serial data transferred by the control data DL lasts may be referred to as a data period hereinafter. The register 357a captures the data received at its input using the rising or falling edge (hereinafter referred to as an edge) of the low-speed clock as a trigger. Moreover, the register 357a outputs the held data using the edge of the low-speed clock SCLK as a trigger. Therefore, in synchronization with the edge of the low-speed clock SCLK, the data held in the register 357a closer to the S / P conversion circuit 359 is transferred to the neighboring register 357a farther from the S / P conversion circuit 359. In this way, each register 357a holds the received data and outputs the held data to another register 357a connected in series with itself. That is, a set of registers 357a connected in series constitutes a shift register 3571a.

[0065] Each resistor 357a is connected to one electrode 355 controlled by the resistor 357a via a level shifter (not shown). The electrode 355 connected to the resistor 357a via the level shifter is referred to as an electrode 355a. Each resistor 357a supplies a voltage whose magnitude is converted by the level shifter to the electrode 355a to which the resistor 357a is connected based on the data held by the resistor 357a. The aperture 353 partially surrounded by each electrode 355a is referred to as an aperture 353a.

[0066] Just as the register 357 which sequentially receives the control data DLa from the S / P conversion circuit 359 is referred to as the register 357a, the registers 357 which receive the control data DLb, DLc, and DLd are referred to as the registers 357b, 357c, and 357d, respectively. Just as the electrode 355 which receives the voltage from the register 357a is referred to as the electrode 555a, the electrodes 355 which receive the voltages from the registers 357b, 357c, and 357d, respectively, are referred to as the electrodes 355b, 355c, and 355d, respectively. Furthermore, just as the aperture 353 which is partially surrounded by the electrodes 355a is referred to as the aperture 353a, the aperture 353 which is partially surrounded by the electrodes 354b, 354c, and 354d, respectively, are referred to as the apertures 353b, 353c, and 353d, respectively.

[0067] The description of the control data DLa, the register 357a, and the electrode 355a with the notation "a" replaced with "b" applies to the control data DLb, the register 357b, and the electrode 355b. Similarly, the description of the control data DLa, the register 357a, and the electrode 355a with the notation "a" replaced with "c" applies to the control data DLc, the register 357c, and the electrode 355c. Similarly, the description of the control data DLa, the register 357a, and the electrode 355a with the notation "a" replaced with "d" applies to the control data DLd, the register 357d, and the electrode 355d.

[0068] Fig. 7 shows elements and connections of one shift register 3571 in the first embodiment. Fig. 7 shows, as an example, a shift register 3571a that transfers control data DLa. As shown in Fig. 7, each register 357a is, for example, a D-type flip-flop.

[0069] The shift register includes n (n is a natural number) D-type flip-flops 357a. The first-stage D-type flip-flop 357a receives control data DLa from an S / P conversion circuit 359 at its D input. For all cases where i (i is a natural number less than or equal to n) is 1 to n, the i-th stage flip-flop is connected at its Q output to the D input of the (i+1)th stage flip-flop 357. Each flip-flop 357a is connected at its Q output to one controlled electrode 355a. Each flip-flop 357a receives a low-speed clock SCLK at its clock input.

[0070] 7 shows the shift register 3571a that transfers the control data DLa, but the same is true for the shift registers that transfer the control data DLb, DLc, and DLd. That is, the description made with reference to FIG. 7 in which the notation "a" is replaced with "b," "c," and "d" applies as the description of the shift registers 3571b, 3571c, and 3571d that transfer the control data DLb, control data DLc, and control data DLd, respectively.

[0071] As shown in FIG. 8, each flip-flop 357 applies a driving voltage DV of a magnitude based on the control data DL currently held by the flip-flop 357 to the electrode 355 connected to the Q output of the flip-flop 357. That is, the control data DL held in each flip-flop 357a instructs application of a low or high driving voltage DV to the electrode 355a connected to the flip-flop 357a. The low voltage has a magnitude of, for example, the common potential VSS (for example, 0V). The high voltage has a magnitude of, for example, the internal power supply potential VCC. The control data DL instructs application of a low driving voltage DV by, for example, "0" data or an "L" level. The control data DL instructs application of a high driving voltage DV by, for example, "1" data or an "H" level.

[0072] When the control data DL in the flip-flop 357 instructs application of a low drive voltage DV, the low drive voltage DV is output from the Q output. In this case, there is no potential difference between the electrodes 355 and 356, and therefore no electric field is generated. Therefore, the trajectory of the electron beam EBm is not deflected (blanked) by the electrodes 355 and 356, and as shown by the solid line, the electron beam EBm advances in the same direction as the direction of advance of the electron beam EBm when it entered the region between the electrodes 355 and 356.

[0073] On the other hand, when the control data DL in the flip-flop 357 instructs application of a high drive voltage DV, the high drive voltage DV is output from the Q output. In this case, a potential difference occurs between the electrodes 355 and 356, and an electric field is generated. Therefore, the trajectory of the electron beam EBm is bent (blanked) by the electrodes 355 and 356, and as shown by the dashed line, the electron beam EBm advances in a direction different from the direction of advance of the electron beam EBm when it entered the region between the electrodes 355 and 356.

[0074] In this way, when a certain register 357 is normal and the control data DL held in this register 357 indicates application of a high voltage, the trajectory of the electron beam EBm is bent by application of a high voltage to the electrode 355 connected to this register 357. On the other hand, when a certain register 357 is abnormal, even if the control data DL held in this register 357 indicates application of a high voltage, a high voltage is not applied to the electrode 355 connected to this register 357, and the trajectory of the electron beam EBm is not bent. The register 357 includes a plurality of transistors T as described in detail later, and a state in which the register 357 is abnormal corresponds to a case in which any of the transistors T included in the register 357 is abnormal. When the transistor T included in the register 357 is abnormal, the performance of the transistor T deteriorates, and the transistor T does not exhibit the same characteristics as the initial state (for example, immediately after the manufacture of the transistor T).

[0075] Fig. 9 shows an example of elements and connections of the D-type flip-flop 357 of the first embodiment. Each D-type flip-flop 357 can have, as an example, the elements and connections shown in Fig. 9. As shown in Fig. 9, the D-type flip-flop 357 includes NAND gates ND1, ND2, ND3, ND4, ND5, ND6, ND7, and ND8, and inverters (negation circuits) IV1 and IV2.

[0076] The input of inverter IV1 serves as the clock input of D-type flip-flop 357. The output of inverter IV1 is connected to the input of inverter IV2.

[0077] A first input of the NAND gate ND1 serves as a D input of the D-type flip-flop 357. A second input of the NAND gate ND1 is connected to the output of the inverter IV1. The output of the NAND gate ND1 is connected to a first input of the NAND gate ND2. The output of the NAND gate ND1 is also connected to a first input of the NAND gate ND3. The second input of the NAND gate ND3 is connected to the output of the inverter IV1. The output of the NAND gate ND3 is connected to a first input of the NAND gate ND4. The second input of the NAND gate ND4 is connected to the output of the NAND gate ND2. The output of the NAND gate ND4 is connected to a second input of the NAND gate ND2.

[0078] The output of the NAND gate ND2 is also connected to a first input of a NAND gate ND5. The second input of the NAND gate ND5 is connected to the output of the inverter IV2. The output of the NAND gate ND5 is also connected to a first input of a NAND gate ND6. The output of the NAND gate ND5 is also connected to a first input of a NAND gate ND7. The second input of the NAND gate ND7 is connected to the output of the inverter IV2. The output of the NAND gate ND7 is connected to a first input of a NAND gate ND8. The second input of the NAND gate ND8 is connected to the output of the NAND gate ND6. The output of the NAND gate ND8 is connected to a second input of the NAND gate ND6.

[0079] The output of NAND gate ND6 serves as the Q output of D-type flip-flop 357. The output of NAND gate ND8 serves as the Q output of D-type flip-flop 357. The symbol "" indicates the inverse logic of the signal whose name is not accompanied by the symbol "".

[0080] The NAND gates ND1 to ND8 may have any elements and connections as long as they function as NAND gates. An example is described below. Figure 10 shows an example of the elements and connections of the NAND gates ND (ND1 to ND8) of the first embodiment.

[0081] 10, the NAND gate ND includes p-type metal oxide silicon field effect transistors (MOSFETs) TP1 and TP2, and n-type MOSFETs TN1 and TN2. The transistors TP1 and TP2 are connected in parallel between a node of an internal power supply potential VCC and a node N1. The node N1 functions as an output Out of the NAND gate ND. The transistors TN1 and TN2 are connected in series between the node N1 and a node of a ground potential VSS.

[0082] The gates of the transistors TP1 and TN1 are connected to each other and function as a first input In1 of the NAND gate ND, while the gates of the transistors TP2 and TN2 are connected to each other and function as a second input In2 of the NAND gate ND.

[0083] The inverters IV1 and IV2 may have any elements and connections as long as they function as inverters. An example is described below. Figure 11 shows an example of the elements and connections of the inverter IV (IV1 and IV2) of the first embodiment.

[0084] 11, the inverter IV includes a p-type MOSFET TP5 and an n-type MOSFET TN5. The transistor TP5 is connected between a node of the internal power supply potential VCC and a node N5. The node N5 functions as an output OUT of the inverter IV. The transistor TN5 is connected between the node N5 and a node of the ground potential VSS. The gates of the transistors TP5 and TN5 are connected to each other and function as an input IN of the inverter IV.

[0085] 1.2.Operation Fig. 12 shows functional blocks of the control device 21 of the first embodiment. That is, the control device 21 operates as including the functional blocks shown in Fig. 12 during the operation of the drawing device 1. Each functional block can be realized by the processor 211 executing a program as described with reference to Fig. 2. Some functional blocks may be realized by hardware.

[0086] As shown in FIG. 12, the control device 21 includes a rasterizer 221, a modulation calculator 222, a high-speed data transfer unit 223, a positioning unit 224, and a BAA diagnostic unit 225.

[0087] The rasterizing unit 221 receives drawing data, for example, in vector format, from the outside based on an input from a user of the drawing device 1, and rasterizes the drawing data to generate drawing data in bitmap format.

[0088] The modulation calculation unit 222 receives drawing data from the rasterization unit 221. The modulation calculation unit 222 generates control data for controlling each element for drawing based on the drawing data. The generated control data includes BAA control data and beam control data. The BAA control data is used for blanking control in the blanking aperture array mechanism 350 and is supplied to the high-speed data transfer unit 223. The BAA control data specifies the register 357 that should output the high-voltage driving voltage DV and specifies the magnitude of the driving voltage DV. Hereinafter, the register 357 that should output the driving voltage DV as specified by the BAA control data may be referred to as a selection register 357s. The beam control data is used to control the position and irradiation amount of the beam and is supplied to the positioning unit 224. The modulation calculation unit 222 takes into account data supplied from the BAA diagnosis unit 225 described later in generating the BAA control data.

[0089] The high-speed data transfer unit 223 supplies the BAA control data to the BAA control unit 24 via an interface 216 (not shown). The positioning unit 224 generates various control data based on the beam control data. The generated control data is supplied to the irradiation dose control unit 25, the deflector amplifier 27, and the stage driving device 28 via the interface 216.

[0090] The BAA diagnosis unit 225 executes a process for diagnosing the BAA based on the program and an input from the user of the drawing device 1, and supplies data indicating the result of this diagnosis to the modulation calculation unit 222. The modulation calculation unit 222 uses the diagnosis result data to generate BAA control data. Next, the operation of the BAA diagnosis unit 225 is described.

[0091] Fig. 13 shows a flow of operations performed by the drawing device 1 of the first embodiment. More specifically, Fig. 13 shows a flow of operations for drawing and preparation for drawing. The flow of Fig. 13 starts, for example, with an operation by a user of the drawing device 1. Some steps will be described in detail later.

[0092] In some steps from step ST1, the BAA diagnostic unit 225 identifies a register 357 that is expected to fail in the near future. Specifically, in step ST1, the BAA diagnostic unit 225 instructs the modulation calculation unit 222 to use a worse condition than the condition normally used for controlling the blanking aperture array mechanism 350, particularly for transmitting the control data DL. The normally used condition is a condition used for a blanking aperture array mechanism 350 that is not deteriorated, for example, a condition used for a blanking aperture array mechanism 350 in a state immediately after the manufacturing of the drawing device 1. The condition changed to a worse value includes, for example, the magnitude of the voltage of the "H" level of the control data DL, and the period of the low-speed clock SCLK (hereinafter, sometimes referred to as the low-speed clock period) and the output period of the set of data periods. The worse condition for the "H" level of the control data DL is a smaller "H" level voltage in magnitude, which is a voltage lower than the "H" level voltage under normal use conditions of the one that each register (flip-flop) 357 receives to hold the "H" level (i.e., "1" data). The worse condition for the set of the slow clock period and data period is a shorter slow clock period and data period output period.

[0093] The BAA diagnostic unit 225 attempts to identify the register 357 that does not operate normally under the control of the blanking aperture array mechanism 350 under the conditions set in step ST1. That is, the BAA diagnostic unit 225 judges (or confirms or checks) whether the register 357 is operating normally. The register 357, particularly the transistor T in the register 357, may deteriorate in performance due to degradation. Even if the register 357 with deteriorated performance operates under control under normal conditions, i.e., conditions that are applied when the register 357 is not deteriorated, at a certain point in time, the deterioration may progress in the near future and the register 357 may not operate normally under normal conditions. For such a register 357, the BAA diagnostic unit 225 can intentionally use conditions that are worse than normal conditions, and detect the register 357 based on whether the register 357 operates normally under these bad conditions. The worse the conditions, the more the BAA diagnostic unit 225 can detect the register 357 with less deterioration. The bad conditions used depend on the degree of deterioration to be detected. The bad conditions used can be determined, for example, by the user of the drawing device 1 selecting or inputting a value. For example, to achieve the most sensitive detection, the worst condition can be used. The worst condition is, for example, the condition at which transistor T turns on according to design and / or specification. For example, the worst condition is the lowest threshold voltage at which transistor T turns on according to design and / or specification. And / or, the worst condition is the shortest slow clock period and data period according to design and / or specification at which shift register 3571 can successfully capture and hold data.

[0094] In step ST2, the BAA diagnostic unit 225 performs a fault diagnosis of the blanking aperture array mechanism 350, particularly the register 357, under the conditions determined to be used. Specifically, the BAA diagnostic unit 225 instructs the modulation calculation unit 222 to irradiate and blank the electron beam under the conditions determined to be used. The modulation calculation unit 222 generates BAA control data instructing to control the register 357 under the instructed conditions based on the received instruction. The generated BAA control data is transmitted from the BAA control unit 24 to the blanking aperture array mechanism 350. The BAA diagnostic unit 225 checks the state of the electron beam EBm during the operation of the blanking aperture array mechanism 350 based on the BAA control data. That is, the BAA diagnostic unit 225 indirectly judges whether a certain register 357s is operating normally by observing whether the electron beam EBm passing between the electrode 355 connected to the selected register 357s and the electrode 356 that forms a pair with the selected electrode 355 is blanked. If blanked, it is determined that the selection register 357s to be inspected is operating normally, and therefore it is determined that the selection register 357s is not faulty (operating normally). If not blanked, it is determined that the selection register 357s to be inspected is not operating normally, and therefore it is determined that the selection register 357s is faulty (not operating normally). The BAA diagnostic unit 225 diagnoses, for example, all the registers 357. The BAA diagnostic unit 225 holds information identifying the register 357 determined to be faulty, for example, in the storage device 213.

[0095] In step ST3, the BAA diagnosis unit 225 judges whether the blanking aperture array mechanism 350 is normal. For example, the judgment is made in step ST2 that none of the registers 357 is faulty. If it is judged to be normal (Yes in step ST3), preparation for drawing is complete. In this case, the drawing device 1 notifies the user, for example, using the output device 215, that the fault diagnosis has been completed and that no fault has been detected. Upon receiving this notification, the user performs drawing (step ST10).

[0096] If it is determined in step ST3 that the blanking aperture array mechanism 350 is not normal (No in step ST3), the process proceeds to step ST4. In several steps after step ST4, the BAA diagnosis unit 225 performs further diagnosis on some or all of the registers 357 that are determined to be faulty in step ST2, among all the registers 357. Hereinafter, the register 357 diagnosed in step ST4 is referred to as the target register 357t.

[0097] Specifically, in step ST4, the BAA diagnostic unit 225 repeatedly changes the magnitude of the “H” level voltage of the control data DL input to the target register 357t, i.e., the control data DL input to the shift register 3571 including the target register 357t, for each loop, to determine whether the target register 357t operates normally. The “H” level voltage is increased by a certain amount each time the number of loops increases, for example, from the “H” level voltage used in step ST2. In a certain loop in the process of loop repetition, the target register 357t operates normally. The BAA diagnostic unit 225 associates the magnitude of the “H” level voltage at that time with the target register 357t and stores it in the storage device 213. The “H” level voltage when the target register 357t operates normally for the first time in a certain loop in the process of loop repetition is closest to the worst condition set in step ST1, for example, the lowest threshold voltage in design and / or specifications at which the transistor T turns on.

[0098] Instead of or in addition to changing the magnitude of the “H” level voltage, the BAA diagnostic unit 225 can determine whether the target register 357t operates normally while changing the period of the low-speed clock SCLK and the data period of the control data DL for each loop. As described above, the period of the low-speed clock SCLK and the data period of the control data DL are synchronized. Therefore, hereinafter, the period of the low-speed clock SCLK and the data period of the control data DL may be simply referred to as the period of the low-speed clock SCLK (or the low-speed clock period). In the following description, the “period of the low-speed clock SCLK” and the “data period of the control data DL” are interchangeable. For example, the low-speed clock period is lengthened by a certain increment from the low-speed clock period used in step ST2 each time the number of loops increases. In a certain loop in the process of repeating the loop, the target register 357t operates normally. The BAA diagnostic unit 225 stores the low-speed clock period at that time in the storage device 213 in association with the target register 357t. The slow clock period when the target register 357t operates normally for the first time in a certain loop during the loop iteration process is closest to the worst-case conditions set in step ST1, for example, the shortest periods in the design and / or specifications of the slow clock period and data period.

[0099] The BAA diagnostic unit 225 can perform the diagnosis of a certain target register 357t described above on all target registers 357t. The BAA diagnostic unit 225 can perform the diagnosis of all target registers 357t in parallel, that is, in a common loop. Step ST4 will be described later.

[0100] In step ST5, the BAA diagnosis unit 225 estimates the time expected to be required until failure for each of all the target registers 357t based on the information obtained in step ST4. That is, the magnitude of the "H" level voltage that operates the target register 357t normally correlates with the degree of deterioration of the target register 357t. The degree of deterioration also correlates with the time from the present until the target register 357t no longer operates under normal conditions due to the progression of deterioration associated with future use, that is, the time until failure. Using this fact, the BAA diagnosis unit 225 estimates the time from the present until failure using the magnitude of the "H" level voltage that operates the target register 357t normally.

[0101] As in step ST4, instead of or in addition to estimating the time to failure based on the magnitude of the “H” level voltage, the BAA diagnosis unit 225 can estimate the time to failure of the target register 357t based on the slow clock period. That is, the slow clock period that causes the target register 357t to operate normally is correlated with the degree of deterioration of the register 357t. Furthermore, the degree of deterioration is correlated with the time from the present until failure due to the progression of deterioration associated with the future use of the register 357t. Using this fact, the BAA diagnosis unit 225 estimates the time from the present until failure using the slow clock period that causes the target register 357t to operate normally.

[0102] Step ST5 will be described further below.

[0103] In step ST6, the BAA diagnosis unit 225 judges whether the failure time estimated for each of all the target registers 357t (hereinafter, sometimes referred to as the estimated failure time) is equal to or less than a certain threshold (reference time). During drawing, even if a failure occurs in a component in the drawing device 1, the failed component cannot be replaced, and one drawing takes time. For this reason, it is required that the components do not fail during drawing. If the estimated failure time of all the target registers 357t is longer than the time required for one drawing, it is possible to prevent the target register 357t from failing during the next drawing. Based on this, the threshold can be set to, for example, the time required for one drawing. There is a possibility that the prediction of the estimated failure time is wrong and a failure occurs in the target register 357t within the time required for one drawing when drawing is actually performed. In consideration of this, the threshold may be set to a time longer than the time required for one drawing, for example, the time required for two drawing, with a small margin for the estimated failure time. Alternatively, the threshold value can be set to a period during which the user wishes to avoid a failure occurring, which period is determined based on a drawing plan. The threshold value can be input by the user in advance, particularly before the start of the flow of FIG. 13, for example.

[0104] If the estimated failure times of all the target registers 357t are not equal to or less than the threshold (exceed the threshold) (No in step ST6), the process proceeds to step ST10.

[0105] If the estimated failure time of any one of the target registers 357t is equal to or less than the threshold (Yes in step ST6), the process proceeds to step ST8. In step ST8, the BAA diagnosis unit 225 notifies the user, for example, using the output device 215, that the time estimated to be required until failure of the blanking aperture array mechanism 350 is equal to or less than the threshold. The notification can include, for example, information identifying the register 357 whose estimated failure time exceeds the threshold.

[0106] In step ST9, the user determines that the register 357 having an estimated failure time equal to or less than the threshold is defective, and performs correction for the defect. This correction includes, for example, increasing the "H" level voltage of the control data DL, or lengthening the low-speed clock period (and the data period of the control data DL) (reducing the frequency). This ensures the operation of the register 357. Alternatively, it includes replacing the blanking aperture array mechanism 350. By replacing it, the operation of the register 357 is ensured. Alternatively, if it is possible to replace only the register 357, the register 357 having an estimated failure time equal to or less than the threshold is replaced. By replacing it, the operation of the register 357 is ensured.

[0107] The following correction is also possible as step ST9. That is, when a failure occurs, the Q output of the failed register 357 is fixed to a level according to the failure, regardless of the control data DL. Therefore, the presence or absence of blanking for the beam whose blanking is controlled by the Q output of the failed register 357 is fixed. Therefore, this beam is used as a beam that is always blanked or is always not blanked, and the operation of the beam whose blanking is fixed is corrected by the beam controlled by another register 357 that is operating normally.

[0108] As a countermeasure against a possible failure in step ST9 of FIG. 13, since the deflection of the output of the failed shift register is fixed, it is possible to perform drawing so that it is corrected by another normal beam, for example as a conventionally known always-on / off beam.

[0109] Next, step ST1 will be further described with reference to FIG. 14. FIG. 14 shows an example of characteristics before and after the deterioration of the characteristics of the transistor T of the first embodiment. FIG. 14 shows, as an example, the relationship between the gate-source voltage and the drain current of an n-type MOSFET TN (e.g., transistor TN1, TN2, or TN5) of the resistor 357. The transistor TN passes different drain currents Id depending on the magnitude of the gate-source voltage Vgs, as shown in FIG. 14(a).

[0110] FIG. 14(b) shows the characteristics of the transistor TN before and after the degradation of its characteristics. As shown in the left part of FIG. 14(b), before the degradation of the characteristics of the transistor TN, the threshold voltage of the transistor TN is a certain magnitude Vth. When a voltage VI (>Vth) is applied between the gate and source of the transistor TN, the transistor TN turns on. The voltage VI is the voltage applied to the transistor TN under normal conditions, and is hereinafter referred to as the standard voltage VI. Assume that the characteristics of the transistor TN deteriorate and have the characteristics shown by the solid line on the right side of FIG. 14(b). Due to the degradation of the characteristics, the transistor TN has a threshold voltage Vthd that is higher than the threshold voltage Vth before the degradation, and the threshold voltage Vthd is higher than the standard voltage VI. Therefore, the transistor TN deteriorated in this way does not turn on even when the standard voltage VI is applied.

[0111] On the other hand, as shown in FIG. 15, the transistor TN has a threshold voltage Vthd1 due to degradation at a certain point in time. The threshold voltage Vthd1 is higher than the threshold voltage Vth but lower than the standard voltage VI. Therefore, the transistor TN is turned on by application of the standard voltage VI. However, the transistor TN may deteriorate during the next drawing, and may have a threshold voltage higher than the standard voltage VI during drawing (e.g., Vthd shown in the right part of FIG. 14(b)). In this case, the transistor TN will not be turned on even by application of the standard voltage VI from the middle of drawing. To prevent this from happening, it is possible to identify that the transistor TN is degraded by applying a voltage lower than the normally applied standard voltage VI, for example, a voltage VIW, to the transistor TN, as described in step ST1 of FIG. 13. 15, the transistor TN before degradation (dotted line characteristics) is turned on by application of a voltage VIW lower than the standard voltage VI for a certain time TR, while the transistor TN having a threshold voltage Vthd1 due to degradation (solid line characteristics) is not turned on by application of the voltage VIW for a certain time TR. Therefore, it is possible to identify that the transistor TN is degraded by application of such a voltage.

[0112] By utilizing this phenomenon, it is possible to identify a register 357 including a deteriorated transistor TN, as described below. That is, each register 357 that receives a certain control data DL (e.g., control data DLa) having an "H" level voltage of a standard magnitude operates normally if none of the transistors TN in this register 357 has deteriorated. That is, a drive voltage VD based on the "H" level is applied to the electrode 355 connected to the register 357 based on the control data DL. However, if any of the transistors TN is deteriorated, this transistor TN will not turn on even if it receives an "H" level voltage lower than the "H" level voltage of the standard magnitude. Therefore, the register 357 including the deteriorated transistor TN will not operate normally even if it receives the control data DL of a lower "H" level voltage. As a result, the electron beam EBm passing through the aperture 353 facing this electrode 355 will not be blanked. Based on this, it is possible to find the register 357 including the deteriorated transistor TN by lowering the "H" level voltage of the control data DL below the standard magnitude.

[0113] By reducing the "H" level voltage of the control data DL, even if the transistor TN (i.e., the transistor TN1 of the NAND gates ND1 and ND3) in the first stage of the register 357 is normal, the output of this transistor TN is smaller than the "H" level output when the control data DL of the standard magnitude of the "H" level voltage is applied. Therefore, a smaller output "H" level voltage is also applied to the gate of the transistor TN1 in the second stage and thereafter. That is, by reducing the "H" level voltage of the control data DL, the "H" level voltage at each node of the register 357 is smaller than the case where the "H" level voltage of the standard magnitude of the control data DL is applied. Therefore, if there is even one transistor TN in a certain register 357 that does not turn on by input of the control data DL of the standard magnitude of the "H" level voltage, the register 357 does not operate normally. Therefore, as a result, by reducing the "H" level voltage of the control data DL, it is possible to determine whether all the transistors TN in a certain register 357 are normal or whether at least one transistor TN is deteriorated.

[0114] With reference to FIG. 14 and FIG. 15, a method for identifying a degraded transistor TN based on the threshold voltage has been described, but the same phenomenon occurs with respect to the application time of the gate-source voltage Vgs. That is, a transistor TN with degraded characteristics may not be turned on even by application of the standard voltage VI for the same voltage application time TI as before the degradation. Even if the time during which the gate-source voltage Vgs is applied to a certain transistor TN to turn on is currently TO (hereinafter, sometimes referred to as the required voltage application time), the degradation may progress between the next drawing and the required voltage application time TOd (>TI). Based on this, as described in step ST1 of FIG. 13, the slow clock period is shortened. The slow clock period affects the time of output of the voltage from the register 357. Therefore, it is possible to identify that the transistor TN is degraded by applying the gate-source voltage Vgs, for example, the standard voltage VI, to the transistor TN for a time shorter than the voltage application time TI included in the normal condition, for example, for a time TOW. The transistor TN before degradation turns on even if the standard voltage VI is applied for only a voltage application time TOW that is shorter than the necessary voltage application time TO. On the other hand, the transistor TN having a necessary voltage application time TOd1 (>TOW) due to degradation does not turn on even if the standard voltage VI is applied for the voltage application time TOW. Therefore, it is possible to identify that the transistor TN has deteriorated by applying the standard voltage VI for such a time.

[0115] By utilizing this phenomenon, the register 357 including the deteriorated transistor TN does not operate normally due to the same principle as when the "H" level voltage of the control data DL is reduced, and therefore it is possible to identify the deteriorated register 357.

[0116] Up to this point, the n-type MOSFET TN has been described with reference to Figs. 14 and 15. This description is also applicable to the p-type MOSFET TP. That is, a more deteriorated p-type transistor TP has a lower threshold voltage. The voltage application time for the p-type transistor TP1 is the same as that for the n-type transistor TN, and the more the transistor TP1 deteriorates, the longer the required voltage application time. Therefore, if a certain resistor 357 includes at least one deteriorated n-type transistor TN or at least one deteriorated p-type transistor TP, this resistor 357 does not operate normally.

[0117] Next, step ST5 in FIG. 13 will be described in more detail with reference to FIG. 16. FIG. 16 shows, as an example, the relationship between the deterioration of the transistor TN of the register 357 of the first embodiment and the usage time. The deterioration of the characteristics of the register 357 (particularly the transistors TN and TP therein) correlates with the accumulated time that the transistors TN and TP have been used. FIG. 16 and the following description relate to a certain transistor TNa that has deteriorated in a certain register 357 and thus prevents the register 357 from operating normally among the transistors TN in the register 357. The same description in FIG. 16 and the following description also applies to a certain deteriorated transistor TP.

[0118] The deterioration of the transistor TN is not caused only by the use of the transistor TN itself, but depends on the time the transistor TN is exposed to the deterioration environment. This is because the transistor TN deteriorates due to the environment caused by drawing, such as exposure to X-rays caused by the irradiation of the electron beam EBm for drawing. Thus, the transistor TN depends at least partially on the drawing time, or more precisely, the irradiation time of the electron beam EBm. This relationship is used to estimate the failure time in step ST4 of FIG. 13.

[0119] As an example, it is assumed that the increase in the threshold voltage of the transistor TN due to degradation occurs after the cumulative time t1 during which drawing has been performed. In this case, the difference between the threshold voltage Vth before degradation and Vthd1 after degradation correlates with the time t1. Such a relationship between the cumulative time and the difference in the threshold voltage before and after degradation is obtained in advance for various cases by experiment and / or simulation. For example, the average of the relationships for the multiple transistors TN, or the relationship for one of the multiple transistors TN, is used as a representative. The multiple discrete relationships thus obtained are interpolated or approximated by a formula. As a result, as shown in the lower part of FIG. 16, the relationship between the cumulative usage time from when the transistor TN was not used and the current threshold voltage is obtained. FIG. 16 shows a linear relationship as an example. For example, such a relationship is stored in the storage device 213 at the start of use of the drawing device 1. The BAA diagnosis unit 225 uses this relationship to determine the estimated failure time.

[0120] For example, assume that transistor TNa has been used for an accumulated usage time Tc1 and has a threshold voltage Vthd1 (<standard voltage VI) at that time. Also assume that the accumulated usage time until the threshold voltage of transistor TNa becomes equal to the standard voltage VI is Tc2. In this case, the time required for the threshold voltage of transistor TNa to reach the standard voltage VI is Tc2-Tc1. The time calculated in this manner is the estimated failure time of transistor TNa, that is, the estimated failure time of resistor 357 including transistor TNa.

[0121] The same applies to the required voltage application time. That is, when an increase in the required voltage application time due to deterioration occurs after the elapse of the cumulative time t1, the difference between the required voltage application time TO before deterioration and the required voltage application time TOd after deterioration correlates with the time t1. Such relationships between the cumulative time and the difference in the threshold voltage before and after deterioration are obtained in advance by experiments and / or simulations for various cases. The plurality of discrete relationships thus obtained are interpolated or approximated by a mathematical formula. In this way, the relationship between the cumulative time and the difference in the required voltage application time before and after deterioration is used to estimate the time required for the transistor TN1 estimated to have the required voltage application time TOd1 (<TI) to exceed the required voltage application time TI. The estimated time is the estimated failure time.

[0122] As described above, the estimated failure time may be based on both the threshold voltage Vth and the required voltage application time TO. Further, as an index of deterioration of the transistor TN and / or TP, a value of another characteristic may be used.

[0123] In the description so far, as an example, the determination of whether the register 357 (shift register 3571) is faulty (operating normally) is based on whether the blanking state when the drive voltage DV according to the control data DL for this register 357 is applied to the electrode 355 connected to this register 357 and the electron beam EBm is blanked, and whether the blanking state of the electron beam EBm formed by applying the drive voltage DV according to the control data DL to the electrode 355 connected to this register matches. The embodiment is not limited to this example. The determination of the fault may be based on whether the control data DL supplied to the register 357 in the first stage (initial stage) of the shift register 3571 matches the control data DL output from any one of the registers 357 after the control data DL supplied to the register 357 in the first stage is transferred through the shift register 3571.

[0124] 1.3. Advantages (Effects) According to the first embodiment, the BAA diagnostic unit 225 applies a voltage and / or a low-speed clock signal SCLK to the register 357 under worse conditions than those used during normal drawing, determines the conditions under which the malfunctioning register 357 operates normally, and estimates the time until the register 357 fails based on the determined conditions. In this way, the BAA diagnostic unit 225 can identify the register 357 that may fail during the next drawing based on the estimated failure time. This allows the failure to be addressed before drawing, and can prevent the register 357 from failing unexpectedly during drawing.

[0125] 1.4. Variations The decision to use the estimated failure time may further be used to plan replacement and production of blanking aperture array features. Figure 17 shows the flow of such a process, and shows the flow of the imaging and inspection method of the modified example of the first embodiment. With respect to Figure 17, only the changes from Figure 13 described in the basic form of the first embodiment will be described.

[0126] As shown in FIG. 17, step ST5 continues to step ST11. In step ST11, the BAA diagnosis unit 225 determines whether the estimated failure time for each of all the target registers 357t is equal to or less than the first threshold value Th1. The first threshold value Th1 is longer than the threshold value to which the estimated failure time is compared in step ST6 of the basic form of the first embodiment (FIG. 13). The first threshold value Th1 can be set to a period during which the user desires the blanking aperture array mechanism 350 to be normal, which is determined based on a drawing plan, for example. Or, the first threshold value Th1 can be set to a period longer than the time required from the current time until the manufacture of the replacement blanking aperture array mechanism 350 is completed and the manufactured blanking aperture array mechanism 350 is replaced. The first threshold value Th1 can be input by the user in advance, for example, before the start of the flow of FIG. 17.

[0127] If the estimated failure times of all the target registers 357t are not equal to or less than the first threshold value Th1 (No in step ST11), it is considered that no failure will occur in the components of the blanking aperture array mechanism 350 for a while. Therefore, the process proceeds to step ST10.

[0128] If the estimated failure times of all the target registers 357t are equal to or less than the first threshold value Th1 (Yes in step ST11), the process proceeds to step ST12. In step ST12, the BAA diagnosis unit 225 determines whether the estimated failure times of all the target registers 357t are equal to or less than the second threshold value Th2. The second threshold value Th2 is shorter than the first threshold value Th1, and is, for example, the same as the threshold value to which the estimated failure times are compared in step ST6 of the basic form of the first embodiment.

[0129] If the estimated failure time of any one of the target registers 357t is not equal to or less than the second threshold Th2 (exceeds the second threshold Th2) (No in step ST12), this means that a failure of a component of the blanking aperture array mechanism 350 will not occur during the drawing that will be performed for the number of times based on the second threshold Th2 in the future, but a failure may occur in the near future. Based on this, in step ST15, the BAA diagnosis unit 225 notifies the user that a failure may occur in the near future, for example, by using the output device 215.

[0130] If the estimated failure times of all the target registers 357t are equal to or less than the second threshold value Th2 (Yes in step ST12), the process proceeds to step ST8. Step ST8 continues to step ST9, and step ST9 continues to step ST10.

[0131] In step ST16, the BAA diagnostic unit 225 plans the replacement time (date and time) of the blanking aperture array mechanism 350 based on the judgment that a failure may occur in the near future. The replacement time is based on the estimated failure time. For example, the replacement time is set to a time before the total time for which drawing is scheduled to be performed exceeds the estimated failure time based on the (for example, average) number of times that the user is expected to perform drawing in the future. The replacement time is notified to the manufacturer of the drawing device 1. For example, data indicating the replacement time is transmitted to the manufacturer of the drawing device 1 via the communication device 217 and received by the manufacturer of the drawing device 1.

[0132] In step ST17, the manufacturer of the drawing apparatus 1 knows the replacement time from the received data indicating the replacement time, and based on the replacement time, creates a schedule for the production of a new blanking aperture array mechanism 350. Step ST17 is followed by step ST10.

[0133] Steps ST15, ST16, and ST17 may be performed in an order different from that shown in FIG. 17, or may be performed in parallel.

[0134] The present invention is not limited to the above-mentioned embodiment, and various modifications can be made in the implementation stage without departing from the gist of the invention. In addition, the embodiments may be implemented in appropriate combination, and in that case, the combined effect can be obtained. Furthermore, the above-mentioned embodiment includes various inventions, and various inventions can be extracted by combinations selected from the multiple components disclosed. For example, if the problem can be solved and the effect can be obtained even if some components are deleted from all the components shown in the embodiment, the configuration from which the components are deleted can be extracted as an invention.

Claims

1. In a blanking aperture array system used in a multi-charged particle beam irradiation device, a shift register including a plurality of flip-flops connected in series and for transferring control data used for beam irradiation; a first electrode connected to each of the plurality of flip-flops and formed on a substrate, and a second electrode sandwiching one of a plurality of apertures for passing a beam between the first electrode and a second electrode connected to ground; a blanking aperture array substrate having supplying the control data to the shift register during a beam irradiation operation, the control data being such that the value held by the flip-flop becomes 1 at a first voltage that is a voltage used during the beam irradiation operation; During a period other than the beam irradiation operation, the control data, which causes the value held by the flip-flop to become 1 at a second voltage lower than the first voltage, is supplied to the shift register, and a determination is made as to whether the control data supplied to the shift register coincides with control data transferred within the shift register and output from one of the flip-flops of the shift register, or whether a blanking state in the case where blanking is performed by the first electrode connected to the first flip-flop of the shift register in accordance with the control data supplied to the shift register coincides with a blanking state performed by the first electrode connected to the first flip-flop in accordance with the control data supplied to the shift register, thereby determining whether the plurality of flip-flops are operating normally. A control device; 1. A blanking aperture array system comprising:

2. the second voltage is a lower limit value at which a transistor included in one of the plurality of flip-flops is turned on; When a first flip-flop, which is one of the plurality of flip-flops, does not operate normally by supplying the control data to the shift register such that the value held by the flip-flop of the second voltage becomes 1, supplying the control data, which are different voltages between the first voltage and the second voltage and which are held by the flip-flops at values ​​of 1, to the shift register in sequence; determining a third voltage among the plurality of different voltages that allows the first flip-flop to operate normally and is closest to the second voltage; using a relationship between an accumulated usage time of the first flip-flop and a threshold voltage, estimating a first time until the first flip-flop stops operating normally by supplying the control data, which causes the flip-flop of the first voltage to hold a value of 1, to the shift register; comparing the first time with a reference time; 2. The blanking aperture array system of claim 1.

3. When the first time exceeds the reference time, the control data that causes the value held by the flip-flop having a voltage higher than the first voltage to become 1 is supplied to the shift register.

3. The blanking aperture array system of claim 2.

4. In a blanking aperture array system used in a multi-charged particle beam irradiation device, a shift register including a plurality of flip-flops connected in series, receiving a clock and transferring control data used for beam irradiation at a timing based on the clock; a first electrode connected to each of the plurality of flip-flops and formed on a substrate, and a second electrode sandwiching one of the plurality of apertures between the first electrode and a second electrode connected to ground; a blanking aperture array substrate having providing the clock having a first period to the shift register during a beam projection operation; supplying the clock having a second period shorter than the first period to the shift register during a period other than the beam irradiation operation, and judging whether the plurality of flip-flops are operating normally by judging whether the control data supplied to the shift register matches the control data supplied to the shift register and the control data output from one flip-flop of the shift register after the control data supplied to the shift register is transferred within the shift register, or by judging whether a blanking state when blanking is performed by the first electrode connected to the first flip-flop of the shift register in accordance with the control data supplied to the shift register matches a blanking state performed by the first electrode connected to the first flip-flop in accordance with the control data supplied to the shift register. A control device; 1. A blanking aperture array system comprising:

5. the second period is a lower limit value at which the shift register operates normally, When a first flip-flop, which is one of the plurality of flip-flops, does not operate normally due to the supply of the clock having the second period to the shift register, the control device supplying the clock having a plurality of different periods between the first period and the second period to the shift register in sequence; finding a third period among the plurality of different periods in which the first flip-flop operates normally and which is closest to the second period; estimating a first time until the first flip-flop stops operating normally by supplying the clock having the first period to the shift register using a relationship between an accumulated usage time of the first flip-flop and the period of the clock; comparing the first time with a reference time; 5. The blanking aperture array system of claim 4.

6. if the first time exceeds the reference time, supplying the clock having a period longer than the first period to the shift register; 6. A blanking aperture array system as claimed in claim 5.

7. A movable stage and a beam source above the stage; a blanking aperture array system according to any one of claims 1 to 6 located between the beam source and the stage; A charged particle beam writing apparatus comprising:

8. A method for inspecting a blanking aperture array system used in a multi-charged particle beam irradiation device, comprising: The blanking aperture array system includes: a shift register including a plurality of flip-flops connected in series and for transferring control data used for beam irradiation; a first electrode connected to each of the plurality of flip-flops and formed on a substrate, and a second electrode sandwiching one of the plurality of apertures between the first electrode and a second electrode connected to ground; a blanking aperture array system having The inspection method includes: supplying the control data to the shift register so that the value held by the flip-flop of a first voltage becomes 1 during a beam irradiation operation; supplying the control data to the shift register during a period other than the beam irradiation operation, such that the value held by the flip-flop of a second voltage lower than the first voltage becomes 1, and judging whether the control data supplied to the shift register matches the control data received from one of the flip-flops of the shift registers, or judging whether a blanking state by the first electrode connected to one of the flip-flops of the shift registers matches a blanking state indicated by the control data supplied to the shift register, thereby judging whether the plurality of flip-flops are operating normally. A method for inspecting a blanking aperture array system comprising:

9. A method for inspecting a blanking aperture array system used in a multi-charged particle beam irradiation device, comprising: The blanking aperture array system includes: a shift register including a plurality of flip-flops connected in series, receiving a clock and transferring control data used for beam irradiation at a timing based on the clock; a first electrode connected to each of the plurality of flip-flops and formed on a substrate, and a second electrode sandwiching one of the plurality of apertures between the first electrode and a second electrode connected to ground; a blanking aperture array system having The inspection method includes: providing the clock having a first period to the shift register during a beam projection operation; supplying the clock having a second period shorter than the first period to the shift register during a period other than the beam irradiation operation, and judging whether the plurality of flip-flops are operating normally by judging whether the control data supplied to the shift register matches the control data received from one of the flip-flops of the shift registers, or by judging whether a blanking state by the first electrode connected to one of the flip-flops of the shift registers matches a blanking state indicated by the control data supplied to the shift register. A method for inspecting a blanking aperture array system comprising:

10. the second voltage is a lower limit value at which a transistor included in one of the plurality of flip-flops is turned on; When the control data that causes the value held by the flip-flop of the second voltage to be 1 is supplied to the shift register, a first flip-flop that is one of the plurality of flip-flops does not operate normally, supplying the control data, which are different voltages between the first voltage and the second voltage and which are held by the flip-flops at values ​​of 1, to the shift register in sequence; determining a third voltage among the plurality of different voltages that allows the first flip-flop to operate normally and is closest to the second voltage; using a relationship between an accumulated usage time of the first flip-flop and a threshold voltage, estimating a first time until the first flip-flop stops operating normally by supplying the control data, which causes the flip-flop of the first voltage to hold a value of 1, to the shift register; Comparing the first time to a first threshold; supplying the control data to the shift register such that the value held by the flip-flop of the first voltage becomes 1 during the beam irradiation operation when the first time is not equal to or less than the first threshold value; comparing the first time with a second threshold less than the first threshold; supplying the control data, which has a fourth voltage higher than the first voltage and is held by the flip-flop with a value of 1 during the beam irradiation operation, to the shift register when the first time is not equal to or less than the second threshold value; if the first time is less than or equal to the second threshold, scheduling when the blanking aperture array system should be replaced based on the first time; scheduling production of the new blanking aperture array system based on said time period; Further, 9. The method of inspecting a blanking aperture array system according to claim 8.

11. the second period is a lower limit value at which the shift register operates normally, When a first flip-flop, which is one of the plurality of flip-flops, does not operate normally due to the clock having the second period being supplied to the shift register, supplying the clock having a plurality of different periods between the first period and the second period to the shift register in sequence; finding a third period among the plurality of different periods in which the first flip-flop operates normally and which is closest to the second period; estimating a first time until the first flip-flop stops operating normally by supplying the clock having the first period to the shift register using a relationship between an accumulated usage time of the first flip-flop and the period of the clock; performing a first comparison of comparing the first time with a first threshold value, and if the result of the first comparison indicates that the first time is not equal to or less than the first threshold value, supplying the clock having the first period to the shift register during the beam irradiation operation, and if the result of the first comparison indicates that the first time is equal to or less than the first threshold value, performing a second comparison of comparing the first time with a second threshold value that is less than the first threshold value; if the result of the second comparison indicates that the first time is not equal to or less than the second threshold, planning when the blanking aperture array system should be replaced based on the first time and scheduling production of a new blanking aperture array system based on this timing, and if the first time is equal to or less than the second threshold, supplying the clock having a fourth period longer than the first period to the shift register during the beam irradiation operation. Further, 10. The method of inspecting a blanking aperture array system according to claim 9.

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