Plasma chamber and method for cleaning chamber parts

Abstract

Embodiments provided herein generally include plasma processing systems and associated methods configured to preferentially clean a desired surface of a substrate support assembly by manipulating one or more characteristics of an in situ plasma. In one embodiment, a plasma processing method includes generating a plasma in a processing region defined by a chamber lid and a substrate support assembly, exposing an edge ring and a substrate support surface to the plasma, and establishing a pulsed voltage (PV) waveform on an edge control electrode.

Description

[Technical field]

[0001]

[0001] Embodiments herein are directed to plasma-generating gas or vapor electric space discharge devices for use in semiconductor device manufacturing, and in particular to processing chambers configured to generate a capacitively or inductively coupled plasma of gas or vapor material supplied to a chamber space and process semiconductor substrates therein. [Background technology]

[0002] Electrostatic chucks (ESCs) are commonly used in semiconductor device manufacturing processes where vacuum chucking is not feasible and mechanical clamping is undesirable, such as supporting and securing a substrate in the low pressure environment of a processing chamber. A typical ESC is formed of one or more layers of dielectric material that provide a surface (e.g., a substrate support surface) for supporting the substrate, and further includes a chucking electrode embedded in or disposed between the one or more layers of dielectric material. The substrate is secured to the ESC by applying a potential difference between the substrate and the chuck electrode, creating an electrostatic attraction force therebetween.

[0003]

[0003] The ESC is often part of an assembly configured to control aspects of a plasma-assisted process performed in a processing chamber, such as a plasma-assisted etch process in which ions bombard a material surface of the substrate through openings in a mask layer formed on the substrate surface. In a typical plasma-assisted etch process, a substrate is placed on the ESC, a plasma is formed above the substrate, and ions are accelerated from the plasma toward the substrate across a plasma sheath, i.e., an electron-depleted region formed between the plasma and the substrate surface.

[0004]

[0004] The ESC assembly may include an edge ring that is used to improve plasma processing uniformity near the edge of the substrate by reducing electrical and thermal discontinuities between the edge of the substrate and portions of the ESC assembly disposed outward from the edge of the substrate. Typically, the edge ring is disposed to surround the substrate and is sized to allow for at least some tolerance for positioning the substrate over the ESC such that an inward facing surface of the edge ring and the outer peripheral edge of the substrate define a gap region therebetween.

[0005]

[0005] Generally, processing by-products from plasma assisted processes will accumulate on chamber surfaces, including the surfaces of the ESC assembly. Conventional methods for cleaning such by-products include exposing the chamber surfaces to activated species of a cleaning gas, which may be formed using a remote plasma source and flowed into the processing chamber, or by flowing a cleaning gas into the chamber and forming an in-situ plasma. The activated species of the cleaning gas react with the processing by-products formed on the chamber surfaces to form volatile species that are exhausted from the processing chamber through the exhaust. Generally, it is best to minimize the number and / or duration of chamber cleaning processes due to the associated downtime and surface damage of chamber parts caused by repeated exposure to activated cleaning gases.

[0006]

[0006] Unfortunately, undesirable process by-products often accumulate in parts of the ESC assembly, such as the gap between the outer peripheral edge of the substrate and the inward facing portion of the edge ring, well before a chamber cleaning process is required for other processing components located there. The process by-products accumulated in the gap can be transferred to the bevel edge of the substrate and / or cause plasma instabilities that result in undesirable arcing between the substrate and the edge ring. Surface defects and / or arcing-related damage at the substrate edge due to the transferred process by-products can cause reliability issues or failures of devices formed on the substrate, thereby limiting the yield of usable devices formed on the substrate. Arcing-induced particles can also increase chamber contamination and increase chamber downtime for cleaning and maintenance, thereby reducing system availability and production capacity. Frequent use of conventional chamber cleaning methods to clean the gap of the ESC reduces system availability and production capacity, as well as potentially damaging other surfaces of the ESC, such as the substrate support surface, reducing their useful life.

[0007]

[0007] Therefore, what is needed in the art is a system and method that solves the above problems. Summary of the Invention

[0008]

[0008] The embodiments provided herein generally include a plasma processing system, and associated methods, configured to preferentially clean desired surfaces of a substrate support assembly by manipulating one or more characteristics of an in-situ plasma.

[0009]

[0009] In one embodiment, a plasma processing method includes (a) generating a plasma in a processing region defined by a chamber lid and a substrate support assembly, the substrate support assembly may include a first portion of a dielectric material forming a substrate support surface, an edge ring surrounding the substrate support surface, the edge ring may include a plasma-facing surface and one or more edge pocket surfaces disposed inwardly from the plasma-facing surface, a bias electrode spaced from the substrate support surface by the first portion of the dielectric material, and an edge control electrode spaced a distance from a center of the bias electrode, the bias electrode being electrically connected to a first pulsed voltage (PV) waveform generator configured to establish a first pulsed voltage (PV) waveform at the bias electrode, the edge control electrode being electrically connected to a second bias generator configured to establish a second pulsed voltage (PV) waveform at the edge control electrode; (b) exposing the edge ring and the substrate support surface to the plasma; and (c) simultaneously with (b), establishing a second pulsed voltage (PV) waveform at the edge control electrode.

[0010] In another embodiment, a method for plasma processing includes (a) igniting and maintaining a plasma in a processing region of a processing chamber, the plasma comprising a substrate support assembly having a first portion disposed between a substrate support surface and the chamber lid and a second portion disposed between an edge ring and the chamber lid, the substrate support assembly including a first portion of dielectric material forming the substrate support surface, and a bias electrode spaced from the substrate support surface by the first portion of dielectric material, the bias electrode being electrically connected to a first pulsed voltage (PV) waveform generator configured to establish a first pulsed voltage (PV) waveform at the bias electrode. (b) igniting and maintaining a plasma comprising an edge control electrode positioned at a distance from a center of the bias electrode, the edge control electrode being electrically connected to a second pulsed voltage (PV) waveform generator, and an edge ring surrounding the substrate support surface, the edge ring may include one or more edge pocket surfaces defining an edge pocket region with an at least partially lifted substrate disposed on the substrate support surface; (b) establishing a second pulsed voltage (PV) waveform at the edge control electrode using the second pulsed voltage (PV) waveform generator; and (c) exposing the at least partially lifted substrate to the plasma.

[0011] In another embodiment, a processing method includes (a) igniting and sustaining a plasma from a gas or vapor supplied to a processing region, the processing region being defined by a chamber lid and a substrate support assembly opposing the chamber lid, the substrate support assembly including a first portion of dielectric material forming a substrate support surface, a first electrode spaced from the substrate support surface by the first portion of dielectric material, an edge ring surrounding the substrate support surface, the edge ring having one or more edge pocket surfaces defining an edge pocket region by a peripheral edge of an at least partially elevated substrate disposed on the substrate support surface, and a second portion of dielectric material spaced from the edge ring. and (b) a second electrode positioned adjacent the first electrode, the substrate support assembly being electrically connected to a radio frequency (RF) generator providing a radio frequency (RF) signal used to ignite and maintain the plasma, the RF signal establishing a first RF waveform at the first electrode and a second RF waveform at the second electrode, the second electrode being electrically connected to an edge tuning circuit configured to adjust one or more characteristics of the second RF waveform relative to the first RF waveform to control plasma density uniformity within the processing region, the at least one characteristic of the second RF waveform being different from a characteristic of the first RF waveform.

[0012] In another embodiment, the plasma chamber includes a chamber body and a chamber lid defining a process space, and a substrate support assembly is disposed within the process space opposite the chamber lid. The substrate support assembly may include a support base and a substrate support disposed on the support base. The substrate support may include a dielectric material forming a substrate support surface, a bias electrode disposed within the dielectric material and spaced from the substrate support surface and the support base by a portion of the dielectric material, and an edge control electrode disposed at a distance from a center of the bias electrode. The chamber also includes an edge tuning circuit electrically connected to the edge control electrode and a non-transitory computer-readable medium having instructions for performing a method, which may include: a) generating a plasma from a gas or vapor supplied to the processing space by using a radio frequency (RF) signal supplied to a support base, the RF signal being supplied to the support base by an RF signal generator, the RF signal establishing a first RF waveform at the bias electrode and a second RF waveform at the edge control electrode; and b) adjusting one or more characteristics of the second RF waveform relative to the first RF waveform by using the edge tuning circuit.

[0013] Other embodiments include corresponding computer systems, apparatus, and computer programs recorded on one or more computer storage devices, each configured to perform the operations of the methods.

[0014]

[0014] It should be noted, however, that the attached drawings show only exemplary embodiments and therefore should not be considered as limiting the scope of the present disclosure, which may also allow other equally effective embodiments. It should be noted, however, that the attached drawings show only exemplary embodiments and therefore should not be considered as limiting the scope of the present disclosure, which may also allow other equally effective embodiments. [Brief description of the drawings]

[0015] [Figure 1A]1 is a schematic cross-sectional view of a processing system according to one or more embodiments configured to perform the methods described herein. [Figure 1B] 1 is a schematic cross-sectional view of a processing system according to one or more embodiments configured to perform the methods described herein. [Figure 1C]

[0016] 1B is a close-up schematic cross-sectional view of a portion of the substrate support assembly shown in FIG. 1A according to one embodiment. [Figure 1D] 1B is a close-up schematic cross-sectional view of a portion of the substrate support assembly shown in FIG. 1A according to one embodiment. [Diagram 2]

[0017] FIG. 2 is a simplified schematic diagram of a biasing and edge control scheme that can be used with one or both of the processing systems shown in FIGS. 1A-1B, according to one or more embodiments. [Figure 3A]

[0018] 1A-1B, in accordance with one or more embodiments, illustrates an exemplary edge-tuned circuit that may be used with one or both of the processing systems illustrated in FIGS. [Figure 3B] 1A-1B, in accordance with one or more embodiments, illustrates an exemplary edge-tuned circuit that may be used with one or both of the processing systems illustrated in FIGS. [Figure 3C] 1A-1B, in accordance with one or more embodiments, illustrates an exemplary edge-tuned circuit that may be used with one or both of the processing systems illustrated in FIGS. [Figure 3D]

[0019] 1A-1B are functionally equivalent circuit diagrams of different electrostatic chuck (ESC) types that can be used with one or both of the processing systems shown in FIGS. [Figure 3E] 1A-1B are functionally equivalent circuit diagrams of different electrostatic chuck (ESC) types that can be used with one or both of the processing systems shown in FIGS. [Figure 4]

[0020] 1 illustrates an example of a pulse voltage (PV) waveform that can be established using embodiments described herein. [Diagram 5]

[0021] AB show exemplary radio frequency (RF) waveforms that can be established using embodiments described herein. [Figure 6]

[0022] 11A-D are graphs of simulation results using an exemplary edge-tuned circuit configuration according to an embodiment herein. [Figure 7A]

[0023] FIG. 1 illustrates a method that can be performed using embodiments described herein. [Figure 7B] FIG. 1 illustrates a method that can be performed using embodiments described herein. [Figure 7C] FIG. 1 illustrates a method that can be performed using embodiments described herein. [Figure 8A]

[0024] 7A-7C, according to embodiments herein, are schematic cross-sectional views of an edge portion of a substrate support assembly illustrating aspects of the method described in FIGS. 7A-7C. [Figure 8B] 7A-7C, according to embodiments herein, are schematic cross-sectional views of an edge portion of a substrate support assembly illustrating aspects of the method described in FIGS. 7A-7C. [Figure 8C] 7A-7C, according to embodiments herein, are schematic cross-sectional views of an edge portion of a substrate support assembly illustrating aspects of the method described in FIGS. 7A-7C. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0016]

[0025] SUMMARY OF THE DISCLOSURE The embodiments provided herein are directed to processing systems and associated methods used in semiconductor device manufacturing processes. In particular, embodiments herein provide for cleaning portions of a substrate support assembly using a plasma formed in a processing chamber, such as an in-situ cleaning plasma. For example, in some embodiments, the systems and methods are preferentially used to clean accumulated processing by-products from portions of a substrate support assembly that define a gap region formed when a substrate is placed on the substrate support assembly. Thus, the methods described herein may be used to beneficially in-situ plasma clean the gap region surfaces of a substrate support assembly while simultaneously reducing plasma damage to and extending the useful life of other surfaces, such as the substrate support surface.

[0017]

[0026] In some embodiments, the processing system is configured for a plasma-assisted etching process in which plasma-generated ions are used to bombard a material surface of the substrate through openings formed in a patterned mask layer formed on the substrate surface. In a typical plasma-assisted etching process, the substrate is placed on a substrate receiving surface of a substrate support assembly, a plasma is formed on the substrate using radio frequency (RF) power, and ions are accelerated from the plasma across a plasma sheath toward the substrate. The plasma sheath generally exhibits nonlinear diode-like characteristics, resulting in rectification of the applied RF electric field and a DC voltage drop (i.e., self-bias) between the substrate and the plasma.

[0018]

[0027] In some embodiments, the processing system is configured to control plasma sheath characteristics using pulsed voltage (PV) waveforms provided from one or more pulsed voltage (PV) generators to bias electrodes and edge control electrodes. In some embodiments, a radio frequency (RF) generated RF waveform is provided from a radio frequency (RF) generator to one or more power electrodes in the processing chamber to establish and maintain a plasma in the processing chamber, while one or more PV waveforms provided from the one or more PV generators are configured to establish a substantially constant sheath voltage (e.g., a constant difference between the plasma potential and the substrate potential) across a surface of the substrate and a surface of a substrate support assembly adjacent thereto. The established substantially constant sheath voltage provides a desired ion energy distribution function (IEDF) at the surface of the substrate during one or more plasma processing steps performed in the processing chamber.

[0019]

[0028] Some embodiments of the present disclosure include apparatus and methods for controlling plasma uniformity, for example, by controlling electron density in the bulk plasma relative to the center of the substrate and across the peripheral edge region of the substrate and the adjacent surface of the substrate support assembly. In some embodiments, the plasma uniformity is controlled using edge tuning circuits to control one or a combination of the voltage amplitude ratio between the RF waveform established at the edge control electrode and the RF waveform established at the bias electrode (e.g., chucking electrode), the current amplitude ratio between the RF waveforms at the edge control electrode and the bias electrode, and the phase difference between the RF waveforms at each electrode.

[0020]

[0029] In some embodiments, ion energy and directionality are controlled by separately biasing the substrate and the edge ring surrounding the substrate using pulsed voltage (PV) waveforms. The PV waveforms may be established on electrodes that form part of the substrate support assembly and are located on portions of the substrate support assembly generally located below the substrate (bias electrodes) and edge ring (edge ​​control electrodes), respectively. As described below, the PV waveforms can be used to manipulate the shape of the plasma sheath boundary to focus ions accelerated across the sheath toward desired regions of the underlying surface. In some embodiments, a method for cleaning chamber components uses focused ions to target the edge of the substrate and / or the gap region between the substrate support surface and the surrounding edge ring to remove undesired processing by-products therefrom, such as polymers formed on the surface of the edge pocket region during reactive ion etching (RIE) plasma processes.

[0021]

[0030] In some embodiments, the ion flux (uniformity of plasma density) is controlled by using an edge tuning circuit to adjust one or more characteristics of the RF waveform established at the edge control electrode relative to one or more characteristics of the RF waveform established at the bias electrode. For example, the edge tuning circuit can be used to adjust the voltage amplitude ratio or current amplitude ratio between the RF waveforms established at the edge control electrode and the bias electrode. The voltage and / or current amplitude ratio can be used to adjust the distribution of plasma (plasma density) on the substrate support assembly, increasing the density of plasma on the edge ring relative to the density of plasma on the center region of the substrate support assembly, or vice versa.

[0022]

[0031] In some embodiments, an edge-tuned circuit is used to provide a desired phase difference between the RF waveforms established at the bias electrode and the edge control electrode. Adjusting the phase difference can amplify the electric field generated between the two electrodes. The electric field amplification can be manipulated to enhance the concentration of ions and reactive neutral species in the gap region located between the edge of the substrate and the inward facing surface of the edge ring. In some embodiments, the phase difference between the RF waveforms is controlled to concentrate the plasma between the bias electrode and the edge control electrode, thus concentrating the plasma in the gap region.

[0023]

[0032] In some embodiments, a pulsed voltage (PV) waveform and / or edge tuned circuitry is used alone or in combination with a substrate dechucking method to preferentially clean the gap region while simultaneously protecting the dielectric substrate support surface from ion-induced damage. For example, in some embodiments, the method includes focusing ions toward the gap region and / or concentrating a plasma in the gap region while the substrate is partially lifted off the substrate support surface.

[0024]

[0033] Beneficially, the present apparatus and methods, alone or in combination, provide individual process tuning knobs for controlling ion energy and directionality uniformity, which may be used to individually control the ion flux and / or reactive neutral species uniformity across the surface of the substrate support assembly and / or the substrate disposed thereon. For example, in some embodiments, the ion energy and directionality uniformity may be controlled by adjusting the PV waveforms established at the edge control electrodes and bias electrodes, respectively, to control the thickness profile of the plasma sheath and the shape of the sheath boundary (between the plasma sheath and the plasma) formed over the gap region of the substrate support assembly. The ion flux and / or reactive neutral species concentration uniformity may be individually controlled by adjusting the RF waveforms established at the respective electrodes. Thus, the apparatus and methods described herein facilitate target cleaning of the gap region of the substrate support assembly by controlling the ion energy, ion directionality, and / or ion and reactive neutral species concentration. An exemplary processing system that may be used to perform the present methods is shown in FIGS. 1A-1D.

[0025] Plasma Processing System Examples

[0034] Figures 1A and 1B are schematic cross-sectional views of processing systems 10A and 10B, respectively, each configured to perform one or more of the plasma processing methods set forth herein. Figure 1C is a close-up view of a portion of the substrate support assembly 136 shown in Figure 1A. Figure 2 is a simplified schematic diagram of a processing scheme that may be used with one or both of the processing systems 10A and 10B. Figures 3A-3B are examples of edge tuning circuits 170 that may be used with one or both of the processing systems 10A and 10B to control and adjust plasma uniformity.

[0026]

[0035] 1A and 1B are configured for a plasma-assisted etch process, such as a reactive ion etch (RIE) plasma process. However, it should be noted that the embodiments described herein may also be used with processing systems configured for use in other plasma-assisted processes, such as plasma deposition processes, e.g., plasma-enhanced chemical vapor deposition (PECVD) processes, plasma-enhanced physical vapor deposition (PEPVD) processes, plasma-enhanced atomic layer deposition (PEALD) processes, plasma treatment processes, or plasma-based ion implantation processes (e.g., plasma doping (PLAD) processes).

[0027]

[0036] As shown in FIGS. 1A-1B, processing systems 10A-10B are configured to form a capacitively coupled plasma (CCP), and a processing chamber 100 includes an upper electrode (e.g., chamber lid 123) disposed within a processing volume 129 facing a lower electrode (e.g., substrate support assembly 136) disposed within the processing volume 129. In a typical capacitively coupled plasma (CCP) processing system, a radio frequency (RF) source (e.g., RF generator 118) is electrically connected to one of the upper or lower electrodes and provides an RF signal configured to ignite and sustain a plasma (e.g., plasma 101), which is capacitively coupled to each of the upper and lower electrodes and disposed in a processing region therebetween. Typically, the opposing one of the upper or lower electrodes is connected to ground or a second RF power source. 1A-1B, one or more components of the substrate support assembly 136, such as the support base 107, are electrically connected to a plasma generator assembly 163 that includes an RF generator 118, and the chamber lid 123 is electrically connected to ground.

[0028]

[0037] 1A-1B, each of processing systems 10A and 10B includes a processing chamber 100, a substrate support assembly 136, a system controller 126, and a plasma control scheme 188. In the embodiments described herein, it is contemplated that any one or combination of the features, configurations, and / or structural components of processing system 10A, such as the structural components of the substrate support assembly 136 and / or the electrical components of the plasma control scheme 188, may be used in processing system 10B, and vice versa.

[0029]

[0038] The processing chamber 100 typically includes a chamber body 113 including a chamber lid 123, one or more sidewalls 122, and a chamber base 124, which collectively define a processing space 129. The one or more sidewalls 122 and the chamber base 124 generally comprise a material sized and shaped to provide structural support for the elements of the processing chamber 100 and configured to withstand pressure and additional energy applied thereto. Meanwhile, the plasma 101 is generated within a vacuum environment that is maintained within the processing space 129 of the processing chamber 100 during processing. In one embodiment, the one or more sidewalls 122 and the chamber base 124 are formed from a metal, such as aluminum, an aluminum alloy, or a stainless steel alloy.

[0030]

[0039] A gas inlet 128 disposed through the chamber lid 123 is used to supply one or more process gases to the process space 129 from a process gas source 119 in fluid communication therewith. In some embodiments, the gases are supplied through a showerhead (not shown). In other embodiments, the gases are supplied through the sidewalls 122 (not shown). The substrate 103 is transferred into and out of the process space 129 through an opening (not shown) in one of the one or more sidewalls 122, which opening is sealed with a slit valve (not shown) during plasma processing of the substrate 103.

[0031]

[0040] In some embodiments, a plurality of lift pins 20 movably disposed through openings formed in the substrate support assembly 136 facilitate the transfer of substrates to and from the substrate support surface 105A. In some embodiments, the plurality of lift pins 20 are disposed above and connected to and / or engageable with a lift pin hoop (not shown) disposed within the processing space 129. The lift pin hoop may be connected to a shaft (not shown) that sealingly extends through the chamber base 124. The shaft may be connected to an actuator (not shown) that is used to raise and lower the lift pin hoop. When the lift pin hoop is in a raised position, it engages the plurality of lift pins 20 to raise the upper surface of the lift pins above the substrate support surface 105A and lift the substrate 103 therefrom, allowing access to the inactive (backside) surface of the substrate 103 by a robotic handler (not shown). When the lift pin hoop is in the lowered position, the plurality of lift pins 20 are flush with or recessed below the substrate support surface 105A, and the substrate 103 rests thereon.

[0032]

[0041] The system controller 126, also referred to herein as a process chamber controller, includes a central processing unit (CPU) 133, a memory 134, and support circuits 135. The system controller 126 is used to control the process sequence used to process the substrate 103, including the substrate bias method described herein. The CPU 133 is a general-purpose computer processor configured for use in an industrial setting to control the process chamber and sub-processors associated with the process chamber. The memory 134 described herein is generally non-volatile memory and may include random access memory, read-only memory, floppy or hard disk drives, or other suitable forms of digital storage (local or remote). The support circuits 135 are conventionally connected to the CPU 133 and include caches, clock circuits, input / output subsystems, power supplies, etc., and combinations thereof. Software instructions (programs) and data may be encoded and stored in the memory 134 for instructing the processor in the CPU 133. Software programs (or computer instructions) readable by CPU 133 within system controller 126 specify which operations are executable by components within processing systems 10A and / or 10B.

[0033]

[0042] Typically, a program is readable by the CPU 133 in the system controller 126 and includes code that, when executed by the processor (CPU 133), performs operations associated with the plasma processing schemes described herein. The program may include instructions that are used to control various hardware and electrical components in the processing systems 10A and / or 10B to thereby perform various process operations and various process sequences used to implement the methods described herein. In one embodiment, the program includes instructions that are used to perform one or more of the operations described below in connection with Figures 7 and 8A-8C.

[0034]

[0043] 1A-1B generally includes a plasma generator assembly 163, a first bias generator 196 for establishing a first PV waveform at the bias electrode 104, and a second bias generator 197 for establishing a second PV waveform at the edge control electrode 115. In some embodiments, the plasma generator assembly 163 provides an RF signal to the support base 107 (e.g., a powered electrode or cathode), which may be used to generate (maintain and / or ignite) the plasma 101 in a processing region disposed between the substrate support assembly 136 and the chamber lid 123. In some embodiments, the RF generator 118 is configured to provide an RF signal having a frequency greater than 400 kHz, such as an RF frequency of about 1 MHz or greater, or about 2 MHz or greater, e.g., about 13.56 MHz or greater, about 27 MHz or greater, or about 40 MHz or greater.

[0035]

[0044] In some embodiments, the plasma control scheme 188 further includes an edge tuning circuit 170 that may be used to adjust one or more characteristics of the plasma 101 formed between the substrate support assembly 136 and the chamber lid 123. In some embodiments, the edge tuning circuit 170 may be used to adjust the density of a portion of the plasma 101 formed on a peripheral edge of a substrate 103 disposed on the substrate support assembly 136 relative to the density of a portion of the plasma 101 formed on a central surface of the substrate 103.

[0036]

[0045] Generally, as used herein, plasma density refers to the number of free electrons in the bulk plasma per unit volume (e.g., number of free electrons / cm 3 ), which in some embodiments refers to about 10 8 cm -3 ~about 10 11 cm -3The edge tuning circuit 170 allows manipulation of one or more characteristics of the RF power used to maintain the plasma 101 in a region on the edge of the substrate support assembly 136 relative to the RF power used to maintain the plasma 101 in a region on a central portion of the substrate support assembly 136. For example, the edge tuning circuit 170 may be used to adjust one or more of the voltage, current, and / or phase of the RF power at the edge of the substrate support assembly 136 relative to the RF power in the central region 103A of the substrate support assembly 136.

[0037]

[0046] As described further below, the edge tuning circuit 170 may be electrically connected to the edge control electrode 115 disposed on the substrate support assembly 136. In some embodiments, an RF signal used to ignite and / or sustain the plasma 101 is provided from the plasma generator assembly 163 to the support base 107, which is capacitively coupled to the edge control electrode 115 through a layer of dielectric material disposed therebetween. The edge tuning circuit 170 may be used to adjust one or more characteristics of the RF power used to sustain the plasma in the region above the edge control electrode 115, for example, by adjusting the voltage, current, and / or phase of the RF power at the edge control electrode 115 relative to the RF power provided to the support base 107.

[0038]

[0047] In some embodiments, the difference between the voltage, current, and / or phase of the RF power used to ignite and / or maintain a plasma in the region over the edge control electrode 115 and the bias electrode 104 is determined and / or monitored by measuring or determining the respective voltage, current, and / or phase of the RF power at the edge control electrode 115 and / or the bias electrode 104. In some embodiments, one or more characteristics of the RF power at the edge control electrode 115 and / or the bias electrode 104 are measured and / or determined using a signal detection module 187, described below.

[0039]

[0048] As described above, in some embodiments, the plasma generator assembly 163, including the RF generator 118 and the RF generator assembly 160, is generally configured to supply a desired amount of continuous wave (CW) or pulsed RF power at a desired substantially fixed sinusoidal waveform frequency to the support base 107 of the substrate support assembly 136 based on control signals provided from the system controller 126. During processing, the plasma generator assembly 163 is configured to supply RF power (e.g., an RF signal) to the support base 107 proximate to the substrate support 105 and disposed within the substrate support assembly 136. The RF power supplied to the support base 107 is configured to ignite and maintain a processing plasma 101 of a processing gas disposed within the process space 129.

[0040]

[0049] In some embodiments, the support base 107 is an RF electrode electrically connected to the RF generator 118 via an RF matching circuit 162 and a first filter assembly 161, both of which are disposed within the RF generator assembly 160. The first filter assembly 161 includes one or more electrical elements configured to substantially prevent current generated by the output of the PV waveform generator 150 from flowing through the RF power supply line 167 and damaging the RF generator 118. The first filter assembly 161 acts as a high impedance (e.g., high Z) to the PV signal generated from the PV pulse generator P1 in the PV waveform generator 150, suppressing the flow of current to the RF matching circuit 162 and the RF generator 118.

[0041]

[0050] In some embodiments, the RF generator assembly 160 and the RF generator 118 are used to ignite and sustain the processing plasma 101 using an electric field generated by the processing gas disposed in the processing space 129 and RF power (RF signal) provided by the RF generator 118 to the support base 107. The processing space 129 is in fluid communication with one or more dedicated vacuum pumps through a vacuum outlet 120. The one or more dedicated vacuum pumps maintain the processing space 129 at sub-atmospheric pressure and evacuate the processing gas and / or other gases from the processing space 129. In some embodiments, the substrate support assembly 136 disposed in the processing space 129 is grounded and disposed on a support shaft 138 that extends through the chamber base 124. However, in some embodiments, the RF generator assembly 160 is configured to provide RF power to a bias electrode 104 disposed in the substrate support 105 relative to the support base 107.

[0042]

[0051] In some embodiments, the edge tuning circuit 170 is used to control and / or adjust one or more characteristics of an RF waveform established on the edge control electrode 115 (e.g., the second RF waveform 502 illustrated in FIG. 5 ) relative to one or more characteristics of an RF waveform established on the bias electrode 104 (e.g., the first RF waveform 501 illustrated in FIG. 5 ). In some embodiments, such as shown in FIGS. 1A and 2 , the edge tuning circuit 170 is electrically connected between the edge control electrode 115 and ground. In other embodiments, such as shown in FIG. 1B and shown by the dotted line in FIG. 2 , the edge tuning circuit 170 can be electrically connected between the edge control electrode 115 and the plasma generator assembly 163, which in turn is electrically connected between the edge control electrode 115 and the support base 107.

[0043]

[0052] As briefly described above, the substrate support assembly 136 generally includes a substrate support 105 (e.g., an ESC substrate support) and a support base 107. In some embodiments, the substrate support assembly 136 may further include an insulator plate 111 and a ground plate 112, which are described further below. The support base 107 is electrically isolated from the chamber base 124 by the insulator plate 111, and the ground plate 112 is interposed between the insulator plate 111 and the chamber base 124. The substrate support 105 is thermally coupled to and disposed on the support base 107. In some embodiments, the support base 107 is configured to regulate the temperature of the substrate support 105 and the substrate 103 disposed on the substrate support 105 during substrate processing.

[0044]

[0053] In some embodiments, the support base 107 includes one or more cooling channels (not shown) disposed therein. The one or more cooling channels are fluidly connected to a coolant source (not shown), such as a coolant source or water source having a relatively high electrical resistance. In some embodiments, the substrate support 105 includes a heater (not shown), such as a resistive heating element embedded within the dielectric material of the substrate support 105. Here, the support base 107 is formed of a corrosion-resistant, heat-conducting material, such as a corrosion-resistant metal (e.g., aluminum, an aluminum alloy, or stainless steel), and is connected to the substrate support by adhesive or mechanical means.

[0045]

[0054] Typically, the substrate support 105 is made of a dielectric material, such as a bulk sintered ceramic material (a corrosion resistant metal oxide or metal nitride material, such as aluminum oxide (Al 2 O 3 ), aluminum nitride (AlN), titanium oxide (TiO), titanium nitride (TiN), yttrium oxide (Y 2 O 3), a mixture thereof, or a combination thereof, etc. In embodiments herein, the substrate support 105 further includes a bias electrode 104 embedded in its dielectric material. In some embodiments, one or more characteristics of the RF power used to maintain the plasma 101 in the processing region above the bias electrode 104 are determined and / or monitored by measuring an RF waveform (e.g., first RF waveform 501 of FIG. 5) established at the bias electrode 104. Typically, the first RF waveform 501 is established by providing an RF signal from the plasma generator assembly 163 to the substrate support 105, which is capacitively coupled to the bias electrode 104 through a dielectric material layer 105C (FIG. 1C) disposed therebetween.

[0046]

[0055] In one configuration, the bias electrode 104 is a chucking pole that is used to secure (i.e., chuck or electrostatically clamp) the substrate 103 to the substrate support surface 105A of the substrate support 105 and bias the substrate 103 against the processing plasma 101 using one or more of the pulsed voltage biasing schemes described herein. Typically, the bias electrode 104 is formed of one or more conductive components, such as one or more metal meshes, foils, plates, or combinations thereof.

[0047]

[0056] In some embodiments, the bias electrode 104 is electrically connected to a clamping network 116. The clamping network 116 supplies a chucking voltage, such as a static DC voltage between about -5000V and about 5000V, to the bias electrode 104 using an electrical conductor, such as a coaxial power supply line 106 (e.g., a coaxial cable). As discussed further below, the clamping network 116 includes a bias compensation circuit element 116A, a DC power supply 155, and a bias compensation module blocking capacitor. The bias compensation module blocking capacitor is referred to herein as a blocking capacitor C. 5 Also called blocking capacitor C 5is disposed between the output of the pulse voltage (PV) waveform generator 150 and the bias electrode 104.

[0048]

[0057] 1A and 1B, the substrate support assembly 136 may further include an edge control electrode 115. The edge control electrode 115 is disposed below the edge ring 114, surrounding the bias electrode 104, and / or spaced apart from the center of the bias electrode 104. Generally, in a processing chamber 100 configured to process a circuit board, the edge control electrode 115 is ring-shaped, made of a conductive material, and configured to surround at least a portion of the bias electrode 104. In some embodiments, as shown in FIG. 1A, the edge control electrode 115 is disposed within the region of the substrate support 105. In some embodiments, as shown in FIG. 1A, the edge control electrode 115 includes a conductive mesh, foil, and / or plate disposed at a similar distance (i.e., in the Z direction) from the edge ring 114 as the bias electrode 104 from the substrate support surface 105A of the substrate support 105. In some other embodiments, such as that shown in FIG. 1B, the edge control electrode 115 includes a conductive mesh, foil, and / or plate disposed on or within the region of the dielectric tube 110. The dielectric tube 110 surrounds at least a portion of the bias electrode 104 and / or the substrate support 105. The dielectric tube 110 can be made of various insulators, such as aluminum oxide, aluminum nitride, quartz, etc. In some embodiments, the dielectric tube 110 can include several parts made of the same or different materials. Alternatively, in some other embodiments (not shown), the edge control electrode 115 is disposed within or connected to an edge ring 114 that is disposed adjacent to the substrate support 105.

[0049]

[0058] FIG. 1D is a close-up view of a portion of the substrate support assembly 136 shown in FIG. 1A. As shown, an edge ring 114 is disposed on the substrate support 105 and surrounds the substrate 103. The edge ring 114 may be used to protect the edge of the substrate support 105 and, in some cases, minimize electrical and / or thermal discontinuities formed at the substrate and substrate support edge. The edge ring 114 includes one or more inner surfaces 114A that face a portion of the substrate support 105 and a peripheral (beveled) edge of the substrate 103 disposed thereon. The inner surface 114A of the edge ring 114 is spaced apart from the substrate support 105 and the substrate 103 disposed thereon, defines one or more gaps 117A-B, and may include a ledge portion 114B that is disposed under the beveled substrate edge when the substrate 103 is disposed on the substrate support 105.

[0050]

[0059] In a typical etching process, the upper plasma-facing surface of the edge ring 114 (e.g., surface 114C) is bombarded with ions during processing, resulting in ion-induced erosion of the dielectric material forming the edge ring 114. Unfortunately, the surfaces of the edge ring 114 that define the gap regions 117A-B are less exposed to the plasma 101 and therefore tend to accumulate process etch by-products that, unless removed, can cause undesirable plasma arcing and / or particle transfer between the edge ring 114 and the surface of the substrate 103. Thus, in some embodiments, bias and plasma control methods used to improve process uniformity at the substrate edge may also be used to preferentially clean the surfaces that define the edge pocket regions 117.

[0051]

[0060] As described below, the edge ring 114 can be energized using a pulsed voltage (PV) waveform to control the shape of the plasma sheath boundary 11 that extends beyond the substrate edge and the edge ring 114 to span the edge pocket region 117. The shape of the plasma sheath boundary 11 affects the energy and directionality of ions accelerated across the plasma sheath. For example, as described below and shown in FIGS. 9A-9C, a height difference between a portion (portion 11A) of the sheath boundary 11 formed on the substrate 103 and a portion (portion 11C) of the sheath boundary formed on the edge ring 114 will cause the sheath boundary to bend at a portion (bend 11B) of the sheath boundary that spans the edge pocket region 117. The change in sheath thickness and sheath boundary bending will affect the ion energy and ion directionality of ions impinging on the surfaces of the substrate 103 and the edge ring 114 disposed thereunder, respectively. Thus, control over the plasma sheath boundary 11 across the edge pocket region 117 allows for tailoring of ion energy and ion directionality at the surface of the substrate edge region 103B, which may be used to improve substrate processing uniformity. Improved control over the plasma sheath boundary 11 may also be used to perform the in situ plasma cleaning methods described herein to target the surface 114A-B of the edge ring 114 to clean undesired processing by-products therefrom.

[0052]

[0061] The edge control electrode 115 is generally positioned such that when used with the edge tuning circuit 170 and / or when energized using the pulsed bias scheme 140 (FIGS. 1A-1B), its position relative to the substrate 103 can affect or modify the portion of the generated plasma 101 that is on or outside the peripheral edge of the substrate 103. In some embodiments, the bias generators 196, 197 can be used to control the shape of the sheath boundary 11 on the plasma-facing surface of the substrate support assembly 136. For example, due to repeated ion bombardment, the edge ring 114 typically undergoes plasma-based erosion, reducing the thickness of the edge ring over its useful life. If the thickness of the plasma sheath formed on the edge ring 114 remained the same, the wear of the edge ring 114 would eventually result in bending of the plasma sheath boundary, causing non-uniform processing results at the substrate edge. Thus, in some embodiments, one or more characteristics of the pulse voltage (PV) waveform established by the bias electrode 104 and / or the edge control electrode 115 may be adjusted to compensate for changes in the height of the edge ring 114 over the life of the edge ring in order to maintain a substantially uniform sheath boundary 11 across the edge of the substrate 103.

[0053]

[0062] In some embodiments, an edge tuning circuit 170 electrically connected to the edge control electrode 115 may be used to manipulate one or more characteristics of the RF power used to ignite and / or maintain a plasma in the processing region 129A above the edge control electrode 115. For example, in some embodiments, the edge tuning circuit 170 may be used to adjust and / or manipulate one or more of the voltage, current, and / or phase of the RF power used to ignite and / or maintain a plasma 101 in the processing region disposed between the edge control electrode 115 and the chamber lid 123.

[0054]

[0063] In some embodiments, one or more characteristics of the RF power used to maintain the plasma 101 in the processing region above the edge control electrode 115 are determined and / or monitored by measuring one or more differences between the second RF waveform 502 and the first RF waveform 501 established at the edge control electrode 115 and the bias electrode 104, respectively. In some embodiments, the difference in one or more characteristics of the second RF waveform 502 and the first RF waveform 501 can be manipulated by using the edge tuning circuit 170 to adjust the plasma density in a region on the circumferential edge of the substrate 103 and / or across the edge pocket region 117.

[0055]

[0064] In some embodiments, the difference in characteristics between the second RF waveform 502 and the first RF waveform 501 can be used to preferentially form a plasma between the edge ring 114 and the edge of the substrate 103 and effectively concentrate the plasma in the edge pocket region 117 to remove undesirable processing by-products from the surface therein. Thus, the edge tuning circuit 170 is advantageously used to control the generation of active species in the bulk plasma, thereby enabling fine control of the flux of ions and / or radicals at the edge (edge ​​region 103B) of the substrate 103 relative to the central region 103A of the substrate 103, and / or the concentration of plasma in the edge pocket region 117.

[0056]

[0065] The edge control electrode 115 may be energized using a PV waveform generator 150 that is different from the PV waveform generator 150 used to energize the bias electrode 104. In some embodiments, the edge control electrode 115 may be energized using a PV waveform generator 150 that is also used to energize the bias electrode 104 by splitting a portion of the power to the edge control electrode 115. In one configuration, a first PV waveform generator 150 of the first bias generator 196 is configured to energize the bias electrode 104 and a second PV waveform generator 150 of the bias generator 197 is configured to energize the edge control electrode 115.

[0057]

[0066] In some embodiments, one or more characteristics of the generated RF power are measured and / or determined using a signal detection module 187 communicatively connected to the system controller 126. The signal detection module 187 is generally configured to receive electrical signals from electrical signal traces (not shown) electrically connected to various components, such as nodes N, within the processing systems 10A and 10B. The signal detection module 187 may include a number of input channels 172, each configured to receive an electrical signal from a corresponding electrical signal trace, and a data acquisition module 169. The received electrical signals may include, but are not limited to, one or more characteristics of an RF signal provided to the support base 107, an RF waveform established on one or both of the bias electrode 104 and the edge control electrode 115, a pulse voltage (PV) waveform established on one or both of the bias electrode 104 and the edge control electrode 115, and a chucking voltage provided to one or both of the bias electrode 104 and the edge control electrode 115.

[0058]

[0067] In some embodiments, the data acquisition module 169 is configured to generate control signals that are used to automatically control one or more characteristics of the RF signal, RF waveform, PV waveform, and / or chucking voltage during substrate processing. In some embodiments, a desired change in one or more characteristics is communicated by the system controller 126 to the signal detection module 187, and the data acquisition module 169 can be used to implement the desired change.

[0059]

[0068] 1A and 1B, the second bias generator 197 includes a clamping network 116 such that the bias applied to the edge control electrode 115 can be configured similarly to the bias applied to the bias electrode 104 by the clamping network 116 connected within the first bias generator 196.

[0060]

[0069] In some embodiments, the processing chamber 100 further includes a dielectric tube 110, or collar, that at least partially surrounds a portion of the substrate support assembly 136 as a dielectric barrier between the RF high temperature substrate support assembly 136 and the grounded liner 108 and prevents the substrate support 105 and / or the support base 107 from contacting the corrosive process gases or plasma, cleaning gases or plasma, or by-products thereof. Typically, the liner 108 circumscribes the dielectric tube 110, the insulator plate 111, and the grounded plate 112. In some embodiments, a plasma screen 109 is disposed between the cathode liner 108 and the sidewall 122 to prevent plasma generation in the space below the plasma screen 109 between the liner 108 and the one or more sidewalls 122.

[0061] Substrate Support Assembly Configuration

[0070] FIG. 1C is a close-up view of a portion of the substrate support assembly 136 shown in FIG. 1A, including a simplified electrical schematic diagram of the electrical properties of various structural elements within one or more embodiments of the substrate support assembly 136. The simplified electrical schematic diagram shown in FIG. 1C is equally applicable to the corresponding structural elements of the substrate support assembly 136 depicted in FIG. 1B. Here, the substrate support assembly 136 is configured as an electrostatic chuck (ESC), which can be either a Coulombic type ESC or a Johnsen-Rahbek type ESC. Simplified equivalent circuit models 191 of the Coulombic type ESC and the Johnsen-Rahbek type ESC are shown in FIG. 3D and FIG. 3E, respectively, and are described below. Generally, in any ESC configuration of the substrate support assembly 136, the substrate 103 is fixed to the substrate support 105 by applying an electric potential between the substrate 103 and the bias electrode 104, resulting in an electrostatic attractive force therebetween. In one embodiment, the bias electrode 104 is also used to facilitate the pulsed voltage (PV) waveform biasing schemes described herein.

[0062]

[0071] The substrate support 105 is formed of a dielectric material and provides a substrate support surface 105A including a bias electrode 104 embedded in the dielectric material. The bias electrode 104 is spaced from the substrate support surface 105A, and thus the substrate 103, by a first dielectric material layer 105B, and from the support base 107 by a second dielectric material layer 105C.

[0063]

[0072] In some embodiments, the ESC arrangement may be used to secure the substrate 103 to the substrate support 105 in a relatively low pressure (e.g., ultra-high vacuum) processing environment. In some embodiments, it may be desirable to heat and / or cool the substrate 103 during processing to maintain the substrate at a desired processing temperature. In these embodiments, the substrate support assembly 136 may be configured to maintain the substrate 103 at a desired temperature by heating or cooling the substrate support 105 and, therefore, the substrate 103 disposed thereon. Often, in these embodiments, the substrate support surface 105A is patterned to have a raised portion (e.g., a mesa) that contacts the substrate 103 and a recess that defines a backside space 105D with the substrate 103. During substrate processing, a gas source 173 fluidly coupled to the substrate support assembly 136 may be used to supply an inert gas, such as helium, to the backside space 105D to enhance heat transfer between the substrate support surface 105A and the substrate 103 disposed thereon. In some embodiments, the gas source 173 is used to supply an inert gas to a region disposed between the edge ring 114 and a surface of the substrate support assembly 136 disposed therebelow.

[0064]

[0073] The bias electrode 104 is electrically connected to a DC power supply 155 (described above in FIGS. 1A-1B), which is configured to provide a potential between the substrate 103 and the bias electrode 104, thereby generating an electrostatic attraction force (chucking force) therebetween. The substrate support assembly 136 may be configured as either a Coulomb type ESC or a Johnsen-Rahbek type ESC. A Johnsen-Rahbek type ESC may provide a higher chucking force and use a lower chucking voltage compared to a Coulomb type ESC. In a Coulomb type ESC, the dielectric material selected for the first dielectric material layer 105B will typically have a higher electrical resistance than the dielectric material selected for a Johnsen-Rahbek type ESC. This results in differences in the simplified functional equivalent circuit models 191 shown in FIGS. 3D and 3E, respectively.

[0065]

[0074] In the simplest case (e.g., the circuit model 191 of the Coulomb-type ESC shown in FIG. 3D), the first dielectric layer 105B is a dielectric material assumed to act as an insulator (e.g., infinite resistance R JR Thus, a functionally equivalent circuit model 191 is formed with a direct capacitance C between the bias electrode 104 and the substrate 103 via the first dielectric layer 105B. 1 In some embodiments of the Coulomb-type ESC, the dielectric material and thickness T of the first dielectric material layer 105B are DL1 is the capacity C 1 is selected to be between about 5 nF and about 100 nF, for example, between about 7 nF and about 20 nF. For example, the dielectric material layer 105B may be a ceramic material (e.g., aluminum oxide (Al 2 O 3 ) and having a thickness T between about 0.1 mm and about 1 mm, for example, between about 0.1 mm and about 0.5 mm, for example, about 0.3 mm. DL1 may have.

[0066]

[0075] In more complicated cases, such as the circuit model 191 of a Johnsen-Rahbek type ESC shown in FIG. 3E, the circuit model 191 has a dielectric material resistance R JRand gap capacitance C JR and capacitance C connected in parallel 1 Typically, in a Johnsen-Rahbek type ESC, the dielectric material layer 105B is considered "leaky" in the sense that it is not a perfect insulator and has some conductivity. For example, the dielectric material can be doped aluminum nitride (AlN) with a dielectric constant (ε) of about 9. Similar to the circuit model 191 of the Coulomb type ESC shown in FIG. 3D, there is a direct capacitance C between the bias electrode 104 and the substrate 103 through the dielectric material layer 105B and the backside space 105D filled with helium. 1 The volume resistivity of the dielectric layer in a Johnsen-Rahbek type ESC is about 10 12 Less than ohm cm (Ω cm), or about 10 10 Less than Ω cm, even 10 8 Ω cm and 10 12 Therefore, the dielectric material layer 105B is in the range of 10 6 Omega and 10 11 Dielectric material resistance R in the range between Ω JR In the model 191 of FIG. 3E, a gap volume C is added to account for the gas-containing backside space 105D between the substrate 103 and the substrate support surface 105A. JR is used. The gap capacitance C JR is the capacity C 1 It is expected to have a slightly larger capacity than

[0067]

[0076] Returning to FIG. 1C, an electrical schematic diagram of the circuit formed within the substrate support assembly 136 is shown with the support base dielectric layer capacitance C 2 , which represents the capacitance of the second dielectric material layer 105C. In some embodiments, the thickness of the portion of the second dielectric material layer 105C is greater than the thickness of the first dielectric material layer 105B. In some embodiments, the dielectric material used to form the dielectric layers on either side of the bias electrode is the same material and forms the structural body of the substrate support 105. In one example, the capacitance of the second dielectric material layer 105C (e.g., Al) measured in a direction extending between the support base 107 and the bias electrode 104 is 2 O3 The thickness of the support base dielectric layer (e.g., AlN) is greater than 1 mm, such as having a thickness between about 1.5 mm and about 100 mm. 2 Typically, the capacitance is between about 0.5 nanofarads (nF) and about 10 nF.

[0068]

[0077] As shown in FIG. 1C, an electrical schematic of the circuit formed within the substrate support assembly 136 also includes a support base resistor R P , insulator plate capacitance C 3 , and a ground plate resistor R connected to ground at one end G The support base 107 and the ground plate 112 are typically made of a metallic material, so that the support base resistance R P and the ground plate resistance R G is very low, less than a few milliohms. 3 denotes the capacitance of the dielectric layer located between the bottom surface of the support base 107 and the top surface of the ground plate 112. In one example, the insulator plate capacitance C 3 has a capacitance between about 0.1 nF and about 1 nF.

[0069] Bias and Edge Control Scheme

[0078] Figure 2 is a simplified schematic diagram of a bias and edge control scheme that may be used with one or both of the processing systems 10A-10B shown in Figures 1A and 1B. As shown in Figure 2, the RF generator 118 and the PV waveform generator 150 are configured to supply RF and pulsed voltage waveforms, respectively, to one or more electrodes disposed within the process space 129 of the process chamber 100. In one embodiment, the RF generator 118 and the PV waveform generator 150 are configured to simultaneously supply RF and pulsed voltage waveforms to one or more electrodes disposed within the substrate support assembly 136.

[0070]

[0079] As described above, the edge-tuned circuit 170 is generally configured to control the uniformity of the plasma formed between the chamber lid 123 and the substrate support assembly 136, for example, by controlling the plasma density (i.e., the free electron density in the bulk plasma) across the peripheral edge of the substrate 103. In some embodiments, as shown in Figures 1A and 2, the edge-tuned circuit 170 is electrically connected between the edge control electrode 115 (edge ​​bias electrode) and ground. In other embodiments, as shown by the dotted lines in Figures 1B and 2, the edge-tuned circuit 170 is electrically connected between the edge control electrode 115 and the plasma generator assembly 163, for example, between the edge control electrode 115 and the RF generator 118.

[0071]

[0080] In some embodiments, the edge-tuned circuit 170 is configured as a resonant circuit including an inductor and a capacitor (e.g., an LC circuit) that may be used to adjust the voltage, current, and / or phase of the RF power used to maintain the plasma in the region above the edge control electrode. Exemplary electrical circuits 170a, 170b, 170c that may be used as the edge-tuned circuit 170 in any one of the embodiments described herein are illustrated in FIGS. 3A-3C. As illustrated, the edge-tuned circuits 170a, 170b are each electrically connected between the power supply line 158 and ground (i.e., between the edge control electrode 115 and ground). However, it is contemplated that each of the exemplary edge-tuned circuits 170a, 170b may also be electrically connected between the power supply line 158 and the plasma generator assembly 163 (i.e., between the edge control electrode 115 and the RF generator 118) as illustrated in FIG. 1B. In some other embodiments, the edge tuned circuit 170 may be simultaneously electrically connected to the power supply line 158, the plasma generator assembly 163, and ground, as shown for the example edge tuned circuit 170c in FIG. 3C.

[0072]

[0081] In one embodiment shown in FIG. 3A, the edge-tuned circuit 170a includes an inductor L 2 and the variable capacitor C 7In another embodiment shown in FIG. 3B, the edge-tuned circuit 170b includes an inductor L 2 and the variable capacitor C 7 In another embodiment shown in FIG. 3C, the edge tuning circuit 170c includes an inductor L 2 and the variable capacitor C 8 (i.e., a series LC resonant circuit) and an inductor L 2 and variable capacitor C 8 and a second variable capacitor C connected to a node disposed between the 7 Includes.

[0073]

[0082] In some embodiments, the variable capacitor C 7 , C 8 One or both of may be adjustable from at least about 50 pF to at least about 200 pF, such as from at least about 20 pF to at least about 250 pF.

[0074]

[0083] The type of LC resonant circuit selected for the edge tuned circuit 170, e.g., parallel, series, or other configuration, may depend on the mechanical dimensions of the substrate support assembly 136 and the resulting electrical connections between conductive components or electrodes, such as the edge ring 114, the edge control electrode 115, the support base 107, the bias electrode 104, the substrate 103, and the ground plate 112.

[0075]

[0084] In some embodiments, the type of LC resonant circuit may be selected based on a desired ability to control the plasma density distribution, which may be achieved by adjusting one or more parameters of the LC resonant circuit such that one or more characteristics of the second RF waveform 502 (FIGS. 5A-5B) established by the edge control electrode 115 may be adjusted relative to one or more characteristics of the first RF waveform 501 established by the bias electrode 104. Simulation results of various control characteristics achievable for an exemplary edge tuned circuit 170 are described below in FIGs. 6A-6D.

[0076]

[0085] 2, by way of a non-limiting example, the RF generator 118 and the PV waveform generator 150 are configured to supply an RF waveform and a pulsed voltage waveform, respectively, to the support base 107 and the bias electrode 104 disposed on the substrate support assembly 136. In another embodiment, the RF generator 118, the first PV waveform generator 150, and the second PV waveform generator 150 are configured to supply an RF waveform, a first pulsed voltage waveform, and a second pulsed voltage waveform, respectively, to the support base 107, the bias electrode 104, and the edge control electrode 115 disposed on the substrate support assembly 136.

[0077]

[0086] 2, the RF generator 118 is configured to provide an RF signal to one or more electrodes disposed within the chamber body 113 by providing a sinusoidal RF waveform (RF signal), including a sinusoidal RF waveform, here RF waveforms 501, 502 (FIGS. 5A-5B), through an RF (plasma) generator assembly 160 including an RF matching circuit 162 and a first filter assembly 161. Additionally, each of the PV waveform generators 150 is configured to provide a PV waveform, typically including a series of voltage pulses (e.g., nanosecond voltage pulses), to one or more electrodes disposed within the chamber body 113 by establishing a PV waveform on the bias electrode 104 through a second filter assembly 151. Components within the clamping network 116 may optionally be disposed between each PV waveform generator 150 and the second filter assembly 151.

[0078]

[0087] During processing, a PV waveform is provided to the bias electrode 104 by the PV waveform generator 150 of the first bias generator 196, and a PV waveform is provided to the edge control electrode 115 by the PV waveform generator 150 of the second bias generator 197. The PV waveform is provided to a load (e.g., the composite load 130 shown in FIGS. 3D-3E) disposed within the processing chamber 100. The PV waveform generators 150 are connected to the bias electrode 104 and the edge control electrode 115 through respective power supply lines 157 and 158. The supply of the PV waveform from each of the PV waveform generators 150 is controlled using signals provided by the system controller 126.

[0079]

[0088] In one embodiment, the PV waveform generator 150 is configured to output a periodic voltage function at a time interval of a predetermined length, for example, using a signal from a transistor-transistor logic (TTL) source (not shown). The periodic voltage function generated by the transistor-transistor logic (TTL) source can be two-states DC pulses between a predetermined negative or positive voltage and zero. In one embodiment, the PV waveform generator 150 is configured to maintain a predetermined substantially constant negative voltage (i.e., relative to ground) across its output during a periodically repeating time interval of a predetermined length by repeatedly opening and closing one or more switches at a predetermined rate. In one example, a first switch is used to connect a high voltage power supply to the bias electrode 104 during a first phase of the pulse interval, and a second switch is used to connect the bias electrode 104 to ground during a second phase of the pulse interval. In another embodiment, PV waveform generator 150 is configured to maintain a predetermined substantially constant positive voltage across its output (i.e., relative to ground) for periodically repeating time intervals of predetermined length by repeatedly opening and closing its internal switches (not shown) at a predetermined rate.

[0080]

[0089] In one configuration, a first switch is used to connect the bias electrode 104 to ground during a first phase of the pulse interval, and a second switch is used to connect the high voltage power supply to the bias electrode 104 during a second phase of the pulse interval. In another configuration, during the first phase of the pulse interval, the first switch is placed in an open state such that the bias electrode 104 is disconnected from the high voltage power supply and the bias electrode 104 is coupled to ground through an impedance network (e.g., an inductor and resistor connected in series). Then, during the second phase of the pulse interval, the first switch is placed in a closed state to connect the high voltage power supply to the bias electrode 104, while the bias electrode 104 remains connected to ground through the impedance network.

[0081]

[0090] PV waveform generator 150 may include, but is not limited to, a PV generator and one or more electrical components, such as a high repetition rate switch (not shown), a capacitor (not shown), an inductor (not shown), a flyback diode (not shown), a power transistor (not shown), and / or a resistor (not shown) configured to provide a PV waveform at an output. An actual PV waveform generator 150, which may be configured as a nanosecond pulse generator, may include any number of internal components.

[0082]

[0091] A power supply line 157 electrically connects the output of the PV waveform generator 150 of the first bias generator 196 to the optional filter assembly 151 and the bias electrode 104. The following discussion will primarily focus on the power supply line 157 of the first bias generator 196 used to connect the PV waveform generator 150 to the bias electrode 104, but the power supply line 158 of the second bias generator 197 connecting the PV waveform generator 150 to the edge control electrode 115 may include the same or similar components. The one or more electrical conductors in the various portions of the power supply line 157 may include: (a) one or a combination of coaxial cables, such as a flexible coaxial cable connected in series with a rigid coaxial cable; (b) an insulated high voltage corona resistant hook-up wire; (c) bare wire; (d) a metal rod; (e) an electrical connector; or (f) any combination of the electrical elements of (a)-(e). Optional filter assembly 151 includes one or more electrical elements configured to substantially prevent current generated by the output of RF generator 118 from flowing through power supply line 157 and damaging PV waveform generator 150. Optional filter assembly 151 acts as a high impedance (e.g., high Z) to the RF signal generated by RF generator 118 and inhibits current flow to PV waveform generator 150.

[0083]

[0092] In some embodiments, as shown in FIGS. 1A-1B, a PV waveform generator 150 of the first bias generator 196 couples a generated pulsed voltage (PV) waveform to a blocking capacitor C 5 , the filter assembly 151, the power supply line 157, and the capacitance C 1 (FIG. 1C) to provide a pulsed voltage (PV) waveform signal to the bias electrode 104, and thus to the composite load 130 (FIGS. 3D-3E). In some embodiments, the plasma control scheme 188 may further include a blocking resistor (not shown) disposed in a component that connects the clamping network 116 to a point in the power supply line 157. A blocking capacitor C 5The main function of is to protect the PV waveform generator 150 from the DC voltage generated by the DC power supply 155, which is connected to the blocking capacitor C 5 155。 The purpose of the blocking resistor in clamping network 116 is to block the pulsed voltage generated by PV waveform generator 150 to a sufficient extent to minimize the current induced in DC power supply 155.

[0084] Waveform example

[0093] 4 shows an example of a PV waveform 402 established at the substrate 103 due to a PV waveform 401 established at the bias electrode 104, where the PV waveform 401 is established at the bias electrode 104 and / or edge control electrode 115 through the use of a PV waveform generator 150 in a respective bias generator 196, 197 and a corresponding DC voltage source 155 in the clamping network 116.

[0085]

[0094] Generally, the output of the PV waveform generator 150, which may be controlled by plasma processing recipe settings stored in the memory of the controller 126, forms a PV waveform 401 that includes a peak-to-peak voltage VPP, also referred to as the pulse voltage level Vpp.

[0086]

[0095] Waveform period T P The PV waveform 402 having a waveform seen by the substrate 103 due to application of the PV waveform 401 to the bias electrode 104 can be characterized as including a sheath collapse and recharge phase 450 (or, for ease of discussion, a sheath collapse phase 450) extending between points 420 and 421, a sheath formation phase 451 extending between points 421 and 422, and an ion current phase 452 extending between point 422 and the beginning of the next successively established pulsed voltage waveform at point 420. The sheath collapse phase 450 generally includes a period during which the sheath capacitance is discharged and the substrate potential is brought to the level of the local plasma potential 433.

[0087]

[0096] Depending on the desired plasma processing conditions, the PV waveform frequency (1 / T P It may be desirable to control and set at least the PV waveform characteristics, such as the PV on-time, the pulse voltage level Vpp, the pulse voltage on-time, and / or other parameters of the PV waveform 401. In one example, the pulse voltage (PV) on-time is defined as the ratio of the ion current period (e.g., the time between point 422 and the next point 420 in FIG. 4) to the waveform period Tp, and is greater than 50%, or greater than 70%, for example, between 80% and 95%. In some embodiments, the PV waveform generator 150 is configured to provide a constant voltage during the ion current phase 452, as shown in FIG. 4. In some embodiments, the PV waveform generator 150 is configured to provide a shaped pulse voltage waveform (not shown) with a non-zero slope during the ion current phase 452 by using one or more internal switches and a DC power supply. In some embodiments, the PV waveform generator 150 is configured to provide a constant positive voltage during one of the phases of the voltage pulse, such as only during the sheath collapse phase 450 (not shown). In general, the DC offset ΔV seen in each PV waveform of the bias electrode depends on the bias applied by the DC power supply 155 of the clamping network 116 and various characteristics of the configuration of the PV waveform generator 150 used to establish the PV waveform 401.

[0088]

[0097] In some embodiments, during ion current phase 452, the ion current (Ii) deposits positive charge on the substrate surface, so that the voltage at the substrate surface will increase over time, as seen by the positive slope of the line between points 422 and 420. The voltage increase at the substrate surface over time will lower the sheath voltage, resulting in a broadening of the ion energy distribution. Therefore, at least the PV waveform frequency (1 / T PD ) (where T PD is the PV waveform period), it is desirable to minimize the effects of sheath voltage drop and broadening of the ion energy distribution.

[0089]

[0098] 5A-5B show a first RF waveform 501 established at the bias electrode 104 and a second RF waveform 502 established at the edge control electrode 115 by capacitive coupling of an RF signal provided to the support base 107 by an RF generator 118 in the plasma generator assembly 163. The waveform characteristics of the first RF waveform 501 and the second RF waveform 502 are controlled by using an edge tuning circuit 170 configuration such as one of the configurations illustrated in FIG. 3A (parallel LC resonant circuit), FIG. 3B (series resonant circuit) and FIG. 3C (more complex resonant circuit). The exemplary waveforms shown in FIG. 5A-5B and the simulation results shown in FIG. 6A-6D below are not intended to limit the scope of the disclosure provided herein, but are provided for ease of discussion.

[0090]

[0099] Generally, the RF signal provided to the support base 107 has a relatively high frequency, so that the first RF waveform 501 and the second RF waveform 502 have corresponding high frequencies (1 / T RF ). The edge tuning circuit 170 described in various embodiments disclosed herein may be used to tune one or more characteristics of a second RF waveform 502 established by the edge control electrode 115 relative to one or more characteristics of a first RF waveform 501 established by the bias electrode 104. In some embodiments, the one or more relative characteristics may include an RF waveform amplitude ratio (e.g., a voltage amplitude ratio V RF2 / V RF1 ), an RF current amplitude ratio between the second RF waveform 502 and the first RF waveform 501 (e.g., current amplitude ratio not shown), a phase difference (ΔΦ) between the second RF waveform 502 and the first RF waveform 501, and / or an RF supply power ratio between the second RF waveform 502 and the first RF waveform 501 (e.g., supply power ratio not shown).

[0091]

[0100] One or more characteristics of the second RF waveform 502 relative to the first RF waveform 501 can be determined and / or monitored by measuring the voltage, current, phase, and / or power of the RF waveforms established at the edge control electrode 115 and the bias electrode 104, respectively. The measured characteristics of the second RF waveform 502 and the first RF waveform 501 correspond to characteristics of the bulk plasma in the portions formed above the edge control electrode 115 and the bias electrode 104, respectively, such as plasma density. The determined difference between the second RF waveform 502 and the first RF waveform 501 can be used to monitor and control the difference in electron density in the portion of the bulk plasma formed above the edge ring 114 and the portion of the bulk plasma formed above the center portion of the substrate 103. The uniformity and / or distribution of the plasma density can be determined by measuring the voltage, current, phase, and / or power of the RF waveforms established at the edge control electrode 115 and the bias electrode 104, respectively. 7 may be controlled and / or adjusted to achieve a desired processing result by using the edge tuning circuit 170, such as using the system controller 126 to adjust

[0092]

[0101] Non-limiting simulation results for the edge tuned circuit 170 shown in Figures 3A and 3B are shown in Figures 6A-6B, and simulation results for the edge tuned circuit 170 combining the series and parallel configurations shown in Figure 3C are shown in Figures 6C-6D. In Figures 6A and 6C, the simulation results show that varying the capacitance (e.g., the variable capacitor C 7を adjusting the voltage amplitude ratio (e.g., V RF2 / V RF1 ) are shown. In FIG. 6B and FIG. 6D, simulation results show that the effect of 7 Varying the capacitance of the second RF waveform 502 and the first RF waveform 501 can change the phase difference (e.g., Φ RF2 -Φ RF1 ) is provided as an example of an LC circuit tuning curve showing the effect on

[0093]

[0102] As shown in FIG. 6A, the variable capacitance C of the edge-tuned circuit 170 (configuration of FIG. 3A) has a value of about 170 pF. 7 has a corresponding voltage swing ratio (V RF2 / V RF1 6B, the phase difference corresponding to the 170 pF capacitance of edge tuned circuit 170 having the same configuration as in FIG. 6A is relatively small, e.g., less than 5 degrees, resulting in an amplification of second RF waveform 502 relative to first RF waveform 501 and a small phase difference (ΔΦ) therebetween, as shown in FIG. 6A.

[0094]

[0103] 6C to 6D, the variable capacitance C 7 (the configuration of FIG. 3C) can be set to a value of about 25 pF. As a result, the voltage swing ratio (V RF2 / V RF1 ) is equal to about 0.5 (FIG. 6C), and the phase difference (ΔΦ) is about null, as shown in FIG. 6D.

[0095]

[0104] As shown in FIG. 6A, simulation results based on the edge-tuned circuit 170 configuration of FIG. 3A (e.g., a parallel LC resonant circuit) show resonance peaks at about 100 pF and about 120 pF. In FIG. 6D, simulation results for the edge-tuned circuit 170 (configuration of FIG. 3C) show resonance phase transitions at 60 pF and 250 pF. In some embodiments, it may be desirable to operate each edge-tuned circuit 170 on either side of resonance during the period during which the RF plasma is sustained. In some embodiments, the edge-tuned circuits 170 may be configured to permit switching operation of the edge-tuned circuits 170 between either side of a resonance peak without crossing the resonance region, such as by using a variable capacitor in combination with a parallel and series LC circuit. As mentioned above, the simulation results shown in FIGS. 6A-6D are not intended to be limiting, since the voltage amplitude ratio (V RF2 / V RF1) and / or current amplitude ratio and / or phase difference between the second RF waveform 502 and the first RF waveform 501, as other edge tuned circuit 170 configurations may be used to provide other desired operating ranges for amplifying, reducing, and / or equalizing the current amplitude ratio and / or phase difference between the second RF waveform 502 and the first RF waveform 501.

[0096]

[0105] In some embodiments, tuning circuitry and / or variable capacitance C 7 It may be desirable to select a tuned circuit arrangement and / or variable capacitance C that results in an amplified electric field between the edge control electrode 115 and the bias electrode 104. The amplified electric field results in a corresponding increase in plasma density in the portion of the plasma 101 formed on the substrate support assembly 136 at a distance between the two electrodes. In some embodiments, a tuned circuit arrangement and / or variable capacitance C that does not introduce a phase difference between the RF waveforms established at the respective electrodes is selected such that the plasma density remains substantially uniform over the region spanning the edge of the substrate 103. 7 It may be desirable to select

[0097]

[0106] Beneficially, the edge tuning circuit 170 may be configured to provide a wide range of desired plasma processing conditions to control and / or adjust the plasma density distribution at different points between the center and edge of the substrate 103. The characteristics of the edge tuning circuit 170, and thus the position of the system on the tuning curve (FIGS. 6A-6D), may be adjusted using the system controller 126 by tuning one or more variable capacitors C 7, may be controlled by adjusting the characteristics of the edge tuned circuit by the system controller 126. Controlled adjustment of the characteristics of the edge tuned circuit by the system controller 126 may allow plasma processing conditions to be changed relatively easily within a single substrate plasma process, between successive substrate plasma processes, and / or for different types of substrates without having to manually change hardware related configurations. In some embodiments, one or both of the bias generators 196, 197, the edge tuned circuit 170, or a combination thereof may be used to preferentially clean a surface of the substrate support assembly 136 within the edge pocket region 117 during an in situ plasma cleaning method such as described below in connection with Figures 7A-7C and 8A-8C.

[0098]

[0107] In some embodiments, the edge tuning circuit 170 is automatically adjusted to maintain desired processing conditions, including accounting for plasma uniformity drift due to changes over time in the geometries and / or materials of the various components of the processing chamber 100. For example, the method may be further adapted to adjust the capacitance C to account for changes in the thickness of the edge ring 114, which may be caused by erosion of dielectric material from the edge ring 114 due to ion bombardment. 7 For example, in some embodiments, the system controller 126 may be configured to detect signals of one or more electrical parameters at corresponding nodes N of the processing systems 10A, 10B by using the signal detection module 187, determine whether the processing systems 10A, 10B are operating within desired processing conditions by comparing characteristics of the detected signals to one or more control limits, and adjust one or more components of the edge tuning circuit 170 if the electrical signal characteristics are outside the control limits. Some embodiments may use a capacitance C to maintain a desired RF voltage amplitude ratio, RF current amplitude ratio, and / or RF phase difference between different RF waveforms at the edge control electrode 115 and the bias electrode 104. 7 This includes automatically adjusting the edge tuned circuit, such as by adjusting the

[0099]

[0108] In some embodiments, the system controller 126 compares one or more process conditions and / or RF waveforms to predetermined limits, e.g., control limits, and adjusts the capacitance C of the edge tuned circuit 170 based on an algorithm or look-up table stored in the memory 134 of the system controller 126. 7 The edge tuning circuit 170 is configured to automatically adjust based on the desired processing conditions and / or desired characteristics between the RF waveforms of the edge control electrode 115 and the bias electrode 104 by modifying one or more set points, such as

[0100]

[0109] In some embodiments, the edge tuning circuit 170 may be manually adjusted and / or controlled by adjusting one or more components of the edge tuning circuit 170 to a desired set point and / or within desired control limits. A list of desired set points and / or controls may be selected by a user and stored in the instructions used to control the processing system 10A, 10B. For example, the capacitance C of the edge tuning circuit 170 may be adjusted to a desired set point and / or within desired control limits. 7 may be controlled to a desired volume determined by the user and stored in the memory of the system controller 126.

[0101]

[0110] Generally, a pulse voltage (PV) waveform established on the electrodes 104 and 115, such as either the negative pulse waveform 401, the shaped pulse waveform 441, or the positive pulse waveform 431, has a period T PD In one example, the PV waveform includes a periodic series of pulse voltage (PV) waveforms that repeat with a period T PD may be between about 1 μs and about 5 μs, such as about 2.5 μs, for example between about 200 kHz and about 1 MHz, or about 400 kHz, for example up to about 1 MHz, or up to about 500 kHz.

[0102]

[0111] As described above, in some embodiments, the process chamber 100 includes at least one or more RF generators 118 and associated first filter assembly 161, and one or more PV generators 314 and associated second filter assembly 151, which are collectively configured to provide a desired waveform to one or more electrodes disposed in the substrate support assembly 136. Software instructions stored in the memory of the system controller 126 are configured to generate RF waveforms configured to establish, maintain, and control one or more aspects of a plasma formed in the process chamber. The one or more aspects of the plasma that are controlled may include, but are not limited to, plasma density, plasma chemistry, and ion energy in the plasma formed in the process space 129.

[0103] Processing method examples

[0112] 7A-7C are process flow diagrams illustrating respective methods that can be used to clean processing by-products from a surface of a substrate support assembly. FIGS. 8A-8C are close-up views of a substrate support assembly 136 used to illustrate aspects of the methods described in FIGS. 7A-7C. In FIGS. 8A-8C, a portion of the substrate support assembly 136 is configured as shown in FIG. 1B, with the edge control electrode 115 disposed in or on the material of the dielectric tube 110 surrounding the substrate support 105. However, it is contemplated that the methods described below may be used with any one or combination of substrate support assembly configurations described herein, such as where the edge control electrode 115 is disposed within the dielectric material of the substrate support 105 (FIGS. 1A, 1D), within the edge ring 114, and / or connected to the edge ring 114.

[0104]

[0113] FIG. 7A is a process flow diagram illustrating a method 700 for preferentially cleaning surfaces defining an edge pocket region 117 of a substrate support assembly 136, according to one embodiment. FIGS. 1A-1D and 8A are referenced in the following description to illustrate aspects of the method 700, but are not intended to be limiting, as it is contemplated that the method 700 may be performed in other processing systems configured to separately energize the substrate and edge ring. Generally, the method 700 uses an in situ plasma (a plasma formed within the processing chamber 100) to remove accumulated processing by-products from the edge ring 114 and / or portions of the substrate support surface 105A adjacent thereto. The method 700 is used to manipulate the shape of the plasma sheath boundary 11 (FIG. 8A) formed on the substrate support assembly 136 by increasing or decreasing the voltage between the edge ring 114 and the plasma relative to the voltage between the substrate support surface 105A and the plasma 101. The voltage difference creates a corresponding difference in ion energy at surfaces 114A-C and 105A, resulting in a bending of the plasma sheath boundary that, in some embodiments, may be advantageously used to preferentially direct plasma generated ions toward a desired portion of the substrate support assembly 136. For example, as shown in FIG. 8A, a height difference between a portion 11A of the sheath boundary 11 formed on the substrate support surface 105A and a portion 11C of the sheath boundary 11 formed on the edge ring 114 causes the sheath boundary to bend at a portion (bend 11B) spanning the edge pocket region 117.

[0105]

[0114] At step 702, the method 700 includes generating a first plasma in a processing region of a processing chamber, where the processing chamber 100 may include any one or combination of the features illustrated in Figures 1A-1D. Here, the processing region 129A is defined by the chamber lid 123 and the substrate support assembly 136. Now referring to Figure 8A, the substrate support assembly 136 generally includes a first portion of dielectric material 105B forming a substrate support surface 105A and an edge ring 114 that surrounds the substrate 103 (shown in dotted lines) when the substrate 103 is disposed on the substrate support surface 105A. One or more edge pocket surfaces 114A,B of the edge ring 114 and the outer peripheral edge of the first portion of dielectric material 105B define an edge pocket region 117 where the edge pocket surfaces 114A,B are disposed inward of the chamber lid facing surface 114C.

[0106]

[0115] In some embodiments, the substrate support assembly 136 further includes the bias electrode 104 spaced apart from the substrate support surface 105A by a first portion 105B of dielectric material, and an edge control electrode 115 spaced apart from a center of the bias electrode 104. Generally, the edge control electrode 115 is spaced apart from the bias electrode 104 by a dielectric material of the substrate support assembly 136, which may include the dielectric material of the substrate support 105, the dielectric material used to form the dielectric tube 110, the dielectric material of the edge ring 114 when the edge control electrode 115 is embedded therein, or a combination thereof. Here, the bias electrode 104 is electrically connected to a first bias generator 196 configured to establish a first pulse voltage (PV) waveform on the bias electrode 104. The edge control electrode 115 is electrically connected to a second bias generator 197 configured to establish a second pulse voltage (PV) waveform on the edge control electrode 115.

[0107]

[0116] In some embodiments, the first plasma generated in step 702 is a capacitively coupled plasma (CCP) generated using a radio frequency (RF) signal from an RF waveform generator 163 electrically connected to the substrate support assembly 136, such as electrically connected to the support base 107, where the chamber lid 123 is electrically connected to ground (as shown) or to a second RF generator. In other embodiments (not shown), the first plasma can be a CCP formed using an RF generator electrically connected to the chamber lid 123, where the substrate support assembly 136 is electrically connected to ground. In other embodiments, the first plasma can be an inductively coupled plasma (ICP) formed using an RF generator electrically connected to one or more ICP coils (not shown) disposed above the chamber lid 123.

[0108]

[0117] In some embodiments, the RF signal used to generate the first plasma has a frequency greater than about 400 kHz, e.g., about 1 MHz or more, or about 2 MHz or more, e.g., about 13.56 MHz or more, about 27 MHz or more, about 40 MHz or more, or for example, between about 30 MHz and about 200 MHz, e.g., between about 30 MHz and about 160 MHz, between about 30 MHz and about 120 MHz, or between about 30 MHz and about 60 MHz.

[0109]

[0118] In step 704, the method includes exposing the edge ring 114 and the substrate support surface 105A to a first plasma. In some embodiments, the first plasma is formed from an oxygen-containing gas, a hydrogen-containing gas, a halogen-containing gas, such as a fluorine- and / or chlorine-based gas, or a combination thereof. In some embodiments, radical species generated in the plasma react with process by-products accumulated on surfaces in the process space 129, such as surfaces 114A-C of the edge ring 114. The reaction forms volatile species that are exhausted from the process space 129 through the vacuum outlet 120. In some embodiments, the first time period with the RF plasma can be about 1 second or more, such as about 5 seconds or more, or about 10 seconds or more.

[0110]

[0119] In step 706 of the method 700, the plasma sheath boundary of the first plasma above the edge pocket region is tuned to the variable capacitor C in the edge tuning circuit 170. 7 and / or C. 8 and / or by establishing a pulsed voltage (PV) waveform at the edge control electrode 115 to provide a greater voltage between the bulk plasma and the edge ring 114 than between the bulk plasma and the substrate support surface 105A.

[0111]

[0120] In some embodiments, the second pulse voltage (PV) waveform established at the edge control electrode during step 706 includes a series of repeating cycles in which the voltage waveform in each cycle has a first portion occurring during a first time interval (e.g., sheath collapse phase 452) and a second portion occurring during a second time interval (e.g., sheath formation phase 451 and ion current phase 452). Generally, the voltage during the first interval differs from the voltage during the second interval, and the voltage difference determines the energy of the ions accelerated across the sheath to the edge ring 114.

[0112]

[0121] In some embodiments, the voltage established at the bias electrode by the first pulse voltage (PV) waveform generator 150 (here, the bias voltage) is maintained at zero volts VPP (e.g., about 0 volts ±1 volt (null volt)) for at least a number of repeat cycles of the second PV waveform established at the edge control electrode 115 in step 704. For example, in some embodiments, the second PV waveform may be established at the edge control electrode 115 with a non-zero VPP. The pulse voltage VPP established at the bias electrode using the first PV waveform generator may be maintained at zero volts (e.g., about 0 volts ±1 volt (null volt)) for about 1 second or more, such as about 5 seconds or more, or about 10 seconds or more. In some embodiments, the bias electrode 104 is connected to ground for the first period of time by using a switch connected between the power supply line 157 and ground. In another embodiment, the bias voltage may be driven to zero volts (null volt) using the PV waveform generator 150 or another driver (not shown).

[0113]

[0122] In some embodiments, as shown in FIG. 8A, steps 702, 704, and 706 are performed in the absence of substrate 103 (shown in dotted lines) such that substrate support surface 105A is exposed to the first plasma. Beneficially, a potential difference between a portion of the plasma formed on substrate support surface 105A and a portion of the plasma formed on edge ring 114 causes plasma sheath boundary 11 to bend at portion 11B. The shape of the plasma sheath boundary shown in FIG. 8A is configured to preferentially direct plasma-generated ions toward edge pocket surface 114A-B based on the formed bend 11B. By directing plasma-generated ions toward edge pocket surface 114A-B while simultaneously reducing the voltage between the plasma and substrate support surface 105A, method 700 can be used to preferentially clean a surface of edge ring 114 while substantially reducing undesired plasma-based erosion of substrate support 105.

[0114]

[0123] In some embodiments, method 700 optionally includes processing substrate 103 using a second plasma formed before or after the preferential cleaning steps described in steps 702-706. For example, method 700 may optionally include positioning substrate 103 on substrate support surface 105A in step 708, generating a second plasma in processing region 129A in step 710, exposing substrate 103 to the second plasma for a second time in step 712, and establishing a first pulsed voltage (PV) waveform on bias electrode 104 in step 714. In some embodiments, substrate 103 used to perform optional steps 708-714 of method 700 is a non-production substrate. That is, the substrate is of a type used to perform cleaning, testing, and / or maintenance operations, commonly referred to as a "blanket" or "dummy" wafer.

[0115]

[0124] In some embodiments, step 708 of method 700 further includes electrostatically clamping the substrate 103 to the substrate support 105 by supplying a chucking voltage to the bias electrode 104 from a DC power supply 155 electrically connected to the bias electrode 104 using power supply line 157. The chucking voltage creates a voltage potential difference between the substrate 103 and the bias electrode 104, resulting in a capacitance C of a first portion of a dielectric material disposed therebetween. 1 (FIG. 1C) is used to generate an electrostatic attraction force (chucking force). In some embodiments, the method 700 further includes electrostatically clamping the edge ring 114 to the substrate support assembly 136 by supplying a chucking voltage to the edge control electrode 115 from a DC power supply 155 electrically connected to the edge control electrode 115 using power supply lines 158. In some embodiments, the method 700 includes flowing an inert gas (e.g., helium) into a backside space 105D (FIG. 1D) disposed between the substrate 103 and the substrate support surface 105A and / or between the edge ring 114 and a surface of the substrate support assembly 136 to facilitate heat transfer therebetween.

[0116]

[0125] In some embodiments, step 714 of method 700 further includes adjusting one or more characteristics of the second pulsed voltage (PV) waveform relative to one or more characteristics of the first pulsed voltage (PV) waveform to control the shape of the plasma sheath boundary 11 formed on the substrate 103 and the edge ring 114 during the second time period. Thus, in some embodiments, step 714 includes adjusting one or more characteristics of the first PV waveform established at the bias electrode 104 relative to one or more characteristics of the second PV waveform established at the edge control electrode 115. In some embodiments, adjusting the one or more characteristics includes adjusting a PV waveform frequency (1 / T P ), pulse voltage level Vpp, pulse voltage on time, or a combination thereof. In some embodiments, one or more properties may be controlled to increase or decrease the sheath height on the edge control electrode 115 relative to the sheath height on the bias electrode 104, bending the plasma sheath at the substrate edge or the edge of the substrate support 105 to allow fine tuning of ion trajectories and ion energy at the edge region of the substrate 103 or substrate support 105.

[0117]

[0126] FIG. 7B is a process flow diagram illustrating a method 720 for preferentially cleaning surfaces defining edge pocket regions 117 of a substrate support assembly 136, according to one embodiment. Aspects of the method 720 are illustrated generally in FIG. 8B. However, it is contemplated that the method 720 may be performed using any of the processing system configurations described in FIGS. 1A-1D. In some embodiments, the substrate 103 is a non-production substrate. That is, the substrate is of a type that is used to perform cleaning, testing, and / or maintenance operations, commonly referred to as a "blanket" or "dummy" wafer. In other embodiments, the method 720 may be performed during plasma processing of a production substrate having semiconductor devices at least partially formed thereon, for example, to remove processing by-product residues from a beveled edge or backside edge of the production substrate.

[0118]

[0127] Here, method 720 generally involves preferentially cleaning the surfaces defining the edge pocket region 117 by adjusting characteristics of respective pulse voltage (PV) waveforms established by bias electrode 104 and edge control electrode 115. During the cleaning process, substrate 103 remains on substrate support surface 105A such that substrate 103 is disposed between substrate support surface 105A and plasma. Substrate 103 provides a cover to prevent ion bombardment and erosion of substrate support surface 105A. In some embodiments, substrate 103 is at least partially lifted off substrate support surface 105A such that plasma and / or radical species formed therein can more easily diffuse into edge pocket region 117 and react with process by-products (e.g., carbon-containing polymers) formed on the surfaces therein. It is contemplated that at least some of the steps of method 720 may be identical or substantially similar to corresponding steps of method 700 described above.

[0119]

[0128] The method 720 generally includes positioning the substrate 103 on the substrate support assembly 136 in step 722, generating a plasma in step 724, exposing the substrate 103 and edge ring 114 to the plasma (optionally) for a first period of time in step 726, and optionally adjusting a plasma sheath boundary in step 728 by energizing one or both of the substrate 103 and edge ring 114.

[0120]

[0129] Positioning the substrate 103 in step 722 generally includes transferring the substrate 103 to the substrate support surface 105A. In some embodiments, the substrate is electrically clamped to the substrate support assembly as described in step 708 of method 700. A plasma may be generated in step 724 using an RF signal as described above in step 702 and / or step 710 of method 700.

[0121]

[0130] In some embodiments, the substrate 103 is optionally exposed to a plasma for a first period of time in step 728. The substrate 103 and edge ring 114 are optionally energized by using first and second pulsed voltage waveform generators to establish PV waveforms at the bias electrodes and edge control electrodes, for example, as described in steps 712 and 714 of method 700.

[0122]

[0131] In step 730, the method 720 includes at least partially lifting the substrate 103 from the substrate support surface 105A, as shown in FIG. 8B. Typically, the substrate 103 is at least partially lifted from the substrate support surface 105A using a plurality of lift pins 20 extending through the substrate support assembly 136. As described in step 708, if the substrate is electrostatically clamped to the substrate support 105, at least partially lifting the substrate 103 may include stopping or adjusting the supply of a chucking voltage to the bias electrode 104 and / or discharging electrostatic charge between the substrate 103 and the bias electrode 104, for example, by setting a DC voltage potential of the bias electrode 104 similar to a DC voltage potential of the substrate 103.

[0123]

[0132] In steps 732 and 734, method 720 includes exposing edge pocket surfaces 114A-B to a plasma while simultaneously adjusting the plasma sheath boundary 11. Steps 732 and 734 may be performed using substantially similar processes as used to perform steps 704 and 706 of method 700 with the addition of a partially elevated substrate 103 disposed on the substrate support surface 105A. It is contemplated that any one or more of the steps of method 720 may be used in combination with method 740, or vice versa, to enhance in situ plasma cleaning efficiency in the edge pocket region 117 while simultaneously protecting the substrate support surface 105A from undesirable plasma-based erosion.

[0124]

[0133] FIG. 7C is a process flow diagram illustrating a method 740 for preferentially cleaning edge pocket surfaces 114A-B of a substrate support assembly 136 according to another embodiment. It is contemplated that the method 740 may be performed using any of the processing systems described herein, such as any one of the substrate support assemblies 136 of FIGS. 1A-1D and 8A-8C. As shown in FIG. 8C, the method 740 generally includes using a tuned circuit 170 to concentrate a plasma between a peripheral edge of the substrate 103, which is at least partially lifted from the substrate support surface 105A, and the edge pocket surfaces 114A-B, e.g., the edge pocket region 117. The concentrated plasma increases the radical and ion concentration in the edge pocket region 117, which may be used to preferentially clean the surfaces 114A-B therein. Typically, the substrate 103 is only partially lifted to a distance small enough to prevent plasma from forming between the substrate 103 and the substrate support surface 105A, thus preventing plasma-based erosion. In some embodiments, substrate 103 is a non-production substrate, commonly referred to as a "blanket" or "dummy" wafer. In other embodiments, method 740 may be performed during plasma processing of a production substrate having semiconductor devices at least partially formed thereon, for example, to remove processing by-product residues from beveled or backside edges of the production substrate.

[0125]

[0134] Step 742 of method 740 includes positioning the substrate 103 on the substrate support surface 105A of the substrate support assembly 136 as shown in Figure 8C. Step 742 may be the same as or substantially similar to step 722 of method 720.

[0126]

[0135] Step 744 of the method 740 includes igniting and maintaining a plasma by using a radio frequency (RF) signal. In some embodiments, the RF signal is provided to the support base 107 of the substrate support assembly 136 using an electrically connected plasma generator assembly 163, where the RF signal is configured to ignite and / or maintain a processing plasma 101 in a processing region 129A of the processing chamber 100. The processing region 129A is disposed between the substrate support assembly 136 and the chamber lid 123. In some embodiments, the RF signal has a frequency of about 1 MHz or greater, such as about 20 MHz or greater, such as between about 30 MHz and about 60 MHz, or about 40 MHz.

[0127]

[0136] Typically, an RF signal provided to the support base 107 establishes a first RF waveform 501 (FIGS. 6A-6B) at the bias electrode 104. The bias electrode 104 is capacitively coupled to the support base 107 through a third portion of dielectric material (e.g., dielectric material layer 105C) disposed therebetween. The bias electrode 104 is spaced from the processing plasma by the first portion of dielectric material (e.g., dielectric material layer 105B), and the substrate 103 is disposed on the substrate support surface 105A. In some embodiments, the method 740 further includes electrostatically clamping the substrate 103 to the substrate support 105 as described in step 708 of the method 700.

[0128]

[0137] At step 746, the method 740 includes exposing the surface of the substrate 103 to a plasma for a first period of time. Step 748 of the method 740 optionally includes adjusting one or both of the plasma density and / or the shape of the plasma sheath boundary 11. In some embodiments, adjusting the plasma density includes adjusting one or more characteristics of the second RF waveform 502 established at the edge control electrode 115 relative to one or more characteristics of the first RF waveform 501 established at the bias electrode 104. In some embodiments, adjusting one or more characteristics of the second RF waveform 502 relative to one or more characteristics of the first RF waveform 501 includes adjusting a voltage amplitude ratio (e.g., V) between the second RF waveform 502 and the first RF waveform 501, as shown in FIG. 5A or FIG. 5B. RF2 / V RF1 ), adjusting a current amplitude ratio between the second RF waveform 502 and the first RF waveform 501, adjusting a phase difference (e.g., delta Φ) between the second RF waveform 502 and the first RF waveform 501, or a combination thereof. In some embodiments, adjusting one or more characteristics of the second RF waveform 502 relative to the first RF waveform 501 is performed by adjusting an electrical characteristic of one or more elements in the edge tuned circuit 170.

[0129]

[0138] In some embodiments, adjusting the second RF waveform 502 relative to the first RF waveform 501 changes the plasma uniformity across at least a portion of the processing region 129A (FIGS. 1A-1B). For example, in one embodiment, the processing region 129A is defined by the chamber lid 123 and the substrate support assembly 136, and the plasma 101 is a bulk plasma formed therebetween. In some embodiments, a first portion of the plasma 101 is formed in a region disposed between the chamber lid 123 and the bias electrode 104. A second portion of the plasma 101 is formed in a region disposed between the chamber lid 123 and the edge control electrode 115. In those embodiments, adjusting the second RF waveform 502 relative to the first RF waveform 501 changes the plasma density in the second portion of the plasma 101 relative to the plasma density in the first portion of the plasma 101.

[0130]

[0139] In some embodiments, adjusting one or more characteristics of the second RF waveform 502 established by the edge control electrode 115 relative to one or more characteristics of the first RF waveform 501 established by the bias electrode 104 includes using an edge tuning circuit 170. In some embodiments, the edge tuning circuit 170 includes one or more variable capacitors C 7 , C 8 and adjusting one or more characteristics of the second RF waveform 502 relative to the one or more characteristics of the first RF waveform 501 includes adjusting one or more capacitances C 7 , C 8 Tuning of the edge tuning circuit 170 involves the system controller 126 varying the capacitance C based on the desired characteristics of and / or the desired difference between the RF waveforms 501, 502. 7 , C 8 This can be done automatically to adjust the electrical characteristics of one or more components of the edge tuning circuit 170, such as

[0131]

[0140] For example, in some embodiments, the system controller 126 may be configured to determine characteristics of the respective waveforms by measuring one or more characteristics of an electrical signal taken at one or more nodes N by using the signal detection module 187, compare the determined characteristics to desired characteristics, and modify the output of components of the edge tuned circuit 170 based on the comparison. 7 , C 8 The edge tuning circuit 170 may be manually adjusted when changing the set points of the components of the edge tuning circuit 170, such as the capacitance of the circuit or the inductance L of the circuit. A user may use the system controller 126 and / or the signal detection module 187 to change the set points, for example, by changing a recipe parameter that corresponds to the component or another setting in the instructions used by the system controller 126 to operate the processing systems 10A, 10B.

[0132]

[0141] Generally, assuming a relatively constant RF power is supplied from the plasma generator assembly 163 to the support base 107, the V RF2 / V RF1 An increase in the ratio results in an increase in the ratio of plasma density near the edge of the substrate to the plasma density near the center of the substrate. The relative increase in plasma density results in a corresponding increase in plasma-generated species in the bulk plasma, resulting in a relative increase in ion flux and reactive neutral concentration at the edge of the underlying substrate surface. Similarly, V RF2 / V RF1 As the ratio decreases, the ratio of plasma density near the edge of the substrate to the plasma density near the center of the substrate decreases, resulting in a corresponding decrease in ion flux and reactive neutral concentration at the edge of the substrate.

[0133]

[0142] By controlling the relative plasma density between the first and second portions of the plasma, the corresponding distribution of activated species within the processing region 129A is also controlled and may be used to improve overall processing non-uniformity, such as within-wafer processing non-uniformity. Advantageously, step 748 includes using the system controller 126 to control the edge tuning circuit 170 to tune the capacitance C 7 and / or C. 8 As such, method 740 may be performed without resorting to mechanical adjustments or hardware configuration changes that are typically required to adjust the bulk plasma distribution in a capacitively coupled plasma (CCP) system, thus preventing fine control thereof.

[0134]

[0143] Step 750 of method 700 optionally includes energizing the substrate 103 and / or edge ring 114 by establishing a pulsed voltage (PV) waveform at one or both of the bias electrode 104 and the edge control electrode 115. The process used to energize the substrate 103 and / or edge ring 114 during the first period of time may be the same as or substantially similar to the process described in step 714 of method 700.

[0135]

[0144] Step 752 of method 740 includes at least partially lifting the substrate from substrate support surface 105A, which may be performed using the same or a substantially similar process as described in step 830 of method 720. In step 754, method 740 includes exposing edge pocket surfaces 114A-B to a plasma for a period of time.

[0136]

[0145] Prior to or during steps 752 and 754, step 756 of method 740 includes adjusting one or more characteristics of radio frequency (RF) waveforms established at bias electrode 104 and edge control electrode 115, respectively, to form a plasma in edge pocket region 117 for at least a portion of the time period. In some embodiments, adjusting one or more characteristics of the RF waveforms includes adjusting a phase difference (e.g., delta Φ) between second RF waveform 502 and first RF waveform 501 such that a plasma is formed between the outer peripheral edge of substrate 103 and edge pocket surface 114A-B, where the substrate is at least partially elevated to provide a gap or space between the substrate and edge pocket surface 114A-B sufficient to allow a plasma to form, while maintaining a gap between the substrate and substrate support surface 105A small enough to prevent a plasma from forming. In some embodiments, the bias voltages established on the bias electrode 104 and the edge control electrode 115, respectively, using the electrically connected waveform generator 150 are maintained at a constant or null value for at least a portion of the time period. For example, in some embodiments, the bias voltages established on one or both of the bias electrode 104 and the edge control electrode 115 are maintained at practically zero volts VPP (e.g., about 0 volts ±1 volt (null volt)) for at least a portion of the time period, such as about 1 second or more, about 5 seconds or more, or about 10 seconds or more. Maintaining the bias voltage at practically zero volts VPP may include connecting the respective electrodes to ground or using the PV waveform generator 150 or another driver (not shown) to drive the bias voltage to zero volts as described in connection with FIG. 7A for method 700.

[0137]

[0146] In some embodiments, the method 740 further includes preferentially adjusting the plasma density towards a portion of the plasma 101 formed on the edge control electrode 115 relative to a plasma density of a portion of the plasma formed on the bias electrode 104, where preferentially adjusting the plasma density includes adjusting the voltage amplitude ratio (e.g., VRF2 / V RF1 ), adjusting the current amplitude ratio between the second RF waveform 502 and the first RF waveform 501, adjusting the phase difference (e.g., delta Φ) between the second RF waveform 502 and the first RF waveform 501, or a combination thereof.

[0138]

[0147] The above-described embodiments may be used alone or in combination to provide fine control over the generation and distribution of active species within the processing region of an inductively coupled plasma (ICP) or capacitively coupled plasma (CCP) chamber. Advantageously, the embodiments may be implemented by using a system controller without adjusting or changing individual chamber components. Thus, process recipe parameters are provided that are easily adjustable during the processing of a single substrate and / or between successively processed substrates. RF plasma density control methods may be implemented independently and / or in combination with pulsed voltage (PV) waveform bias methods to provide independent and fine control over ion energy, IEDF, ion directionality, ion flux, and reactive neutral molecule concentration at the substrate surface, as compared to conventional RF biased CCP systems.

[0139]

[0148] While the above description is directed to embodiments of the present disclosure, other and additional embodiments of the disclosure may be devised without departing from the basic scope thereof, the scope of which is determined by the claims that follow.

Claims

1. 1. A plasma processing method, comprising: (a) generating a plasma within a processing volume defined by a chamber lid and a substrate support assembly, the substrate support assembly comprising: a first portion of a dielectric material forming a substrate support surface; an edge ring surrounding the substrate support surface, the edge ring comprising a plasma-facing surface and one or more edge pocket surfaces disposed inwardly from the plasma-facing surface; a bias electrode spaced from the substrate support surface by a first portion of the dielectric material; an edge control electrode disposed at a distance from the center of the bias electrode; Equipped with the bias electrode is electrically connected to a first bias generator configured to establish a first pulsed voltage (PV) waveform at the bias electrode; generating a plasma, wherein the edge control electrode is electrically connected to a second bias generator configured to establish a second pulsed voltage (PV) waveform at the edge control electrode; (b) exposing the edge ring and the substrate support surface to the plasma; (c) simultaneously with (b), establishing the second pulsed voltage (PV) waveform at the edge control electrode to induce a curvature in the shape of a plasma sheath boundary formed on the substrate support surface and the edge ring to preferentially direct plasma generated ions toward the edge pocket surface. A plasma processing method comprising:

2. The method of claim 1, wherein the voltage established at the bias electrode is maintained at approximately 0±1 volts (V) during at least a portion of the time that the edge ring and the substrate support surface are exposed to the plasma and the second pulse voltage (PV) waveform is established at the edge control electrode.

3. 2. The method of claim 1, wherein the first pulsed voltage (PV) waveform and the second pulsed voltage (PV) waveform have a frequency of about 1 MHz or less.

4. the second pulsed voltage (PV) waveform comprises a series of repeating cycles; the waveform in each cycle has a first portion occurring during a first time interval and a second portion occurring during a second time interval; The method of claim 1 , wherein the voltage during the second time interval is lower than the voltage during at least a portion of the first time interval.

5. 3. The method of claim 2, wherein the voltage established at the bias electrode is maintained at about 0±1 volts (V) by electrically connecting the bias electrode to ground.

6. 3. The method of claim 2, wherein the voltage established at the bias electrode is maintained at approximately 0±1 volts (V) by controlling the first bias generator.

7. Adjusting one or more characteristics of the second pulse voltage (PV) waveform relative to one or more characteristics of the first pulse voltage (PV) waveform while the first pulse voltage (PV) waveform and the second pulse voltage (PV) waveform are established on the bias electrode and the edge control electrode, respectively, to control the shape of the plasma sheath boundary formed on the substrate support surface and the edge ring. The method of claim 1 , comprising:

8. 8. The method of claim 7, wherein the shape of the plasma sheath boundary is determined at least in part by a difference in voltage pulse frequency, duration, and / or amplitude between the first pulsed voltage (PV) waveform and the second pulsed voltage (PV) waveform.

9. The plasma is generated using a radio frequency (RF) signal from an RF waveform generator; the RF signal has a frequency of about 1 MHz or greater; the RF waveform generator comprising: electrically connected to the chamber lid or a support base having a substrate support disposed thereon and configured to provide an RF signal to ignite and maintain the plasma; or electrically connected to a plasma generator assembly configured to generate an electromagnetic field used to ignite and maintain the plasma; The method of claim 1.

10. 1. A plasma processing method, comprising: (a) igniting and maintaining a plasma in a processing region of a processing chamber, the plasma including a first portion disposed between a substrate support surface of a substrate support assembly and a chamber lid, and a second portion disposed between an edge ring and the chamber lid, the substrate support assembly comprising: a first portion of a dielectric material forming the substrate support surface; a bias electrode spaced from the substrate support surface by a first portion of the dielectric material, the bias electrode being electrically connected to a first pulsed voltage (PV) waveform generator configured to establish a first pulsed voltage (PV) waveform at the bias electrode; an edge control electrode spaced apart from the center of the bias electrode, the edge control electrode being electrically connected to a second pulsed voltage (PV) waveform generator; the edge ring surrounding the substrate support surface, the edge ring including one or more edge pocket surfaces defining an edge pocket region with an at least partially elevated substrate disposed on the substrate support surface; igniting and maintaining a plasma; (b) exposing the at least partially elevated substrate to the plasma; (c) simultaneously with (b), establishing a second pulsed voltage (PV) waveform at the edge control electrode using the second pulsed voltage (PV) waveform generator to induce a bend in the shape of a plasma sheath boundary formed over the substrate and the edge ring to preferentially direct plasma generated ions toward the edge pocket surface. A plasma processing method comprising:

11. the second pulse voltage (PV) waveform established at the edge control electrodes comprises a series of repeating cycles; the waveform in each cycle has a first portion occurring during a first time interval and a second portion occurring during a second time interval; The method of claim 10 , wherein the voltage during the second time interval is lower than the voltage during at least a portion of the first time interval.

12. 11. The method of claim 10, wherein a voltage established at the bias electrode with the first pulsed voltage (PV) waveform generator is maintained between about −1 volt (V) and about 1 V for at least a portion of a period during which the at least partially lifted substrate is exposed to the plasma.

13. 12. The method of claim 11, wherein the repeating cycles of the second pulsed voltage (PV) waveform have a frequency of about 1 MHz or less.

14. Adjusting one or more characteristics of the first pulsed voltage (PV) waveform, the second pulsed voltage (PV) waveform, or both, while the first pulsed voltage (PV) waveform and the second pulsed voltage (PV) waveform are established on the bias electrode and the edge control electrode, respectively, to change the shape of the plasma sheath boundary. The method of claim 10, comprising:

15. The method of claim 14, wherein the adjusting includes increasing a frequency, duration, and / or amplitude of voltage pulses in the second pulsed voltage (PV) waveform.

16. The plasma is ignited and maintained using a radio frequency (RF) signal from an RF generator; The method of claim 10 , wherein the RF signal has a frequency of about 1 MHz or greater.

17. the substrate support assembly further comprising a support base and a second portion of dielectric material disposed on the support base; the RF generator is electrically connected to the support base; The method of claim 16 , wherein the bias electrode is spaced from the support base by a second portion of the dielectric material.

Images