Production control device, control method and control program

Abstract

To enable early recovery when a malfunction occurs in a performance control circuit. [Solution] A performance control unit 10, which is capable of reading and writing data to a memory device 43, outputs a data write request and a designation of the number of pieces of write data to the memory device 43 via an input / output control unit 20, or outputs a data read request and a designation of the number of pieces of read data to the memory device 43 via an input / output control unit 20, and the input / output control unit 20 writes the designated number of pieces of data to the memory device 43 when the performance control unit 10 is initialized before writing to the memory device 43 is completed, and reads the designated number of pieces of data from the memory device 43 when the performance control unit 10 is initialized before reading of data from the memory device 43 is completed.

Description

[Technical field]

[0001] The present invention relates to a performance control device, a control method, and a control program. [Background technology]

[0002] 2. Description of the Related Art Gaming machines such as pachinko machines in which a game is played using a gaming ball as a gaming medium are known. In an amusement hall, game balls are supplied to the game machines from the island equipment, but as the game balls circulate between the island equipment and the game machines, they rub against each other and become charged with static electricity. This static electricity can cause static noise that can affect the operation of the performance control device and its external storage device. Furthermore, noise generated by other gaming machines placed opposite one another can become a disturbance and affect the operation of the presentation control device and storage device placed behind the gaming machine. For this reason, various technologies are used in gaming machines to reduce the effects of electrostatic noise. As a related technique, for example, electromagnetic noise that has entered a control board such as a peripheral control board, a peripheral data ROM board, or a liquid crystal output board flows from the ground (GND) line of the control board such as the peripheral control board, the peripheral data ROM board, or the liquid crystal output board to the GND line of the power supply board. A technique has been disclosed in which this electromagnetic noise is removed by flowing it to the earth of the island equipment of the game hall via a frame earth board (for example, Patent Document 1). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2018-42588 A Summary of the Invention [Problem to be solved by the invention]

[0004] However, even if measures are taken to reduce the effects of noise, it is difficult to completely eliminate the effects of disturbances on the performance control device and memory device equipped in the gaming machine. One aspect of the present invention is to quickly restore a performance control device that has developed a malfunction due to the influence of an external disturbance or the like, and enable normal operation. [Means for solving the problem]

[0005] According to one aspect, the present invention provides a performance control device that includes a first control unit and a second control unit and performs synchronous communication with a storage device, the first control unit controlling Specify and a designation of the number of pieces of write data to the storage device; and an initialization unit that initializes the first control unit, wherein the second control unit comprises a monitoring unit that monitors whether the first control unit has been initialized or not, and a writing unit that, when the first control unit is initialized after outputting the write request and before the first control unit outputs the designated number of pieces of write data to the storage device, writes dummy data to the storage device in a number such that the number of pieces of write data that the first control unit has output is less than the designated number. According to one aspect of the present invention, there is provided a performance control device that includes a first control unit and a second control unit and performs synchronous communication with a storage device, the first control unit being configured to read data from the storage device. Specify and a designation of the number of the read data to the storage device; and an initialization unit that initializes the first control unit, wherein the second control unit comprises a monitoring unit that monitors whether the first control unit has been initialized, and an acquisition unit that acquires from the storage device a number of the read data that is less than the designated number when the first control unit is initialized after the output of the read request but before the first control unit has acquired the designated number of the read data. Effect of the Invention

[0006] According to one aspect of the present invention, a performance control device that has experienced a malfunction can be quickly restored to normal operation. [Brief description of the drawings]

[0007] [Figure 1] 1 is a diagram showing a schematic configuration of a gaming machine according to an embodiment of the present invention; [Diagram 2] A figure showing an example of the hardware configuration of a gaming machine including a performance control device of this embodiment. [Diagram 3] A diagram showing the functional configuration of the performance control device of this embodiment. [Figure 4] A diagram explaining communication between the performance control unit and the memory unit during the writing process when the performance control unit is not reset. [Diagram 5] A diagram explaining communication between the performance control unit and the memory unit or external storage device during a read process when the performance control unit is not reset. [Figure 6] 13 is a diagram illustrating communication between the performance control unit and the memory unit during a writing process when the performance control unit is reset. FIG. [Figure 7] 13 is a diagram illustrating communication between the performance control unit and a memory unit or an external storage device during a read process when the performance control unit is reset. FIG. [Figure 8] 13 is a flowchart showing a process performed by an input / output control unit when writing data. [Figure 9] 13 is a flowchart showing a process performed by an input / output control unit when reading data. [Figure 10] FIG. 1 is a block diagram illustrating an embodiment of a computing device. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0008] Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings. FIG. 1 is a diagram showing a schematic configuration of a gaming machine according to this embodiment. As shown in FIG. 1, the gaming machine 100 includes a main control board 1, a performance control board 2A, an external storage device 3, a display device 4, a sound emitting device 5, and a lighting device 6. The main control board 1 is equipped with a main control device (main CPU). The performance control board (sub-board) 2A is equipped with a performance control device 2 (sub-CPU). The gaming machine 100 is, for example, a pachinko gaming machine in which a game is played using gaming balls as a gaming medium. In this embodiment, the performance control device 2 and the external storage device 3 are collectively referred to as a performance control system. The main control board 1 and the performance control board 2A, the performance control board 2A and the external storage device 3, and the performance control board 2A, the display device 4, the sound emission device 5, and the lighting device 6 are each connected so that they can communicate with each other. However, the communication between the main control board 1 and the performance control board 2A is a one-way communication in which only input of commands from the main control board 1 to the performance control device 2 is permitted. Data or commands cannot be input from the performance control device 2 to the main control board 1.

[0009] In the case where the gaming machine 100 is a pachinko gaming machine, when the gaming medium shot out into the gaming area by the launching device enters a start winning hole provided in the gaming area, the main control device performs a lottery for a pattern using random numbers and determines whether or not there is a jackpot based on the result of this lottery. The main control board 1 outputs a command to the performance control device 2 to specify the time and pattern of symbol variation based on the result of the jackpot determination. Alternatively, if no start winning occurs for a certain period of time, the main control board 1 puts the gaming machine 100 into a customer waiting state (standby state) and inputs a command to the performance control device 2 indicating that the gaming machine has entered the customer waiting state. If a jackpot is determined to have been won in the jackpot determination, after the pattern change has ended, the game medium enters the opened attacker, and the jackpot is awarded by paying out prize balls.

[0010] The performance control device 2 is a sub-CPU for the main CPU of the main control board 1, and has the functions of a VDP (Video Display Processor). The term VDP originally refers to a processor that controls video output. However, the performance control device 2 of this embodiment is an SoC (System on Chip) that integrates the image control circuit, audio control circuit, lamp control circuit, and control device (performance control CPU) shown in Figure 2. The performance control device 2 selects a performance to be performed using performance devices such as a display device 4, a sound emitting device 5, and a lighting device 6 based on a command input from the main control board 1, and controls the execution of the selected performance during a specified variable time or a performance while waiting for customers. The display device 4 is, for example, a display device such as an LCD (Liquid Crystal Display), a PDP (Plasma Display Panel), or an OLED (Organic Light Emitting Diode). The sound emitting device 5 is, for example, a speaker. The lighting device 6 is, for example, a light-emitting device such as an LED (Light Emitting Diode).

[0011] The external storage device 3 is an external storage device connected to a memory I / F 204 (FIG. 2) provided in the performance control device 2. The external storage device 3 stores image data, sound data, and lighting data used for game effects, customer waiting effects (standby effects), and effects during a big win. The image data includes moving image data. The performance control board 2A is capable of outputting richly expressive performances using images and sounds by reading performance data from the external storage device 3 in accordance with the progress of the game.

[0012] Based on commands input from the main control board 1, the performance control device 2 reads performance data from the external storage device 3 or an internal storage device 203 (FIG. 2) described later, and performs various types of processing on the read performance data. The performance control device 2 performs drawing processing on the read image data and outputs the data to the display device 4 to display the image (image processing). The performance control device 2 also performs playback processing on the read audio data and outputs the data to the sound emitting device 5 to output the audio (audio processing). Furthermore, the performance control device 2 outputs the read lighting data to the lighting device 6 to light the lamp (lighting processing). In this embodiment, a request made by each performance control circuit 201 (FIG. 2) included in the performance control device 2 to the external storage device 3 or the internal storage device to read performance data is referred to as a "read request."

[0013] The performance control device 2 also performs processing to write performance data after processing (e.g. image processing) in each performance control circuit 201 to the internal storage device 203 based on a command input from the main control board 1. Note that in this embodiment, data is only read from the external storage device 3, and data is not written to the external storage device 3. In this embodiment, a request from each performance control circuit 201 to write data to the internal storage device 203 is referred to as a "write request."

[0014] A "read request" includes a specification of the read data, an address of the read data, and a specification of the size of the read data. The size of the read data is expressed by a burst size and a burst length in the AXI (Advanced eXtensible Interface) bus specification, which will be described later. The burst size is the number of bytes output during one burst transfer process. The burst length is the number of burst transfer processes required to be executed in a read process. In other words, the burst length is the number of burst-sized data (unit data) to be read. Therefore, the size of the read data is specifically the burst size x burst length. The size of the read data is information for transmitting and receiving data via the AXI bus included in the performance control device 2. That is, the "read request" includes the specification of the data to be read and the number of unit data. The data to be read can be specified by the address where the desired data is located in the storage area of ​​the external storage device 3 or the internal storage device 203.

[0015] In addition to specifying the write data, the "write request" also includes a specification of the address of the write data in the internal storage device 203 and the size of the write data. The size of the write data is expressed by a burst size and a burst length, similar to the case of the read data described above. As with read data, the burst size is the number of bytes output during one burst transfer process, and the burst length is the number of burst transfer processes required to be executed in a write process. In other words, the burst length is the number of burst-sized data (unit data) to be written. Therefore, the size of the write data is specifically the burst size x burst length. The size of the write data is information for transmitting and receiving data via the AXI bus. That is, a "write request" includes a specification of the data to be written and the number of unit data. The data to be written can be specified by an address in the internal storage device 203 where the desired data is located.

[0016] FIG. 2 is a diagram showing an example of the hardware configuration of a gaming machine including the performance control device of this embodiment, and is a diagram showing the performance control device of FIG. 1 in detail. In FIG. 2, the performance control device 2 includes an image control circuit 201a, a sound control circuit 201b, and a lamp control circuit 201c. The image control circuit 201a is a circuit that executes image processing using data acquired from the external storage device 3 or the internal storage device 203, and is connected to the display device 4. The image control circuit 201a functions as the image control unit 10a in FIG. The audio control circuit 201b is a circuit that executes audio processing using data acquired from the external storage device 3 or the internal storage device 203, and is connected to the sound emitting device 5. The audio control circuit 201b functions as the audio control unit 10b in FIG. The lamp control circuit 201c is a circuit that executes lighting processing using data acquired from the external storage device 3 or the internal storage device 203, and is connected to the lighting device 6. The lamp control circuit 201c functions as the lamp control unit 10c in FIG.

[0017] The performance control device 2 may also include a motor control circuit as the performance control circuit 201 that controls the motors that drive the movable props, attackers, electric tulips, etc. used in the performance. In this case, the motor control circuit is connected to the bus 207 and performs the drive process of the motor using the data acquired from the external storage device 3. In the following description, when there is no particular distinction between the image control circuit 201a, the sound control circuit 201b, and the lamp control circuit 201c, they are also simply referred to as the performance control circuit 201.

[0018] The performance control device 2 also includes an image input / output control circuit 202a, an audio input / output control circuit 202b, and a lamp input / output control circuit 202c, which correspond to the image control circuit 201a, the audio control circuit 201b, and the lamp control circuit 201c, respectively. Moreover, the image input / output control circuit 202 a , the audio input / output control circuit 202 b , and the lamp input / output control circuit 202 c are also simply referred to as input / output control circuits 202 . The input / output control circuit 202 is a circuit that controls the transfer of data between each of the performance control circuits 201 and the internal storage device 203 and the external storage device 3. The input / output control circuit 202 functions as the input / output control unit 20 in FIG. As will be explained below, when the performance control circuit 201 is reset due to a malfunction, the input / output control circuit 202 writes the necessary data to the internal memory device 203 and reads it from the internal memory device 203 or the external memory device 3, thereby enabling early recovery without resetting the entire performance control device 2.

[0019] The performance control device 2 also includes an internal memory device 203 , a memory I / F 204 , a general control device 205 , and an arbitration circuit 206 . The internal storage device 203 is a VRAM or DRAM provided inside the performance control device 2. The internal storage device 203 may be a DRAM provided on the performance control board 2A that implements the performance control device 2. The internal storage device 203 functions as the storage unit 43 in FIG. The memory I / F 204 is an interface that connects the performance control device 2 and the external storage device 3, and is an input / output interface used when communicating data between the performance control device 2 and the external storage device 3.

[0020] The performance control device 2 is connected to the external storage device 3 via the memory I / F 204 . The memory I / F 204 executes initialization of communication with the external storage device 3 to perform link-up processing, and controls communication between the performance control device 2 and the external storage device 3. The memory I / F 204 functions as the input / output unit 41 in FIG. The overall control device 205 is a processor that controls the entire performance control device 2, and functions as the overall control unit 40 in FIG. The arbitration circuit 206 is a circuit that performs processing to allocate the right to use the bus 207 (AXI bus) to a plurality of masters (here, each of the performance control circuits 201) based on the AXI protocol, and functions as the arbitration unit 42 in FIG. The arbitration circuit 206 monitors whether writing of the number of data items specified in the "write request" has been completed, and when writing is completed, releases the bus 207 and accepts a request for allocation of the right to use the bus 207. The arbitration circuit 206 also monitors whether or not the reading of the number of data items specified in the "read request" from the bus 207 has been completed, and when the reading is completed, releases the bus 207 and accepts a request for allocation of the right to use the bus 207.

[0021] The input / output control circuit 202 , the memory I / F 204 , the overall control device 205 and the arbitration circuit 206 are connected by a bus 207 . The bus 207 is an AXI bus conforming to the AXI specifications, and communicatively connects each component such as the performance control circuit 201, the input / output control circuit 202, and the general control device 205 inside the performance control device 2. Each performance control circuit 201 is not directly connected to the bus 207, but is connected to the bus 207 via each input / output control circuit 202.

[0022] FIG. 3 is a diagram showing the functional configuration of the performance control device of the present embodiment. FIG. 3 shows the functional configuration of a performance control device corresponding to the hardware configuration of FIG. As shown in FIG. 3, the performance control device 2 includes an image control unit 10a, a sound control unit 10b, and a lamp control unit 10c. The performance control device 2 also includes an input / output control unit 20 a , an input / output control unit 20 b , an input / output control unit 20 c , a general control unit 40 , an input / output unit 41 , an arbitration unit 42 , and a memory unit 43 . 2. The image control unit 10a corresponds to the image control circuit 201a in FIG. 2, the audio control unit 10b corresponds to the audio control circuit 201b in FIG. 2, and the lamp control unit 10c corresponds to the lamp control circuit 201c in FIG. 2. The input / output control unit 20a corresponds to the input / output control circuit 202a in FIG. 2, the input / output control unit 20b corresponds to the input / output control circuit 202b in FIG. 2, and the input / output control unit 20c corresponds to the input / output control circuit 202c in FIG. In the following description, when there is no particular distinction between the image control unit 10a, the audio control unit 10b, and the lamp control unit 10c, they are also simply referred to as the performance control unit 10. When there is no particular distinction between the image input / output control unit 20a, the audio input / output control unit 20b, and the lamp input / output control unit 20c, they are also simply referred to as the input / output control units 20.

[0023] The overall control unit 40 corresponds to the overall control device 205 in Fig. 2, and controls the entire performance control device 2. The overall control unit 40 also determines the performance in response to commands input from the main control board 1, and requests each performance control unit 10 to perform the necessary control. The input / output unit 41 corresponds to the memory I / F 204 in FIG. 2, executes a process of initializing communication with the external storage device 3 to establish a link-up, and controls communication with the external storage device 3. The memory unit 43 corresponds to the internal memory device 203 in FIG. 2, and is a DRAM or VRAM inside the performance control device 2, or a DRAM on the performance control board 2A. The arbitration unit 42 corresponds to the arbitration circuit 206 in FIG.

[0024] The input / output control unit 20 controls the input / output of data between the performance control unit 10 and the external storage device 3 or the internal storage device 203 (storage unit 43). The input / output control unit 20 has a characteristic configuration in the performance control device 2 of this embodiment. The performance control unit 10 is an example of a first control unit. The input / output control unit 20 is also an example of a second control unit.

[0025] Each performance control unit 10 will be described. The image control unit 10a includes a request unit 11a, an image processing unit 12a, an initialization unit 13a, and an input / output unit 14a. The image control unit 10a controls image processing in the performance control device 2 in response to a request from the overall control unit 40. The request unit 11a outputs a "read request" to the input / output control unit 20a, which requests the reading of image data for performance from the external storage device 3 or the memory unit 43, or a "write request" to the input / output control unit 20a, which requests the writing of data to the memory unit 43. The image processing unit 12a executes image processing for drawing an image using image data acquired from the external storage device 3 or the storage unit 43 via the input / output control unit 20a. The initialization unit 13a performs initialization processing for the image control unit 10a when a malfunction occurs in the operation of the image control unit 10a. The input / output unit 14a processes input and output of data with the external storage device 3 and the storage unit 43 via the input / output control unit 20a. More specifically, the input / output unit 14a accepts input of the number of data items specified in a "read request" from the external storage device 3 or the storage unit 43, and outputs the number of data items specified in a "write request" to the storage unit 43.

[0026] The audio control unit 10b includes a request unit 11b, an audio processing unit 12b, an initialization unit 13b, and an input / output unit 14b. The audio control unit 10b controls audio processing in the performance control device 2 in response to a request from the overall control unit 40. The request unit 11b outputs a "read request" requesting the reading of sound data for performance from the external storage device 3 or the memory unit 43, and a "write request" requesting the writing of data to the memory unit 43, to the input / output control unit 20b. The audio processing unit 12b executes image processing for reproducing audio using audio data acquired from the external storage device 3 or the storage unit 43 via the input / output control unit 20b. The initialization unit 13b performs initialization processing for the voice control unit 10b when a malfunction occurs in the operation of the voice control unit 10b. The input / output unit 14b processes input and output of data to and from the external storage device 3 and the storage unit 43 via the input / output control unit 20b. More specifically, the input / output unit 14b accepts input of the number of data items specified in a "read request" from the external storage device 3 or the storage unit 43, and outputs the number of data items specified in a "write request" to the storage unit 43.

[0027] The lamp control unit 10c includes a request unit 11c, a lighting processing unit 12c, an initialization unit 13c, and an input / output unit 14c. The lamp control unit 10c controls the lighting process in the performance control device 2 in response to a request from the general control unit 40. The request unit 11c outputs a "read request" for requesting the reading of lighting data for effects from the external storage device 3 or the memory unit 43, and a "write request" for requesting the writing of data to the memory unit 43, to the input / output control unit 20c. The lighting processing unit 12c executes lighting processing for lighting the lamp using lighting data acquired from the external storage device 3 or the storage unit 43 via the input / output control unit 20c. The initialization unit 13c performs initialization processing for the lamp control unit 10c when a malfunction occurs in the operation of the lamp control unit 10c. The input / output unit 14c processes input and output of data with the external storage device 3 and the storage unit 43 via the input / output control unit 20c. More specifically, the input / output unit 14c accepts input of the number of data items specified in a "read request" from the external storage device 3 or the storage unit 43, and outputs the number of data items specified in a "write request" to the storage unit 43. In the following description, it is assumed that the performance control unit 10 that sends the request to the external storage device 3 is the image control unit 10a. However, the sound control unit 10b and the lamp control unit 10c can also perform similar control.

[0028] The input / output control unit 20 will now be described. The input / output control unit 20a includes an input / output unit 21, a monitoring unit 22, a writing unit 23, a discarding unit 24, and a storage unit 25. When a “write request” including designation of write data and the number of pieces of write data, and a “read request” including designation of read data and the number of pieces of read data are input from the image control unit 10a, the input / output unit 21 stores the request in the storage unit 25. In addition, the input / output unit 21 outputs the “write request” and the “read request” to the external storage device 3 and the storage unit 43.

[0029] The monitor unit 22 monitors whether the image control unit 10a has started the initialization process. When the monitor unit 22 detects that the image control unit 10a has been initialized, the writing unit 23 judges whether data is being written from the image control unit 10a to the storage unit 43. If the image control unit 10a is writing data to the storage unit 43 by outputting a "write request" and the number of pieces of data specified in the "write request" has not been written, the writing unit 23 writes dummy data to the storage unit 43 in a quantity that makes up for the number of pieces of data already written to the storage unit 43 that is less than the specified number. The dummy data may be, for example, data stored in the storage unit 25. The written data includes data that has already been output from the image control unit 10a to the bus 50 and has not been written to the storage unit 43. For example, if a "write request" specifies writing of eight pieces of data, two pieces of data have already been written to storage unit 43, and two pieces of data are waiting to be written on bus 50, writing unit 23 will write four pieces of dummy data to storage unit 43. The number of pieces of dummy data that have not yet been output to bus 50 can be known by counting each time data is written to bus 50.

[0030] The discard unit 24 determines whether data is being read from the external storage device 3 or the storage unit 43 when the monitor unit 22 detects that the image control unit 10a has been initialized. When data is being read by outputting a "read request" and the number of data specified in the "read request" has not been transferred to the image control unit 10a, the discarding unit 24 obtains and discards from the external storage device 3, the memory unit 43, or the bus 50 the amount of data that has been read by the image control unit 10a that falls short of the specified number. A case where the specified number of data items have not been transferred includes a case where the specified number of data items have not been output from the external storage device 3 or the storage unit 43, or a case where data being transferred is stuck on the bus 50. In other words, the discard unit 24 acquires and discards all of the data stuck on the bus 50 and the data that the external storage device 3 or the storage unit 43 will output to the bus 50 from now on. A flag such as LAST is set at the end of the data acquired from the bus 50, and by referring to this, it is possible to know that there is the last data to be read from the bus 50. When the last data has been read, the data that has been read can be discarded.

[0031] The storage unit 25 includes a storage area 25a and a storage area 25b. The storage unit 25 stores the dummy data in the storage area 25a, and stores the "write request" and the "read request" input from the image control unit 10a in the storage area 25b. The input / output control unit 20b and the input / output control unit 20c have the same configuration as the input / output control unit 20a, except that the targets of monitoring by the monitoring unit 22 are the voice control unit 10b and the lamp control unit 10c, and the target "read requests" and "write requests" are from the voice control unit 10b and the lamp control unit 10c, and therefore their explanation is omitted.

[0032] The dummy data may be any data, such as a random value or a fixed value, as long as it is identifiable as dummy data. The dummy data may be, for example, all-zero data. The dummy data itself is certainly sent to the storage unit 43 and stored in the storage unit 43, but the dummy data does not write substantial information to the storage unit 43. What is important is the number of dummy data items output to the storage unit 43 and the bus 50 to establish the AXI protocol. If the required number of dummy data items are to be generated randomly, there is no need to provide the storage unit 25 with the storage area 25a.

[0033] During normal operation when no malfunction occurs in the performance control unit 10, the input / output control unit 20 stores the “read request” and the “write request” output from the performance control unit 10 in the memory area 25b and then relays them to the bus 50. The input and output of data between the external storage device 3 and the storage unit 43 caused by "read requests" and "write requests" is controlled by the performance control unit 10 itself, and the processing of the writing unit 23 and the discarding unit 24 are bypassed and in a non-functioning state. However, the relay of data between the performance control unit 10 and the external storage device 3 or the storage unit 43 can be controlled by the input / output unit 21 of the input / output control unit 20. On the other hand, if the performance control unit 10 is initialized due to a malfunction, the input / output control unit 20 (write unit 23, discard unit 24) takes over and controls the input and output of data between the external storage device 3 and the memory unit 43. After the initialization of the performance control unit 10 is complete, the input / output control unit 20 processes unprocessed data (obtains data from the external storage device 3 and the memory unit 43 from the bus 50 and discards it, and outputs dummy data to the memory unit 43), establishes the AXI protocol, and the performance control device 2 returns to its normal state. Furthermore, the input / output control unit 20 may process unprocessed data in parallel with the initialization of the performance control unit 10 and establish the AXI protocol. In this case, since the establishment of the AXI protocol opens the bus 50, communication between other components other than the performance control unit 10 being initialized is possible even while the performance control unit 10 is being initialized. After that, once the initialization of the performance control unit 10 is complete, the performance control device 2 returns to the normal state. In other words, since the performance control device 2 can establish the AXI protocol and open the bus 50 even while the performance control unit 10 is being initialized, communication between other components other than the performance control unit 10 being initialized can be continued. The following will provide a more detailed explanation using Figures 2 and 3, but the explanation will basically be based on the configuration of the functional parts shown in Figure 3, except when referring to the circuit configuration of the performance control device.

[0034] [Communication method between production control device and external storage device] Here, a communication method between the performance control device 2 and the external storage device 3 will be described. The performance control device 2 includes an input / output control unit 20 that controls communication between the performance control device 2 and the external storage device 3 and relays communication between each performance control unit 10 and the external storage device 3 . The external storage device 3 is a storage device that performs synchronous communication with the performance control device 2, and is, for example, an SSD (Solid State Drive). In the following description, it is assumed that the external storage device 3 is an SSD. The external storage device 3 includes a storage area 3a formed of, for example, a NAND flash memory, and a controller 3b that controls reading and writing from and to the storage area 3a, as well as communication between the performance control device 2 and the external storage device 3. If the handshake is successful, the controller 3b of the external storage device 3 reads the data requested by the input / output control unit 20 from the storage area 3a and transfers the data to the input / output control unit 20.

[0035] The following describes handshake communication between the I / O control unit 20 and the external storage device 3. If there is no disturbance and the handshake is successful, the I / O control unit 20 can receive the requested data normally. If the handshake fails due to the disturbance or the like, the I / O control unit 20 cannot receive the requested data normally. A successful handshake means that the receiving side has successfully received a signal from the sending side indicating that data is being sent, and that the sending side has successfully received a signal from the receiving side indicating that data sent by the sending side has been received. A handshake failure occurs when the sender and receiver are unable to receive either the signal indicating that data is being sent, the signal indicating that data has been received, or the data itself. The external storage device 3 employs SATA (Serial ATA) as a communication interface. Like other high-speed serial communications, SATA requires communication negotiation to establish communication. Communication negotiation is a process for ensuring the reliability of communication.

[0036] Here, in this embodiment, communication negotiation is executed between the performance control device 2 and the external storage device 3. The communication negotiation is a process that includes initialization of communication and adjustment of communication speed. The communication initialization is a process for establishing communication between the performance control device 2 and the external storage device 3. The communication initialization is executed when the power of the gaming machine 100 is turned on or when at least one of the performance control device 2 and the external storage device 3 is restarted. In the communication initialization process, the performance control device 2 and the external storage device 3 each independently start sending an initialization signal. Then, when the performance control device 2 and the external storage device 3 receive each other's initialization signal, they transition to the next state and establish communication by repeating the process of sending another signal multiple times (for example, the OOB sequence of SATA communication). The initialization signal is, for example, the COMINIT, COMORESET, COMWAKE, etc. of the OOB sequence used to establish communication. The adjustment of the communication speed is a process of adjusting the communication speed between the performance control device 2 and the external storage device 3 after communication is established (for example, speed negotiation of SATA communication).

[0037] The gaming machine 100 of this embodiment performs SATA communication between the performance control device 2 and the external storage device 3. Therefore, the gaming machine 100 executes communication negotiation between the performance control device 2 and the external storage device 3 after the power is turned on or when at least one of the performance control device 2 and the external storage device 3 is restarted. It should be noted that the input / output unit 21 of the performance control device 2 and the controller 3b of the external storage device 3 control communications, including communications negotiation, between the performance control device 2 and the external storage device 3.

[0038] The communication negotiation that is carried out when the gaming machine 100 is powered on or when at least one of the performance control device 2 and the external storage device 3 is restarted will be described. When the gaming machine 100 is powered on or the performance control device 2 is restarted, the voltage input to the performance control device 2 rises and operation stabilizes, and the performance control device 2 executes a reset process. Then, when the reset of the performance control device 2 is released, the performance control device 2 starts an initialization process for communication with the external storage device 3. Resetting the performance control device 2 includes, for example, initialization of flip-flops (FFs), registers, and the like. In addition, when the power supply of the gaming machine 100 is turned on or the external storage device 3 is restarted, the voltage input to the external storage device 3 rises and the operation becomes stable, and the external storage device 3 executes a reset process. Then, when the reset of the external storage device 3 is released, the external storage device 3 starts an initialization process of the communication with the performance control device 2. In the initialization process, the input / output control unit 20 of the performance control device 2 transmits a COMRESET signal to the external storage device 3. When the external storage device 3 receives this COMRESET signal, it transmits a COMINIT signal to the performance control device 2. When the performance control device 2 receives the COMINIT signal, it transmits a COMWAKE signal to the external storage device 3. When the performance control device 2 receives the COMWAKE signal, it transmits the COMWAKE signal to the external storage device 3. If these negotiations are performed normally, the initialization of communication is completed, communication is established between the performance control device 2 and the external storage device 3, and communication between the two devices becomes possible. After that, the performance control device 2 and the external storage device 3 perform speed negotiation to adjust their communication speeds.

[0039] After the gaming machine 100 is powered on or the performance control device 2 is restarted, when communication negotiation with the external storage device 3 is completed, the performance control device 2 reads out the performance control program from the external storage device 3. The performance control device 2 completes startup by executing the read program. As a result, the performance control device 2 finishes initialization for receiving commands from the main control board 1, and goes into a standby state in which it can receive commands from the main control board 1. The performance control device 2 starts performance control in response to commands from the main control board 1. In this embodiment, the series of processes in which the performance control device 2 starts performance control after it has restarted is called a system reset.

[0040] [Data transfer method within the performance control device] A communication method between the input / output control unit 20 and the external storage device 3 and storage unit 43 using the bus 207 (bus 50) shown in FIGS. 2 and 3 will be described. The bus 207 (bus 50) employs the AXI protocol as a communication protocol. The AXI protocol is based on handshaking between devices. The AXI protocol defines five channels between a master and a slave: two channels for read transactions (read address and read data), and three channels for write transactions (write address, write data, and write response). In this embodiment, the performance control unit 10 of the performance control device 2 reads performance data from the external storage device 3 and storage unit 43 via the input / output control unit 20 , and writes the data to the storage unit 43 . In a read transaction, the master transmits a read address and a burst length (LENGTH) to the slave. This is the "read request" of this embodiment. In a write transaction, the master transmits a write address and a burst length (LENGTH) to the slave, which is the "write request" of this embodiment.

[0041] The burst length is a value that indicates how many unit data transfers are requested of the slave when data of the burst size specified in the AXI protocol is regarded as one unit data. For example, when the master requests 128-bit data from the slave, if the unit data is 32 bits, it requests the reading of four unit data since 128 / 32=4. In this case, the requested data is transferred when four unit data are transferred from the slave to the master. For example, when the master requests 140-bit data from the slave, if the unit data is 32 bits, it requests five unit data pieces, including four unit data pieces corresponding to 128 bits, plus one unit data piece containing 18 bits as a remainder. In this case, the requested data is transferred when the five unit data pieces are transferred from the slave to the master. The number of data units is specified in the request by a value called LENGTH. LENGTH is set to the burst length minus 1. Therefore, when requesting four data units, LENGTH = 3 is specified. When the master receives the number of unit data specified by the request, it determines that the requested data has been received normally.

[0042] In the AXI protocol, a read transaction is performed in the following steps (1) to (5). (1) The master outputs a VALID signal indicating that it is making a read request to the slave (sets the signal to HIGH). (2) The slave outputs a READY signal to the master (sets the signal to LOW) to indicate that it is ready to accept a read request. (3) While the slave is outputting a VALID signal to the master indicating that the read data is valid (turning the signal ON), the target data is sent to the master. (4) The master can accept data while the master has the READY signal ON, which indicates that it is ready to accept data. (5) The slave outputs a signal to the master indicating that the read requested data has been sent. In the AXI protocol, the master reads data from the slave through this handshake procedure using the READY and VALID signals. A write transaction can be similarly performed in the following procedure. (1) The master outputs a VALID signal to the slave indicating that it is making a write request (sets the signal to HIGH). (2) The slave outputs a READY signal to the master (sets the signal to LOW) to indicate that it is ready to accept a write request. (3) While the slave is outputting a VALID signal to the master indicating that the write data is valid (turning the signal ON), the target data is sent to the master. (4) The master can accept data while the master has the READY signal ON, which indicates that it is ready to accept data. (5) The slave outputs a signal to the master indicating that the requested write data has been sent.

[0043] In FIG. 3, the input / output control unit 20 corresponds to the master of the AXI protocol, the external storage device 3 and the storage unit 43 correspond to the slaves, and the input / output control unit 20 and the external storage device 3 communicate with each other via a bus 50 according to the AXI protocol. 3 shows a many-to-many configuration having multiple masters for multiple slaves. However, the present invention is not limited to this, and may be a one-to-many configuration in which multiple masters are connected to one slave via the bus 50. In the case of a many-to-many configuration, for example, the image control unit 10a and the external storage device 3, the audio control unit 10b and the storage unit 43, etc. can share the bus 50 and simultaneously communicate in accordance with the AXI protocol. By providing an input / output control unit 20 for each performance control unit 10, the processing of the input / output control unit 20 of this embodiment can be performed independently and in parallel for each performance control unit 10. In that case, even if any of the image control unit 10a, audio control unit 10b, and lamp control unit 10c is reset, the other performance control units 10 can communicate in accordance with the AXI protocol without being affected by communication with the paired slave.

[0044] The basic configuration of the performance control device 2 of this embodiment has been described above, and will be explained in more detail below. The external storage device 3, storage unit 43, and performance control device 2 of the gaming machine 100 may be affected by electrostatic noise caused by static electricity generated on the gaming ball, noise generated by other gaming machines arranged back to back, and other disturbances. The external storage device 3 has a long signal line between it and the performance control device 2 on the performance control board 2A, and is connected to the performance control board 2A via a connector. As a result, data transfer between the performance control board 2A and the external storage device 3 is easily affected by disturbances such as electrostatic noise. The same problem may occur with the DRAM on the performance control board 2A and the performance control device 2. Therefore, when data used by the performance control unit 20 is obtained from the external storage device 3 or storage unit 43 (DRAM on the performance control board 2A), electrostatic noise may be applied to the transmission path between the performance control device 2 and the external storage device 3, destroying the data being transferred.

[0045] Even when data is transferred from memory unit 43 (DRAM or VRAM) in performance control device 2, strong electrostatic noise may not always have any effect on the data being transferred, and the data may be corrupted. As a result, reading of the number of pieces of data requested in the "read request" from the external storage device 3 or the storage unit 43 may not be completed. Writing of the number of pieces of data requested in the "write request" to the storage unit 43 may not be completed. In that case, when reading data from the external storage device 3 or the storage unit 43, there is a problem that the performance control unit 10 that requested the data continues to wait for the data. This is because, under the AXI protocol, a request once made cannot be canceled. When this happens, it is necessary to restart the entire performance control system that includes the performance control device 2 and the external storage device 3 (a system reset).

[0046] Restarting the performance control system involves restarting the external storage device 3, restarting the performance control device 2, and then negotiating communications between the performance control device 2 and external storage device 3 after the restart. After that, the performance control device 2 reads out the performance control program from the external storage device 3. The performance control device 2 then executes the read program to complete startup, and goes into a standby state in which it can receive commands from the main control board 1. This completes the restart of the performance control system. During the restart of the performance control system, no performance image is displayed on the display device 4, and a blackout or blue screen appears. No sound is output from the sound emitting device 5, and the LED of the lighting device 6 does not light up. As described above, restarting the performance control system takes a relatively long time because it includes, in addition to restarting the external storage device 3 and communication negotiation, the processing until the performance control device 2 enters a reception standby state in which it can receive commands from the main control board 1. Therefore, when the performance control system is restarted, it takes time to restore the performance control system and resume screen display and audio output. In the gaming machine 100, there are cases where impressive effects are performed on the player by going dark on the screen or muting the sound effects, and a blackout caused by restarting the effect control system is undesirable as it may give the player erroneous information.

[0047] In contrast, by inputting dummy data to the performance control unit 10, the request is completed without any problem in terms of the protocol. Therefore, the performance control unit 10 that made the request does not continue to wait for data. In the case of data transfer from the external storage device 3, the performance control system can be restored and the performance required by the main control board 1 can be performed simply by restarting the external storage device 3 and negotiating communication between the performance control device 2 and the external storage device 3. In the case of data transfer from the storage unit 43, the problem can be solved by simply inputting dummy data to the performance control unit 10. There is no need to restart the entire performance control device 2, and each performance control unit can continue processing. The time required to restart the entire performance control device 2 is no longer necessary, and the time it takes for the performance control system to recover to normal operation can be reduced. However, it cannot be denied that inputting dummy data into the performance control unit 10 may cause a malfunction in the performance control unit 10.

[0048] Even if the reading of the number of pieces of data requested in the "read request" is completed, data (programs or content data) corrupted by electrostatic noise may be input to the performance control unit 10, which may cause a malfunction in the operation of the performance control unit 10. In this case, it is necessary to initialize the entire performance control system. Furthermore, regardless of electrostatic noise, a malfunction in the performance control program may cause a malfunction in the operation of the performance control unit 10. In such a case, it is also necessary to initialize the entire performance control system. When initializing the entire performance control system, it takes time to restore normal operation, including the above-mentioned communication negotiations.

[0049] For a quick recovery, it is possible to initialize (reset) only the defective performance control unit 10 to avoid initializing the entire performance control system. However, when the initialized performance control unit 10 is executing a read request and has not finished reading the number of data specified in the "read request", the arbitration unit 42 cannot release the bus 50 to accept the next request (read request, write request). Since the specified number of data has not been read from the external storage device 3 and the storage unit 43, they cannot accept the next request (read request, write request).

[0050] Furthermore, when a write request is being executed by the initialized performance control unit 10 and writing of the number of pieces of data specified in the "write request" is not completed, data accumulates on the bus, so arbitration unit 42 cannot release bus 50 to accept the next request. Furthermore, since the specified number of pieces of data has not been written to memory unit 43, it cannot accept the next request (read request, write request). When the performance control unit 10 is reset, the handshake (the above-mentioned read transaction and write transaction) in the AXI protocol between the performance control unit 10 and the input / output control unit 20 is not completed. In the AXI protocol, the master continues to wait until all requested unit data have been transferred to the slave and the handshake is completed. In the AXI protocol, the transfer cannot be aborted before the specified number of unit data has been transferred. The performance control unit 10 during data transfer continues to occupy communication with the external storage device 3 or the storage unit 43 on the bus 50. As a result, other performance control units 10 cannot read or write data to the external storage device 3 or the storage unit 43 in use. It is now difficult for the performance control device 2 to control the performance normally. In this case, too, a process is executed to restart the entire performance control system, so the time it takes to restore normal operation will be longer than if only initialization of the performance control unit 10 in which the malfunction has occurred is executed.

[0051] In contrast, in the present embodiment, the constraints of the AXI protocol are satisfied, the storage unit 43 is put into a state in which it can accept the next request, and the bus 50 is released. Therefore, regardless of the state of the writing operation of the image control unit 10a, for example, the initialization unit 13a immediately executes the initialization process when a problem occurs in the image control unit 10a, and the entire performance control system can be restored to normal operation. This reduces the time it takes for the system to restore to normal operation. Since the arbitration unit 42 and the storage unit 43 receive the specified number of data, they do not have to continue waiting for data transmission. Also, the AXI protocol constraints are satisfied, and the memory unit 43 or the external storage device 3 is put into a state in which it can accept the next request, and the bus 50 is released. Therefore, regardless of the state of the read operation of the image control unit 10a, the initialization unit 13a immediately executes initialization processing at the time when a malfunction occurs in the image control unit 10a, and the entire performance control system can be restored to normal operation. This reduces the time it takes for the system to restore to normal operation. The arbitration unit 42 does not continue to wait for the image control unit 10a to acquire data after determining that the specified number of data has been transferred. Therefore, even if a problem occurs in image control unit 10a, the entire performance control system can be quickly restored by simply initializing image control unit 10a, without having to initialize the entire performance control system.

[0052] FIG. 4 is a diagram illustrating communication between the performance control unit and the storage unit in the write process when the performance control unit is not reset. The input / output control unit 20 acts as a host in AXI protocol communication with the storage unit 43 and SATA communication with the external storage device 3, and acts as a slave in AXI protocol communication with the performance control unit 10. The following description will be given with reference to FIG. When the gaming machine 100 is powered on and communication negotiation between the performance control device 2 and the external storage device 3 is completed, the performance control device 2 reads out the performance control program from the external storage device 3. The performance control device 2 then executes the read program to complete startup and enters a standby state in which it can receive commands from the main control board 1.

[0053] When the performance control device 2 receives a command from the main control board 1, the performance control unit 10 makes a "write request" to the input / output control unit 20 specifying the number of pieces of performance data to be written (4 pieces) according to the AXI protocol (S11). The input / output control unit 20 requests the memory unit 43 to write the specified number of pieces of data (4 pieces) to the address specified in the "write request" (S21). The performance control unit 10 outputs the first data to the input / output control unit 20 (S12), and the input / output control unit 20 outputs the requested data to the storage unit 43 (S22). The performance control unit 10 outputs the second data to the input / output control unit 20 (S13), and the input / output control unit 20 outputs the requested data to the storage unit 43 (S23). The performance control unit 10 outputs the third data to the input / output control unit 20 (S14), and the input / output control unit 20 outputs the requested data to the storage unit 43 (S24). The performance control unit 10 outputs the fourth data to the input / output control unit 20 (S15), and the input / output control unit 20 outputs the requested data to the storage unit 43 (S25). When the writing of the number of data items (four) specified in the "write request" (data transfer to the memory unit 43) is completed, the AXI protocol ends normally, and the performance control unit 10 can again execute the write request and read request.

[0054] FIG. 5 is a diagram for explaining communication between the performance control unit and the storage unit or an external storage device (not shown) in the read process when the performance control unit is not reset. Description will be given with reference to FIG. 4, when the performance control device 2, which is in a reception waiting state, receives a command from the main control board 1, the performance control unit 10 makes a "read request" to the input / output control unit 20 specifying the number (4) of performance data to be read / written according to the AXI protocol (S31). The input / output control unit 20 requests the memory unit 43 or the external storage device 3 to read the specified number (4) of data from the address specified in the "read request" (S41).

[0055] The storage unit 43 or the external storage device 3 outputs the first data to the input / output control unit 20 (S51), and the input / output control unit 20 outputs the requested first data to the performance control unit 10 (S32). The storage unit 43 or the external storage device 3 outputs the second data to the input / output control unit 20 (S52), and the input / output control unit 20 outputs the requested second data to the performance control unit 10 (S33). The storage unit 43 or the external storage device 3 outputs the third data to the input / output control unit 20 (S53), and the input / output control unit 20 outputs the requested third data to the performance control unit 10 (S34). The storage unit 43 or the external storage device 3 outputs the fourth data to the input / output control unit 20 (S54), and the input / output control unit 20 outputs the requested fourth data to the performance control unit 10 (S35). When the reading of the number (four) of data items specified in the "read request" (data transfer from the memory unit 43) is completed, the AXI protocol ends normally, and the performance control unit 10 can again execute the write request and read request.

[0056] FIG. 6 is a diagram illustrating communication between the performance control unit and the storage unit in a writing process when the performance control unit is reset. 4, when the performance control device 2, which is in a waiting state, receives a command from the main control board 1, the performance control unit 10 makes a "write request" to the input / output control unit 20 specifying the number of pieces of performance data to be written (4 pieces) according to the AXI protocol (S11). The input / output control unit 20 requests the memory unit 43 to write the specified number (4 pieces) of data to the address specified in the "write request" (S21). The performance control unit 10 outputs the first data to the input / output control unit 20 (S12), and the input / output control unit 20 outputs the requested first data to the storage unit 43 (S22). The performance control unit 10 outputs the second data to the input / output control unit 20 (S13), and the input / output control unit 20 outputs the requested second data to the storage unit 43 (S23). Here, it is assumed that the performance control unit 10 is reset (S16). The input / output control unit 20 outputs two pieces of dummy data to the storage unit 43 until the number of pieces reaches the number specified in the "write request" (S26, S27). With the above, writing of the number of pieces of data specified in the "write request" (data transfer to storage unit 43) is completed. Therefore, the handshake in the AXI protocol between performance control unit 10 and storage unit 43 (the above write transaction (1) to (5)) is completed. Since the AXI protocol ends normally, performance control unit 10 can execute the write request and read request again.

[0057] FIG. 7 is a diagram illustrating communication between the performance control unit and the storage unit or the external storage device in a read process when the performance control unit is reset. Description will be given with reference to FIG. 4, when the performance control device 2, which is in a reception waiting state, receives a command from the main control board 1, the performance control unit 10 makes a "read request" to the input / output control unit 20 specifying the number (4) of performance data to be read / written according to the AXI protocol (S31). The input / output control unit 20 requests the memory unit 43 or the external storage device 3 to read the specified number (4) of data from the address specified in the "read request" (S41).

[0058] The storage unit 43 or the external storage device 3 outputs the first data to the input / output control unit 20 (S51), and the input / output control unit 20 outputs (transfers) the requested first data to the performance control unit 10 (S32). The storage unit 43 or the external storage device 3 outputs the second data to the input / output control unit 20 (S52), and the input / output control unit 20 outputs the requested second data to the performance control unit 10 (S33). Here, it is assumed that the performance control unit 10 is reset (S16). The storage unit 43 or the external storage device 3 outputs the third data to the input / output control unit 20 (S53), and the input / output control unit 20 acquires the data and discards it without outputting it to the performance control unit 10 (S42). The storage unit 43 or the external storage device 3 outputs the fourth data to the input / output control unit 20 (S54), and the input / output control unit 20 acquires the data and discards it without outputting it to the performance control unit 10 (S43). This completes the reading of the number of pieces of data (four) specified in the "read request" (data transfer from the storage unit 43 or external storage device 3). This completes the handshake in the AXI protocol between the performance control unit 10 and the storage unit 43 or external storage device 3 (the above read transaction (1) to (5)). This completes the AXI protocol, allowing the performance control unit 10 to execute write requests and read requests again.

[0059] FIG. 8 is a flowchart showing the input / output control process performed by the input / output control unit when writing data. The processing of the input / output control unit can be executed as software processing by the input / output control circuit 202 or a processor provided in the performance control device 2 instead of the input / output control circuit 202. In the following explanation with reference to Fig. 8, it is assumed that a "write request" for image data is made from the image control unit 10a. In step S101, the input / output control unit 20 determines whether or not a request to write image data has been input from, for example, the request unit 11a of the image control unit 10a. When the input / output control unit 20 determines that a write request has been input (Yes in step S101), it stores the write request (S102). Then, in step S103, the input / output control unit 20 starts outputting a request to write image data to the storage unit 43 (transferring the write request).

[0060] In step S104, the input / output control unit 20 outputs one piece of data to the storage unit 43 (to the bus 50). In step S105, the input / output control unit 20 determines whether the designated number of data items have been output. If it is determined that the designated number of data items have been output (Yes in step S105), the input / output control unit 20 advances the process to step S106 and ends the input / output control process. If it is determined that the specified number of data items have not been output (there is remaining data to be output) (No in step S105), the input / output control unit 20 determines in step S107 whether the image control unit 10a has been reset (initialized) or not. When it is determined that the image control unit 10a has not been reset (No in step S107), the input / output control unit 20 returns to step S104 and outputs the next data to the storage unit 43. If it is determined that the image control unit 10a has been reset (Yes in step S107), the input / output control unit 20 outputs, in step S108, a number of dummy data pieces that is less than the specified number to the memory unit 43, and when this is completed, proceeds to step S106 and ends the input / output control processing.

[0061] FIG. 9 is a flowchart showing the input / output control process performed by the input / output control unit when reading data. The processing of the input / output control unit can be executed as software processing by the input / output control circuit 202 or a processor provided in the performance control device 2 instead of the input / output control circuit 202. In the following explanation with reference to Fig. 9, it is assumed that a read request for image data is made from the image control unit 10a. In step S201, the input / output unit 21 of the input / output control unit 20 determines whether or not a read request for image data has been input from, for example, the request unit 11a of the image control unit 10a. When the input / output control unit 20 determines that a read request has been input (Yes in step S201), it stores the read request (S202). Then, the input / output control unit 20 starts outputting a read request for the image data from the storage unit 43 or the external storage device 3 (transfer of the read request) in step S203. The input / output control unit 20 reads one piece of data from the storage unit 43 or the external storage device 3 in step S204. In step S205, the input / output control unit 20 inputs the read data to the image control unit 10a. In step S206, the input / output control unit 20 determines whether the reading of the designated number of data items has been completed. If it is determined that the designated number of data items have been read out (Yes in step S206), the input / output control unit 20 advances the process to step S207 and ends the input / output control process. The image control unit 10a renders an image using image data acquired from the storage unit 43 or the external storage device 3, and displays the image on the display device 4.

[0062] If the input / output control unit 20 determines that reading of the specified number of data items has not been completed (there is remaining data to be read) (No in step S206), then in step S208, it determines whether the image control unit 10a has been reset (initialized). If the input / output control unit 20 determines that the image control unit 10a has not been reset (No in step S208), the process returns to step S204, and the input / output control unit 20 reads the next data from the storage unit 43 or the external storage device 3 (bus 50). If it is determined that the image control unit 10a has been reset (Yes in step S208), the input / output control unit 20 acquires the next data from the bus 50 in step S209, and discards the data that was read out in step S210. In step S211, the input / output control unit 20 determines whether the reading of the designated number of data items, including the data to be discarded, has been completed. If it is determined that reading of the specified number of data items has not been completed (there is remaining data to be read) (No in step S211), the process returns to step S209 to obtain the next data item from the bus 50, and the data read in step S210 is discarded before the determination in step S211 is made. If it is determined that the designated number of data items have been read out (Yes in step S211), the input / output control unit 20 advances the process to step S212 and ends the input / output control process. The image control unit 10a outputs, for example, an image previously drawn (for example, the previous frame) stored in the frame buffer to the display device 4 without performing drawing using the image data corresponding to the current read request.

[0063] According to this embodiment, even if the performance control unit 10 is reset while writing or reading data to or from the external storage device 3 and the storage unit 43, it acquires all data that the external storage device 3 and the storage unit 43 have output to the bus 50, and outputs dummy data to the storage unit 43. This ensures that the number of data items specified by the "read request" and "write request" from the performance control unit 10 are correctly transferred within the bus. Therefore, the arbitration unit 42 that manages the bus 50 releases the bus 50. As a result, it is possible for another performance control unit 10 to communicate with the external storage device 3 and the storage unit 43 without the need to reset the entire output control device 2 or negotiate communication with the external storage device 3, and normal performance can be continued.

[0064] FIG. 10 is a block diagram illustrating an embodiment of a computer system. The configuration of the computer device 300 will be described with reference to FIG. 10, computer device 300 includes a control circuit 301, a storage device 302, a reading / writing device 303, a recording medium 304, a communication interface 305, an input / output interface 306, an input device 307, and a display device 308. The communication interface 305 is connected to a network 309. The components are connected by a bus 310. The main control board 1, the performance control device 2, and the external storage device 3 can be configured by appropriately selecting some or all of the components described in computer device 300. The control circuit 301 controls the entire computer device 300. The control circuit 301 is a processor such as a central processing unit (CPU), a multi-core CPU, a field programmable gate array (FPGA), or a programmable logic device (PLD). And the control circuit 301 functions as, for example, the performance control unit 10 and the input / output control unit 20 in FIG.

[0065] The storage device 302 stores various data. The storage device 302 is, for example, a memory such as a ROM (Read Only Memory) or a RAM (Random Access Memory), or a non-temporary recording medium such as a HD (Hard Disk) or an SSD (Solid State Drive). The storage device 302 functions as, for example, the storage unit 25 or the storage unit 43 in FIG. 3. The ROM also stores programs such as a boot program. The RAM is used as a work area for the control circuit 301. The HD stores programs such as the OS, application programs, and firmware, as well as various data. When performing various processes, the performance control device 2 reads out the performance control program stored in the storage device 302 into the RAM. By executing the performance control program read out into the RAM in the control circuit 301, the performance control device 2 executes processes including one or more of request processing, image processing, audio processing, lighting processing, and input / output processing. Note that the performance control device 2 may also execute processes including one or more of request processing, image processing, audio processing, lighting processing, and input / output processing by reading out the performance control program from the external storage device 3 and executing it. Each of the above-mentioned programs may be stored in a storage device of a server on the network 309 as long as the control circuit 301 can access the programs via the communication interface 305 .

[0066] The reading / writing device 303 is controlled by the control circuit 301 and reads / writes data from / to a removable recording medium 304. The reading / writing device 303 is communicatively connected to, for example, the performance control device 2 and the external storage device 3. The reading / writing device 303 is, for example, a FDD (Floppy Disk Drive), a CDD (Compact Disc Drive), a DVDD (Digital Versatile Disk Drive), a BDD (Blu-ray (registered trademark) Disk Drive), a USB (Universal Serial Bus), a SATA, or the like. Various data is stored in the recording medium 304. The recording medium 304 may store, for example, a processing program for a performance control device. The performance control program includes one or more of request processing, image processing, audio processing, lighting processing, and input / output processing. The recording medium 304 is connected to the bus 310 via the reading / writing device 303, and the control circuit 301 controls the reading / writing device 303 to read / write data. The recording medium 304 is a non-transitory recording medium such as an SD memory card, a floppy disk (FD), a compact disc (CD), a digital versatile disk (DVD), a Blu-ray (registered trademark) disk (BD), a hard disk drive (HDD), a solid state drive (SSD), a flash memory, etc. The recording medium 304 functions as the external storage device 3 in FIGS.

[0067] The communication interface 305 connects the computer device 300 to other devices via the network 309 so that they can communicate with each other. The communication interface 305 may also include an interface having a wireless LAN function and an interface having a short-range wireless communication function. The wireless LAN interface may support, for example, Wi-Fi (registered trademark) as a wireless LAN standard. The short-range wireless interface may support, for example, Bluetooth (registered trademark) as a short-range wireless communication standard. LAN is an abbreviation for Local Area Network.

[0068] The input / output interface 306 is connected to, for example, an input device 307, and when a signal indicating various information is input from the connected input device 307, the input / output interface 306 outputs the input signal via a bus 310 to the control circuit 301. Furthermore, when a signal indicating various information output from the control circuit 301 is input via the bus 310, the input / output interface 306 outputs the signal to various devices connected thereto. The input device 307 is, for example, a keyboard, a mouse, or a touch panel. The display device 308 displays various information. For example, the display device 308 displays an image drawn by the performance control device 2. The display device 308 may display information for receiving input from a touch panel. The display device 308 functions as the display device 4 in FIG. 1, for example. The input / output interface 306, the input device 307, and the display device 308 may function as a GUI (Graphical User Interface), which allows the computer device 300 to receive intuitive operations using a touch panel, a mouse, or the like. The network 309 may be, for example, a LAN, wireless communication, or the Internet, and communicatively connects the computer device 300 to other devices.

[0069] This embodiment is not limited to the embodiment described above, and various configurations or embodiments can be adopted without departing from the gist of this embodiment. [Explanation of symbols]

[0070] 1 main control board, 2 performance control device, 2A performance control board, 3 external storage device, 4 display device, 5 sound emission device, 6 lighting device, 10 performance control unit, 10a image control unit, 10b audio control unit, 10c lamp control unit, 20 input / output control unit, 20a input / output control unit, 20b input / output control unit, 20c input / output control unit, 21 input / output unit, 22 monitoring unit, 23 writing unit, 24 discarding unit, 25 memory unit 40 general control unit, 41 input / output unit, 42 arbitration unit, 43 memory unit, 50 bus, 100 gaming machine, 201 performance control circuit, 201a image control circuit, 201b audio control circuit, 201c lamp control circuit, 202 input / output control circuit, 202a image input / output control circuit, 202b audio input / output control circuit, 202c lamp input / output control circuit, 203 internal storage device, 204 Memory I / F, 205 overall control device, 206 arbitration circuit, 207 bus

Claims

1. A performance control device including a first control unit and a second control unit, and performing synchronous communication with a storage device, The first control unit is a request unit that outputs a write request to the storage device, the write request including a designation of data to be written to the storage device and a designation of the number of pieces of the data to be written; An initialization unit that initializes the first control unit, The second control unit is a monitoring unit that monitors whether the first control unit has been initialized; a writing unit that, when the first control unit is initialized before the first control unit outputs a specified number of the write data to the storage device after outputting the write request, writes dummy data to the storage device in a number that corresponds to a number of the write data that has been output by the first control unit that is less than the specified number; Equipped with A performance control device comprising:

2. In the performance control device according to claim 1, The second control unit stores pre-created dummy data in a storage unit, and writes the dummy data stored in the storage unit to the storage device. A performance control device comprising:

3. A performance control device including a first control unit and a second control unit, and performing synchronous communication with a storage device, The first control unit is a request unit that outputs a read request to the storage device, the read request including a designation of data to be read from the storage device and a designation of the number of data to be read; An initialization unit that initializes the first control unit, The second control unit is a monitoring unit that monitors whether the first control unit has been initialized; and an acquisition unit configured to acquire, when the first control unit is initialized before the first control unit acquires the specified number of read data after the read request is output, the read data in a quantity that is less than the specified number of read data that has already been acquired from the storage device. A performance control device comprising:

4. The performance control device according to claim 3, The second control unit discards the read data acquired by the acquisition unit. A performance control device comprising:

5. In the performance control device according to any one of claims 1 to 4, The number is information indicating how many bus widths connecting the first control unit and the storage device the data corresponds to. A performance control device comprising:

6. A control method for a performance control device that performs synchronous communication with a storage device, when the control unit outputs a write request to the storage device, the write request including designation of data to be written to the storage device and designation of the number of pieces of the write data, and the control unit is initialized before the control unit outputs the designated number of pieces of the write data to the storage device, the control unit writes dummy data to the storage device in a number such that the number of pieces of the write data that the control unit has already output is less than the designated number; A control method comprising:

7. A control method for a performance control device that performs synchronous communication with a storage device, When the control unit outputs a read request to the storage device, the read request including designation of read data from the storage device and designation of the number of the read data, and the control unit is initialized before the control unit acquires the designated number of the read data, the control unit acquires from the storage device a number of the read data whose number of the acquired read data is less than the designated number. A control method comprising:

8. A control program executed by a processor of a performance control device that synchronously communicates with a storage device, When the control unit outputs a write request to the storage device, the write request including designation of data to be written to the storage device and designation of the number of pieces of the write data, and the control unit is initialized before the control unit outputs the designated number of pieces of the write data to the storage device, the processor writes dummy data to the storage device in a number such that the number of pieces of the write data already output by the control unit is less than the designated number. A control program comprising:

9. A control program executed by a processor of a performance control device that synchronously communicates with a storage device, A control program characterized in that, after a control unit outputs a read request to the storage device, including a specification of read data from the storage device and a specification of the number of the read data, when the control unit is initialized before the control unit acquires the specified number of the read data, the control unit acquires from the storage device a number of the read data that is less than the specified number of the read data that has already been acquired.

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