Integrated circuit package with integrated voltage regulator

Abstract

Various semiconductor chip devices and methods for fabricating the same are disclosed. In one aspect, an apparatus is provided that includes a first redistribution layer (RDL) structure (172) having a first plurality of conductor traces (165d, 165e), a first shaping layer (120) on the first RDL structure, a plurality of conductive pillars (205a, 205b) in the first shaping layer, each conductive pillar including a first end and a second end, and a second RDL structure (115) on the first shaping layer, the second RDL structure having a second plurality of conductor traces (165a, 165b), wherein a portion of the conductive pillars (205b, 205c) are electrically connected between a portion of the first plurality of conductor traces and a portion of the second plurality of conductor traces to provide a first inductor coil.

Description

[Background technology]

[0001] Conventional integrated circuits are often mounted on a semiconductor substrate or die, which consists of a small, often rectangular piece of semiconductor material (typically silicon) formed with two opposing major surfaces. The active circuitry of the die is concentrated near one of the two major surfaces. Conventional dies are usually mounted on some form of substrate, such as a package substrate or printed circuit board. Electrical conductivity between the die and the underlying substrate or board is established by a variety of conventional mechanisms. In the so-called flip-chip configuration, the active circuitry side of the die is provided with a number of conductor balls or bumps designed to establish a metallurgical bond with a corresponding number of conductor pads located on the substrate or circuit board. The die is flipped over, active circuitry side down, and secured to the underlying substrate. A subsequent heat treatment is performed to establish the necessary metallurgical bond between the bumps and the pads. One of the main advantages of the flip-chip mounting strategy is the relatively short electrical path between the integrated circuit and the substrate. These relatively low inductance paths result in high speed performance of electronic devices.

[0002] Power is provided to a board or circuit board from an external power source that may be on or connected to the system board. The input power is typically generated by a voltage regulator on the system board. A regulated voltage of 3.3 volts is typical of current integrated circuit power supplies. However, conventional semiconductor chips often require power at various voltage levels. For example, providing a regulated step-down voltage from a 3.3 volt input can produce surprisingly high currents. For example, an integrated circuit operating at 100 watts and 1 volt may consume approximately 100 amps of current. A conventional voltage regulator typically includes an inductor and switching logic to charge and discharge the inductor according to some algorithm.

[0003] These and other advantages of the present invention will become apparent upon reading the following detailed description and upon reference to the drawings. [Brief description of the drawings]

[0004] [Figure 1] FIG. 1 is a diagram of an exemplary configuration of a semiconductor chip device. [Diagram 2] FIG. 2 is a cross-sectional view of a portion of the device shown in FIG. [Diagram 3] FIG. 1 is a schematic diagram of an exemplary integrated voltage regulator. [Figure 4] 1A-1C are diagrams of example configurations of inductors. [Diagram 5] 11A-11C are diagrams of alternative exemplary configurations of inductors. [Figure 6] 11A-11C are diagrams of alternative exemplary configurations of multiple inductors. [Figure 7] 1A-1D are cross-sectional views illustrating an exemplary process for a carrier wafer for manufacturing a semiconductor device. [Figure 8] FIG. 2 is a diagram of an exemplary carrier wafer. [Figure 9] 8 is a cross-sectional view similar to FIG. 7, but showing an exemplary process for fabricating multiple conductive pillars. [Figure 10] 10 is a cross-sectional view similar to FIG. 9, but showing an exemplary additional process for fabricating multiple conductive pillars. [Figure 11] 11 is a cross-sectional view similar to FIG. 10, but showing an exemplary process for placing any high permeability inductor core. [Figure 12] 12 is a cross-sectional view similar to FIG. 11, but showing an exemplary process for fabricating a shaping layer around a plurality of conductive pillars. [Figure 13] 13 is a cross-sectional view similar to FIG. 12, but showing an exemplary additional process for producing a shaped layer. [Figure 14] 14 is a cross-sectional view similar to FIG. 13, but showing an exemplary process for fabricating a redistribution layer (RDL) structure on a shaping layer. [Figure 15] 15 is a cross-sectional view similar to FIG. 14, but showing an exemplary process for attaching one or more semiconductor chips onto the RDL structure. [Figure 16]16 is a cross-sectional view similar to FIG. 15, but showing an exemplary process for fabricating the interconnects. [Figure 17] 17 is a cross-sectional view similar to FIG. 16, but showing an exemplary process for attaching dicing tape and performing singulation. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0005] A traditional solution to providing a regulated voltage would be to incorporate regulator inductors on the semiconductor chip. However, integrated inductors for high currents require thick metal with very low resistivity that is generally not present in current semiconductor chip processing technologies. For example, current CMOS processes require unacceptable I 2 This creates a top metal layer with too high a resistance to act as an inductor without R losses. Some conventional designs incorporate magnetic core inductors into the semiconductor chip. Such devices may have current limitations due to the device geometry. Still other designs use inductors mounted on the surface of the package substrate, with attendant performance penalties associated with the path length from the inductor to the chip input / output (I / O) where a regulated voltage is required.

[0006] The disclosed configuration provides a semiconductor chip package with an integrated voltage regulator. The voltage regulator is fabricated by placing conductive pillars on a molding layer and using these conductive pillars, along with conductor traces on opposite sides of the pillars, to provide one or more inductor coils. The molding layers are sandwiched between redistribution layer (RDL) structures, and one or more semiconductor chips are attached to one RDL structure. Such inductor coils are configured like a solenoid with the coil axis oriented such that the generated magnetic field does not project toward the semiconductor chip. The conductive pillars are configured with a smaller I 2R losses. The inductor coil does not occupy space on the package substrate. The molding layers are electrically isolated, resulting in low coupling losses. Furthermore, the inductor coils can be substantially coaxial and nested to generate multiple phases.

[0007] According to one aspect of the invention, an apparatus is provided that includes a first redistribution layer (RDL) structure having a first plurality of conductor traces, a first shaping layer on the first RDL structure, a plurality of conductive pillars in the first shaping layer, each conductive pillar including a first end and a second end, and a second RDL structure on the first shaping layer, the second RDL structure having a second plurality of conductor traces, some of the conductive pillars electrically connected between some of the first plurality of conductor traces and some of the second plurality of conductor traces to provide a first inductor coil.

[0008] The apparatus includes control and switching logic coupled to an inductor to provide a voltage regulator.

[0009] The device includes a first semiconductor chip mounted on a second RDL structure.

[0010] In this apparatus, a first semiconductor chip includes control and switching logic coupled to an inductor to provide a voltage regulator.

[0011] The apparatus includes a second molding layer over the second RDL structure that at least partially encapsulates the first semiconductor chip.

[0012] The device includes a circuit board on which the device is mounted.

[0013] The apparatus includes a high permeability core disposed inside a first inductor coil.

[0014] The apparatus has another conductive pillar electrically connected between another one of the first plurality of conductor traces and another one of the second plurality of conductor traces to provide a second inductor coil.

[0015] In this apparatus, the second inductor coil is substantially coaxial with the first inductor coil.

[0016] According to another aspect of the present invention, a semiconductor chip device is provided that includes a first redistribution layer (RDL) structure having a first plurality of conductor traces; a first shaping layer on the first RDL structure; a plurality of conductive pillars in the first shaping layer, each conductive pillar including a first end and a second end; a second RDL structure on the first shaping layer having a second plurality of conductor traces, some of the conductive pillars being electrically connected between a portion of the first plurality of conductor traces and a portion of the second plurality of conductor traces to provide a first inductor coil; and a first semiconductor chip mounted on the second RDL structure, the first semiconductor chip having voltage regulator switching and control logic connected to the first inductor coil to provide an integrated voltage regulator.

[0017] The semiconductor chip device includes a second semiconductor chip mounted on the second RDL structure, and the integrated voltage regulator is operable to provide a regulated voltage to the second semiconductor chip.

[0018] The semiconductor chip device includes a second molding layer on the second RDL structure that at least partially encapsulates the first semiconductor chip.

[0019] The semiconductor chip device includes a circuit board, and the semiconductor chip device is mounted on the circuit board.

[0020] The semiconductor chip device includes a highly permeable core disposed inside a first inductor coil.

[0021] The semiconductor chip device has another conductive pillar electrically connected between another one of the first plurality of conductor traces and another one of the second plurality of conductor traces to provide a second inductor coil.

[0022] The semiconductor chip device has a second inductor coil that is substantially coaxial with the first inductor coil.

[0023] According to another aspect of the invention, a manufacturing method is provided that includes fabricating a first redistribution layer (RDL) structure having a first plurality of conductor traces; fabricating a first molding layer on the first RDL structure; fabricating a plurality of conductive pillars in the first molding layer, each conductive pillar including a first end and a second end; fabricating a second RDL structure on the first molding layer, the second RDL structure having a second plurality of conductor traces; and electrically connecting some of the conductive pillars between some of the first plurality of conductor traces and some of the second plurality of conductor traces to provide a first inductor coil.

[0024] The method includes coupling control and switching logic to an inductor to provide a voltage regulator.

[0025] The method includes attaching a first semiconductor chip onto the second RDL structure.

[0026] The method includes a first semiconductor chip having control and switching logic coupled to an inductor to provide a voltage regulator.

[0027] The method includes attaching a first RDL structure onto a circuit board.

[0028] The method includes a first semiconductor chip having control and switching logic coupled to an inductor to provide a voltage regulator.

[0029] The method includes fabricating a second molding layer over the second RDL structure that at least partially encapsulates the first semiconductor chip.

[0030] The method includes mounting a device on a circuit board.

[0031] The method includes providing a high permeability core disposed inside a first inductor coil.

[0032] The method includes electrically connecting another conductive pillar between another conductor trace of the first plurality of conductor traces and another conductor trace of the second plurality of conductor traces to provide a second inductor coil.

[0033] The method of manufacture includes forming the second inductor coil substantially coaxial with the first inductor coil.

[0034] In the figures described below, numbers are generally repeated when identical elements appear in multiple figures. Referring now to the drawings, and in particular to FIG. 1, there is shown a diagram of an exemplary configuration of a semiconductor chip device 100 including a molded fan-out package 105 mounted on a circuit board 110. The molded fan-out package 105 includes an RDL structure 115 sandwiched between a molding layer 120 and another molding layer 125. The molding layer 125 at least partially encases one or more semiconductor chips, in this exemplary configuration, semiconductor chips 130 and 135. The molding layer 125 may also optionally house one or more capacitors, two of which are shown at 140 and 145, respectively, and are shown in dashed lines as they are obscured by the top surface of the molding layer 125.

[0035] None of the configurations disclosed herein are dependent on the particular function of the semiconductor chip 130, 135 or the circuit board 110. Thus, the semiconductor chip 130, 135 may be any of a variety of different types of circuit devices used in electronic devices, such as, for example, an interposer, a microprocessor, a graphics processor, a combined microprocessor / graphics processor, an application specific integrated circuit, a memory device, etc., and may be single-core or multi-core. The semiconductor chip 130, 135 may be constructed of bulk semiconductors, such as silicon or germanium, or semiconductor-on-insulator materials, such as silicon-on-insulator materials, or insulator materials. Thus, the term "semiconductor chip" also contemplates insulating materials. Stacked dies may be used if desired.

[0036] The circuit board 110 may be another semiconductor chip of the type described above, a semiconductor chip package substrate, a circuit card, or virtually any other type of printed circuit board. Monolithic or laminate structures may be used. A build-up design is one example of a laminate. In this regard, the circuit board 110 may be constructed of a central core over which one or more build-up layers are formed and below which additional one or more build-up layers are formed. The core itself may be constructed of a stack of one or more layers. So-called "coreless" designs may also be used. The layers of the circuit board 110 may be constructed of insulating materials such as various well-known epoxies or other resins interspersed with metal traces. Multi-layer configurations other than build-up may also be used. Optionally, the circuit board 110 may be constructed of well-known ceramic or other materials suitable for packaging substrates or other printed circuit boards. The circuit board 110 includes a number of I / Os 147, which may be solder balls as shown, or may be lands, pins, or the like.

[0037] Further details of the semiconductor chip device 100 can be seen by reference to FIG. 2, which is a cross-sectional view of FIG. 1 taken at section 2-2, but without the circuit board 110. Note that due to the location of section 2-2, both the semiconductor chip 130, the semiconductor chip 135 are shown in cross section, as well as the molding layers 120, 125 and a portion of the RDL structure 115. The molded fan-out package 105 includes one or more embedded inductors disposed inside the molding layer 120. There can be one or more such inductors. In this exemplary configuration, three such inductors 150, 155, 160 are shown and illustrated with dashed lines, as they are hidden by the molding layer 125, the RDL structure 115 and the molding layer 120. Note that due to the location of section 2-2, the embedded inductor 155 is shown in cross section in FIG. 2. Before describing the structure of the inductor 155 in detail, the molding layer 120, the RDL structure 115 and the molding layer 125 will be described in more detail. The RDL structure 115 is comprised of one or more layers of metallization, such as the disclosed traces 165a, 165b, 165c, interconnected with other traces through vias 170 and interspersed with one or more layers of insulating material 171. Additional conductor traces 165d, 165e, 165f, 165g are fabricated in another RDL structure 172 formed on the molding layer 120 opposite the RDL structure 115. The traces 165a, 165b, 165c, 165d, 165e, 165f, 165g form part of the inductor 155. The traces 165a, 165b, 165c, 165d, 165e, 165f, 165g and the vias 170 can be comprised of a variety of conductor materials, such as copper, aluminum, silver, gold, platinum, palladium, titanium, refractory metals, refractory metal compounds, alloys thereof, and the like. Instead of a unitary structure, the traces 165a, 165b, 165c, 165d, 165e, 165f, 165g and the vias 170 may be comprised of a stack of multiple metal layers. However, those skilled in the art will appreciate that a wide variety of conductive materials may be used for the traces 165a, 165b, 165c, 165d, 165e, 165f, 165g and the vias 170.A variety of well-known techniques can be used to apply the metallic material, such as physical vapor deposition (sputtering), chemical vapor deposition (CVD), plating, etc. The insulating material 171 can be composed of a variety of dielectric materials, such as polyimide, polybenzoxazole, benzocyclobutene, or other polymers, and can be applied using well-known application and curing techniques.

[0038] The semiconductor chips 130, 135 include device regions 175, 180 facing the RDL structure 115 and interconnected to the RDL structure 115 via multiple interconnects 185, 190. The device regions 175, 180 may include multiple circuit structures, such as transistors, passive devices, or other types of structures, multiple layers of metallization, or the like, for eventual connection to the interconnects 185, 190. The device region 175 may include an integrated voltage regulator circuit 192, and the device region 180 may include an integrated voltage regulator circuit 194. The integrated voltage regulator circuit 192 may be connected to one or more inductors, such as inductors 145, 150, 155, to provide an integrated voltage regulator. The integrated voltage regulator circuit 194 may be connected to one or more inductors, such as inductors 145, 150, 155, to provide an integrated voltage regulator. The interconnects 185, 190 are then connected to the RDL structure 115 via the metallization layers 195. The interconnects 185, 190 can be solder bumps, solder microbumps, connecting pillars, or other types of conductive structures. To reduce the effect of differences in CTE between the chips 130, 135 and other structures of the molded fan-out package 100, an underfill 200 can be placed between the chips 130, 135 and the RDL structure 115. The underfill 200 can be placed by capillary action after attachment of the chips 130, 135 or prior to attachment of the chips 130, 135.

[0039] The molding layer 125 can be constructed from a variety of polymer molding materials. Commercially available ones are Sumitomo EME-G750 and G760. Well known compression molding techniques can be used to mold the molding layer 125, where the molding layer 125 has a vertically flush edge with the top surfaces of the chips 130, 135. This can be accomplished by grinding, or in some cases, molding the molding layer 125 so that it does not cascade onto the tops of the chips 130, 135.

[0040] Shaping layer 120 includes a plurality of conductive pillars, some of which are designated 205a, 205b, 205c, 205d, and 205e, whose top ends are connected to one or more of conductor traces 165a, 165b, and 165c of RDL structure 115, and whose bottom ends are connected to conductor traces 165d, 165e, 165f, and 165g fabricated in conductor structure 210 or RDL structure 172. Shaping layer 120 can be constructed from the same types of materials as shaping layer 125 and can be applied using the same techniques.

[0041] The RDL structure 172 may be comprised of the conductor traces 165d, 165e, 165f, 165g and conductor structure 210 described above, which are shown as vertically extending structures that may include laterally extending traces or other types of RDL-type metallization and one or more layers of dielectric material, such as polyimide, polybenzoxazole, benzocyclobutene, or other polymers, applied using known application and curing techniques. A number of interconnects 220 protrude from the RDL structure 172 and are electrically connected to some of the conductive pillars, such as 205a, through the conductor structure 210 and I / O pads 225. Note that conductive pillars 205b, 205c, 205d, 205e are not located in the same plane as the other conductive pillars (e.g., pillar 205a, shown hatched). Conductive pillars 205b, 205c, 205d, and 205e are positioned further back in the page than pillar 205a and are therefore hidden by shaping layer 120 and are shown with dashed lines.

[0042] The embedded inductor 155 is comprised of conductive pillars 205b, 205c, 205d, 205e and conductor traces 165a, 165b, 165c, 165d, 165e, 165f interconnected by additional conductive pillars that are within the molding layer 120 but are located outside the page relative to the cross-section shown in FIG. 2 and therefore not visible. The embedded inductor 155 may include an optional highly permeable core 230 comprised of ferrite or other highly permeable material secured to the RDL structure 215 by a suitable adhesive layer 235. The embedded inductor 155 in this exemplary configuration is a solenoid coil with a coil axis 236 that does not pass through any of the semiconductor chips. The inductor 155 generates a magnetic field B that is substantially parallel to the coil axis 236. This configuration reduces electromagnetic interference to the semiconductor chips 130, 135.

[0043] Various IVR architectures can be used with the semiconductor chip device 100 to provide regulated voltage power. Exemplary architectures and exemplary electrical paths associated with the chips 130, 135 of the semiconductor chip device 100 will now be described with reference to schematic diagrams 2 and 3. A high voltage input HV (from a source such as the circuit board 110 shown in FIG. 1 or other device not shown) DDis provided to any of the I / Os 220 and provided to the voltage regulator circuit 192 of the semiconductor chip 130 via an electrical path 237. The electrical path 237 may include one or more conductive pillars 205a, RDL structures 115, metal layers 195, and interconnects 185. The voltage regulator logic 192 further includes a controller 239 and switching logic 241 that together with a passive device circuit, such as a passive device circuit 243, constitute an IVR. The switching logic 241 is electrically connected to the passive device circuit 243 via the RDL structure 115. The passive device circuit 243 includes a pair of inductors (e.g., inductors 155, 160) and a pair of capacitors 245, 246 (and optionally more than two of each) that may be located on the chip 130 or elsewhere in the semiconductor chip device 100. The switching logic 241 includes two or more transistors to selectively pass current through the inductors 155, 160 of the passive device circuit 243. The common output of inductors 155 and 160 is coupled through RDL structure 115 to a regulated voltage, R DD , is provided as an input to the semiconductor chip 135. The outputs of the inductors 125 and 130 are also connected to ground via respective capacitors 245 and 246. The capacitors 245 and 246 may be internal or external to the semiconductor chip device 100 and may number more than two. In this way, the semiconductor chip 135 receives the input voltage HV DD and via a controller 239, via switching logic 241 and passive device circuitry 243, to provide a regulated voltage RV DDas an input to the semiconductor chip 135. The controller 239, the switching logic 241, the inductors 155, 160, and the capacitors 245, 246 are configured to function as a buck regulator as is well known. The controller 239 may be implemented on the semiconductor chip 130 or as a separate component. The switching logic 241 may likewise be implemented on the semiconductor chip 130 or as a separate component. In fact, the controller 239 and the switching logic 241 may be integrated into a single device integrated into the semiconductor chip 130 as shown. It should be appreciated that the semiconductor chip 135 with the voltage regulator circuit 194 can provide similar IVR functionality as the semiconductor chip 130 described above. It should be appreciated that multiple IVRs can be fabricated and chained together within or on a given chip, such as the semiconductor chips 130, 135. Of course, other IVR architectures utilizing inductors can also be used.

[0044] Further details of the embedded inductor 155 can be seen by reference to Figure 4, which is a diagram of the components of the embedded inductor 155 removed from the shaping layer 120, RDL structure 115, and RDL structure 172 shown in Figure 2. As mentioned above, the embedded inductor 155 can be composed of conductor traces 165a, 165b, 165c, 165d, 165e, 165f, 165g interconnected by conductive pillars 205b, 205c, 205d not visible in Figure 2 and pillars 205e, 205f, 205g, 205h discussed above. The high permeability core 230 is disposed inside the inductor coil formed by the conductor traces 165a, 165b, 165c, 165d, 165e, 165f, 165g and pillars 205b, 205c, 205d, 205e, 205f, 205g, 205h described above. Here, the high permeability core 230 is configured with a rectangular cross section, but other shapes such as circular or elliptical can be used. It should be understood that the number of traces and pillars that make up the inductor 155 and the disclosed alternatives can be varied. Indeed, it should be noted that the structure that makes up a given inductor, such as the inductor 155 or any of the disclosed alternatives, can be configured to provide a desired inductance. For example, the width, thickness, spacing, number and material composition of conductor traces 165a, 165b, 165c, 165d, 165e, 165f, 165g and pillars 205b, 205c, 205d, 205e, 205f, 205g, 205h can be selected to generate a desired inductance. As discussed above, inductor 155 generates a magnetic field B that is preferably substantially aligned with coil axis 236.

[0045] It should be understood that the high permeability core 230 is an optional feature. For example, as shown in FIG. 5, which is a diagram of an alternative exemplary embedded inductor 155', the high permeability core 230 shown in FIG. 3 can be omitted, and the embedded inductor simply includes traces 165a, 165b, 165c, 165d, 165e, 165f, 165g interconnected by conductive pillars 205b, 205c, 205d, 205e, 205f, 205g, 205h. Of course, it should be understood that the final input and output paths of the embedded inductors 155, 155' shown in FIGS. 4 and 5 are not shown for ease of illustration. The inductor 155' generates a magnetic field B that is preferably substantially aligned with the coil axis 236.

[0046] In yet another alternative exemplary configuration of the embedding 155″ shown in FIG. 6, multiple inductor coils can be substantially coaxial or otherwise nested together to provide multiple phases. For example, the embedded inductor 155″ can consist of one inductor including traces 165a, 165b, 165c, 165d, 165e, and 165f and interconnected by conductive pillars 205a, 205b, 205c, 205d, 205e, and 205f. This combination constitutes a first inductor capable of generating a first magnetic field B1 with a first phase φ1, and another substantially coaxial inductor made of conductor traces 165g, 165h, 165i, 165j, 165k, 165l interconnected by conductive pillars 205g, 205h, 205i, 205j, 205k, 205l generating a second magnetic field B2 with a second phase φ2, where B1 and B2 are substantially aligned with the coil axis 236. In this exemplary configuration, there are two inductors nested together to provide multiple phases. However, one skilled in the art will understand that more than two inductors may be nested together in the same general location as shown in FIG. 6, with or without a high permeability core 230.

[0047] An exemplary method for fabricating the molded fan-out package 100 shown in FIGS. 1 and 2 can be understood with reference to FIGS. 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, and 17, and initially with reference to FIG. 7. The following description focuses on the construction of the inductor 155, but the structures of the other inductors 150, 160 are described as well. The process begins with the fabrication of structures associated with the conductive pillars 205a, 205b, 205c, etc., as shown in FIG. 7. A release layer 250 is applied to the carrier wafer 255. The release layer 250 may be a light-activated, heat-activated, or other type of adhesive, or some form of tape that allows the carrier wafer 255 to be removed without destructively damaging the structures mounted thereon upon separation. The carrier wafer 255 can be composed of various types of glass or semiconductors such as silicon. This and subsequent processing can be performed at the wafer level as shown in FIG. 8, which shows the release layer 250 applied to the carrier wafer 255. Rectangular boxes 256 represent diagrammatically the locations where individual molded packages will be separated in subsequent processing. As shown in FIG. 9, a dielectric layer 257 is applied to the release layer 250. The dielectric layer 257 will ultimately form part of the RDL structure 172 shown in FIG. 2. If the RDL structure 172 shown in FIG. 2 includes multiple metal layers, multiple layers of dielectric material may be applied, interspersed with metallization as desired. A plating seed layer 258 is applied to the dielectric layer 257. The plating seed layer 258 may be composed of a variety of materials suitable for plating seed layers, such as copper, and may be applied by well-known sputtering, chemical vapor deposition, electroless plating, and the like. A photolithography mask 260 is applied to the plating seed layer 258 and photolithographically patterned to create a plurality of openings 270 that are used to plate the conductive pillars 205a, and the like. The photolithography mask 260 may be composed of a negative tone or positive tone resist as desired. Note that some openings 270 are shown with dashed lines because they are not in the same plane as other openings.The openings 270 shown in dashed lines are locations where the conductive pillars 205a, 205b, 205c, 205d, and 205e shown in Figure 2 will be fabricated, for example. For ease of illustration, the plating seed layer 258 is not shown in the other figures.

[0048] With the photolithography mask 260 in place and patterned, a plating process is performed to produce conductive pillars 205a, 205b, 205c, 205d, 205e, and the photolithography mask 260 is stripped using ashing, solvent stripping, etc., to obtain conductive pillars 205a, 205b, 205c, 205d (and others not labeled). Portions of the plating seed layer 258 (not shown) on the lateral dielectric layer 257 of pillars 205a, 205b, 205c, 205d are etched using well-known etching techniques. At this stage, the dielectric layer 257 remains attached to the carrier wafer 255 by the release layer 250.

[0049] Next, as shown in FIG. 11, any high permeability cores 230 are attached to the polymer dielectric layer 258 and secured thereto by the adhesive 235 described above. Note that some of the conductive pillars 205b, 205c, 205d are located further back into the page than, for example, conductive pillar 205a and its adjacent unnumbered pillars. Thus, most of the pillars 205a, 205b, 205c, 205d are hidden by the placement of the high permeability cores 230. Of course, multiple high permeability cores 230 can be placed when multiple inductors 150, 155, 160, etc. are configured. It should also be understood that other pillars are configured elsewhere on the dielectric layer 257, whether or not they function as inductor components. At this stage, the dielectric layer 257 remains attached to the carrier wafer 255 by the release layer 250.

[0050] 12, a molding layer 120 is then applied onto the dielectric layer 257 over the pillars 205a, 205b, 205c, 205d and any highly permeable cores 230 using well known compression molding techniques. The molding layer 120 is applied at some initial height z1 that is higher than the embedded conductive pillars 205a, 205b, 205c, 205d. At this stage, the dielectric layer 257 remains attached to the carrier wafer 255 by the release layer 250.

[0051] Next, a grinding process is performed on the molding layer 120 to expose the tops of the conductive pillars 205a, 205b, 205c, 205d, as shown in Figure 13. This reduces the height of the molding layer 120 to a new height z2. At this stage, the dielectric layer 257 remains attached to the carrier wafer 255 by the release layer 250.

[0052] Next, as shown in FIG. 14, a number of steps are performed to fabricate the RDL structure 115 on the molding layer 120. These include well-known material deposition and patterning techniques, which may be either additive or subtractive techniques, to establish the conductive pillars 205b, 205c, 205d and others shown but not individually labeled, as well as the conductor traces 165a, 165b, 165c that are in electrical contact with the vias 170 and the various dielectric layers 171. The fabrication of the multiple dielectric layers 171 may include coating and firing processes as required. At this stage, the dielectric layer 257 remains attached to the carrier wafer 255 by the release layer 250.

[0053] Next, as shown in FIG. 15, a metallization layer 195 is fabricated on the RDL structure 115 using well-known material application and patterning techniques. The semiconductor chips 130, 135 are then attached onto the metallization layer 195 and interconnected with the metallization layer 195 via the interconnects 185, 190 described above. If the interconnects are made of solder or use solder, this may involve solder reflow. The underfill 200 may be applied before or after the attachment of the chips 130, 135 as described above and may be subjected to a firing process to harden it. The molding layer 125 is then formed by well-known compression molding techniques. The molding layer 125 may be applied at some initial height z3 that at least partially accommodates the semiconductor chips 130, 135, which may be above their top surface as shown, or may be at a lower height if desired. A grinding operation may be used to adjust the molding height of the molding layer 125 to the height shown in FIG. 2. At this stage, the dielectric layer 257 remains attached to the carrier wafer 255 by the release layer 250 .

[0054] Next, as shown in FIG. 16, the carrier wafer 255 can be removed by activating the release layer 250 or some other non-destructive means and flipping the combination of molding layers 120, 125 and chips 130, 135 from the orientation shown in FIG. 15. The dielectric layer 257 may be appropriately patterned to provide suitable openings, and the conductor structures 210 can be formed by well-known material deposition techniques such as sputtering, CVD, etc. to fabricate the RDL structures 172. The I / O pads 225 can then be fabricated using well-known sputtering, plating, etc. The interconnects 220 can be attached to the pads 225 or otherwise formed using well-known plating, sputtering, pick and place, etc.

[0055] As shown in Figure 17, a dicing tape 280 can be applied to the sides of the molded fan-out package 100 and a dicing operation can be performed to singulate it from the others that make up the reconstituted wafer. The dicing tape 280 can then be removed and the molded fan-out package 100 can be attached to the circuit board 110 shown in Figure 1.

[0056] While the invention may be susceptible to various modifications and alternative forms, specific embodiments have been shown by way of example in the drawings and are described in detail herein. It should be understood, however, that the invention is not intended to be limited to the particular forms disclosed. Rather, the invention is intended to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the invention as defined by the appended claims.

Claims

1. a first redistribution layer (RDL) structure (172) having a first plurality of conductor traces (165d, 165e); a first shaping layer (120) on the first RDL structure; a plurality of conductive pillars (205a, 205b) in the first shaping layer, each conductive pillar including a first end and a second end; a second RDL structure (115) on the first shaping layer, the second RDL structure (115) having a second plurality of conductor traces (165a, 165b); a first semiconductor chip (130) including voltage regulator control and switching logic (192); a portion of the conductive pillars (205b, 205c) electrically connected between a portion of the first plurality of conductor traces and a portion of the second plurality of conductor traces to provide a first inductor coil (155); the voltage regulator control and switching logic (192) is connected to the first inductor coil through the second RDL structure to provide an integrated voltage regulator. Device.

2. the voltage regulator control and switching logic comprises a controller (239) and switching logic (241) connected to the first inductor coil via the second RDL structure to provide the integrated voltage regulator.

2. The apparatus of claim 1.

3. The first semiconductor chip (130) is mounted on the second RDL structure.

2. The apparatus of claim 1.

4. The apparatus further comprising a second semiconductor chip that receives a regulated voltage from the integrated voltage regulator.

4. The apparatus of claim 3.

5. a second molding layer (125) on the second RDL structure at least partially encapsulating the first semiconductor chip; 4. The apparatus of claim 3.

6. A circuit board (110), The device is mounted on the circuit board.

2. The apparatus of claim 1.

7. a high permeability core (230) disposed inside the first inductor coil; 2. The apparatus of claim 1.

8. another conductive pillar (205a, 205c) is electrically connected between another one of the first plurality of conductor traces and another one of the second plurality of conductor traces to provide a second inductor coil.

2. The apparatus of claim 1.

9. the second inductor coil being substantially coaxial with the first inductor coil; 9. The apparatus of claim 8.

10. a first redistribution layer (RDL) structure (172) having a first plurality of conductor traces (165d, 165e); a first shaping layer (120) on the first RDL structure; a plurality of conductive pillars (205a, 205b) in the first shaping layer, each conductive pillar including a first end and a second end; a second RDL structure (115) on the first shaping layer having a second plurality of conductor traces (165a, 165b), a portion of the conductive pillars (205b, 205c) electrically connected between a portion of the first plurality of conductor traces and a portion of the second plurality of conductor traces to provide a first inductor coil; a first semiconductor chip (130) mounted on the second RDL structure, the first semiconductor chip (130) having voltage regulator switching and control logic (192) connected to the first inductor coil through the second RDL structure to provide an integrated voltage regulator. Semiconductor chip device.

11. a high permeability core (230) disposed inside the first inductor coil; The semiconductor chip device of claim 10.

12. another conductive pillar (205a, 205c) is electrically connected between another one of the first plurality of conductor traces and another one of the second plurality of conductor traces to provide a second inductor coil. The semiconductor chip device of claim 10.

13. the second inductor coil being substantially coaxial with the first inductor coil; The semiconductor chip device of claim 12.

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