Voltage conversion device, power chip and electronic device

Abstract

The present disclosure relates to a voltage conversion device, a power supply chip, and an electronic device. The voltage conversion device includes a first NMOS transistor and a voltage hold unit, and is used to convert an input signal belonging to a first voltage range to an output signal belonging to a second voltage range. The power supply terminal of the voltage hold unit is used to input a first power supply voltage, the ground terminal of the voltage hold unit is grounded, and the second terminal of the voltage hold unit is used to generate the output signal. The voltage hold unit is used to maintain the potential of an inverted signal of the output signal at the first terminal and maintain the potential of the output signal at the second terminal when the second power supply voltage generating the input signal disappears after maintaining it for a certain period of time. The voltage conversion device according to the embodiment of the present disclosure can maintain the stability of the output signal and reduce power consumption by operating with a single power supply.

Description

[Technical field]

[0001] The present disclosure relates to the technical field of power management, and in particular to a voltage conversion device, a power chip, and an electronic device. [Background technology]

[0002] A voltage conversion device is usually used in a semiconductor circuit to convert a signal level in one voltage domain to a different voltage level in another voltage domain. Currently, a voltage conversion device in the related art usually performs level conversion using two power supplies. If one of the power supplies stops working for some reason, the voltage conversion device in the related art cannot operate stably, the output signal becomes unstable, and a through current flows in a downstream circuit that operates according to the output signal. In addition, the voltage conversion device in the related art has a problem of high power consumption when realizing its function. Summary of the Invention

[0003] In view of this, the present disclosure provides a voltage conversion device, the voltage conversion device including a first NMOS transistor and a voltage holding unit, used for converting an input signal belonging to a first voltage range into an output signal belonging to a second voltage range, comprising: A gate of the first NMOS transistor is used for receiving an input signal, and a drain of the first NMOS transistor is electrically connected to a first end of the voltage holding unit, and a voltage signal at the first end of the voltage holding unit is an inverted signal of the output signal; Provided is a voltage conversion device in which a power supply terminal of the voltage holding unit is used for inputting a first power supply voltage, a ground terminal of the voltage holding unit is grounded, and a second terminal of the voltage holding unit is used for generating the output signal, and the voltage holding unit is used to maintain the potential of an inverted signal of the output signal at the first terminal and to maintain the potential of the output signal at the second terminal when a second power supply voltage generating the input signal disappears after being maintained for a certain period of time.

[0004] In one possible embodiment, the voltage holding unit includes a first inverter and a second inverter, the first inverter and the second inverter being cross-coupled.

[0005] In one possible embodiment, the first inverter includes a second NMOS transistor and a first PMOS transistor, and the second inverter includes a third NMOS transistor and a second PMOS transistor; a drain of the second NMOS transistor is electrically connected to the drain of the first PMOS transistor, the gate of the third NMOS transistor, the gate of the second PMOS transistor and the drain of the first NMOS transistor, and is used for generating an inverted signal of the output signal; a gate of the second NMOS transistor is electrically connected to the gate of the first PMOS transistor, the drain of the third NMOS transistor and the drain of the second PMOS transistor, and is used to generate the output signal; The source of the second NMOS transistor is electrically connected to the source of the third NMOS transistor and is used to ground; The source of the first PMOS transistor is electrically connected to the source of the second PMOS transistor and is used to receive the first power supply voltage.

[0006] In one possible embodiment, the source of the first NMOS transistor is electrically connected to the source of the second NMOS transistor and to the source of the third NMOS transistor.

[0007] In one possible embodiment, the voltage conversion device further includes a fourth NMOS transistor, a fifth NMOS transistor, and a sixth NMOS transistor; The drain of the fourth NMOS transistor is electrically connected to the source of the first NMOS transistor, the gate of the fourth NMOS transistor is used to receive the second power supply voltage, and the source of the fourth NMOS transistor is grounded; A drain of the fifth NMOS transistor is electrically connected to a second end of the voltage holding unit, and a gate of the fifth NMOS transistor is used to receive an inverted signal of the input signal; A drain of the sixth NMOS transistor is electrically connected to a source of the fifth NMOS transistor, a gate of the sixth NMOS transistor is used to receive the second power supply voltage, and a source of the sixth NMOS transistor is grounded.

[0008] In one possible embodiment, the voltage of the first power supply voltage is higher than the voltage of the second power supply voltage.

[0009] According to another aspect of the present disclosure, there is provided a power chip including the voltage conversion device.

[0010] According to another aspect of the present disclosure, there is provided an electronic device including the power chip.

[0011] In one possible embodiment, the electronic device includes a portable computer, an intelligent handheld electronic device.

[0012] The voltage conversion device according to the embodiment of the present disclosure can maintain the potential of the inverted signal of the output signal at the first terminal and the potential of the output signal at the second terminal when the second power supply voltage generating the input signal is maintained for a certain period of time and then disappears, thereby making it possible to maintain the stability of the output signal when one of the power supplies stops operating, and to reduce power consumption by operating with one power supply.

[0013] Other features and aspects of the present disclosure will become apparent from the following detailed description of illustrative embodiments taken in conjunction with the drawings. [Brief description of the drawings]

[0014] The drawings, which are incorporated in and constitute a part of the specification, illustrate exemplary embodiments, features and aspects of the disclosure and, together with the specification, serve to explain the principles of the disclosure. [Figure 1] 1 shows a schematic diagram of a voltage conversion device according to an embodiment of the present disclosure. [Diagram 2] 1 shows a schematic diagram of a voltage conversion device according to an embodiment of the present disclosure. [Diagram 3] 1 shows a schematic diagram of a voltage conversion device according to an embodiment of the present disclosure. [Figure 4] 2 shows a schematic diagram of the effect of the operation of a voltage conversion device according to an embodiment of the present disclosure; [Diagram 5] 2 shows a schematic diagram of the effect of the operation of a voltage conversion device according to an embodiment of the present disclosure; DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0015] Various exemplary embodiments, features, and aspects of the present disclosure are described in detail below with reference to the drawings, in which like reference numerals indicate functionally identical or similar elements, and in which various aspects of the embodiments are illustrated, but which are not necessarily drawn to scale unless otherwise indicated.

[0016] The terms "first", "second" and similar terms used in this disclosure do not denote any order, number or importance, but are used to distinguish between different components. Similarly, similar terms such as "one", "an" or "the" do not denote a number limitation, but denote the presence of at least one. Similar terms such as "comprise" or "include" mean that the element or part appearing before the term covers the element or part appearing after the term and its equivalents, and does not exclude other elements or parts. Similar terms such as "connect" or "connect" are not limited to physical or mechanical connections, but may include direct or indirect electrical connections. "Top", "bottom", "left", "right", and the like are merely relative positional relationships, and these relative positional relationships may change depending on the absolute position of the object being described.

[0017] The word "exemplary" herein means "serving as an example, embodiment, or illustration." Any embodiment described herein as "exemplary" is not necessarily to be construed as preferred or superior over other embodiments.

[0018] In addition, in order to better explain the present disclosure, many specific details are shown in the following specific embodiments. It should be understood by those skilled in the art that the present disclosure can be similarly implemented without any specific details. In some instances, in order to emphasize the gist of the present disclosure, methods, means, elements and circuits that are well known to those skilled in the art are not described in detail.

[0019] Referring to FIG. 1, a schematic diagram of a voltage conversion device according to one embodiment of the present disclosure is shown.

[0020] As shown in FIG. 1, the voltage conversion device includes a first NMOS transistor 110 and a voltage holding unit 120, and the voltage conversion device is used to convert an input signal A belonging to a first voltage range into an output signal Y belonging to a second voltage range.

[0021] Here, the gate of the first NMOS transistor 110 is used to receive an input signal A, the drain of the first NMOS transistor 110 is electrically connected to a first end of the voltage holding unit 120, and the voltage signal Y at the first end of the voltage holding unit 120 is b is the inverted signal of the output signal Y.

[0022] The power supply terminal of the voltage holding unit 120 is connected to a first power supply voltage V DDH A first end of the voltage holding unit 120 is connected to ground, and a second end of the voltage holding unit 120 is used to generate the output signal Y. Here, when the second power supply voltage generating the input signal A disappears after being maintained for a certain period of time, the voltage holding unit 120 outputs an inverted signal Y of the output signal Y at the first end. b is used to maintain the potential of the output signal Y at the first end and to maintain the potential of the output signal Y at the second end.

[0023] The voltage conversion device according to the embodiment of the present disclosure can maintain the potential of the inverted signal of the output signal at the first terminal and the potential of the output signal at the second terminal when the second power supply voltage generating the input signal is maintained for a certain period of time and then disappears, thereby making it possible to maintain the stability of the output signal when one of the power supplies stops operating, and to reduce power consumption by operating with one power supply.

[0024] The voltage conversion device of the embodiment of the present disclosure can be applied to a power chip, and the power chip can be applied to an electronic device. Here, the electronic device may include digital products such as mobile phones, speakers, smart wearable devices, digital cameras, mp3, mp4, routers, e-books, switches, modems, PSPs, PS3s, NDSs, XBOXs, U-disks, digital satellite receivers, and may also include computer motherboards, printer BIOS, graphics card BIOS, mice, displays, optical drives, hard disks, keyboards, GPS terminals, precision electronic instruments (e.g., nuclear magnetic resonance devices), and the like. In one example, the first voltage range may be a voltage range formed by the second power supply voltage and the ground voltage, and the second voltage range may be a range formed by the first power supply voltage and the ground voltage.

[0025] In one example, the voltage conversion device may be a level shifter.

[0026] In one possible embodiment, the voltage of the first power supply voltage may be higher than the voltage of the second power supply voltage, and the voltage of the first power supply voltage may be higher than the logic 1 potential of the input signal A.

[0027] In one example, if the second voltage power supply for generating the input signal A is lost after the input signal A remains at a logic 1 potential for a certain period of time, the first NMOS transistor 110 will not turn on the inverted output signal Y b When the potential of the input signal A falls to the reference ground due to the disappearance of the second voltage power supply, the channel of the first NMOS transistor 110 exhibits high impedance, so that the potential of the output signal Y and the inverted output signal Y of the voltage holding unit 120 fall to the reference ground. b are the high potentials (V DDH) and low potential (close to this reference ground). That is, in the voltage conversion device, if the second voltage power supply for generating the input signal A is maintained for a certain period of time, effective transmission and retention of the logic state can be ensured, thereby reducing the power consumption of the entire circuit.

[0028] In one possible embodiment, the voltage holding unit 120 may be realized by a hardware circuit.

[0029] Referring to FIG. 2, a schematic diagram of a voltage conversion device according to one embodiment of the present disclosure is shown.

[0030] In one possible embodiment, the voltage hold unit 120 may include a first inverter and a second inverter, where the first inverter and the second inverter are cross-coupled.

[0031] In the embodiment of the present disclosure, the first inverter and the second inverter are cross-coupled to realize the potential holding function of the voltage holding unit.

[0032] In one possible embodiment, as shown in FIG. 2, the first inverter includes a second NMOS transistor 121a and a first PMOS transistor 122a, and the second inverter includes a third NMOS transistor 121b and a second PMOS transistor 122b.

[0033] Here, the drain of the second NMOS transistor 121a is electrically connected to the drain of the first PMOS transistor 122a, the gate of the third NMOS transistor 121b, the gate of the second PMOS transistor 122b and the drain of the first NMOS transistor, and is used to generate an inverted signal of the output signal.

[0034] The gate of the second NMOS transistor 121a is electrically connected to the gate of the first PMOS transistor 122a, the drain of the third NMOS transistor 121b and the drain of the second PMOS transistor 122b, and is used to generate the output signal.

[0035] The source of the second NMOS transistor 121a is electrically connected to the source of the third NMOS transistor 121b and is used for grounding.

[0036] The source of the first PMOS transistor 122a is electrically connected to the source of the second PMOS transistor 122b and is used to receive the first power supply voltage.

[0037] In one possible embodiment, the source of the first NMOS transistor 110 is electrically connected to the source of the second NMOS transistor 121a and to the source of the third NMOS transistor 121b.

[0038] In one example, under the control of the second power supply voltage, the voltage conversion device receives an input signal A, the voltage range of the input signal A is between the second power supply voltage and the ground voltage, and the voltage conversion device can convert the input signal A belonging to between the second power supply voltage and the ground voltage into an output signal Y between the first power supply voltage and the ground voltage. Assuming that the input signal A is logic 1, the first NMOS transistor 110 is turned on, and the drain of the first NMOS transistor 110 (i.e., the first end of the voltage holding unit) becomes a low level. In this case, the second PMOS transistor 122b is turned on, the third NMOS transistor 121b is turned off, and the drain of the third NMOS transistor 121b (i.e., the second end of the voltage holding unit, the output end of the voltage conversion device) becomes a high level logic 1. When the second power supply voltage is powered down and the input signal A goes from high level to low level (in fact, the input signal A remains at high level), the first inverter formed by the second NMOS transistor 121a and the first PMOS transistor 122a and the second inverter formed by the third NMOS transistor 121b and the second PMOS transistor 122b are cross-coupled, so that the second end of the voltage holding unit maintains the output signal Y at a high level, and the first end of the voltage holding unit maintains the inverted signal Y at a high level. b can be kept at a low level.

[0039] The above describes the case where the second power supply voltage directly supplies power to the input signal A, but the second power supply voltage may also supply power to the input signal A in other forms, which are described below as examples.

[0040] Referring to FIG. 3, a schematic diagram of a voltage conversion device according to one embodiment of the present disclosure is shown.

[0041] In one possible embodiment, as shown in FIG. 3, the voltage converter further includes a fourth NMOS transistor 110a, a fifth NMOS transistor 112 and a sixth NMOS transistor 112a.

[0042] Here, the drain of the fourth NMOS transistor 110a is electrically connected to the source of the first NMOS transistor, and the gate of the fourth NMOS transistor 110a is connected to the second power supply voltage V DDL , and the source of the fourth NMOS transistor 110a is grounded.

[0043] The drain of the fifth NMOS transistor 112 is electrically connected to the second end of the voltage holding unit 120, and the gate of the fifth NMOS transistor 112 is electrically connected to the inverted signal A of the input signal. b is used to receive

[0044] The drain of the sixth NMOS transistor 112a is electrically connected to the source of the fifth NMOS transistor 112, and the gate of the sixth NMOS transistor 112a is connected to the second power supply voltage V DDL , and the source of the sixth NMOS transistor 112a is grounded.

[0045] The voltage holding unit 120 may be described above, and will not be described again here.

[0046] In one example, the second power supply voltage V DDL However, when the input signal A disappears after maintaining a logic 1 potential for a certain period of time, the fourth NMOS transistor 110a and the sixth NMOS transistor 112a are turned off, and accordingly, the first NMOS transistor 110 and the fifth NMOS transistor 112 are turned off. As a result, the output signal Y of the voltage holding unit 120 and the inverted signal Y of the output signal Y are b are the high potentials (V DDH ) and low potential (close to this reference ground). That is, the voltage converter is maintained at the second power supply voltage V DDL If the second power supply voltage V is maintained for a certain period of time, effective transfer and retention of the logic state can be ensured, thereby reducing the power consumption of the entire circuit. DDLThis can avoid data loss caused by abnormal power down and maintain the stability of the circuit.

[0047] 4 and 5, schematic diagrams of the operation effect of a voltage conversion device according to an embodiment of the present disclosure are shown in FIG. 4 and FIG.

[0048] According to the voltage conversion device of the embodiment of the present disclosure, as shown in FIG. DDL When the power is turned off after maintaining the high level for a certain period of time, the level of the input signal A also drops from high to low, but due to the action of the voltage holding unit, the output signal Y is held at high level, and the normal and stable output of the circuit is maintained.

[0049] According to the voltage conversion device of the embodiment of the present disclosure, as shown in FIG. 5, when an input signal A is input to the voltage conversion device, the logic state of the output signal Y at the output end of the voltage conversion device can change in phase according to the logic state of the input signal A. DDH is 5.5V, and V DDL is 2.5V, the logic 1 potential of the input signal A is equal to 2.5V, the logic 1 potential of the output signal Y is equal to 5.5V, and when the input signal is logic 1 or logic 0, the voltage conversion device can still output the output signal Y in phase with the input signal A even if the second power supply voltage that controls the potential of the input signal A is powered down (shown in FIG. 4 ).

[0050] By using the above voltage conversion device, the embodiment of the present disclosure can effectively maintain the logic state of the output signal using only the bias voltage of the high-voltage first power supply voltage after the low-voltage second power supply voltage disappears, which on the one hand maintains the stability of the circuit, and on the other hand does not require constant voltage output from the low-voltage power supply, thereby further reducing power consumption.

[0051] Although the embodiments of the present disclosure have been described above, the above description is merely illustrative and not exhaustive, and is not limited to the embodiments disclosed. Various modifications and changes are obvious to those skilled in the art without departing from the scope and spirit of the embodiments described. The terms selected in this specification are intended to appropriately interpret the principles, practical applications, or improvements to existing technology of the embodiments, or to allow other skilled in the art to understand the embodiments disclosed in this specification.

Claims

1. 1. A voltage conversion device, comprising: a first NMOS transistor and a voltage holding unit, the voltage conversion device being used to convert an input signal belonging to a first voltage range to an output signal belonging to a second voltage range, A gate of the first NMOS transistor is used for receiving an input signal, and a drain of the first NMOS transistor is electrically connected to a first end of the voltage holding unit, and a voltage signal at the first end of the voltage holding unit is an inverted signal of the output signal; a power supply terminal of the voltage holding unit is used for inputting a first power supply voltage, a ground terminal of the voltage holding unit is grounded, and a second terminal of the voltage holding unit is used for generating the output signal, and the voltage holding unit is used for maintaining a potential of an inverted signal of the output signal at the first terminal and maintaining a potential of the output signal at the second terminal when the second power supply voltage generating the input signal disappears after being maintained for a certain period of time; the voltage holding unit includes a first inverter and a second inverter, the first inverter and the second inverter being cross-coupled; the first inverter includes a second NMOS transistor and a first PMOS transistor, the second inverter includes a third NMOS transistor and a second PMOS transistor; a drain of the second NMOS transistor is electrically connected to the drain of the first PMOS transistor, the gate of the third NMOS transistor, the gate of the second PMOS transistor, and the drain of the first NMOS transistor, and is used for generating an inverted signal of the output signal; a gate of the second NMOS transistor is electrically connected to the gate of the first PMOS transistor, the drain of the third NMOS transistor and the drain of the second PMOS transistor, and is used to generate the output signal; The source of the second NMOS transistor is electrically connected to the source of the third NMOS transistor and is used to ground; a source of the first PMOS transistor is electrically connected to a source of the second PMOS transistor and is used to receive the first power supply voltage; a source of the first NMOS transistor is electrically connected to a source of the second NMOS transistor and a source of the third NMOS transistor; the voltage conversion device includes one each of the power supply terminal, the ground terminal, and a signal input terminal, the signal input terminal being only the gate of the first NMOS transistor; an input signal to the voltage holding unit is input from a drain of the first NMOS transistor to the first end of the voltage holding unit; when the input signal is logic 1, the first NMOS transistor is turned on, the drain of the first NMOS transistor is at a low level, the second PMOS transistor is turned on, the third NMOS transistor is turned off, and the drain of the third NMOS transistor is at a high level logic 1; when the second power supply voltage is powered down and the input signal goes from a high level to a low level, the first inverter constituted by the second NMOS transistor and the first PMOS transistor and the second inverter constituted by the third NMOS transistor and the second PMOS transistor are cross-coupled, so that the second end of the voltage holding unit can maintain the output signal at a high level and the first end of the voltage holding unit can maintain an inverted signal at a low level.

2. 2. The voltage conversion device according to claim 1, wherein the first power supply voltage is higher than the second power supply voltage.

3. A power supply chip comprising the voltage conversion device according to any one of claims 1 to 2.

4. An electronic device comprising the power chip according to claim 3.

5. 5. The electronic device of claim 4, wherein the electronic device includes a portable computer, an intelligent handheld electronic device.

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