Substrate for printed circuit, printed circuit, and method for manufacturing substrate for printed circuit

Abstract

The disclosed printed circuit board is provided with: a base film mainly composed of polyimide; and a conductive layer formed on at least one surface side of the base film. The conductive layer has a metal sintered layer formed on the base film, and an electroless plating layer formed on the metal sintered layer. In the base film, the number of voids having a maximum width of 5 μm or more in a plane view is 10 or less per a reference unit area of 0.25 mm2 in the surface of the base film.

Description

[Technical field]

[0001] The present disclosure relates to a substrate for printed circuits, a printed circuit, and a method for manufacturing a substrate for printed circuits. This application claims priority to Japanese Application No. 2020-171170 filed on October 9, 2020, and incorporates by reference all of the contents of said Japanese application. [Background technology]

[0002] Patent Document 1 discloses a substrate for printed circuits that includes a base film mainly made of polyimide and a conductive layer.

[0003] The conductive layer of Patent Document 1 has a first conductive layer formed by applying and baking a conductive ink containing metal particles, and a second conductive layer formed by electroless plating on one side of the first conductive layer.

[0004] The manufacturing method of the printed circuit board in Patent Document 1 includes the steps of forming a first conductive layer by applying and baking a conductive ink on one side of a base film, forming a second conductive layer on the surface of the first conductive layer after forming the first conductive layer by performing electroless plating using palladium as a catalyst, and dispersing palladium in the base film by heat treatment after the electroless plating.

[0005] In Patent Document 1, the process of forming the second conductive layer by electroless plating includes a process of adsorbing palladium to the first conductive layer, and a process of immersing the laminate on which the first conductive layer is formed in an electroless plating solution to deposit a metal such as copper that will become the second conductive layer on the surface of the first conductive layer. [Prior art documents] [Patent documents]

[0006] [Patent Document 1] JP 2016-119424 A Summary of the Invention

[0007] One aspect of the present disclosure is a substrate for a printed circuit. The substrate disclosed includes a base film mainly composed of polyimide and a conductor layer formed on at least one side of the base film, the conductor layer having a metal sintered layer formed on the base film and an electroless plating layer formed on the metal sintered layer, and the number of voids having a maximum width of 5 μm or more in a plan view in the base film is within 0.25 mm2 of the surface of the base film. 2 There are 10 or less particles per unit area.

[0008] Another aspect of the present disclosure is a printed circuit. The disclosed printed circuit includes a base film mainly composed of polyimide and a conductive pattern formed on at least one surface side of the base film, the conductive pattern has a minimum conductor width and a minimum conductor spacing, and either or both of the minimum conductor width and the minimum conductor spacing are 20 μm or less, the conductive pattern includes a metal sintered layer formed on the base film and an electroless plating layer formed on the metal sintered layer, and the number of voids having a maximum width of 5 μm or more in a plan view in the base film is within 0.25 mm2 of the surface of the base film. 2 There are 10 or less particles per unit area.

[0009] Another aspect of the present disclosure is a method for producing a substrate for printed circuits, comprising the steps of forming a first conductor layer, which is a metal sintered layer, on one side of a base film mainly composed of polyimide, and forming a second conductor layer on the first conductor layer by electroless plating using a catalyst, the step of forming the second conductor layer including precipitating a conductor serving as the catalyst from the electroless plating solution on the first conductor layer by electrolytic assistance in which a potential is applied to the first conductor layer in an electroless plating solution. [Brief description of the drawings]

[0010] [Figure 1] FIG. 1 is a schematic cross-sectional view of a substrate for printed circuits according to an embodiment. [Diagram 2] FIG. 2 is a flowchart showing a method for producing a printed circuit board according to an embodiment. [Diagram 3] FIG. 3 is a schematic plan view showing the electroless plating apparatus. [Figure 4] FIG. 4 is a schematic cross-sectional view of a printed circuit. [Diagram 5] FIG. 5 is a schematic cross-sectional view showing the inner wall and the periphery of a through-hole included in a base film. [Figure 6] FIG. 6 is a flowchart showing a method for producing a printed circuit board according to a reference example. [Figure 7] FIG. 7 is a schematic cross-sectional view of a printed circuit board according to a reference example. [Figure 8] FIG. 8 is an enlarged cross-sectional view of a location where a void occurs in a printed circuit board according to a reference example. [Figure 9] FIG. 9 is an enlarged cross-sectional view of the base film after the conductor layer has been removed by etching from the circuit substrate shown in FIG. [Figure 10] FIG. 10 is an enlarged image (schematic diagram) of a location where voids occur on the surface of the base film. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011] [Problem that this disclosure aims to solve] When a conductive layer is formed by electroless plating as in Patent Document 1, voids are generated in the base film, which is mainly composed of polyimide. The voids are cavities that occur inside the base film. The voids are formed near the interface between the base film and the conductive layer, and cause the surface of the base film to expand locally.

[0012] The present inventors have found that voids in a base film cause circuit defects in printed circuits having fine patterns. The voids are relatively small, about several μm in size. For this reason, in the case of normal printed circuits in which the conductor width or conductor spacing of the conductive pattern is sufficiently larger than the voids, the presence of voids is hardly a problem. However, in the case of fine patterns, the conductor width or conductor spacing is fine, so the presence of voids causes circuit defects. For example, when the size of the voids is equal to or larger than the narrow conductor width, if a conductor is present on the surface of the base film expanded by the voids, the conductor may peel off, causing a conduction defect. In addition, the peeling of the conductor may cause insulation defects between the conductors.

[0013] Therefore, a fine pattern printed circuit board having a base film mainly composed of polyimide and an electroless plating layer is provided. Base material In such a case, it is desirable to suppress circuit defects. [Effects of this disclosure]

[0014] According to the present disclosure, circuit defects in printed circuits having fine patterns can be suppressed.

[0015] [Description of the embodiments of the present disclosure]

[0016] (1) A printed circuit board according to an embodiment of the present invention comprises a base film mainly composed of polyimide and a conductor layer formed on at least one surface side of the base film, the conductor layer having a metal sintered layer formed on the base film and an electroless plating layer formed on the metal sintered layer, and the number of voids having a maximum width of 5 μm or more in a plan view in the base film is within 0.25 mm 2In particular, when the printed circuit board according to the embodiment is used in a printed circuit having a fine pattern (e.g., one or both of a minimum conductor width and a minimum conductor spacing are 20 μm or less), the number of voids that may cause circuit defects is small, thereby making it possible to suppress circuit defects in the fine pattern printed circuit. Here, the fine pattern has both or either one of a minimum conductor width of 20 μm or less and a minimum conductor spacing of 20 μm or less. Hereinafter, unless otherwise specified, the "voids" described in this specification refer to voids formed in the base film near the interface between the base film and the conductor layer.

[0017] (2) The conductor layer may further include an electroplating layer or a metal foil layer on the electroless plating layer. The conductor layer further includes an electroplating layer or a metal foil layer on the electroless plating layer. By forming the electroplating layer or the metal foil layer, the thickness of the entire conductor layer can be easily and accurately adjusted. The metal foil layer may be an extremely thin metal foil layer, for example, an extremely thin copper foil layer.

[0018] (3) The number of the voids per reference unit area may be equal to or less than 5. A smaller number of voids can further suppress circuit defects.

[0019] (4) The base film does not contain palladium. "The base film does not contain palladium" means that the base film does not contain any palladium at all, or that the base film does not substantially contain palladium. "The base film does not substantially contain palladium" means that the base film does not contain palladium except for the amount that is inevitably contained. The amount that is inevitably contained is, for example, a content of 0.05 ppm or more and 10 ppm or less, which is the result of cutting out the polyimide on the base film surface on the conductor layer side and performing ICP analysis. By not containing palladium, the generation of voids in the base film can be suppressed.

[0020] (5) The height of the base film surface at a portion where the voids are present relative to the base film surface at a portion where the voids are not present may be 1.5 μm or more. If the height of the voids is 1.5 μm or more, the voids are likely to cause circuit defects, but as described above, the number of voids is small, so that circuit defects are appropriately suppressed. Here, the height of the voids is measured by observing the surface of the base film from which the conductor layer has been removed with a laser microscope.

[0021] (6) A printed circuit according to an embodiment of the present invention comprises a base film mainly composed of polyimide and a conductive pattern formed on at least one surface side of the base film, the conductive pattern having a minimum conductor width and a minimum conductor spacing, and either or both of the minimum conductor width and the minimum conductor spacing are 20 μm or less, the conductive pattern includes a metal sintered layer formed on the base film and an electroless plating layer formed on the metal sintered layer, and the number of voids in the base film having a maximum width of 5 μm or more in a planar view is within 0.25 mm2 of the surface of the base film. 2 The number of voids per unit area is 10 or less. The small number of voids that may cause circuit defects can suppress circuit defects in fine pattern printed circuits.

[0022] (7) In the printed circuit according to the embodiment, either or both of the minimum conductor width and the minimum conductor spacing are 15 μm or less. Since the number of voids that may cause circuit defects is reduced, circuit defects in the fine pattern printed circuit can be suppressed.

[0023] (8) The base film has a through hole penetrating in the thickness direction.

[0024] (9) A method for manufacturing a substrate for a printed circuit board according to an embodiment includes the steps of forming a first conductor layer, which is a metal sintered layer, on one side of a base film mainly composed of polyimide, and forming a second conductor layer on the first conductor layer by electroless plating using a catalyst, and the step of forming the second conductor layer includes precipitating a conductor serving as the catalyst from the electroless plating solution onto the first conductor layer by electrolytic assistance in which a potential is applied to the first conductor layer in an electroless plating solution.

[0025] [Details of the embodiment of the present disclosure]

[0026] Hereinafter, details of the embodiments of the present disclosure will be described with reference to the drawings.

[0027] [Printed circuit boards]

[0028] 1 includes an insulating base film 1 and a conductor layer 2 laminated on at least one surface of the base film 1. A printed circuit 300 is manufactured by forming a conductive pattern of a circuit on the conductor layer 2 of the printed circuit substrate 200. The printed circuit 300 is, for example, a flexible printed circuit (FPC).

[0029] [Base film]

[0030] The base film 1 is a sheet-like member that supports a conductive pattern in a printed circuit 300 formed using a substrate 200 for printed circuits.

[0031] In the embodiment, the material of the base film 1 is polyimide. The base film 1 only needs to be mainly composed of polyimide, and may contain other components. The "main component" here refers to a component with a content of 50 wt% or more. Alternatively, the "main component" refers to a component with the largest content among the components contained. Polyimide may be used because it has a strong bond with metal oxides and the like formed on the surface of the conductor layer 2.

[0032] The thickness of the base film 1 is set by the printed circuit 300 using the printed circuit substrate 200 and is not particularly limited, but for example, the lower limit of the average thickness of the base film 1 may be 5 μm or 12 μm. On the other hand, the upper limit of the average thickness of the base film 1 may be 2 mm or 1.6 mm. If the average thickness of the base film 1 is less than 5 μm, the strength of the base film 1 may be insufficient. Conversely, if the average thickness of the base film 1 exceeds 2 mm, it may be difficult to make the printed circuit 300 thinner.

[0033] The base film 1 may be subjected to a hydrophilization treatment on the surface on which the conductor layer 2 is laminated. The hydrophilization treatment may be, for example, a plasma treatment in which the surface is hydrophilized by irradiating the surface with plasma, or an alkali treatment in which the surface is hydrophilized with an alkaline solution. By subjecting the base film 1 to a hydrophilization treatment, the surface tension of the conductive ink relative to the base film 1 is reduced, making it easier to apply the conductive ink uniformly to the base film 1.

[0034] [Conductor layer]

[0035] The conductor layer 2 has at least a first conductor layer 4 and a second conductor layer 5. The conductor layer 2 may further have the first conductor layer 4, the second conductor layer 5, and a third conductor layer 6 formed on the second conductor layer 5. The first conductor layer 4 is a fired conductor layer formed by applying and firing a conductive ink containing conductor particles such as metal particles. The first conductor layer 4 is formed on the base film 1. The second conductor layer 5 is an electroless plating layer formed by electroless plating on one surface side of the first conductor layer 4 (the side opposite to the base film 1). The third conductor layer 6 is, for example, an electroplating layer formed by electroplating on one surface side of the second conductor layer 5 (the side opposite to the base film 1).

[0036] The thickness of the conductor layer 2 is determined depending on what kind of printed circuit 300 is to be produced using the printed circuit board 200. The lower limit of the average thickness of the conductor layer 2 is not particularly limited, but may be 1 μm or 2 μm. On the other hand, the upper limit of the average thickness of the conductor layer 2 is not particularly limited, but may be 100 μm or 50 μm. If the average thickness of the conductor layer 2 is less than 1 μm, the conductor layer 2 may be easily damaged. Conversely, if the average thickness of the conductor layer 2 exceeds 100 μm, it may be difficult to make the printed circuit 300 thinner.

[0037] [First conductor layer]

[0038] The first conductor layer 4 is a metal sintered layer. The metal sintered layer is, for example, a sintered layer of metal particles. The first conductor layer 4 is formed, for example, by applying and baking a conductive ink containing metal particles. The first conductor layer 4 is laminated on one side of the base film 1. In the printed circuit board 200, the first conductor layer 4 is formed by applying and baking a conductive ink, so that one side of the base film 1 can be easily covered with a conductive coating. In addition, in order to remove unnecessary organic matter and the like in the conductive ink and reliably fix the metal particles to one side of the base film 1, the first conductor layer 4 is formed by applying the conductive ink and then baking it.

[0039] The conductive ink forming the first conductor layer 4 contains metal particles as a conductive material that provides conductivity. In this embodiment, the conductive ink used contains metal particles, a dispersant for dispersing the metal particles, and a dispersion medium. By applying such a conductive ink, the first conductor layer 4 made of fine metal particles is laminated on one side of the base film 1.

[0040] The metal constituting the metal particles contained in the conductive ink is not particularly limited, but may be one that generates a metal oxide based on that metal or a group derived from that metal oxide, and a metal hydroxide based on that metal or a group derived from that metal hydroxide, from the viewpoint of improving the adhesion between the first conductor layer 4 and the base film 1, and may be, for example, copper, nickel, aluminum, gold, or silver. Among these, copper may be used because of its good conductivity and excellent adhesion to the base film 1.

[0041] The lower limit of the average particle size of the metal particles contained in the conductive ink may be 1 nm or 30 nm. On the other hand, the upper limit of the average particle size of the metal particles may be 500 nm or 100 nm. If the average particle size of the metal particles is less than 1 nm, the dispersibility and stability of the metal particles in the conductive ink may be reduced. Conversely, if the average particle size of the metal particles is more than 500 nm, the metal particles may be more likely to settle, or the density of the metal particles may be less uniform when the conductive ink is applied.

[0042] The lower limit of the average thickness of the first conductor layer 4 may be 0.05 μm or 0.1 μm. On the other hand, the upper limit of the average thickness of the first conductor layer 4 may be 2 μm or 1.5 μm. If the average thickness of the first conductor layer 4 is less than 0.05 μm, there is a risk that the first conductor layer 4 will have a break and the conductivity will decrease. On the other hand, if the average thickness of the first conductor layer 4 exceeds 2 μm, there is a risk that it will be difficult to make the conductor layer 2 thin, or that the pores in the first conductor layer 4 cannot be filled with metal when forming the second conductor layer 5 described later, and therefore the conductivity and strength of the first conductor layer 4 and the conductor layer 2 may be insufficient.

[0043] [Second conductor layer]

[0044] The second conductor layer 5 is laminated by electroless plating on the surface of the first conductor layer 4, i.e., the surface opposite the base film 1. Because the second conductor layer 5 is formed by electroless plating in this manner, the metal of the second conductor layer 5 fills the gaps between the metal particles that form the first conductor layer 4. If gaps remain in the first conductor layer 4, these gaps will become the starting points of breakdown and make the first conductor layer 4 more likely to peel off from the base film 1, but peeling of the first conductor layer 4 is suppressed by filling these gaps with the metal that constitutes the second conductor layer 5.

[0045] Metals that can be used for electroless plating include copper, nickel, silver, and the like, which have good conductivity, but when copper is used for the metal particles that form the first conductor layer 4, copper or nickel may be used in consideration of adhesion to the first conductor layer 4. When a metal other than nickel is used for electroless plating, the plating solution used for electroless plating may contain nickel or a nickel compound in addition to the plating metal.

[0046] The lower limit of the average thickness of the second conductor layer 5 formed by electroless plating may be 0.2 μm or 0.3 μm. On the other hand, the upper limit of the average thickness of the second conductor layer 5 formed by electroless plating may be 1 μm or 0.5 μm. If the average thickness of the second conductor layer 5 formed by electroless plating is less than 0.2 μm, the second conductor layer 5 may not be sufficiently filled in the voids of the first conductor layer 4, and the conductivity may decrease. Conversely, if the average thickness of the second conductor layer 5 formed by electroless plating exceeds 1 μm, the time required for electroless plating may be long, and the productivity may decrease.

[0047] [Third conductor layer]

[0048] The third conductor layer 6 is formed, for example, by laminating the third conductor layer 6 on the surface of the second conductor layer 5 formed by electroless plating, by electroplating. In this case, the third conductor layer 6 is an electroplated layer formed by electroplating. The third conductor layer 6 may also be a metal foil layer provided on the surface of the second conductor layer 5. The metal foil layer may be an extremely thin metal foil layer, for example, an extremely thin copper foil layer. The thickness of the metal foil layer is, for example, 0.5 μm or more and 10 μm or less. In this way, by laminating the third conductor layer 6 on the surface of the second conductor layer 5, the thickness of the conductor layer 2 can be easily and accurately adjusted, and a conductor layer having a thickness required to form the printed circuit 300 can be formed in a relatively short time.

[0049] Copper, nickel, silver, etc., which have good conductivity, can be used as a metal used in electroplating to form the third conductor layer 6. When the third conductor layer 6 is an ultra-thin copper foil layer, it can be laminated by bonding it by thermocompression bonding or the like.

[0050] The thickness of the third conductor layer 6 is determined according to the required thickness of the entire conductor layer 2.

[0051] [Method of manufacturing printed circuit boards]

[0052] FIG. 2 shows the steps of a method for producing the printed circuit board shown in FIG.

[0053] In an embodiment, the method for manufacturing a substrate for a printed circuit board includes a conductive ink preparation step (step S11), a conductive ink application and baking step (step S12), an electroless plating step (step S14), a heat treatment step (step S15), and an electroplating step (step S16).

[0054] [Preparation step (step S11)]

[0055] Step S11 preparation In the process, a conductive ink containing metal particles is preparationIn the preparation step, a dispersant is dissolved in a dispersion medium, and the above-mentioned metal particles are dispersed in the dispersion medium. That is, the dispersant surrounds the metal particles, suppressing aggregation and allowing the metal particles to be well dispersed in the dispersion medium. The dispersant may also be added to the reaction system in the form of a solution dissolved in water or a water-soluble organic solvent.

[0056] The dispersion medium for the conductive ink may be water, a highly polar solvent, or a mixture of two or more of these. Of these, a mixture containing water as the main component and a highly polar solvent that is compatible with water is preferably used.

[0057] From the viewpoint of preventing deterioration of the substrate for printed circuits, the dispersant contained in the conductive ink is preferably one that does not contain sulfur, phosphorus, boron, halogens, or alkalis. Examples of such dispersants include amine-based polymer dispersants such as polyethyleneimine and polyvinylpyrrolidone, hydrocarbon-based polymer dispersants having a carboxylic acid group in the molecule such as polyacrylic acid and carboxymethylcellulose, and polymer dispersants having a polar group such as poval (polyvinyl alcohol), styrene-maleic acid copolymer, olefin-maleic acid copolymer, and copolymers having a polyethyleneimine portion and a polyethylene oxide portion in one molecule.

[0058] [Coating and baking process (step S12)]

[0059] In the coating and baking process of step S12, a conductive ink is applied to one side of the insulating base film 1 and baked to form a first conductor layer 4. In the coating and baking process, the conductive ink prepared in step S11 is applied to the surface of the base film 1, dried, and then heated and baked. Note that the surface of the base film 1 to which the conductive ink is applied has been modified in advance by a hydrophilic treatment such as the above-mentioned alkali treatment.

[0060] The conductive ink having dispersed metal particles can be applied to one side of the base film 1 using any conventional coating method such as spin coating, spray coating, bar coating, die coating, slit coating, roll coating, or dip coating. Alternatively, the conductive ink may be applied to only a portion of one surface of the base film 1 by screen printing, a dispenser, or the like.

[0061] Next, the dispersion medium in the conductive ink applied to the base film 1 is evaporated, and the conductive ink is dried.

[0062] The conductive ink can be dried by natural drying, drying by heating, drying by hot air, etc. However, the method should be such that a strong wind that may roughen the surface of the conductive ink before drying is not blown onto it.

[0063] Furthermore, the dried conductive ink is heated to thermally decompose the dispersion medium in the conductive ink and to sinter the metal particles, forming the first conductor layer 4. This sintering process brings the metal particles into a sintered state or into a state prior to sintering where they are in close contact with each other and are solidly bonded together. Therefore, the first conductor layer 4 after this conductive ink application and baking step may have pores that correspond to the gaps between the metal particles.

[0064] The firing is performed in an atmosphere containing a certain amount of oxygen. The lower limit of the oxygen concentration in the firing atmosphere is 1 volume ppm, and may be 10 volume ppm. The upper limit of the oxygen concentration is 10,000 volume ppm, and may be 1,000 volume ppm. If the oxygen concentration is less than 1 volume ppm, the amount of metal oxide generated near the interface of the first conductor layer 4 is small, and the effect of improving the adhesion between the first conductor layer 4 and the base film 1 by the metal oxide may not be sufficiently obtained. On the other hand, if the oxygen concentration exceeds 10,000 volume ppm, the metal particles may be excessively oxidized, and the conductivity of the first conductor layer 4 may be reduced.

[0065] The lower limit of the firing temperature may be 150° C. or 200° C. The upper limit of the firing temperature may be 500° C. or 400° C. If the firing temperature is less than 150° C., the first conductor layer 4 may be damaged. Near the interface Therefore, the amount of metal oxide produced during the baking process may be reduced, and the effect of improving the adhesion between the first conductor layer 4 and the base film 1 due to the metal oxide may not be sufficiently obtained. On the other hand, if the baking temperature exceeds 500° C., the base film 1 may be deformed when it is made of an organic resin such as polyimide.

[0066] [Electroless plating process (step S14)]

[0067] In the electroless plating process of step S14, an electroless plating solution is used to perform electroless plating to deposit metal on the surface of the first conductor layer 4 and in pores inside the first conductor layer 4, thereby forming the second conductor layer 5. Note that, prior to the electroless plating process of step S14, the base film 1 having the first conductor layer 4 formed on its surface may be subjected to degreasing and pickling treatment.

[0068] The electroless plating solution deposits a metal. As described above, examples of the metal to be deposited include copper, nickel, and silver. For example, when copper is to be deposited, a copper plating solution containing a small amount of nickel is used as the copper plating solution used in the electroless plating. By using a copper plating solution containing nickel or a nickel compound, a second conductor layer 5 with low stress can be formed. The copper plating solution may contain, for example, 0.1 mol to 60 mol of nickel per 100 mol of copper. In addition, other components such as a complexing agent, a reducing agent, and a pH adjuster may be appropriately blended into the copper plating solution.

[0069] The electroless plating process in step S14 includes a process (step S14-1) in which a metal (conductor) that serves as a catalyst is deposited on the first conductor layer 4 from an electroless plating solution by electrolytic assistance. In the electroless plating process in step S14, a metal (conductor) is deposited on the surface and inside of the first conductor layer 4 by electroless plating using the metal (conductor) deposited by electrolytic assistance in step S14-1 as a catalyst. In a general electroless plating process, a pretreatment for attaching a catalyst such as palladium is required, but in the electroless plating process in step S14, the metal deposited by electroless plating is used as a catalyst, so that pretreatment for attaching a catalyst such as palladium is not required. Examples of catalysts that can be used in a general electroless plating process include platinum (Pt), nickel (Ni), cobalt (Co), iron (Fe), chromium (Cr), silver (Ag), and gold (Au) in addition to palladium. The printed circuit substrate 200 manufactured by the method for manufacturing a printed circuit substrate of the present disclosure does not contain any, or substantially does not contain, in the base film 1 at least one of palladium (Pd), platinum (Pt), nickel (Ni), cobalt (Co), iron (Fe), chromium (Cr), silver (Ag), and gold (Au).

[0070] Electrolytic assistance is a plating technique in which an electric potential is applied to an article (object to be plated) treated with an electroless plating solution during initial deposition in electroless plating. By performing electrolytic assistance, metal is deposited on the first conductive layer 4 from the electroless plating solution by utilizing electrical energy as in electroplating (electrolytic plating) while using an electroless plating solution. In other words, in electrolytic assistance, plating is performed supplementarily by passing electricity through an electroless plating solution. In the manufacturing method according to the embodiment, before the electroless plating process in step S14, the base film 110, which is an article treated with an electroless plating solution, has a first conductive layer 4 formed on its surface and is conductive. In electrolytic assistance, the fact that the electroless plating process item can be electrified by the first conductor layer 4 is utilized, and metal is deposited on the first conductor layer 4 from the electroless plating solution by electrical energy.

[0071] FIG. 3 includes an electrolytic assist process (step S14-1). None 1 shows an example of an electroless plating apparatus 100 capable of performing the electrolytic plating step (step S14). The electroless plating apparatus 100 includes an electroless plating tank 101 containing an electroless plating solution. The electroless plating apparatus 100 includes rollers 102 that transport a base film 110 having a first conductor layer 4 formed thereon to the electroless plating tank 101. The base film 110 having the first conductor layer 4 formed thereon is transported by the rollers 102 into the electroless plating tank 101 and immersed in the electroless plating solution.

[0072] The roller 102 is made of a conductive material, for example, SUS. The roller 102 is connected to the negative pole of a DC power supply 105, and applies a negative potential to the base film 110 on which the first conductor layer 4 is formed. In this manner, the roller 102 acts as a first electrode that applies a negative potential to the first conductor layer 4 outside the electroless plating tank 101. In addition, a Ti plate that serves as a counter electrode 103 (second electrode) is provided in the electroless plating tank 101. The counter electrode 103 is connected to the positive pole of the DC power supply 105, and a positive potential is applied to the electroless plating solution.

[0073] A negative potential is applied to the first conductive layer 4 from the roller 102 as the first electrode, thereby lowering the potential of the first conductive layer 4 immersed in the electroless plating solution. This causes metals such as copper to be deposited from the electroless plating solution onto the first conductive layer 4 immersed in the electroless plating solution. The metal deposited by electrolytic assistance serves as a catalyst for electroless plating. In this way, the electrolytic assistance process is also a process of attaching a catalyst for electroless plating to the first conductive layer 4.

[0074] In the electroless plating bath 101, electroless plating is performed using the metal deposited by electrolytic assistance as a catalyst. This electroless plating deposits metal on the surface of the first conductor layer 4 to form the second conductor layer 5, and simultaneously deposits metal in the pores inside the first conductor layer 4 to densify the first conductor layer 4. This densification of the first conductor layer 4 not only improves the conductivity of the first conductor layer 4, but also increases the adhesion area of ​​the first conductor layer 4 to the base film 1, thereby increasing the peel strength of the first conductor layer 4 and, ultimately, the conductor layer 2 from the base film 1.

[0075] In the electroless plating process of step S14, when the base film 110 on which the first conductive layer 4 is formed is immersed in the electroless plating solution, electrolytically assisted plating is instantly formed on the surface of the first conductive layer 4, and then electroless plating is formed using the electroless plating solution. This prevents the electroless plating solution from penetrating the base film 1. As a result, damage caused to the base film 1 by the electroless plating solution can be reduced. By reducing the damage caused to the base film 1, thermal decomposition of the base film 1 is reduced. In this way, by forming electrolytically assisted plating on the base film 1, even if the base film 1 is subjected to electroless plating, damage caused by electroless plating is reduced, and a base film 1 with reduced thermal decomposition can be obtained.

[0076] After the electroless plating process in step S14, a post-pickling process may be performed.

[0077] [Heat treatment process (step S15)]

[0078] Returning to FIG. 2, after the electroless plating process, a heat treatment process in step S15 is performed. The lower limit of the treatment temperature in the heat treatment process may be 150° C. or 200° C. Meanwhile, the upper limit of the treatment temperature in the heat treatment process may be 500° C. or 400° C. The lower limit of the heat treatment time in the heat treatment process may be 15 minutes or 30 minutes. Meanwhile, the upper limit of the heat treatment time in the heat treatment process may be 720 minutes or 360 minutes.

[0079] [Electroplating process (step S16)]

[0080] In the electroplating process of step S16, a third conductor layer 6 is formed by further stacking a metal by electroplating on the surface of the second conductor layer 5 formed in the electroless plating process of step S14. At this time, the first conductor layer 4 is made more dense by filling the voids remaining inside the first conductor layer 4 with metal by electroplating, and the peel strength of the first conductor layer 4 from the base film 1 is further increased. This electroplating process allows the thickness of the conductor layer 2 to be easily and reliably grown to a desired thickness.

[0081] As a specific method of electroplating in this electroplating step, a known electroplating method can be applied. Note that, instead of the electroplating step (step S16), thermocompression bonding of an ultra-thin copper foil can be performed. In this case, an ultra-thin copper foil layer is formed as the third conductor layer 6.

[0082] [Printed Circuit]

[0083] The printed circuit 300 is produced by subjecting the printed circuit board 200 shown in FIG. 1 to a circuit pattern forming process for forming a conductive pattern.

[0084] 4 shows a printed circuit 300. Conductive patterns 2A, 2B, and 2C are formed on a base film 1. The conductive patterns 2A, 2B, and 2C in the printed circuit 300 according to the embodiment are fine patterns, and have a very small minimum conductor width W and an equally small minimum conductor spacing S. Here, the minimum conductor width W refers to the smallest of the conductor widths included in the conductive patterns 2A, 2B, and 2C. The minimum conductor spacing refers to the smallest of the spacings between conductors formed by the conductive patterns 2A, 2B, and 2C.

[0085] The minimum conductor width W may be 20 μm or less, 15 μm or less, or 10 μm or less. The minimum conductor spacing S may be 20 μm or less, 15 μm or less, or 10 μm or less. It is sufficient if either the minimum conductor width or the minimum conductor spacing is within the above range, but both the minimum conductor width and the minimum conductor spacing may be within the above range.

[0086] Each of the conductive patterns 2A, 2B, and 2C includes a conductor layer 2 on a base film 1. The conductor layer 2 includes a first conductor layer 4 and a second conductor layer 5 on the first conductor layer. A third conductor layer 6 may be further included on the second conductor layer 5. Each of the conductive patterns 2A, 2B, and 2C may further include one or more fourth conductor layers 7 on the conductor layer 2. The base film 1 may include a through hole penetrating in the thickness direction. FIG. 5 is a schematic cross-sectional view showing the inner wall and surroundings of a through hole when a through hole is included.

[0087] [Manufacturing method of printed circuits]

[0088] The circuit pattern forming process is, for example, a subtractive process or a semi-additive process.

[0089] In the subtractive method, a photosensitive resist is formed and coated on one side of the printed circuit board 200, and the resist is patterned by exposure, development, etc. to correspond to the conductive pattern. Next, the patterned resist is used as a mask to remove the conductive layer 2 except for the conductive pattern by etching. Finally, the remaining resist is removed to obtain the printed circuit 300 having the conductive pattern formed from the remaining portion of the conductive layer 2 of the printed circuit board 200 in FIG. 1.

[0090] In the semi-additive method, a photosensitive resist is formed on one side of the printed circuit board 200, and openings corresponding to the conductive pattern are patterned in the resist by exposure, development, etc. Then, plating is performed using the patterned resist as a mask, and a conductive layer is selectively laminated on the conductive layer 2 exposed in the openings of the mask. Thereafter, the resist is peeled off, and the surface of the conductive layer and the conductive layer 2 on which the conductive layer is not formed are removed by etching, thereby obtaining the printed circuit having a conductive pattern formed by laminating a further conductive layer on the remaining part of the conductive layer 2 of the printed circuit board 200 in FIG. 1.

[0091] The base film 1 in the printed circuit board 200 manufactured by the manufacturing method of FIG. 2 does not contain palladium. This is because the manufacturing method of FIG. 2 does not include a step of attaching palladium as a catalyst for electroless plating in step S14. "The base film does not contain palladium" means that the base film does not contain any palladium at all, or that the base film does not substantially contain palladium. "The base film does not substantially contain palladium" means that the base film does not contain palladium except for the content that is inevitably contained. The content that is inevitably contained is, for example, a content of 0.05 ppm or more and 10 ppm or less, which is the result of cutting out polyimide on the surface of the base film on the conductor layer side and performing ICP analysis.

[0092] The absence of palladium in the base film 1 can suppress the generation of voids (see FIGS. 8 to 10) in the base film 1. The generation of voids will be described in detail later in the description of the method for producing a printed circuit board according to a reference example.

[0093] The base film 1 in the printed circuit board 200 manufactured by the manufacturing method of FIG. 2 has a void count of 0.25 mm 2 The number of voids per standard unit area D is 10 or less. The number of voids per standard unit area D may be 5 or less, or may be 1 or less. It is preferable that the number of voids is zero.

[0094] The voids may have a maximum void width L (see Figs. 8 and 9) of 5 µm to 10 µm in plan view of the base film. Voids with a maximum width L of 5 µm to 10 µm are likely to cause circuit defects in fine patterns such as those described above, but by limiting the number of voids to 10 or less per reference unit area D, the probability of circuit defects occurring can be sufficiently reduced.

[0095] The maximum width L of the void may be 1 / 4 or more times the minimum conductor width W, or 1 / 4 or more times the minimum conductor spacing S. The maximum width L of the void may be 1 / 2 or less times the minimum conductor width W, or 1 / 2 or less times the minimum conductor spacing S. If the maximum width L of the void is this large, it is likely to cause circuit defects in the fine pattern, but by limiting the number of voids to 10 or less per reference unit area D, the probability of circuit defects occurring can be sufficiently suppressed.

[0096] The area of ​​the void is 20 μm 2 More than 100μm 2 If the voids are this large, they are likely to cause circuit defects in fine patterns, but by keeping the number of voids per reference unit area D to 10 or less, the probability of circuit defects occurring can be sufficiently reduced.

[0097] Moreover, the voids may have a height H (see Figs. 8 and 9) of 1.5 µm or more and 5 µm or less. Voids with a large height H are likely to cause circuit defects. As shown in Fig. 9, the height H is defined as the height of the base film surface at a portion 1B where a void is present, relative to the portion 1A where no void is present on the base film. Note that Fig. 9 shows a cross section of the base film after removing the conductor layer 2 by etching from the printed circuit board 200 of Fig. 8. The portion 1A where no void is present on the base film may be selected as the portion with the lowest height on the base film surface. The height H can be determined by scanning the base film surface with a laser microscope.

[0098] [Method of manufacturing a printed circuit board according to a reference example]

[0099] FIG. 6 shows the procedure of a method for manufacturing a printed circuit board according to a reference example. The manufacturing method shown in FIG. 6 differs from the manufacturing method shown in FIG. 2 in that a pretreatment step (step S13) is performed before the electroless plating step, and electrolytic assistance is not performed in the electroless plating step. In the manufacturing method shown in FIG. 6, the conductive ink preparation step (step S11), the conductive ink application and baking step (step S12), and the electroplating step (step S16) are the same as those in the manufacturing method shown in FIG. 2. The pretreatment step (step S13), the electroless plating step (step S14A), and the heat treatment step (step S15) shown in FIG. 6 will be described below.

[0100] [Pretreatment step (step S13)]

[0101] In the pretreatment process of step S13, for example, palladium, which serves as a catalyst in electroless plating, is adsorbed on the first conductive layer 4. In the pretreatment process, the first conductive layer 4 is brought into contact with a catalytic solution containing palladium to adsorb palladium ions, which are then reduced to metallic palladium. The palladium concentration of this catalytic solution can be, for example, 20 ppm by mass or more and 1000 ppm by mass or less.

[0102] The lower limit of the temperature of the catalyst solution during immersion may be 30° C. or 40° C., depending on the immersion time. On the other hand, the upper limit of the temperature of the catalyst solution during immersion may be 70° C. or 60° C.

[0103] The lower limit of the immersion time in the catalyst solution may be 1 minute, 2 minutes, or 3 minutes, depending on the temperature of the catalyst solution, while the upper limit of the immersion time in the catalyst solution may be 10 minutes, 7 minutes, or 5 minutes.

[0104] [Electroless plating process (step S14A: no electrolytic assistance)]

[0105] In the electroless plating process of step S14A, palladium adsorbed on the first conductor layer 4 in the pretreatment process of step S13 is used as a catalyst to deposit metal on the surface and inside of the first conductor layer 4. In the manufacturing method according to the reference example, palladium is used as a catalyst, so electrolytic assistance is not performed.

[0106] In the electroless plating process of step S14A, electroless plating is performed using an electroless plating solution to deposit metal on the surface of the first conductor layer 4 and in the pores inside the first conductor layer 4, thereby forming the second conductor layer 5. S14A Prior to the electroless plating step, the base film 1 having the first conductor layer 4 formed on the surface thereof may be subjected to degreasing and pickling treatment.

[0107] During electroless plating, palladium penetrates into base film 1. In addition, the electroless plating solution penetrates into base film 1 through first conductor layer 4.

[0108] [Heat treatment process (step S15)]

[0109] The heat treatment process of step S15 shown in FIG. 6 is performed in the same manner as the heat treatment process shown in FIG. However, the heat treatment promotes the penetration of palladium present in the vicinity of the interface between the conductor layer 2 and the base film 1 into the base film 1 .

[0110] Fig. 7 shows a printed circuit board in which palladium is dispersed inside a base film 1. The base film 1 shown in Fig. 7 has a dispersion portion 3 in which palladium is dispersed. In the case of the manufacturing method of the reference example shown in Fig. 6, the palladium content in the base film 1 in the dispersion portion 3 is 290 ppm or more as determined by ICP mass spectrometry.

[0111] The dispersed portion 3 is formed by introducing and dispersing palladium from the surface of the base film 1 into the interior of the base film 1. The dispersed portion 3 is formed in a layer shape having a substantially constant thickness such that palladium is introduced and dispersed substantially evenly from the interface between the base film 1 and the conductor layer 2, and occupies part or all of the base film 1 in the thickness direction from the interface with the conductor layer 2. In other words, the dispersed portion 3 may include a region from the interface between the base film 1 and the conductor layer 2 to a certain depth.

[0112] When a printed circuit board is manufactured by the manufacturing method according to the reference example, voids 10 are generated in the base film 1, as shown in Figures 8 to 10. The voids 10 are cavities generated inside the base film 1. The voids 10 are formed in the vicinity of the interface 11 between the base film 1 and the conductor layer 2, and cause the surface of the base film 1 to expand locally toward the conductor layer 2. The voids 10 are generated in a scattered manner on the surface of the base film 1. The voids 10 are irregular in shape, but are formed in roughly dot-like shapes.

[0113] The inventors discovered that the cause of the voids 10 is palladium that has infiltrated into the base film 1, which is mainly composed of polyimide. The palladium catalyst infiltrates into the base film 1 during electroless plating. When the palladium infiltrates into the base film 1 and a reduction reaction occurs due to the catalytic action of the palladium, gas is generated within the base film 1. The generation of gas causes the voids 10 to occur within the base film 1.

[0114] FIG. 8 is an enlarged cross-sectional view of a void occurrence location in a printed circuit board according to a reference example. In the reference example, the void 10 has a maximum width L of about 1 μm to 10 μm in a plan view of the base film. The void 10 has a height H of about 0.1 μm to 5 μm. A large number of voids 10 are confirmed in the base film of the printed circuit board according to the reference example. On the other hand, in the base film 1 of the printed circuit board according to the present disclosure, voids 10 having a maximum width L of 5 μm or more in a plan view are suppressed. Here, the maximum width L of the void 10 according to the reference example and the void suppressed in the printed circuit board according to the present disclosure is measured, for example, by removing the conductor layer 2 of the manufactured printed circuit board by etching and observing the surface of the base film 1 with a fluorescent microscope. The height H of the void 10 is measured, for example, by observing the surface of the base film 1 from which the conductor layer 2 has been removed with a laser microscope.

[0115] The void 10 is relatively small. Therefore, in a normal printed circuit in which the conductor width or conductor spacing is sufficiently larger than the void, the presence of the void 10 is hardly a problem. However, in a printed circuit having a fine pattern, the conductor width or conductor spacing is fine, so the presence of the void 10 may cause a circuit failure. For example, if a conductive pattern with a conductor width equal to or smaller than the size of the void 10 exists directly above the void 10 shown in Figures 8 to 10, a continuity failure of the conductive pattern may occur. Such a circuit failure is more likely to occur as the maximum width L of the void 10 is larger, and is more likely to occur as the height H of the void 10 is larger.

[0116] Thus, when a substrate for fine pattern printed circuits is manufactured by the manufacturing method according to the reference example shown in Fig. 6, voids 10 are generated in the base film 1, which may cause circuit defects in the fine pattern printed circuit. In contrast, when a substrate for fine pattern printed circuits is manufactured by the manufacturing method shown in Fig. 2, the generation of voids 10 can be suppressed. 2, in the electroless plating process, a catalyst generated by electrolytic assistance is used instead of a metal catalyst such as palladium. Since there is no palladium, which causes the generation of voids 10, the generation of voids 10 in the base film 1 is suppressed. When a fine pattern printed circuit is manufactured from a printed circuit substrate with almost no voids 10, the occurrence of circuit defects can be suppressed. EXAMPLES

[0117] The results of prototype printed circuit boards will be described below.

[0118] [1st, 2nd, and 3rd prototypes (with electrolytic assistance: copper catalyst)]

[0119] The first, second and third prototypes of the printed circuit board were manufactured according to steps S11, S12 and S14 shown in FIG. 2. Specifically, they were manufactured as follows. First, copper particles with an average particle size of 60 nm were dispersed in water as a solvent to prepare a conductive ink with a copper concentration of 26 mass%. In addition, both sides of a polyimide film (Kapton "EN-S" by Toray DuPont Co., Ltd.) with an average thickness of 25 μm as an insulating base film were modified by alkali treatment. The conductive ink was applied to both sides of the modified polyimide film, dried in the air, and then heated at 350° C. for 2 hours in a nitrogen atmosphere with an oxygen concentration of 100 ppm by volume to sinter the copper particles in the conductive ink, thereby forming a first conductor layer, which is a sintered layer with an average thickness of 0.15 μm.

[0120] Next, electroless plating (step S14) including electrolytic assistance (step S14-1) was performed using the electroless plating apparatus 100 shown in FIG. 3. In the manufacture of the first, second, and third prototypes, palladium was not used as a catalyst for electroless plating, and copper precipitated from an electroless copper plating solution by electrolytic assistance was used. The electroless copper plating solution used contained 0.1 moles of nickel per 100 moles of copper. A second conductor layer with an average thickness of 0.4 μm was formed on the first conductor layer on both sides of the base film by electroless plating. The formation of the third conductor layer was omitted, and a printed circuit board in which the first conductor layer and the second conductor layer were formed on the base film was obtained. The first, second, and third prototypes were all manufactured by the above manufacturing method, but were manufactured by different manufacturing lines (plating solution tanks).

[0121] [Fourth prototype (no electrolytic assistance: palladium catalyst)]

[0122] The fourth prototype of the printed circuit board was manufactured according to steps S11, S12, S13, and S14A shown in Fig. 6. In manufacturing the fourth prototype, the process was the same as for the first, second, and third prototypes up to the point where the first conductor layer, which is a sintered layer of metal particles, was manufactured.

[0123] In the manufacture of the fourth prototype, after the formation of the first conductive layer, palladium was adsorbed onto the first conductive layer as a pretreatment (step S13). A catalyst solution containing 50 ppm palladium by mass was used, and the first conductive layer was immersed in the solution at a temperature of 40° C. for 120 seconds to adsorb palladium.

[0124] In the manufacture of the fourth prototype, electroless plating (step S14A) using palladium as a catalyst was performed using the electroless plating apparatus 100 shown in FIG. 3 without performing electrolytic assistance (step S14-1). The same electroless copper plating solution was used as that used in the manufacture of the first, second and third prototypes. A second conductor layer with an average thickness of 0.4 μm was formed on the first conductor layer on each side of the base film by electroless plating. The formation of the third conductor layer was omitted, and the first prototype of the substrate for printed circuit board in which the first conductor layer and the second conductor layer were formed on the base film was 4 I got a prototype.

[0125] [Fifth prototype]

[0126] The fifth prototype of the printed circuit board is the fourth prototype with the first conductor layer omitted. In other respects, the fifth prototype is the same as the fourth prototype. That is, the fifth prototype has a base film and a second conductor layer formed directly on the base film. The fifth prototype was manufactured by removing the conductive layer from the manufacturing process of the fourth prototype. sex ink preparation The fifth prototype was manufactured by omitting the step of applying and baking conductive ink (step S11) and the step of applying and baking conductive ink (step S12). The second conductive layer was formed by electroless plating (step S14A) using palladium as a catalyst, using the electroless plating apparatus 100 shown in FIG. 3. However, in the manufacture of the fifth prototype, electrolytic assistance (step S14-1) was not performed.

[0127] [6th prototype]

[0128] The sixth prototype of the printed circuit board is a vacuum deposition layer, instead of the first conductor layer of the first, second, and third prototypes, which is a sintered layer of metal particles. The vacuum deposition was performed using a high vacuum deposition device RD-1400 manufactured by SANVAC, where copper with a purity of 4N was deposited at a vacuum degree of 5 x 10 -4The sixth prototype was similar to the first, second, and third prototypes in other respects. That is, the sixth prototype includes a base film, a first conductor layer which is a vacuum deposition layer formed on the base film, and a second conductor layer formed by an electroless plating process (step S14) including an electrolytic assist process (step S14-1).

[0129] [Measurement of palladium content]

[0130] The palladium content of each prototype was measured by ICP mass spectrometry. The ICPMS analyzer used was an Agilent Technologies ICPMS7700X. As a pretreatment, the exposed polyimide portion of the base film (the interface with the conductor layer 2) was cut out, and the cut polyimide was totally decomposed in 8 mL of concentrated sulfuric acid using microwaves. Ultrapure water was added to the liquid after total decomposition to make the volume constant at 50 mL.

[0131] [Measurement of carbon dioxide emissions]

[0132] In order to evaluate whether the thermal decomposition of the first prototype using electrolytic assistance was suppressed, the amount of carbon dioxide released from the first prototype and the fourth prototype at high temperatures was measured. The size of the first prototype used for the measurement was 20 x 20 mm (8 cm on both sides). 2 ) was decided.

[0133] A thermobalance-mass spectrometer (TG-MS) was used for the measurement. NETZSCH STA449 F5 Jupiter and JEOL JMS-Q1500GC were used as the thermobalance-mass spectrometer. Helium was used as the measurement atmosphere gas. Electron ionization was used as the ionization method for the generated gas components. The temperature conditions were room temperature (RT) to 100°C at a rate of 10°C / min, then to 350°C at a rate of 5°C / min, and held at 350°C for 90 minutes. When held at 350°C for 90 minutes, the amount of carbon dioxide generated from each of the first prototype and the fourth prototype was measured. The amount of carbon dioxide generated was calculated by introducing a known amount of carbon dioxide into the thermobalance-mass spectrometer and creating a calibration curve from the detection intensity. Then, the detection intensity at the time of measurement of each of the first prototype and the fourth prototype was converted into the amount of carbon dioxide generated using the calibration curve.

[0134] In the first prototype, the amount of carbon dioxide generated when left at 350°C for 90 minutes was 0.5μg / cm 2 In the fourth prototype, the amount of carbon dioxide generated when left at 350°C for 90 minutes was 8.3μg / cm 2 Thus, in the first prototype, the amount of carbon dioxide generated when left at 350°C for 90 minutes was 1μg / cm 2 The results are shown below, which shows that damage caused by electroless plating is suppressed and thermal decomposition is inhibited.

[0135] [Observation results of prototype]

[0136] The conductor layer of each of the first to sixth prototypes was etched to expose the base film surface. The etching was performed using an etching solution containing iron chloride (specific gravity 1.33 g / cm 3 The etching was performed by immersing the film in a solution of 0.2 mol / L free hydrochloric acid at 45°C for 2 minutes. After immersion, the film was washed with water and dried. The surface of the base film that was removed by etching was observed. The surface of the base film was observed using an OLYMPUS BX51 metallurgical microscope, and images were taken in bright field.

[0137] In the metallurgical microscope image, 0.25 mm2 The number N of voids per reference unit area D was visually measured. Voids with a maximum width of less than 5 μm were not counted. In other words, the voids that were counted were those with a maximum void width L of 5 μm or more and a height H of 1.5 μm or more in a metallurgical microscope image of the base film viewed in plan.

[0138] The maximum width L of the void was obtained by applying image processing to the metallurgical microscope image to extract the void area and measuring the maximum width of the extracted void area. The area of ​​the void was obtained by counting the number of pixels in the extracted void area. The height H was obtained by scanning the base film surface with a laser microscope.

[0139] The number of voids per reference unit area D was calculated by converting the total number T of voids present in the metallurgical microscope image into the number N of voids per reference unit area D. Specifically, the metallurgical microscope image contained voids within 0.02 mm 2 Since an area of ​​X appears, the number of voids N per unit area D was calculated by T / (X / D).

[0140] No voids with a maximum width of 5 μm or more were observed on the surface of the base film of the first prototype. In other words, the number of voids N per reference unit area D was 0 in the first prototype.

[0141] In the second prototype, the number N of voids per reference unit area D was 3. The maximum width L of the largest void confirmed in the second prototype was 6 μm, and the height H was 3 μm.

[0142] In the third prototype 、 The number N of voids per reference unit area D was 9. The maximum width L of the largest void confirmed in the third prototype was 8 μm, and the height H was 4 μm.

[0143] Voids were present scattered on the surface of the base film of the fourth prototype. In the fourth prototype, the number of voids N per reference unit area D was 76. The maximum width L of the largest void confirmed in the fourth prototype was 8 μm, and the height H was 2 μm.

[0144] In the fifth prototype, the number of voids N per reference unit area D was 135. The largest void among those confirmed in the fifth prototype had a maximum width L of 25 μm and a height H of 2.5 μm.

[0145] In the sixth prototype, the number of voids N per reference unit area D was zero.

[0146] The number N of voids per reference unit area D was evaluated on a four-level scale of A to D. Of these four levels, A or B is considered to be good. The evaluation results are shown below.

[0147] [Table 1]

[0148] A: The number of voids N is 5 or less B: The number of voids N is 6 or more and 10 or less. C: The number of voids N is 11 or more and 100 or less. D: The number of voids N is 101 or more.

[0149] The first, second and third prototypes have fewer voids than the fourth and fifth prototypes, and are therefore suitable for suppressing circuit defects in printed circuits having fine patterns. In particular, the fifth prototype has a very large number of voids, which are also large in size, making it prone to frequent circuit defects and therefore disadvantageous.

[0150] [Evaluation of Pd content] The Pd content was below 7 ppm for the first, second, third and sixth prototypes, which underwent electroless plating with electrolytic assistance. This was Pd that was unintentionally included in each production line (plating solution tank), and was inevitably introduced. Meanwhile, the fourth and fifth prototypes, which underwent electroless plating using a Pd catalyst, had Pd content of 291 ppm and 1485 ppm, respectively.

[0151] [Evaluation of adhesion of prototypes]

[0152] An electrolytic copper plating layer with an average thickness of 20 μm was formed on the second conductor layer of each of the first to sixth prototypes by electrolytic copper plating, and these were used to evaluate adhesion. Value The samples were used. The adhesion strength was evaluated by measuring the peel strength between the polyimide base film and the conductor layer in accordance with JIS-K-6854-2 (1999) "Adhesives - Peel Adhesion Strength Test Method - Part 2: 180-degree Peel". Specifically, the evaluation was performed using a load cell of 50N in a Shimadzu Corporation tabletop precision testing machine AGS-X series. The measurement conditions were a stroke length of 50mm and a speed of 50mm / min, and the exposed copper foil side was grasped and a 180-degree peel was performed. The measurement results were calculated as the average peel strength within the stroke length range of 10 to 50mm. Based on the obtained measurement results, the adhesion strength between the base film and the conductor layer was evaluated on a five-point scale from A to E below. Of these five levels, A or B is considered to be good. The evaluation results are shown in Table 1.

[0153] A: Peel strength is 9N / cm or more. B: Peel strength is 7N / cm or more and less than 9N / cm C: Peel strength is 5N / cm or more and less than 7N / cm D: Peel strength is 3N / cm or more and less than 5N / cm E: Peel strength is less than 3N / cm

[0154] [Overall evaluation of number of voids and adhesion]

[0155] The number of voids and adhesion were evaluated on a four-point scale from A to D. A was the best, followed by B, C, and D in decreasing order.

[0156] The first and second prototypes had a low number of voids N per standard unit area D, which was good (rating: A), and the adhesion was also very good (rating: A).The overall rating of the number of voids and adhesion was also determined to be an A (see Table 1).

[0157] The third prototype has a small number of voids N per unit area D, making it favorable (evaluation: B ), and the adhesion was also good (rating: A). The overall rating of the number of voids and adhesion was also determined to be a rating of B (see Table 1).

[0158] The fourth prototype had low adhesion (rating: C ), and a large number of voids (rating: C), the overall rating was determined to be C (see Table 1).

[0159] The fifth prototype had low adhesion (Evaluation: D ), and the number of voids was very large (rating: D), so the overall rating was determined to be a rating of D (see Table 1).

[0160] The sixth prototype had a small number of voids N per reference unit area D, which was very good (rating: A), but the adhesion was very low (rating: E), so the overall rating was determined to be a D (see Table 1).

[0161] It should be noted that the embodiments and examples disclosed herein are illustrative in all respects and should not be considered as limiting. The scope of the present invention is indicated by the scope of the claims, not by the meaning described above, and is intended to include the meaning equivalent to the scope of the claims and all modifications within the scope. [Explanation of symbols]

[0162] 1 Base film 1A Area where no voids exist 1B Areas where voids exist 2 Conductor layer 3 Dispersion part 4 First conductor layer (sintered layer of metal particles, metal sintered layer) 5 Second conductor layer (electroless plating layer) 6 Third conductor layer 7 4th conductor layer 8 Through Hole 10. Void 11 Interface 100 Electroless plating equipment 101 Electroless plating Treatment tank 102 Laura (1st pole) 103 Opposite (2nd Pole) 105 Power supply 200 Printed circuit boards 300 Printed Circuits 110: Base film on which a first conductor layer is formed S11 Conductive ink preparation S12 Conductive ink coating Firing S13 Pretreatment S14 Electroless plating S14-1 Electric Solution assist S14A Electroless plating Solution No assist) S15 Heat Treatment S16 Electroplating 2A, 2B, 2C Conductive patterns

Claims

1. A base film mainly composed of polyimide; A conductor layer formed on at least one surface of the base film; Equipped with The conductor layer has a metal sintered layer formed on the base film and an electroless plating layer formed on the metal sintered layer, In the base film, the number of voids having a maximum width of 5 μm or more in a plan view is 0.25 mm ２ 10 or less per unit area of ​​the reference The height of the surface of the base film at a portion where the voids are present relative to the surface of the base film at a portion where the voids are not present is 1.5 μm or more. Substrate for printed circuits.

2. The conductor layer further includes an electroplating layer or a metal foil layer on the electroless plating layer. The substrate for printed circuits according to claim 1 .

3. The number of the voids is 5 or less per standard unit area. The substrate for printed circuits according to claim 1 or 2.

4. The base film does not contain palladium. The substrate for printed circuits according to any one of claims 1 to 3.

5. A base film mainly composed of polyimide; A conductive pattern is formed on at least one surface of the base film, the conductive pattern has a minimum conductor width and a minimum conductor spacing; Either one or both of the minimum conductor width and the minimum conductor spacing is 20 μm or less; The conductive pattern includes a metal sintered layer formed on the base film and an electroless plating layer formed on the metal sintered layer, In the base film, the number of voids having a maximum width of 5 μm or more in a plan view is 0.25 mm ２ 10 or less per unit area of ​​the reference The height of the surface of the base film at a portion where the voids are present relative to the surface of the base film at a portion where the voids are not present is 1.5 μm or more. Printed circuit.

6. Either or both of the minimum conductor width and the minimum conductor spacing is 15 μm or less.

6. The printed circuit of claim 5.

7. The base film has a through hole penetrating in the thickness direction.

7. A printed circuit according to claim 5 or claim 6.

8. A step of forming a first conductor layer, which is a metal sintered layer, on one side of a base film mainly composed of polyimide; forming a second conductor layer on the first conductor layer by electroless plating using a catalyst; Equipped with The step of forming the second conductive layer includes depositing the conductor serving as the catalyst from the electroless plating solution on the first conductive layer by electrolytic assistance of applying a potential to the first conductive layer in the electroless plating solution. A method for manufacturing a substrate for printed circuits.

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