A / D Converter

Abstract

The problem of the present disclosure is to provide an A / D converter in which conversion errors are reduced and which is capable of subjecting a plurality of analog input voltages to A / D conversion by time division. A comparator (7) compares a comparison reference voltage (V5) to the differential voltage (V4) between a conversion target voltage (V3), which is constituted by analog input voltages (V1, V2), and a comparison voltage produced by a D / A conversion unit (5). A switching circuit (62) connects capacitance elements (C11, C12), which correspond to the analog input voltages (V1, V2) selected as the conversion target voltage (V3), to an output terminal of an integrator (61). The integrator (61) integrates the differential voltage (V4) in a state in which an A / D conversion unit (3) has carried out a conversion operation on the least significant bit. A comparison reference generation unit (6) uses, as the comparison reference voltage (V5), a charging voltage for the capacitance elements (C11, C12) corresponding to the analog input voltages (V1, V2) selected as the conversion target voltage (V3).

Description

[Technical field]

[0001] The present disclosure relates to an AD converter, and more particularly to a successive approximation type analog-to-digital (AD) converter. [Background technology]

[0002] Patent Document 1 discloses a noise-shaping successive approximation type AD converter. The noise-shaping successive approximation type AD converter has a configuration in which an integrating circuit is added to a normal successive approximation type AD converter. In the noise-shaping successive approximation type AD converter, the residual voltage of a DA (Digital-to-Analog) converter after successive approximation operation is performed up to the least significant bit is integrated and fed back to the next sampling, thereby obtaining a noise-shaping characteristic that moves noise in the low frequency band to the high frequency band. In Patent Document 1, the noise moved to the high frequency band is attenuated by a low-pass filter, thereby realizing high resolution of the AD converter.

[0003] In a noise-shaping successive approximation type AD converter, the integration result of the residual voltage is fed back to the next sampling. Therefore, the noise-shaping successive approximation type AD converter of Patent Document 1 cannot be used to perform AD conversion of multiple analog input voltages in a time-division manner. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] JP 2017-147712 A Summary of the Invention

[0005] An object of the present disclosure is to provide an AD converter capable of AD converting a plurality of analog input voltages in a time-division manner and with reduced conversion errors.

[0006] An AD converter according to an embodiment of the present disclosure includes an input switching circuit and a successive approximation type AD conversion unit. A plurality of analog input voltages are input to the input switching circuit, and one analog input voltage selected from the plurality of analog input voltages is output as a conversion target voltage. The AD conversion unit performs AD conversion to convert the conversion target voltage input from the input switching circuit into a multi-bit digital signal. When the conversion operation of the conversion target voltage by the AD conversion unit is completed, the input switching circuit switches the analog input voltage selected as the conversion target voltage from the plurality of analog input voltages. The AD conversion unit performs a conversion operation for each target bit from the most significant bit to the least significant bit. The AD conversion unit includes a control unit, a DA conversion unit, a comparison reference generation unit, and a comparator. The DA conversion unit generates an analog comparison voltage corresponding to the target bit in response to a control signal from the control unit. The comparison reference generation unit generates a comparison reference voltage corresponding to the analog input voltage selected as the conversion target voltage. The comparator determines the value of the target bit by comparing a difference voltage between the conversion target voltage and the comparison voltage with the comparison reference voltage. The control unit determines the control signal at the next bit of the target bit based on the comparison result of the comparator at the target bit. The comparison reference generation unit has an integrator, a plurality of capacitive elements, and a switching circuit. The integrator integrates the difference voltage in a state where the AD conversion unit has performed the conversion operation of the least significant bit. The plurality of capacitive elements are provided corresponding to the plurality of analog input voltages, respectively. The switching circuit connects a capacitive element corresponding to the analog input voltage selected as the conversion target voltage among the plurality of capacitive elements to an output terminal of the integrator. A capacitive element connected to the output terminal of the integrator via the switching circuit among the plurality of capacitive elements is charged with the output voltage of the integrator. The comparison reference generation unit sets the charging voltage of a capacitive element corresponding to the analog input voltage selected as the conversion target voltage among the plurality of capacitive elements as the comparison reference voltage. [Brief description of the drawings]

[0007] [Figure 1]FIG. 1 is a schematic circuit diagram of an AD converter according to an embodiment of the present disclosure. [Diagram 2] FIG. 2 is a schematic circuit diagram showing an example of an integrator included in the AD converter. [Diagram 3] FIG. 3 is a time chart illustrating the operation of the AD converter. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0008] (Embodiment) (1) Overview 1, an AD converter 1 of this embodiment includes an input switching circuit 2 and a successive approximation type AD conversion unit 3. Note that the AD conversion unit 3 of this embodiment is a noise-shaping type successive approximation type AD conversion unit in which an integrating circuit is added to the successive approximation type AD conversion unit.

[0009] The input switching circuit 2 receives a plurality of analog input voltages (for example, two analog input voltages V1 and V2 in FIG. 1), and outputs one analog input voltage selected from the plurality of analog input voltages as a conversion target voltage V3. The AD conversion unit 3 performs AD conversion to convert the conversion target voltage V3 input from the input switching circuit 2 into a multi-bit digital signal (D1 or D2). When the conversion operation of the conversion target voltage V3 by the AD conversion unit 3 is completed, the input switching circuit 2 switches the analog input voltage selected as the conversion target voltage V3 from the plurality of analog input voltages.

[0010] The AD conversion unit 3 performs a conversion operation for each target bit from the most significant bit to the least significant bit. The AD conversion unit 3 has a control unit 4, a DA conversion unit 5, a comparison reference generation unit 6, and a comparator .

[0011] The DA conversion unit 5 generates an analog comparison voltage for the target bit in response to the control signal S1 from the control unit 4. In other words, the DA conversion unit 5 generates an analog comparison voltage corresponding to the target bit in response to the control signal S1 from the control unit 4. The analog comparison voltage corresponding to the target bit is, for example, an analog voltage corresponding to a digital signal in which the most significant bit to the bit immediately above the target bit have a value determined by the comparator 7, the target bit is "1," and the bit next to the target bit to the least significant bit are "0."

[0012] The comparison reference generating section 6 generates a comparison reference voltage V5 corresponding to the analog input voltage selected as the conversion target voltage V3.

[0013] The comparator 7 determines the value of the target bit by comparing a difference voltage V4 between the conversion target voltage V3 and the comparison voltage with a comparison reference voltage V5.

[0014] The control unit 4 determines the control signal S1 for the bit next to the target bit based on the comparison result of the comparator 7 for the target bit. That is, the control unit 4 determines the comparison voltage to be generated by the DA conversion unit 5 for the bit next to the target bit based on the comparison result of the comparator 7 for the target bit, and determines the control signal S1 for generating the determined comparison voltage.

[0015] The comparison reference generating section 6 includes an integrator 61, a plurality of capacitive elements C11 and C12 (for example, two in the example of FIG. 1), and a switching circuit 62.

[0016] The integrator 61 integrates the difference voltage V4 in a state where the AD conversion unit 3 has performed the conversion operation of the least significant bit. The multiple capacitive elements C11 and C12 are provided corresponding to the multiple analog input voltages V1 and V2, respectively. The switching circuit 62 connects the capacitive element C11 or C12 corresponding to the analog input voltage V1 or V2 selected as the conversion target voltage V3 among the multiple capacitive elements C11 and C12 to the output terminal of the integrator 61. The capacitive element C11 or C12 connected to the output terminal of the integrator 61 via the switching circuit 62 among the multiple capacitive elements C11 and C12 is charged with the output voltage of the integrator 61. The comparison reference generating unit 6 sets the charging voltage of the capacitive element C11 or C12 corresponding to the analog input voltage V1 or V2 selected as the conversion target voltage V3 among the multiple capacitive elements C11 and C12 as the comparison reference voltage V5.

[0017] In the AD converter 1 of this embodiment, when the conversion operation of the conversion target voltage V3 by the AD conversion unit 3 is completed, the input switching circuit 2 switches the analog input voltage selected as the conversion target voltage V3 from the multiple analog input voltages V1 and V2. Therefore, the AD converter 1 can perform AD conversion of the multiple analog input voltages V1 and V2 in a time-division manner. In addition, the AD converter 1 of this embodiment includes multiple capacitive elements C11 and C12 corresponding to the multiple analog input voltages V1 and V2, respectively. Each of the multiple capacitive elements C11 and C12 is charged with the integration result of the integrator 61 when the corresponding analog input voltages V1 and V2 are the conversion target voltage V3. Since the charging voltages V51 and V52 of the capacitive elements C11 and C12 are used as the comparison reference voltage V5 when the corresponding analog input voltages V1 and V2 are next AD converted, the conversion error can be reduced by using the value obtained by integrating the conversion error in the AD conversion as the comparison reference voltage V5 in the next AD conversion. Therefore, it is possible to provide an AD converter 1 capable of AD-converting a plurality of analog input voltages in a time-division manner and reducing conversion errors.

[0018] In the following embodiment, a case will be described in which two analog input voltages V1, V2 are input to the input switching circuit 2, and the AD converter 1 performs AD conversion on the two analog input voltages V1, V2 alternately in a time-division manner. Note that the number of analog input voltages input to the input switching circuit 2 is not limited to two, and three or more analog input voltages may be input to the input switching circuit 2, and the AD converter 1 may perform AD conversion on the three or more analog input voltages in a time-division manner.

[0019] (2)Details (2.1) Structure The configuration of the AD converter 1 according to this embodiment will be described in detail below with reference to Fig. 1 and Fig. 2. Note that Fig. 1 and Fig. 2 are schematic circuit diagrams of the AD converter 1, and some of the circuit configuration is omitted.

[0020] The AD converter 1 of this embodiment is a noise-shaping successive approximation type AD converter. As described above, the AD converter 1 includes the input switching circuit 2 and the AD conversion unit 3. In addition to the input switching circuit 2 and the AD conversion unit 3, the AD converter 1 of this embodiment further includes input terminals TA1 and TA2, a serial-parallel conversion unit (denoted as SP in FIG. 1) 8, and a filter circuit 9. The "terminal" referred to here may be a component (terminal) for connecting an electric wire or the like, but may also be, for example, a lead of an electronic component or a part of a conductor formed as wiring on a circuit board.

[0021] An analog input voltage V1 is input to the input terminal TA1, and an analog input voltage V2 is input to the input terminal TA2. The analog input voltages V1 and V2 are output signals from various sensors such as an acceleration sensor, an angular velocity sensor, or a gyro sensor.

[0022] The output terminal TA3 of the input switching circuit 2 is connected to one input terminal of the comparator 7. The input switching circuit 2 includes a switch 21 connected between the input terminal TA1 and the output terminal TA3, and a switch 22 connected between the input terminal TA2 and the output terminal TA3. The switches 21 and 22 are semiconductor switches such as CMOS transistors, and are switched on / off by control signals φA and φB input from the control unit 4. When the switch 21 is on and the switch 22 is off, the input switching circuit 2 outputs the analog input voltage V1 to the AD conversion unit 3 as the conversion target voltage V3. When the switch 21 is off and the switch 22 is on, the input switching circuit 2 outputs the analog input voltage V2 to the AD conversion unit 3 as the conversion target voltage V3.

[0023] The AD conversion section 3 includes a control section 4, a DA conversion section 5, a comparison reference generation section 6, and a comparator .

[0024] The control unit 4 is realized, for example, by wired logic. The control unit 4 controls the operations of the input switching circuit 2, the DA conversion unit 5, the comparison reference generation unit 6, and the filter circuit 9, thereby alternately performing AD conversion of the analog input voltages V1 and V2 in a time-division manner in the AD converter 1. The control unit 4 may be realized by a computer system having one or more processors and memories.

[0025] The DA conversion section 5 is, for example, a 12-bit DA conversion section, and is configured by combining a lower-order DA conversion section 51 for the lower 4 bits and an upper-order DA conversion section 52 for the upper 8 bits.

[0026] The DA conversion unit 5 is a capacitive DA conversion unit including a plurality of capacitive elements C1, C2 and a voltage switching circuit 55. One end of each of the capacitive elements C1, C2 is connected to the output terminal TA3 of the input switching circuit 2. The voltage switching circuit 55 selectively connects the other end of each of the capacitive elements C1, C2 to either the first voltage VH or the second voltage VL in response to a control signal S1 from the control unit 4. The DA conversion unit 5 is a capacitive DA conversion unit including a plurality of capacitive elements C1, C2 and the voltage switching circuit 55, and therefore has the advantage that the DA conversion unit 5 can be realized by a simple circuit. The first voltage VH and the second voltage VL are DC voltages with constant voltage values, and the first voltage VH is set to a voltage higher than the second voltage VL.

[0027] The lower-order DA conversion unit 51 includes a plurality of capacitive elements C1 and a plurality of switches Q1 provided corresponding to the plurality of capacitive elements C1, respectively. One end of each of the plurality of capacitive elements C1 is connected to an output terminal TA3 of the input switching circuit 2. The plurality of switches Q1 are realized using semiconductor switches such as CMOS transistors. The plurality of switches Q1 selectively connect each of the plurality of capacitive elements C1 to either a first voltage VH or a second voltage VL in response to a control signal S1 from the control unit 4.

[0028] The upper DA conversion unit 52 also includes a plurality of capacitive elements C2 and DEMs (Dynamic Element Matching) 53 and 54. One end of each of the capacitive elements C2 is connected to an output terminal TA3 of the input switching circuit 2. The DEMs 53 and 54 selectively connect each of the plurality of capacitive elements C2 to either a first voltage VH or a second voltage VL in response to a control signal S1 from the control unit 4.

[0029] In this embodiment, a voltage switching circuit 55 is configured with a plurality of switches Q1 and DEMs 53 and 54. The plurality of switches Q1 and DEMs 53 and 54 connect each of the plurality of capacitive elements C1 and C2 to either the first voltage VH or the second voltage VL in response to a control signal S1 input from the control unit 4, whereby the DA conversion unit 5 generates a comparison voltage of a desired voltage value. Here, the output terminal of the DA conversion unit 5 is connected to one input terminal of the comparator 7 together with the output terminal TA3 of the input switching circuit 2. Therefore, a difference voltage V4 between the conversion target voltage V3 output from the input switching circuit 2 and the comparison voltage generated by the DA conversion unit 5 is input to one input terminal of the comparator 7.

[0030] The comparison reference generating section 6 includes an integrator 61, a plurality of capacitive elements C11 and C12 (the same number as the analog input voltages V1 and V2, for example, two in this embodiment), and a switching circuit 62.

[0031] 2 shows an example of a specific circuit of the integrator 61. The integrator 61 of this embodiment includes multiple stages of integration circuits 61A, 61B, and 61C that sequentially perform integration operations. Each of the multiple stages of integration circuits 61A to 61C performs integration operations using operational amplifiers OP1 to OP3.

[0032] The integrating circuit 61A is a first-stage integrating circuit. The integrating circuit 61A includes an operational amplifier OP1, a capacitive element C21, and a switch Q21. The inverting input terminal of the operational amplifier OP1 is connected to an input terminal TA4 of the integrator 61 via the switch Q21. The capacitive element C21 is connected between the inverting input terminal and the output terminal of the operational amplifier OP1. The non-inverting input terminal of the operational amplifier OP1 is connected to a reference voltage of the AD converter 1. Here, the integrating circuit 61A is configured by the operational amplifier OP1, the capacitive element of the DA conversion unit 5 connected to the input terminal TA4, and the capacitive element C21. The output terminal of the operational amplifier OP1 (i.e., the output terminal of the integrating circuit 61A) is connected to the input terminal of the integrating circuit 61B.

[0033] The integrating circuit 61B is a second-stage integrating circuit, and includes an operational amplifier OP2, capacitive elements C22 to C24, and switches Q22 to Q25. The inverting input terminal of the operational amplifier OP2 is connected to the input terminal TA4 of the integrator 61 via the switches Q22 and Q23. The inverting input terminal of the operational amplifier OP2 is connected to the output terminal of the integrating circuit 61A via the switches Q24 and Q25. The non-inverting input terminal of the operational amplifier OP2 is connected to the reference potential of the AD converter 1. Here, the connection point of the switches Q22 and Q23 is connected to the reference voltage of the AD converter 1 via the capacitive element C22. The connection point of the switches Q24 and Q25 is connected to the reference voltage of the AD converter 1 via the capacitive element C23. The capacitive element C24 is connected between the inverting input terminal and the output terminal of the operational amplifier OP2. The output terminal of the operational amplifier OP2 (i.e., the output terminal of the integrating circuit 61B) is connected to the input terminal of the integrating circuit 61C.

[0034] Here, a feedforward path FF1 is formed between the input terminal TA4 of the integrator 61 and the input terminal of the operational amplifier OP2 included in the second-stage integration circuit 61B. The difference voltage V4 input from the input terminal TA4 of the integrator 61 is sampled by the capacitance element C22, and the sampled difference voltage V4 is input to the operational amplifier OP2 of the second-stage integration circuit 61B.

[0035] The integrating circuit 61C is a third-stage integrating circuit, and includes an operational amplifier OP3, capacitive elements C25 to C27, and switches Q26 to Q29. The inverting input terminal of the operational amplifier OP3 is connected to the input terminal TA4 of the integrator 61 via the switches Q26 and Q27. The inverting input terminal of the operational amplifier OP3 is connected to the output terminal of the integrating circuit 61B (i.e., the output terminal of the operational amplifier OP2) via the switches Q28 and Q29. The non-inverting input terminal of the operational amplifier OP3 is connected to the reference potential of the AD converter 1. Here, the connection point of the switches Q26 and Q27 is connected to the reference voltage of the AD converter 1 via the capacitive element C25. The connection point of the switches Q28 and Q29 is connected to the reference voltage of the AD converter 1 via the capacitive element C26. The capacitive element C27 is connected between the inverting input terminal and the output terminal of the operational amplifier OP3.

[0036] Here, a feedforward path FF2 is formed between the input terminal TA4 of the integrator 61 and the input terminal of the operational amplifier OP3 included in the third-stage integration circuit 61C. The difference voltage V4 input from the input terminal TA4 of the integrator 61 is sampled by the capacitance element C25, and the sampled difference voltage V4 is input to the operational amplifier OP3 of the third-stage integration circuit 61C.

[0037] The output terminal of the integrating circuit 61C (i.e., the output terminal of the operational amplifier OP3) is electrically connected to the output terminal TA5 of the integrator 61 via the switch Q30. That is, the output terminal of the integrating circuit 61C is connected to the switching circuit 62.

[0038] The multiple switches Q21-Q30 are realized by semiconductor switches such as CMOS transistors. The switches Q22 and Q26 are switched on or off in response to a control signal φ0 input from the control unit 4. The switches Q21 and Q24 are switched on or off in response to a control signal φ1 input from the control unit 4. The switches Q23, Q25, and Q28 are switched on or off in response to a control signal φ2 input from the control unit 4. The switches Q27, Q29, and Q30 are switched on or off in response to a control signal φ3 input from the control unit 4.

[0039] 2, the integrator 61 has three integrating circuits 61A, 61B, and 61C connected in series, and the three stages of the integrating circuits 61A to 61C perform integration operations in sequence, thereby realizing a noise shaping characteristic that moves noise in the low frequency band to the high frequency band. In the integrator 61 of this embodiment, the three integrating circuits 61A, 61B, and 61C are connected in series, but this is only one example, and the number of stages of the integrating circuits can be changed as appropriate as long as it is one or more. In addition, when the number of stages of the integrating circuits is two or more, it is not essential to form a feedforward path between the input terminal TA4 of the integrator 61 and one or more integrating circuits connected to the second stage or later, and the feedforward path can be omitted as appropriate.

[0040] A plurality of (two in this embodiment) capacitive elements C11, C12 are provided corresponding to a plurality of (two in this embodiment) analog input voltages V1, V2, respectively. One end of the plurality of capacitive elements C11, C12 is connected to a reference voltage of the AD converter 1. The switching circuit 62 includes a plurality of (two in this embodiment) switches Q11, Q12 respectively connected between the other ends of the plurality of capacitive elements C11, C12 and the output terminal of the integrator 61. That is, the other end of the capacitive element C11 is connected to the output terminal TA5 of the integrator 61 and the input terminal of the comparator 7 via the switch Q11. The other end of the capacitive element C12 is connected to the output terminal TA5 of the integrator 61 and the input terminal of the comparator 7 via the switch Q12. The switches Q11, Q12 are realized by semiconductor switches such as CMOS transistors. The switches Q11, Q12 are switched on / off according to a control signal input from the control unit 4.

[0041] The comparator 7 compares, for each target bit, the voltage input from the DA conversion unit 5, i.e., the difference voltage V4 between the conversion target voltage V3 and the output voltage of the DA conversion unit 5, with a comparison reference voltage V5 input via the switching circuit 62. The comparator 7 determines, for each target bit, the value (0 or 1) of the target bit by comparing the difference voltage V4 between the conversion target voltage V3 and the output voltage of the DA conversion unit 5 with the comparison reference voltage V5.

[0042] When the analog input voltage V1 is the conversion target voltage V3, the control unit 4 turns on the switch Q11 and turns off the switch Q12 to input the charging voltage V51 of the capacitive element C11 as the comparison reference voltage V5 to the other input terminal of the comparator 7. As a result, when AD conversion of the analog input voltage V1 is performed, the integration result obtained by integrating the difference voltage V4 remaining at the time of conversion of the least significant bit in the previous AD conversion by the integrator 61 is used as the comparison reference voltage V5. This makes it possible to realize a noise shaping characteristic that moves noise in the low frequency region to the high frequency region.

[0043] Furthermore, when the analog input voltage V2 is the conversion target voltage V3, the control unit 4 turns off the switch Q11 and turns on the switch Q12 to input the charging voltage V52 of the capacitive element C12 as the comparison reference voltage V5 to the other input terminal of the comparator 7. As a result, when AD conversion of the analog input voltage V2 is performed, the integration result obtained by integrating the difference voltage V4 remaining at the time of conversion of the least significant bit in the previous AD conversion by the integrator 61 is used as the comparison reference voltage V5. This makes it possible to realize a noise shaping characteristic that moves noise in the low frequency region to the high frequency region.

[0044] In addition, the control unit 4 generates a control signal S1 to cause the DA conversion unit 5 to generate a comparison voltage for the next bit of the target bit based on the comparison result of the target bit by the comparator 7, and outputs this control signal S1 to the DA conversion unit 5 when performing a comparison operation of the next bit.

[0045] While performing AD conversion of the conversion target voltage V3, the serial-parallel conversion unit 8 converts the serial digital signal D11 input from the AD conversion unit 3 into a parallel digital signal D12 and outputs the converted digital signal D12 to the filter circuit 9.

[0046] The filter circuit 9 attenuates high frequency components of the digital signal (digital signal D12 after being converted into a parallel signal in this embodiment) output from the AD conversion unit 3. The filter circuit 9 includes a plurality of filters (referred to as LPF in FIG. 1) 91, 92 and a filter switching circuit 93. The plurality of filters 91, 92 correspond to a plurality of analog input voltages V1, V2, respectively. The filter switching circuit 93 inputs the digital signal D12 to a filter of the plurality of filters 91, 92 that corresponds to an analog input voltage selected as a conversion target voltage V3.

[0047] The filters 91 and 92 are digital filters having low-pass characteristics and attenuate high-frequency components included in the digital signal D12. The filters 91 and 92 are digital filters realized by, for example, wired logic, but may be realized by a processor. The filter switching circuit 93 connects the output terminal of the serial-parallel conversion unit 8 to either the filter 91 or 92 in response to a control signal S3 input from the control unit 4. When the analog input voltage V1 is the conversion target voltage V3, the control unit 4 controls the filter switching circuit 93 so that the digital signal D12 is input to the filter 91 corresponding to the analog input voltage V1. When the analog input voltage V2 is the conversion target voltage V3, the control unit 4 controls the filter switching circuit 93 so that the digital signal D12 is input to the filter 92 corresponding to the analog input voltage V2.

[0048] As a result, when an analog input voltage V1 is input to the AD conversion unit 3, the digital signal D11 output from the AD conversion unit 3 is converted by the serial-parallel conversion unit 8 into a parallel digital signal D12, which is then input to the filter 91. Then, a digital signal D1 with high-frequency components contained in the digital signal D12 attenuated by the filter 91 is output from the AD converter 1.

[0049] Furthermore, when an analog input voltage V2 is input to the AD conversion unit 3, the digital signal D11 output from the AD conversion unit 3 is converted by the serial-parallel conversion unit 8 into a parallel digital signal D12, which is then input to the filter 92. Then, a digital signal D2 in which high-frequency components contained in the digital signal D12 have been attenuated by the filter 92 is output from the AD converter 1.

[0050] (2.2) Operation Description The operation of the AD converter 1 of this embodiment will be described with reference to FIG.

[0051] Fig. 3 is an example of a timing chart illustrating the operation of the AD converter 1 shown in Fig. 1 and Fig. 2. Fig. 3 is a time chart illustrating a part of the operation of the AD converter 1. The operation of the AD converter 1 will be described below with reference to Figs. 1 to 3.

[0052] The control signal φA is a control signal for the switch 21, and the control signal φB is a control signal for the switch 22. Moreover, the control signals φ0, φ1, φ2, and φ3 are control signals for the switches Q21 to Q30 included in the integrator 61. The control signals φA, φB, and φ0 to φ3 are output from the control unit 4.

[0053] The control unit 4 performs AD conversion of the two analog input voltages V1 and V2 in a time-division manner by alternately setting a first period TA in which AD conversion of the analog input voltage V1 is performed and a second period TB in which AD conversion of the analog input voltage V2 is performed.

[0054] First, the operation of the AD converter 1 in the first period TA will be described. In a reset period T1 of the first period TA, the control unit 4 controls the switch Q1 to perform a reset operation of the capacitive elements C1 and C2 included in the DA conversion unit 5. Also, in the first period TA, the control unit 4 turns on the switch Q11 and turns off the switch Q12 to input the charging voltage V51 of the capacitive element C11 to the comparator 7 as the comparison reference voltage V5. Also, in the first period TA, the control unit 4 switches the filter switching circuit 93 so that the digital signal D12 output from the serial-parallel conversion unit 8 is input to the filter 91.

[0055] When the reset operation is completed, in a sampling period T2, the control unit 4 turns on the switch 21 and turns off the switch 22, and the analog input voltage V1 input to the input terminal TA1 is charged as the conversion target voltage V3 to the DA conversion unit 5. The control unit 4 also turns on the switch Q11 and turns off the switch Q12, and inputs the charging voltage V51 of the capacitive element C11 corresponding to the analog input voltage V1 to the comparator 7 as the comparison reference voltage V5. In the initial state when the AD converter 1 starts AD conversion, the value of the charging voltage V51 is close to the reference voltage of the AD converter 1.

[0056] During the subsequent AD conversion period T3, the control unit 4 causes the AD conversion unit 3 to perform AD conversion while keeping the switches 21 and 22 off.

[0057] The control unit 4 first outputs a control signal S1 to the DA conversion unit 5 to generate a comparison voltage ((VH-VL) / 2) corresponding to a 12-bit digital value "100000000000" in which only the most significant bit is, for example, "1." At this time, the comparator 7 finds the value of the most significant bit, which is the target bit, by comparing the difference voltage V4 between the conversion target voltage V3 (analog input voltage V1) and the comparison voltage with a comparison reference voltage V5.

[0058] Here, if the difference voltage V4 is equal to or greater than the comparison reference voltage V5, the comparator 7 sets the value of the most significant bit (target bit) to, for example, "1," and if the difference voltage V4 is less than the comparison reference voltage V5, the comparator 7 sets the value of the most significant bit (target bit) to, for example, "0." When determining the value of the bit next to the target bit, the control unit 4 generates a control signal S1 that determines the value of the comparison voltage to be generated by the DA conversion unit 5 based on the comparison result of the comparator 7, and outputs this control signal S1 to the DA conversion unit 5.

[0059] For example, if the value of the most significant bit is "1", the control unit 4 outputs a control signal S1 to the DA conversion unit 5 to generate a comparison voltage (3(VH-VL) / 4) corresponding to the digital value "110000000000" when determining the value of the bit next to the most significant bit. At this time, the comparator 7 determines the value of the target bit by comparing the difference voltage V4 between the conversion target voltage V3 (analog input voltage V1) and the comparison voltage with the comparison reference voltage V5. If the difference voltage V4 is equal to or greater than the comparison reference voltage V5, the comparator 7 sets the value of the target bit (most significant - 1) bit to "1", and if the difference voltage V4 is less than the comparison reference voltage V5, the comparator 7 sets the value of the target bit (most significant - 1) bit to "0".

[0060] On the other hand, if the value of the most significant bit is "0", the control unit 4 outputs a control signal S1 to the DA conversion unit 5 to generate a comparison voltage ((VH-VL) / 4) corresponding to the digital value "010000000000" when determining the value of the bit next to the most significant bit. At this time, the comparator 7 determines the value of the target bit by comparing the difference voltage V4 between the conversion target voltage V3 (analog input voltage V1) and the comparison voltage with the comparison reference voltage V5. If the difference voltage V4 is equal to or greater than the comparison reference voltage V5, the comparator 7 sets the value of the target bit (most significant - 1) bit to "1", and if the difference voltage V4 is less than the comparison reference voltage V5, the comparator 7 sets the value of the target bit (most significant - 1) bit to "0".

[0061] The AD conversion unit 3 repeats such an operation from the most significant bit to the least significant bit to determine the value of each bit. The comparison result of each bit is converted by the serial-parallel conversion unit 8 into a parallel digital signal D12 of multiple bits and output to the filter circuit 9. Here, the digital signal D12 is input to a filter 91 by a filter switching circuit 93, and the filter 91 outputs a digital signal D1 with noise in the high frequency band reduced.

[0062] Furthermore, when the comparison operation of the target bits by the AD conversion unit 3 is completed up to the least significant bit, the control unit 4 starts the operation in the integration period T4. In the integration period T4, the control unit 4 causes the integrator 61 to perform an integration operation, and performs an operation of generating a comparison reference voltage V5 to be used the next time AD conversion of the analog input voltage V1 is performed.

[0063] In the integration period T4, the control unit 4 first outputs a control signal φ0 to the integrator 61 to turn off the switches Q22 and Q26. Here, the switches Q22 and Q26 are on in the AD conversion period T3. Therefore, at the timing when the integration period T4 starts, the capacitance elements C22 and C24 are charged to the difference voltage V4 between the conversion target voltage V3 and the comparison voltage at the time when the successive approximation process up to the least significant bit is completed.

[0064] In the integration period T4, the control unit 4 outputs a control signal φ1 that turns on the switches Q21 and Q24 at the same time as turning off the switches Q22 and Q26, thereby turning on the switches Q21 and Q24. As a result, the difference voltage V4 between the conversion target voltage V3 and the comparison voltage at the time when the successive approximation process up to the least significant bit is completed is integrated by the integration circuit 61A, and the integral value is stored in the capacitance element C23.

[0065] Next, the control unit 4 turns off the switches Q21 and Q24, samples and holds the integral value of the integrating circuit 61A in the capacitive element C23, and then outputs a control signal φ2 that turns on the switches Q23, Q25, and Q28 to turn on the switches Q23, Q25, and Q28. As a result, the integral value sampled and held in the capacitive element C23 is integrated in the second-stage integrating circuit 61B. In addition, the difference voltage at the least significant bit sampled and held in the capacitive element C22 is input to the integrating circuit 61B via the feedforward path FF1 and integrated in the integrating circuit 61B. At this time, the integral value of the integrating circuit 61B is stored in the capacitive element C25.

[0066] Next, the control unit 4 turns off the switches Q23, Q25, and Q28, samples and holds the integral value of the integrating circuit 61B in the capacitive element C26, and then outputs a control signal φ3 to turn on the switches Q27, Q29, and Q30 to turn on the switches Q27, Q29, and Q30. As a result, the integral value sampled and held in the capacitive element C26 is integrated in the third-stage integrating circuit 61C. In addition, the difference voltage at the least significant bit sampled and held in the capacitive element C25 is input to the integrating circuit 61C via the feedforward path FF2 and integrated in the integrating circuit 61C. At this time, the integral value of the integrating circuit 61C is stored in the capacitive element C11 via the switching circuit 62.

[0067] Then, the control unit 4 turns off the switches Q27, Q29, and Q30, and samples and holds the integral value of the third-stage integration circuit 61C in the capacitance element C11. As a result, third-order integration is realized in the comparison reference generation unit 6, and the integral value of the third-order integration sampled and held in the capacitance element C11 is fed back to the comparator 7 as the comparison reference voltage V5 for the next AD conversion of the analog input voltage V1. In other words, the integration result of the integrator 61 after AD conversion of the analog input voltage V1 in the previous first period TA is set as the comparison reference voltage V5 for the next AD conversion of the analog input voltage V1 in the first period TA. This realizes a successive approximation type AD converter 1 having third-order noise shaping characteristics.

[0068] The operation of the AD converter 1 in the second period TB is different from that in the first period TA in that AD conversion is performed with the analog input voltage V2 as the conversion target voltage V3. In the sampling period T2 of the second period TB2, the switch 21 is turned off and the switch 22 is turned on to cause the DA conversion unit 5 to sample the analog input voltage V2. In addition, in the integration period T4, the switch Q11 is turned off and the switch Q12 is turned on to cause the capacitance element C12 to integrate the integral value of the integrator 61, and the integral value sampled and held by the capacitance element C12 is fed back to the comparator 7 as the comparison reference voltage V5 at the next AD conversion of the analog input voltage V2. In addition, the digital signal D12 output from the serial-parallel conversion unit 8 is input to the filter 92 via the filter switching circuit 93. When the digital signal D12 is input, the filter 92 outputs the digital signal D2 with noise in the high frequency band reduced.

[0069] In this embodiment, two filters 91 and 92 corresponding to two analog input voltages V1 and V2, respectively, are provided. Then, a filter switching circuit 93 inputs a digital signal D12 to the filter 91 or 92 corresponding to the analog input voltage V1 or V2 selected as the conversion target voltage V3 to reduce noise in the high frequency band. In this way, a plurality of filters 91 and 92 corresponding to a plurality of analog input voltages V1 and V2 are prepared. Therefore, there is an advantage that a plurality of filters 91 and 92 corresponding to a plurality of analog input voltages V1 and V2, respectively, can be designed according to the frequencies of the analog input voltages V1 and V2. As a result, even if the frequencies of the analog input voltages V1 and V2 are different, it is possible to output digital signals D1 and D2 obtained by converting the analog input voltages V1 and V2 into digital values, respectively.

[0070] In this embodiment, each of the multiple capacitive elements C11, C12 preferably has a capacitance 100 times or more larger than the amount of charge leaking through the switches Q11, Q12 during the holding period. The holding period is the period until the next AD conversion of the corresponding analog input voltages V1, V2 among the multiple analog input voltages V1, V2. If charge leaks through the switches Q11, Q12 during the holding period, the charging voltage of the capacitive elements C11, C12 fluctuates, and the comparison reference voltage V5 in the next AD conversion fluctuates. Therefore, each of the multiple capacitive elements C11, C12 preferably has a capacitance 100 times or more larger than the amount of charge leaking through the switches Q11, Q12 during the holding period, and even if leakage occurs, the fluctuation of the charging voltages V51, V52 can be suppressed, and thus the fluctuation of the comparison reference voltage V5 can be suppressed. Each of the capacitance elements C11, C12 only needs to have a capacitance that is 100 times or more the amount of charge leaking through the switches Q11, Q12 during the retention period, and the upper limit of the capacitance can be determined by factors such as the size of the capacitance elements C11, C12.

[0071] (3) Modifications The above embodiment is merely one of various embodiments of the present disclosure. The above embodiment can be modified in various ways depending on the design and the like as long as the object of the present disclosure can be achieved.

[0072] Modifications of the above embodiment are listed below. The modifications described below can be applied in appropriate combinations.

[0073] In the above embodiment, the circuit configurations of the DA conversion unit 5, the integrator 61, etc. are merely examples and can be modified as appropriate.

[0074] In the above embodiment, the analog input voltages V1, V2 input to the input terminals TA1, TA2 are output signals of various sensors such as an acceleration sensor, an angular velocity sensor, a gyro sensor, or a pressure sensor, but may be voltage signals other than the output signals of sensors.

[0075] In the above embodiment, the input switching circuit 2 may be realized by a multiplexer or the like.

[0076] In the above embodiment, the serial-parallel conversion unit 8 is provided separately from the filter circuit 9, but the serial-parallel conversion unit 8 is not an essential component. If the filter circuit 9 has the function of the serial-parallel conversion unit, the serial-parallel conversion unit 8 may be omitted.

[0077] In the above embodiment, in a comparison of two values, such as a comparison between a differential voltage and a comparison reference voltage, "greater than" may be used instead of "greater than." In other words, in a comparison of two values, whether or not the two values ​​are equal can be arbitrarily changed depending on the setting of the reference value, etc., so there is no technical difference between "greater than" and "greater than." Similarly, "less than" may be used instead of "less than."

[0078] (summary) As described above, the AD converter (1) of the first embodiment includes an input switching circuit (2) and a successive approximation type AD conversion unit (3). The input switching circuit (2) receives a plurality of analog input voltages (V1, V2) and outputs one analog input voltage selected from the plurality of analog input voltages (V1, V2) as a conversion target voltage (V3). The AD conversion unit (3) performs AD conversion to convert the conversion target voltage (V3) input from the input switching circuit (2) into a multi-bit digital signal (D11). When the conversion operation of the conversion target voltage (V3) by the AD conversion unit (3) is completed, the input switching circuit (2) switches the analog input voltage selected as the conversion target voltage (V3) from the plurality of analog input voltages (V1, V2). The AD conversion unit (3) performs a conversion operation for each target bit from the most significant bit to the least significant bit. The AD conversion unit (3) includes a control unit (4), a DA conversion unit (5), a comparison reference generation unit (6), and a comparator (7). The DA conversion unit (5) generates an analog comparison voltage corresponding to the target bit in response to a control signal (S1) from the control unit (4). The comparison reference generation unit (6) generates a comparison reference voltage (V5) corresponding to the analog input voltage (V1, V2) selected as the conversion target voltage (V3). The comparator (7) determines the value of the target bit by comparing a difference voltage (V4) between the conversion target voltage (V3) and the comparison voltage with the comparison reference voltage (V5). The control unit (4) determines a control signal (S1) for the next bit of the target bit based on the comparison result of the comparator (7) for the target bit. The comparison reference generation unit (6) includes an integrator (61), a plurality of capacitance elements (C11, C12), and a switching circuit (62). The integrator (61) integrates the difference voltage (V4) in a state where the AD conversion unit (3) has performed a conversion operation of the least significant bit. The multiple capacitive elements (C11, C12) are provided corresponding to the multiple analog input voltages (V1, V2), respectively. The switching circuit (62) connects the capacitive element (C11, C12) among the multiple capacitive elements (C11, C12) corresponding to the analog input voltage (V1, V2) selected as the conversion target voltage (V3) to the output terminal of the integrator (61). The capacitive element (C11, C12) among the multiple capacitive elements (C11, C12) connected to the output terminal of the integrator (61) via the switching circuit (62) is charged by the output voltage of the integrator (61).The comparison reference generating unit (6) sets the charging voltages (V51, V52) of the capacitive elements corresponding to the analog input voltage selected as the conversion target voltage (V3) among the plurality of capacitive elements (C11, C12) as the comparison reference voltage (V5).

[0079] According to this embodiment, when the conversion operation of the conversion target voltage (V3) by the AD conversion unit (3) is completed, the input switching circuit (2) switches the analog input voltage (V1, V2) selected as the conversion target voltage (V3) from the multiple analog input voltages (V1, V2). Therefore, the AD converter (1) can perform AD conversion of the multiple analog input voltages (V1, V2) in a time-division manner. Also, each of the multiple capacitive elements (C11, C12) is charged with the integration result of the integrator (61) when the corresponding analog input voltage (V1, V2) is the conversion target voltage (V3). Since the charging voltage (V51, V52) of the capacitive elements (C11, C12) is used as the comparison reference voltage (V5) when the corresponding analog input voltage (V1, V2) is next AD converted, the conversion error can be reduced by using a value obtained by integrating the conversion error in the AD conversion as the comparison reference voltage (V5) in the next AD conversion. Therefore, it is possible to provide an AD converter (1) capable of AD converting a plurality of analog input voltages (V1, V2) in a time-division manner and with reduced conversion errors.

[0080] In the AD converter (1) of the second aspect, in the first aspect, one ends of the plurality of capacitance elements (C11, C12) are connected to a reference voltage of the AD converter (1). The switching circuit (62) includes a plurality of switches (Q11, Q12) respectively connected between the other ends of the plurality of capacitance elements (C11, C12) and the output terminal of the integrator (61).

[0081] According to this embodiment, it is possible to provide an AD converter (1) capable of AD converting a plurality of analog input voltages (V1, V2) in a time-division manner and with reduced conversion errors.

[0082] In the AD converter (1) of the third aspect, in the second aspect, each of the plurality of capacitive elements (C11, C12) has a capacitance 100 times or more the amount of charge leaking through the switch during a holding period. The holding period is the time until the corresponding analog input voltage (V1, V2) among the plurality of analog input voltages (V1, V2) is next AD converted.

[0083] According to this embodiment, it is possible to suppress fluctuations in the charging voltages (V51, V52) stored in the plurality of capacitance elements (C11, C12) during the hold period.

[0084] The AD converter (1) of the fourth aspect is in any one of the first to third aspects and includes a filter circuit (9) that attenuates high-frequency components of a digital signal (D12) output from the AD conversion unit (3). The filter circuit (9) includes a plurality of filters (91, 92) corresponding to a plurality of analog input voltages (V1, V2), respectively, and a filter switching circuit (93). The filter switching circuit (93) inputs the digital signal (D12) to the filter (91, 92) corresponding to the analog input voltage (V1, V2) selected as a conversion target voltage (V3) from among the plurality of filters (91, 92).

[0085] According to this embodiment, there is an advantage that a plurality of filters (91, 92) corresponding to the plurality of analog input voltages (V1, V2), respectively, can be designed according to the frequencies of the plurality of analog input voltages (V1, V2).

[0086] In the AD converter (1) of the fifth aspect, in any one of the first to fourth aspects, the DA conversion section (5) includes a plurality of capacitive elements (C1, C2) and a voltage switching circuit (55). One end of each of the plurality of capacitive elements (C1, C2) is connected to an output terminal of the input switching circuit (2). The voltage switching circuit (55) selectively connects the other end of each of the plurality of capacitive elements (C1, C2) to either a first voltage (VH) or a second voltage (VL) in response to a control signal (S1).

[0087] This embodiment has the advantage that the DA conversion unit (5) can be realized with a simple circuit.

[0088] In the AD converter (1) of the sixth aspect, in any one of the first to fifth aspects, the integrator (61) includes multiple stages of integration circuits (61A to 61C) that sequentially perform integration operations. Each of the multiple stages of integration circuits (61A to 61C) performs the integration operation using operational amplifiers (OP1 to OP3).

[0089] According to this embodiment, by performing a multi-stage integration operation using the multi-stage integrating circuits (61A to 61C), it is possible to realize a noise shaping characteristic that moves noise in a low frequency band to a high frequency band.

[0090] Without being limited to the above-mentioned aspects, various configurations (including modified examples) of the control unit (4) provided in the AD converter (1) according to the above-mentioned embodiment can be embodied as a control method for the control unit (4), a (computer) program, or a non-transitory recording medium having a program recorded thereon, etc.

[0091] The configurations according to the second to sixth aspects are not essential for the AD converter (1) and can be omitted as appropriate. [Explanation of symbols]

[0092] 1. A / D converter 2 Input switching circuit 3 AD conversion section 5. DA Conversion Section 6 Comparison standard generator 7 Comparators 9 Filter Circuits 55 Voltage switching circuit 61 Integrator 62 Switching circuit 91,92 Filter 93 Filter switching circuit C1, C2 Capacitor element C11, C12 Capacitor element D11 Digital Signal OP1~OP3 operational amplifiers Q11, Q12 Switch S1 Control signal V1, V2 Analog input voltage V3 Conversion target voltage V4 Differential voltage V5 Comparison reference voltage VH First voltage VL Second voltage

Claims

1. an input switching circuit that receives a plurality of analog input voltages and selects one analog input voltage from the plurality of analog input voltages and outputs the selected analog input voltage as a voltage to be converted; a successive approximation type AD conversion unit that performs AD conversion to convert the conversion target voltage input from the input switching circuit into a multi-bit digital signal, the input switching circuit switches an analog input voltage to be selected as the conversion target voltage from among the plurality of analog input voltages when the conversion operation of the conversion target voltage by the AD conversion unit is completed; The AD conversion unit performs a conversion operation for each target bit from the most significant bit to the least significant bit, The AD conversion unit includes: A control unit; a DA conversion unit that generates an analog comparison voltage corresponding to the target bit in response to a control signal from the control unit; a comparison reference generating unit that generates a comparison reference voltage corresponding to the analog input voltage selected as the conversion target voltage; a comparator that determines a value of the target bit by comparing a difference voltage between the conversion target voltage and the comparison voltage with the comparison reference voltage; The control unit determines the control signal for a bit subsequent to the target bit based on a comparison result of the comparator for the target bit; The comparison reference generation unit an integrator that integrates the difference voltage in a state in which the AD conversion unit has performed a conversion operation of the least significant bit; a plurality of capacitance elements provided corresponding to the plurality of analog input voltages, respectively; a switching circuit that connects a capacitive element corresponding to the analog input voltage selected as the conversion target voltage among the plurality of capacitive elements to an output terminal of the integrator, a capacitance element connected to the output terminal of the integrator via the switching circuit among the plurality of capacitance elements is charged by an output voltage of the integrator; the comparison reference generating unit sets a charging voltage of a capacitive element selected as the conversion target voltage from among the plurality of capacitive elements as the comparison reference voltage; Analog to digital converter.

2. one end of each of the plurality of capacitance elements is connected to a reference voltage of the AD converter; the switching circuit includes a plurality of switches respectively connected between the other ends of the plurality of capacitive elements and an output terminal of the integrator; 2. The AD converter according to claim 1.

3. each of the plurality of capacitive elements has a capacitance 100 times or more larger than an amount of charge leaking through the switch during a holding period until a corresponding one of the plurality of analog input voltages is next AD converted; 3. The AD converter according to claim 2.

4. a filter circuit that attenuates high-frequency components of the digital signal output from the AD conversion unit, The filter circuit includes: a plurality of filters respectively corresponding to the plurality of analog input voltages; a filter switching circuit that inputs the digital signal to a filter that corresponds to the analog input voltage selected as the conversion target voltage from among the plurality of filters, 4. The AD converter according to claim 1, wherein the first and second inputs are connected to the first and second inputs.

5. The DA conversion unit is a plurality of capacitance elements each having one end connected to an output terminal of the input switching circuit; a voltage switching circuit that selectively connects the other ends of the plurality of capacitive elements to either a first voltage or a second voltage in response to the control signal.

5. The AD converter according to claim 1.

6. the integrator includes a plurality of stages of integration circuits that sequentially perform an integration operation; Each of the multiple stages of integrating circuits performs an integrating operation using an operational amplifier.

6. The AD converter according to claim 1,

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