RF signal filter configuration for plasma processing systems

Abstract

The variable edge sheath (TES) system includes a coupling ring configured to couple to a bottom surface of an edge ring surrounding a wafer support region in a plasma processing chamber. The TES system includes an annular electrode embedded in the coupling ring. The TES system also includes a plurality of RF signal feed pins coupled to the electrodes in the coupling ring. The plurality of RF signal feed pins each extend through a corresponding hole formed through the bottom surface of the coupling ring. The TES system includes a plurality of RF signal filters respectively connected to the plurality of RF feed pins. Each of the plurality of RF signal filters is configured to provide a high impedance to an RF signal used to generate plasma in the plasma processing chamber.

Description

[Technical field]

[0001] 1. Field of disclosure

[0002] The present disclosure relates to semiconductor device manufacturing. [Background technology]

[0003] 2. Description of Related Technology

[0004] Plasma etching processes are often used in the fabrication of semiconductor devices on semiconductor wafers. In a plasma etching process, a semiconductor wafer containing the semiconductor device under fabrication is exposed to a plasma generated in a plasma processing region. The plasma interacts with material on the semiconductor wafer to remove material from the semiconductor wafer and / or modify material so that it can subsequently be removed from the semiconductor wafer. The plasma can be generated using specific reactive gases, such that components of the plasma can interact with material to be removed or modified from the semiconductor wafer without significant interaction with material on other wafers that is not removed / modified. The plasma is generated using radio frequency (RF) signals to excite specific reactive gases. These RF signals are transmitted through a plasma processing region that contains the reactive gases and in which the semiconductor wafer is held for exposure. The transmission path of the RF signal through the plasma processing region can affect how the plasma is generated in the plasma processing region. For example, in areas of the plasma processing region where a larger amount of RF signal power is transmitted, the reactive gases can be excited to a greater extent, resulting in spatial non-uniformity of the plasma characteristics throughout the plasma processing region. The spatial non-uniformity of the plasma characteristics may manifest itself as spatial non-uniformity of ion density, ion energy, and / or reactive species density, among other plasma characteristics. Corresponding spatial non-uniformity of the plasma characteristics may result in spatial non-uniformity of the plasma processing results on the semiconductor wafer. That is, the uniformity of the plasma processing results on the semiconductor wafer may be affected by how the RF signal is transmitted through the plasma processing region. The present disclosure is described in this context. Summary of the Invention

[0005] In an exemplary embodiment, a variable edge sheath system is disclosed. The variable edge sheath system includes a coupling ring configured to couple to a bottom surface of an edge ring surrounding a wafer support region in a plasma processing chamber. The variable edge sheath system also includes an electrode embedded in the coupling ring. The electrode has an annular shape. The variable edge sheath system also includes a plurality of RF signal supply pins coupled to the electrode embedded in the coupling ring. The plurality of RF signal supply pins each extend through a corresponding hole formed through a bottom surface of the coupling ring. The variable edge sheath system also includes a plurality of RF signal filters respectively connected to the plurality of RF signal supply pins. Each of the plurality of RF signal filters is configured to provide a high impedance to a corresponding RF signal used to generate a plasma in the plasma processing chamber. In an exemplary embodiment, a plasma processing system is disclosed. The plasma processing system includes a primary electrode having a substantially cylindrical shape defined by a top surface, a bottom surface, and an outer surface. The plasma processing system also includes a ceramic layer disposed on the top surface of the primary electrode. The ceramic layer is configured to receive and support a semiconductor wafer. The plasma processing system also includes an RF signal generator electrically connected to the primary electrode via an impedance matching system. The RF signal generator is configured to generate and supply an RF signal to the primary electrode. The plasma processing system also includes an edge ring formed of a conductive material and configured to surround the ceramic layer. The edge ring is disposed radially adjacent to the ceramic layer. The plasma processing system also includes a coupling ring coupled to a bottom surface of the edge ring. The coupling ring is formed of an electrically insulating material. The coupling ring includes a recessed electrode. The plasma processing system also includes a plurality of RF signal supply pins electrically and physically connected to the recessed electrode. The plurality of RF signal supply pins each extend through a corresponding hole formed through a bottom surface of the coupling ring. The plasma processing system also includes a plurality of RF signal filters respectively coupled to the plurality of RF signal supply pins, each of the plurality of RF signal filters configured to present a high impedance to an RF signal supplied by the RF signal generator to the primary electrode. [Brief description of the drawings]

[0006] [Figure 1A] FIG. 1A illustrates a vertical cross-sectional view of a plasma processing system for use in semiconductor chip manufacturing, according to some embodiments.

[0007] [Figure 1B] FIG. 1B illustrates the system of FIG. 1A with the cantilever arm assembly moved downward to allow for the movement of the wafer through the door, according to some embodiments.

[0008] [Diagram 2]FIG. 2 shows a top view of ceramic layers and electrodes according to some embodiments.

[0009] [Figure 3A] FIG. 3A shows an electrical schematic of an impedance matching system according to some embodiments.

[0010] [Figure 3B] FIG. 3B illustrates an example electrical schematic of a TES impedance matching system according to some embodiments.

[0011] [Figure 4] FIG. 4 shows a close-up vertical cross-sectional view of a fixed outer support flange, according to some embodiments.

[0012] [Diagram 5] FIG. 5 illustrates a top view of a connecting outer support flange and a fixed outer support flange, according to some embodiments, showing a number of conductive straps connected between the connecting outer support flange and the fixed outer support flange.

[0013] [Figure 6] FIG. 6 illustrates a perspective view of the top of a connecting outer support flange and a fixed outer support flange, according to some embodiments, showing a number of conductive straps connected between the connecting outer support flange and the fixed outer support flange.

[0014] [Figure 7] FIG. 7 illustrates an isometric view of a conductive strap, according to some embodiments.

[0015] [Figure 8A] FIG. 8A illustrates a vertical cross-sectional view of a top electrode according to some embodiments.

[0016] [Figure 8B] FIG. 8B illustrates a top view of the upper electrode, according to some embodiments.

[0017] [Figure 9A] FIG. 9A shows a vertical cross-sectional close-up view of a connection between a coupling ring and an edge ring according to some embodiments.

[0018] [Figure 9B] FIG. 9B shows a close-up vertical cross-sectional view of a hold-down rod connected to a coupling ring according to some embodiments.

[0019] [Figure 9C] FIG. 9C illustrates a top perspective view of a coupling ring according to some embodiments.

[0020] [Figure 10A] FIG. 10A shows a bottom perspective view of a portion of a TES system disposed within a cantilever arm assembly according to some embodiments.

[0021] [Figure 10B] FIG. 10B illustrates a bottom perspective view of a TES system as shown in FIG. 10A having TES RF signal filters, each configured as a conductive coil, according to some embodiments.

[0022] [Figure 11] FIG. 11 illustrates a bottom perspective view of an alternative TES system that uses a single TES RF signal filter for all TES RF signal supply pins according to some embodiments.

[0023] [Figure 12A] FIG. 12A shows a wafer map of plasma processing results across a wafer obtained using the TES system of FIG. 11 according to some embodiments.

[0024] [Figure 12B] FIG. 12B shows a wafer map of plasma processing results across a wafer obtained using the TES systems of FIGS. 1A, 1B, 3B, 9A, 9B, 9C, 10A, and 10B, according to some embodiments.

[0025] [Figure 12C] FIG. 12C shows a wafer map of plasma processing results across the wafer obtained with the TES RF signal supply pins decoupled from their respective TES RF signal filters, according to some embodiments.

[0026] [Figure 13A] FIG. 13A illustrates a perspective view of an edge ring according to some embodiments.

[0027] [Figure 13B] FIG. 13B illustrates a top view of an edge ring, according to some embodiments.

[0028] [Figure 13C] FIG. 13C illustrates a vertical cross-sectional view of the edge ring shown as a view at (section line) AA in FIG. 13B, according to some embodiments.

[0029] [Figure 14] FIG. 14 illustrates an example schematic diagram of the control system of FIG. 1A, according to some embodiments. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0030] In the following description, numerous specific details are set forth in order to provide an understanding of the embodiments of the present disclosure. However, it will be apparent to one skilled in the art that the embodiments of the present disclosure can be practiced without some or all of these specific details. In other instances, detailed descriptions of well-known processing operations are omitted in order to avoid unnecessarily obscuring the present disclosure.

[0031] In plasma etching systems for semiconductor wafer manufacturing, the spatial variation of the etching results across the semiconductor wafer is characterized by radial etch uniformity and azimuthal etch uniformity. Radial etch uniformity can be characterized by the variation of the etch rate as a function of radial position on the semiconductor wafer extending outward from the center of the semiconductor wafer to the edge of the semiconductor wafer at a given azimuthal position on the semiconductor wafer. Also, azimuthal etch uniformity can be characterized by the variation of the etch rate as a function of azimuthal position on the semiconductor wafer about the center of the semiconductor wafer at a given radial position on the semiconductor wafer. In some plasma processing systems, such as the system described herein, the semiconductor wafer is placed on an electrode from which an RF signal is emitted to generate a plasma in a plasma generating region over the semiconductor wafer. The plasma has controlled characteristics to produce a predetermined etching process on the semiconductor wafer.

[0032] FIG. 1A illustrates a vertical cross-sectional view of a plasma processing system 100 for use in semiconductor chip manufacturing, according to some embodiments. The system 100 includes a chamber 101 formed by walls 101A, a top member 101B, and a bottom member 101C. The walls 101A, the top member 101B, and the bottom member 101C collectively form an interior region 103 within the chamber 101. The bottom member 101C includes an exhaust port 105 through which exhaust gases of a plasma processing operation are directed. In some embodiments, during operation, a suction force is applied to the exhaust port 105, such as by a turbo pump or other vacuum device, to draw process exhaust gases from the interior region 103 of the chamber 101. In some embodiments, the chamber 101 is formed of aluminum. However, in various embodiments, the chamber 101 can be formed of essentially any material, such as stainless steel, that has sufficient mechanical strength, acceptable thermal performance, and is chemically compatible with other materials that are in contact with and exposed to during plasma processing operations within the chamber 101. At least one wall 101A of the chamber 101 includes a door 107 through which semiconductor wafers W are transferred in and out of the chamber 101. In some embodiments, the door 107 is configured as a slit valve door.

[0033] In some embodiments, the semiconductor wafer W is a semiconductor wafer in a manufacturing process. For ease of description, the semiconductor wafer W is hereinafter referred to as a wafer W. However, in various embodiments, the wafer W can be essentially any type of substrate that is subjected to a plasma-based manufacturing process. For example, in some embodiments, the wafer W referred to herein can be a substrate formed of silicon, sapphire, GaN, GaAs, or SiC, or other substrate materials, and can include glass panels / substrates, metal foils, metal sheets, polymeric materials, and the like. Also, in various embodiments, the wafer W referred to herein can vary in form, shape, and / or size. For example, in some embodiments, the wafer W referred to herein can be a circular semiconductor wafer on which integrated circuit devices are fabricated. In various embodiments, the circular wafer W can have a diameter of 200 mm (millimeters), 300 mm, 450 mm, or other sizes. Also, in some embodiments, the wafer W referred to herein can be a non-circular substrate, such as a rectangular substrate for a flat panel display.

[0034] The plasma processing system 100 includes an electrode 109 disposed on a facility plate 111. In some embodiments, the electrode 109 and the facility plate 111 are formed of aluminum. However, in other embodiments, the electrode 109 and the facility plate 111 can be formed of other conductive materials that have sufficient mechanical strength and compatible thermal and chemical performance characteristics. A ceramic layer 110 is formed on a top surface of the electrode 109. In some embodiments, the ceramic layer has a vertical thickness of about 1.25 millimeters (mm) when measured perpendicular to the top surface of the electrode 109. However, in other embodiments, the ceramic layer 110 can have a vertical thickness greater than or less than 1.25 mm. The ceramic layer 110 is configured to receive and support the wafer W while plasma processing operations are performed on the wafer W. In some embodiments, the top surface of the electrode 190 and the peripheral side of the electrode 109, which are radially outward of the ceramic layer 110, are covered with a ceramic spray coat.

[0035] The ceramic layer 110 includes an arrangement of one or more clamping electrodes 112 for generating an electrostatic force that holds the wafer W on the top surface of the ceramic layer 110. In some embodiments, the ceramic layer 110 includes an arrangement of two clamping electrodes 112 operating in a bipolar manner to provide a clamping force to the wafer W. The clamping electrodes 112 are connected to a direct current (DC) power supply 117 that generates a controlled clamping voltage to hold the wafer W on the top surface of the ceramic layer 110. Electrical wires 119A, 119B are connected between the DC power supply 117 and the facility plate 111. Electrical wires / conductors are routed through the facility plate 111 and the electrodes 109 to electrically connect the wires 119A, 119B to the clamping electrodes 112. The DC power supply 117 is connected to a control system 120 via one or more signal conductors 121.

[0036] The electrode 109 also includes a configuration of temperature control fluid channels 123 through which a temperature control fluid flows to control the temperature of the electrode 109, and in turn, the temperature of the wafer W. The temperature control fluid channels 123 are plumbed (fluidically connected) to ports on the facility plate 111. Temperature control fluid supply and return lines are connected to these ports on the facility plate 111 and to a temperature control fluid circulation system 125, as indicated by arrows 126. The temperature control fluid circulation system 125 includes a temperature control fluid supply, a temperature control fluid pump, and heat exchangers and other devices, and controls the flow of temperature control fluid through the electrode 109 to set and maintain a predetermined wafer W temperature. The temperature control fluid circulation system 125 is connected to the control system 120 via one or more signal conductors 127. In various embodiments, various types of temperature control fluids can be used, such as water or a refrigerant liquid / gas. Additionally, in some embodiments, the temperature control fluid channels 123 are configured to allow for spatially varying control of the temperature of the wafer W, for example, in two dimensions (x and y) across the wafer W.

[0037] The ceramic layer 110 also includes an arrangement of backside gas supply ports 108 (see FIG. 2) fluidly connected to corresponding backside gas supply channels in the electrode 109. The backside gas supply channels in the electrode 109 are routed through the electrode 109 to an interface between the electrode 109 and the facility plate 111. One or more backside gas supply lines are connected to ports on the facility plate 111, as indicated by arrows 130, and to a backside gas supply system 129. The facility plate 111 is configured to supply backside gas from one or more backside gas supply lines to the backside gas supply channels in the electrode 109. The backside gas supply system 129 includes a backside gas source, mass flow controllers, flow control valves and other devices to provide a controlled backside gas flow through the arrangement of backside gas supply ports 108 in the ceramic layer 110. In some embodiments, the backside gas supply system 129 also includes one or more components for controlling the temperature of the backside gas. In some embodiments, the backside gas is helium. Also in some embodiments, a backside gas supply system 129 can be used to supply clean dry air (CDA) to the arrangement of backside gas supply ports 108 in the ceramic layer 110. The backside gas supply system 129 is connected to the control system 120 via one or more signal conductors 131.

[0038] The three lift pins 132 extend through the facility plate 111, the electrode 109, and the ceramic layer 110 to allow vertical movement of the wafer W relative to the top surface of the ceramic layer 110. In some embodiments, the vertical movement of the lift pins 132 is controlled by respective electromechanical and / or pneumatic lift devices 133 connected to the facility plate 111. The three lift devices 133 are connected to the control system 120 via one or more signal conductors 134. In some embodiments, the three lift pins 132 are positioned to have substantially equal azimuthal spacing with respect to a vertical centerline of the electrode 109 / ceramic layer 110 that extends perpendicular to the top surface of the ceramic layer 110. Note that the lift pins 132 rise to accept and remove the wafer W into and from the chamber 101 (see FIG. 1B). The lift pins 132 also lower to place the wafer W on the top surface of the ceramic layer 110 during processing of the wafer W.

[0039] FIG. 2 illustrates a top view of the ceramic layer 110 and the electrode 109, according to some embodiments. An exemplary placement of the clamping electrode 112 within the ceramic layer 110 is shown. Note that the clamping electrode 112 is located within the vertical thickness of the ceramic layer 110 such that a portion of the ceramic layer 110 resides above the clamping electrode 112. FIG. 2 also illustrates an exemplary placement of the backside gas supply ports 108. Note that the number and spatial placement of the backside gas supply ports 108 may vary in different embodiments. In some embodiments, the backside gas supply ports 108 are filled with a porous ceramic material that allows for backside gas flow through the backside gas supply ports 108 while simultaneously providing a solid surface at the backside gas supply ports 108. FIG. 2 also illustrates an exemplary placement of three lift pins 132.

[0040] Also, in various embodiments, one or more of the electrodes 109, facility plate 111, ceramic layer 110, clamping electrodes 112, lift pins 132, or essentially any other components associated therewith, may include one or more sensors, such as sensors for measuring temperature, voltage, and current, etc. Any sensors located on the electrodes 109, facility plate 111, ceramic layer 110, clamping electrodes 112, lift pins 132, or essentially any other components associated therewith, are connected to the control system 120 via electrical wires, optical fibers, or wireless connections.

[0041] The facility plate 111 is set within an opening in, and supported by, the ceramic support 113. The ceramic support 113 is disposed on a support surface 114 of the cantilever arm assembly 115. In some embodiments, the ceramic support 113 has a substantially annular shape such that the ceramic support 113 substantially surrounds the radial periphery of the facility plate 111 while also providing a support surface 116 on which a bottom peripheral surface of the facility plate 111 rests. The cantilever arm assembly 115 extends through the wall 101A of the chamber 101. In some embodiments, a sealing mechanism 135 is provided within the wall 101A of the chamber 101 in which the cantilever arm assembly 115 is disposed to seal the interior region 103 of the chamber 101 while allowing the cantilever arm assembly 115 to move up and down in the z-direction in a controlled manner.

[0042] The cantilever arm assembly 115 has an open area 118 through which various devices, wires, cables, and tubes are routed to support the operation of the system 100. The open area 118 in the cantilever arm assembly is exposed to the atmospheric conditions outside the chamber 101, such as air composition, temperature, pressure, and relative humidity. Also disposed within the cantilever arm assembly 115 is an RF signal supply rod 137. More specifically, the RF signal supply rod 137 is disposed within a conductive tube 139, and the RF signal supply rod 137 is spaced apart from the inner wall of the tube 139. The size of the RF signal supply rod 137 and the tube 139 can be varied. The area within the tube 139 between the inner wall of the tube 139 and the RF signal supply rod 137 is occupied by air along the entire length of the tube 139. In some embodiments, the outer diameter (D rod ) and the inner diameter of the tube 139 (D tube ) is ln(D tube / D rod )>=e 1 is set so as to satisfy the relationship:

[0043] In some embodiments, the RF signal feed rod 137 is substantially centrally located within the tube 139, and a substantially uniform radial thickness of air exists between the RF signal feed rod 137 and the inner wall of the tube 139 along the length of the tube 139. However, in some embodiments, the RF signal feed rod 137 is not centrally located within the tube 139. There is still air space along the length of the tube 139 at all locations within the tube 139 between the RF signal feed rod 137 and the inner wall of the tube 139. The delivery end of the RF signal feed rod 137 is electrically and physically connected to the bottom end of the RF signal feed shaft 141. In some embodiments, the delivery end of the RF signal feed rod 137 is bolted to the bottom end of the RF signal feed shaft 141. The top end of the RF signal feed shaft 141 is electrically and physically connected to the bottom of the facility plate 111. In some embodiments, the top end of the RF signal feed shaft 141 is bolted to the bottom of the facility plate 111. In some embodiments, both the RF signal feed rod 137 and the RF signal feed shaft 141 are made of copper. In some embodiments, the RF signal feed rod 137 is made of copper, aluminum, or anodized aluminum. In some embodiments, the RF signal feed shaft 141 is made of copper, aluminum, or anodized aluminum. In other embodiments, the RF signal feed rod 137 and / or the RF signal feed shaft 141 are made of another conductive material that allows for the transmission of RF electrical signals. In some embodiments, the RF signal feed rod 137 and / or the RF signal feed shaft 141 are coated with a conductive material (such as silver or other conductive material) that allows for the transmission of RF electrical signals. Also, in some embodiments, the RF signal feed rod 137 is a solid rod. However, in other embodiments, the RF signal feed rod 137 is a tube. It should be noted that the area 140 surrounding the connection between the RF signal feed rod 137 and the RF signal feed shaft 141 is occupied by air.

[0044] The feed end of the RF signal feed rod 137 is electrically and physically connected to an impedance matching system 143. The impedance matching system 143 is connected to a first RF signal generator 147 and a second RF signal generator 149. The impedance matching system 143 is also connected to the control system 120 via one or more signal conductors 144. The first RF signal generator 147 is also connected to the control system 120 via one or more signal conductors 148. The second RF signal generator 149 is also connected to the control system 120 via one or more signal conductors 150. The impedance matching system 143 includes an arrangement of inductors and capacitors sized and connected to enable impedance matching so that RF power can be transmitted along the RF signal feed rod 137 and the RF signal feed shaft 141, through the facility plate 111 and the electrode 109, and to the plasma processing region 182 above the ceramic layer 110. In some embodiments, the first RF signal generator 147 is a high frequency RF signal generator and the second RF signal generator 149 is a low frequency RF signal generator. In some embodiments, the first RF signal generator 147 generates an RF signal in a range of about 50 megahertz (MHz) to about 70 MHz, or in a range of about 54 MHz to about 63 MHz, or at about 60 MHz. In some embodiments, the first RF signal generator 147 provides RF power in a range of about 5 kilowatts (kW) to about 25 kW, or in a range of about 10 kW to about 20 kW, or in a range of about 15 kW to about 20 kW, or at about 10 kW or about 16 kW. In some embodiments, the second RF signal generator 149 generates an RF signal in a range of about 50 kilohertz (kHz) to about 500 kHz, or in a range of about 330 kHz to about 440 kHz, or at about 400 kHz. In some embodiments, the second RF signal generator 149 provides RF power in the range of about 15 kW to about 100 kW, or in the range of about 30 kW to about 50 kW, or at about 34 kW or about 50 kW. In one exemplary embodiment, the first RF signal generator 147 is configured to generate an RF signal at a frequency of about 60 MHz and the second RF signal generator 149 is configured to generate an RF signal at a frequency of about 400 kHz.

[0045] 3A shows an electrical schematic diagram of the impedance matching system 143 according to some embodiments. The impedance matching system 143 includes a first branch 302A (high frequency branch) and a second branch 302B (low frequency branch). The first branch 302A includes circuit components such as an inductor L4, a capacitor C2, a capacitor C7, and a capacitor C3. The second branch 302B includes circuit components such as an inductor L1, an inductor L2, a capacitor C1, a capacitor C4, a capacitor C5, a capacitor C6, and an inductor L3. In some embodiments, the capacitors C1, C2, and C3 are variable capacitors. The capacitors C1 and C2 are main capacitors and the capacitor C3 is a reserve capacitor. The inductors L1, L2, L3, and L4 are each formed as a coil made of a conductive material, for example copper. The first branch 302A has an input I1 connected to the output of the first RF signal generator 147. The second branch 302B has an input I2 connected to the output of the second RF signal generator 149. The input I2 is connected to an inductor L1.

[0046] As an example, the RF straps referred to herein are flat, elongated pieces of conductive material such as copper. Thus, the RF straps have a length, a width, and a thickness. The length of the RF strap is greater than the width of the RF strap. Additionally, the width of the RF strap is greater than the thickness of the RF strap. In some embodiments, the RF straps are flexible to allow them to bend or reshape themselves.

[0047] The first branch 302A includes RF strap portion 304A (represented as inductor LA), RF strap portion 304B (represented as inductor LB), RF strap 304C (represented as inductor LC), RF strap 304D (represented as inductor LD), and RF strap 304E (represented as inductor LE). In some embodiments, RF strap portions 304A and 304B are separate parts of one RF strap, i.e., inductors LA and LB represent separate parts of one RF strap. However, in some embodiments, instead of one RF strap including two RF strap portions 304A and 304B, two separate RF straps are used as RF strap portions 304A and 304B, respectively. For example, a first RF strap having an inductance of RF strap portion 304A is connected to a second RF strap having an inductance of RF strap portion 304B via a conductive connector.

[0048] The capacitor C3 is coupled to a predetermined position P1 on the RF strap including both RF strap portions 304A and 304B via the RF strap 304C. Thus, the predetermined position P1 where the RF strap 304C is connected to the RF strap including both RF strap portions 304A and 304B determines the length of each of the RF strap portions 304A and 304B. The capacitor C7 is also coupled to the end of the RF strap portion 304A opposite to the predetermined position P1. The predetermined position P1 is coupled to the RF signal supply rod 137 via the RF strap portion 304B. The RF straps 304D and 304E are coupled to each other at the predetermined position P2. The terminal of the capacitor C2 is also connected to the predetermined position P2. The RF strap 304D is coupled to the inductor L4 and the input I1 of the impedance matching system 143. Each of the RF strap portions 304A and 304B, and each of the RF straps 304C, 304D, and 304E has an inductance. For example, RF strap portion 304A has an inductance LA, RF strap portion 304B has another inductance LB, RF strap 304C has another inductance LC, RF strap 304D has an inductance LD, and RF strap 304E has an inductance LE. Note that any of the RF straps such as RF straps 304A-304E described herein are not wound into a coil to form an inductor, but rather are formed as a flat strip of metal.

[0049] In various embodiments, any of the capacitors and / or non-strap inductors shown in FIG. 3A may be fixed or variable. For example, in various embodiments, any one or more of capacitors C4-C7 are fixed capacitors, meaning that their inductance cannot be changed or adjusted. Also, in some embodiments, any one or more of capacitors C4-C7 are variable capacitors, meaning that their capacitance can be changed / adjusted. In various embodiments, any one or more of inductors L1-L4 are fixed inductors, meaning that their inductance cannot be changed or adjusted. Also, in various embodiments, any one or more of inductors L1-L4 are variable inductors, meaning that their inductance can be changed or adjusted.

[0050] 1A, the bonding ring 161 is configured and positioned to extend around the radial circumference of the electrode 109. In some embodiments, the bonding ring 161 is formed of a ceramic material. The quartz ring 163 is configured and positioned to extend around the radial circumference of both the bonding ring 161 and the ceramic support 113. In some embodiments, the bonding ring 161 and the quartz ring 163 are configured to have substantially aligned top surfaces when the quartz ring 163 is disposed around both the bonding ring 161 and the ceramic support 113. Also, in some embodiments, the substantially aligned top surfaces of the bonding ring 161 and the quartz ring 163 are substantially aligned with the top surface of the electrode 109 that is outside the radial circumference of the ceramic layer 110. Also, in some embodiments, the cover ring 165 is configured and positioned to extend around the radial circumference of the top surface of the quartz ring 163. In some embodiments, the cover ring 165 is formed of quartz. Additionally, in some embodiments, the cover ring 165 is configured to extend vertically above the top surface of the quartz ring 163. As such, the cover ring 165 provides a peripheral boundary around which the edge ring 167 is disposed.

[0051] The edge ring 167 is configured to facilitate extending the plasma sheath radially outward beyond the periphery of the wafer W to improve processing results near the periphery of the wafer W. In various embodiments, the edge ring 167 is formed from a conductive material, such as crystalline silicon, polycrystalline silicon (polysilicon), boron-doped single crystal silicon, aluminum oxide, quartz, aluminum nitride, silicon nitride, silicon carbide, or a silicon carbide layer on an aluminum oxide layer, or an alloy of silicon, or a combination thereof, or other materials. It should be noted that the edge ring 167 is formed as an annular structure, such as a ring structure. The edge ring 167 can perform many functions, such as shielding components below the edge ring 167 to prevent damage from ions of the plasma 180 formed in the plasma processing region 182. The edge ring 167 also enhances the uniformity of the plasma 180 at and along the peripheral edge region of the wafer W.

[0052] A fixed outer support flange 169 is attached to the cantilever arm assembly 115. FIG. 4 shows a close-up view of a vertical cross section of the fixed outer support flange 169, according to some embodiments. The fixed outer support flange 169 is configured to extend around the outer vertical side 113A of the ceramic support 113, around the outer vertical side 163A of the quartz ring 163, and around the lower outer vertical side 165A of the cover ring 165. The fixed outer support flange 169 has an annular shape that surrounds the assembly of the ceramic support 113, the quartz ring 163, and the cover ring 165. The fixed outer support flange 169 has an L-shaped vertical cross section that includes a vertical portion 169A and a horizontal portion 169B. The L-shaped cross-sectional vertical portion 169A of the fixed outer support flange 169 has an inner vertical surface 169C disposed relative to the outer vertical side 113A of the ceramic support 113, the outer vertical side 163A of the quartz ring 163, and the lower outer vertical side 165A of the cover ring 165. In some embodiments, the L-shaped cross-sectional vertical portion 169A of the fixed outer support flange 169 extends over the entire outer vertical side 113A of the ceramic support 113, the entire outer vertical side 163A of the quartz ring 163, and the lower outer vertical side 165A of the cover ring 165. In some embodiments, the cover ring 165 extends radially outward above the top surface 169E of the L-shaped cross-sectional vertical portion 169A of the fixed outer support flange 169. In some embodiments, the upper outer vertical side surface 165B of the cover ring 165 (located above the top surface 169E of the vertical portion 169A of the L-shaped cross section of the fixed outer support flange 169) is substantially vertically aligned with the outer vertical surface 169D of the vertical portion 169A of the L-shaped cross section of the fixed outer support flange 169. The horizontal portion 169B of the L-shaped cross section of the fixed outer support flange 169 is disposed on and fixed to the support surface 114 of the cantilever arm assembly 115. The fixed outer support flange 169 is formed of a conductive material. In some embodiments, the fixed outer support flange 169 is formed of aluminum or anodized aluminum. However, in other embodiments, the fixed outer support flange 169 can be formed of other conductive materials, such as copper or stainless steel.In some embodiments, the horizontal portion 169 B of the L-shaped cross section of the fixed outer support flange 169 is bolted to the support surface 114 of the cantilever arm assembly 115 .

[0053] The connecting outer support flange 171 is configured and positioned to extend around the outer vertical surface 169D of the vertical portion 169A of the L-shaped cross section of the fixed outer support flange 169 and to extend around the upper outer vertical side surface 165B of the cover ring 165. The connecting outer support flange 171 has an annular shape that surrounds both the vertical portion 169A of the L-shaped vertical cross section of the fixed outer support flange 169 and the upper outer vertical side surface 165B of the cover ring 165. The connecting outer support flange 171 has an L-shaped vertical cross section that includes a vertical portion 171A and a horizontal portion 171B. The vertical portion 171A of the L-shaped cross section of the connecting outer support flange 171 has an inner vertical surface 171C that is adjacent to and spaced from both the outer vertical side surface 169D of the vertical portion 169A of the L-shaped cross section of the fixed outer support flange 169 and the upper outer vertical side surface 165B of the cover ring 165. In this manner, the interlocking outer support flange 171 is movable vertically (z-direction) along both the vertical portion 169A of the L-shaped vertical cross section of the fixed outer support flange 169 and the upper outer vertical side surface 165B of the cover ring 165, as shown by arrow 172. The interlocking outer support flange 171 is formed of a conductive material. In some embodiments, the interlocking outer support flange 171 is formed of aluminum or anodized aluminum. However, in other embodiments, the interlocking outer support flange 171 may be formed of other conductive materials, such as copper or stainless steel.

[0054] A number of conductive straps 173 are connected between the interlocking outer support flange 171 and the fixed outer support flange 169 around the radial circumference of both the interlocking outer support flange 171 and the fixed outer support flange 169. In the exemplary embodiment shown in FIGS. 1A, 1B, 4A, 4B, 5, and 6, the conductive straps 173 are shown having an "outward" configuration, in which the conductive straps 173 are bent outwardly away from the fixed outer support flange 169. FIG. 5 illustrates a top view of the interlocking outer support flange 171 and the fixed outer support flange 169, according to some embodiments, showing a number of conductive straps 173 connected between the interlocking outer support flange 171 and the fixed outer support flange 169. FIG. 6 illustrates a top perspective view of the interlocking outer support flange 171 and the fixed outer support flange 169, according to some embodiments, showing a number of conductive straps 173 connected between the interlocking outer support flange 171 and the fixed outer support flange 169. In some embodiments, the conductive straps 173 are formed of stainless steel. However, in other embodiments, the conductive straps 173 may be formed from other conductive materials, such as aluminum or copper.

[0055] In the example of FIGS. 1A, 1B, 5, and 6, 48 conductive straps 173 are substantially equally spaced around the radial circumference of the connecting outer support flange 171 and the fixed outer support flange 169. It should be noted, however, that the number of conductive straps 173 can vary in different embodiments. In some embodiments, the number of conductive straps 173 is in a range of about 24 to about 80, or in a range of about 36 to about 60, or in a range of about 40 to about 56. In some embodiments, the number of conductive straps 173 is less than 24. In some embodiments, the number of conductive straps 173 is greater than 80. The number of conductive straps 173 can affect the uniformity of process results across the wafer W because the number of conductive straps 173 affects the ground return path of the RF signal near the periphery of the plasma processing region 182. Also, the size of the conductive straps 173 can vary in different embodiments. FIG. 7 illustrates an isometric view of a conductive strap 173, according to some embodiments. The conductive strap 173 has a rectangular prism shape defined by a width (d1), a length (d2), and a thickness (d3).

[0056] 5 also illustrates the azimuthal spacing (d4) between adjacent conductive straps 173 when connected between the connecting outer support flange 171 and the fixed outer support flange 169. In some embodiments, the conductive straps 173 are substantially equally spaced around the circumference of the connecting outer support flange 171 and similarly around the circumference of the fixed outer support flange 169. Thus, in these embodiments, the azimuthal spacing (d4) between adjacent conductive straps 173 around the circumference of the horizontal portion 171B of the L-shaped vertical cross section of the connecting outer support flange 171 depends on the number of conductive straps 173, the width dimension (d1) of the conductive straps 173, and the outer diameter of the horizontal portion 171B of the L-shaped vertical cross section of the connecting outer support flange 171. Similarly, the azimuthal spacing (d4) between adjacent conductive straps 173 around the outer periphery of the horizontal portion 169B of the L-shaped vertical cross-section of the fixed outer support flange 169 depends on the number of conductive straps 173, the width dimension (d1) of the conductive straps 173, and the outer diameter of the horizontal portion 169B of the L-shaped vertical cross-section of the fixed outer support flange 169.

[0057] In some embodiments, the conductive straps 173 are connected to the fixed outer support flange 169 by a clamping force applied by fastening the clamp ring 175 to the top surface 169F of the horizontal portion 169B of the L-shaped cross section of the fixed outer support flange 169. In some embodiments, the clamp ring 175 is bolted to the fixed outer support flange 169. In some embodiments, the bolts fastening the clamp ring 175 to the fixed outer support flange 169 are disposed at a location between the conductive straps 173. However, in some embodiments, the bolt or bolts fastening the clamp ring 175 to the fixed outer support flange 169 may be disposed to extend through the conductive straps 173. In some embodiments, the clamp ring 175 is formed of the same material as the fixed outer support flange 169. However, in other embodiments, the clamp ring 175 and the fixed outer support flange 169 may be formed of different materials.

[0058] In some embodiments, as shown in FIG. 4A , the conductive straps 173 are connected to the connecting outer support flange 171 by a clamping force applied by fastening a clamp ring 177 to a bottom surface 171D of the horizontal portion 171B of the L-shaped cross section of the connecting outer support flange 171. Alternatively, in some embodiments, a first end of each of the plurality of conductive straps 173 is connected to a top surface 171F of the horizontal portion 171B of the connecting outer support flange 171 by a clamp ring 177. In some embodiments, the clamp ring 177 is bolted to the connecting outer support flange 171. In some embodiments, the bolts fastening the clamp ring 177 to the connecting outer support flange 171 are disposed at a position between the conductive straps 173. However, in some embodiments, the bolt or bolts fastening the clamp ring 177 to the connecting outer support flange 171 may be disposed to extend through the conductive straps 173. In some embodiments, the clamp ring 177 is formed of the same material as the connecting outer support flange 171. However, in other embodiments, the clamp ring 177 and the associated outer support flange 171 may be formed from different materials.

[0059] A set of support rods 201 are disposed around the cantilever arm assembly 115 and extend vertically through the horizontal portion 169B of the L-shaped section of the fixed outer support flange 169. The upper ends of the support rods 201 are configured to engage with the bottom surface 171D of the horizontal portion 171B of the L-shaped section of the connecting outer support flange 171. In some embodiments, the lower ends of each of the support rods 201 are engaged with a resistance mechanism 203. The resistance mechanism 203 is configured to provide an upward force to the corresponding support rod 201, which resists downward movement of the support rod 201 while allowing some downward movement of the support rod 201. In some embodiments, the resistance mechanism 203 includes a spring for providing an upward force to the corresponding support rod 201. In some embodiments, the resistance mechanism 203 includes a material, such as, for example, a spring and / or rubber, having a spring constant sufficient to provide an upward force to the corresponding support rod 201. It should be noted that as the interlocking outer support flange 171 moves downward to engage the set of support rods 201, the set of support rods 201 and corresponding resistance mechanisms 203 exert an upward force on the interlocking outer support flange 171. In some embodiments, the set of support rods 201 includes three support rods 201 and corresponding resistance mechanisms 203. In some embodiments, the support rods 201 are positioned to have substantially equal azimuthal spacing relative to the vertical centerline of the electrode 109. However, in other embodiments, the support rods 201 are positioned to have unequal azimuthal spacing relative to the vertical centerline of the electrode 109. Also, in some embodiments, more than three support rods 201 and corresponding resistance mechanisms 203 are provided to support the interlocking outer support flange 171.

[0060] 1A, the plasma processing system 100 further includes a C-shroud member 185 disposed above the electrode 109. The C-shroud member 185 is configured to interface with the associated outer support flange 171. Specifically, a seal 179 is disposed on the top surface 171E of the horizontal portion 171B of the L-shaped cross section of the associated outer support flange 171 such that the seal 179 is engaged by the C-shroud member 185 when the associated outer support flange 171 moves upward toward the C-shroud member 185. In some embodiments, the seal 179 is electrically conductive to facilitate establishing electrical conduction between the C-shroud member 185 and the associated outer support flange 171. In some embodiments, the C-shroud member 185 is formed of polysilicon. However, in other embodiments, the C-shroud member 185 is formed of another type of electrically conductive material that is chemically compatible with processes to be performed in the plasma processing region 182 and has sufficient mechanical strength.

[0061] The C-shroud is configured to extend around the plasma processing region 182, radially extending the extent of the plasma processing region 182 into an area defined within the C-shroud member 185. The C-shroud member 185 includes a bottom wall 185A, an outer vertical wall 185B, and an upper wall 185C. In some embodiments, the outer vertical wall 185B and the upper wall 185C of the C-shroud member 185 are solid, non-perforated members, and the bottom wall 185A of the C-shroud member 185 includes a number of vents 186 that channel process gases from within the plasma processing region 182. In some embodiments, a throttle member 196 is disposed below the vents 186 of the C-shroud member 185 to control the flow of process gases through the vents 186. More specifically, in some embodiments, the throttle member 196 is configured to move vertically up and down in the z-direction relative to the C-shroud member 185 to control the flow of process gas through the vents 186. In some embodiments, the throttle member 196 is configured to engage and / or enter the vents 186.

[0062] The top wall 185C of the C-shroud member 185 is configured to support the top electrodes 187A / 187B. In some embodiments, the top electrodes 187A / 187B include an inner top electrode 187A and an outer top electrode 187B. Alternatively, in some embodiments, the inner top electrode 187A is present but the outer top electrode 187B is not present, with the inner top electrode 187A extending radially to the location that the outer top electrode 187B should occupy. In some embodiments, the inner top electrode 187A is formed of single crystal silicon and the outer top electrode 187B is formed of polysilicon. However, in other embodiments, the inner top electrode 187A and the outer top electrode 187B may be formed of other materials that are structurally, chemically, electrically, and mechanically compatible with the processes performed in the plasma processing region 182. The inner top electrode 187A includes a number of through ports 197, defined as holes that extend through the entire vertical thickness of the inner top electrode 187A. Through ports 197 are distributed throughout the inner upper electrode 187A relative to the xy plane and provide a flow of process gas from the plenum region 188 above the upper electrodes 187A / 187B to the plasma processing region 182 below the upper electrodes 187A / 187B.

[0063] 8A illustrates a vertical cross-sectional view of the top electrodes 187A / 187B according to some embodiments. In some embodiments, the inner top electrode 187A includes a plate 211 formed of a semiconductor material, such as single crystal silicon. In some embodiments, a highly conductive layer 213 is formed on the top surface of the plate 211 and is integral with the plate 211. The highly conductive layer 213 has a lower electrical resistance than the semiconductor material of the plate 211. Each through port 197 extends through the entire thickness of the inner top electrode 187A from the top surface 215 of the inner top electrode 187A to the bottom surface 217 of the inner top electrode 187A. As previously described, the inner top electrode 187A is configured to physically separate the process gas plenum region 188 from the plasma processing region 182 and provide a flow of process gas from the process gas plenum region 188 to the plasma processing region 182 through a distribution of the through ports 197.

[0064] FIG. 8B illustrates a top view of the upper electrodes 187A / 187B, according to some embodiments. FIG. 8B illustrates an example distribution of through ports 197 across the inner upper electrode 187A. It should be noted that the distribution of through ports 197 across the inner upper electrode 187A may be configured differently in other embodiments. For example, the total number of through ports 197 in the inner upper electrode 187A and / or the spatial distribution of through ports 197 in the inner upper electrode 187A may vary in other embodiments. The diameter of the through ports 197 may also vary in other embodiments. In general, it is important to reduce the diameter of the through ports 197 to a size small enough to prevent the ingress of plasma 180 from the plasma processing region 182 into the through ports 197. In some embodiments, if the diameter of the through ports 197 is reduced, the total number of through ports 197 in the inner upper electrode 187A is increased to maintain a predetermined total flow rate of process gas from the process gas plenum region 188 through the inner upper electrode 187A to the plasma processing region 182. Also, in some embodiments, the top electrodes 187A / 187B are electrically connected to a reference ground potential, but in other embodiments, the inner top electrode 187A and / or the outer top electrode 187B are electrically connected to either a respective direct current (DC) power source or a respective RF power source by corresponding impedance matching circuits.

[0065] 1A, the plenum region 188 is defined by a top member 189. One or more gas supply ports 192 are formed through the chamber 101 and the top member 189 and are in fluid communication with the plenum region 188. The one or more gas supply ports 192 are fluidly connected (plumbed) to a process gas supply system 191. The process gas supply system 191 may include, for example, one or more process gas sources, one or more mass flow controllers, one or more flow control valves or other devices, and provides a controlled flow of one or more process gases through the one or more gas supply ports 192 to the plenum region 188, as indicated by arrows 193. In some embodiments, the process gas supply system 191 also includes one or more components for controlling the temperature of the process gas. The process gas supply system 191 is connected to the control system 120 via one or more signal conductors 194.

[0066] The process gap (g1) is defined as the vertical (z-direction) distance measured between the top surface of the ceramic layer 110 and the bottom surface of the inner upper electrode 187A. The size of the process gap (g1) can be adjusted by moving the cantilever arm assembly 115 in the vertical (z-direction). As the cantilever arm assembly 115 moves upward, the linked outer support flange 171 eventually engages the bottom wall 185A of the C-shroud member 185, at which point the linked outer support flange 171 moves along the fixed outer support flange 169 as the cantilever arm assembly 115 continues to move upward until the set of support rods 201 engages the linked outer support flange 171, achieving a predetermined process gap (g1) size. Then, to reverse this movement to remove the wafer W from the chamber, the cantilever arm assembly 115 moves downward until the linked outer support flange 171 clears the bottom wall 185A of the C-shroud member 185. FIG 1B illustrates the system 100 of FIG 1A with the cantilever arm assembly 115 moved downward to allow movement of the wafer W through the door 107, according to some embodiments. In various embodiments, the size of the process gap (g1) during plasma processing of the wafer W is controlled to a range of up to about 10 centimeters, up to about 8 centimeters, or up to about 5 centimeters. Also in FIG 1B, the wafer W is shown in an elevated position by lift pins 133. Note that FIG 1A illustrates the system 100 in a closed configuration with the wafer W positioned on the ceramic layer 110 for plasma processing.

[0067] During plasma processing operations in the plasma processing system 100, one or more process gases are supplied to the plasma processing region 182 via the process gas supply system 191, the plenum region 188, and the through port 197 in the inner upper electrode 187A. RF signals are also transmitted into the plasma processing region 182 by the first and second RF signal generators 147, 149, the impedance match system 143, the RF signal supply rod 137, the RF signal supply shaft 141, the facility plate 111, the electrode 109, and through the ceramic layer 110. The RF signals convert the process gases into a plasma 180 in the plasma processing region 182. The ions and / or reactive components of the plasma interact with one or more materials on the wafer W to change the composition and / or shape of certain materials present on the wafer W. Exhaust gases from the plasma processing region 182 are influenced by the suction force applied to the exhaust port 105 as shown by arrows 195 and flow through vents 186 in the C-shroud member 185 and through the interior region 103 within the chamber 101 to the exhaust port 105.

[0068] In various embodiments, the electrode 109 can be configured to have different diameters. However, in some embodiments, the diameter of the electrode 109 is extended to increase the surface of the electrode 109 upon which the edge ring 167 rests. In some embodiments, the conductive gel 226 is disposed between the bottom of the edge ring 167 and the top of the electrode 109 and / or between the bottom of the edge ring 167 and the top of the bonding ring 161. In these embodiments, the diameter of the electrode 109 is extended to increase the surface area of ​​the conductive gel disposed between the edge ring 167 and the electrode 109.

[0069] It should be noted that the combination of the coupled outer support flange 171, the conductive straps 173, and the fixed outer support flange 169 are electrically at a reference ground potential, and collectively they form a ground return path for the RF signal transmitted from the electrode 109 through the ceramic layer 110 to the plasma processing region 182. The azimuthal uniformity of this ground return path around the periphery of the electrode 109 may affect the uniformity of the process results on the wafer W. For example, in some embodiments, the etch rate uniformity across the wafer W may be affected by the azimuthal uniformity of the ground return path around the periphery of the electrode 109. It should be noted, therefore, that the number, configuration, and placement of the conductive straps 173 around the periphery of the electrode 109 may affect the uniformity of the process results across the wafer W.

[0070] 1A, a variable edge sheath (TES) system is implemented including a TES electrode 415 disposed (embedded) within the coupling ring 161. The TES system also includes a number of TES RF signal supply pins 413 physically and electrically connected to the TES electrode 415. Each of the TES RF signal supply pins 413 extends through a corresponding insulator feedthrough member 421 configured to electrically isolate the TES RF signal supply pins 413 from surrounding structures, such as the ceramic support 113 and the cantilever arm assembly 115 structures. In some embodiments, the O-rings 417 and 419 are positioned such that an area within the insulator feedthrough member 421 is not exposed to any material / gas present within the plasma processing region 182. In some embodiments, the TES RF signal supply pins 413 are formed of, for example, copper, aluminum, anodized aluminum, or the like.

[0071] The TES RF signal supply pins 413 extend into the open area 118 inside the cantilever arm assembly 115, and each of the TES RF signal supply pins 413 is electrically connected to the TES RF signal supply lead 409 through a corresponding TES RF signal filter 411. In some embodiments, three TES RF signal supply pins 413 are positioned to physically and electrically connect to the TES electrode 415 at substantially equally spaced azimuth positions about the centerline of the electrode 109. However, other embodiments may have more than three TES RF signal supply pins 413 physically and electrically connected to the TES electrode 415. Also, some embodiments may have one or two TES RF signal supply pins 413 physically and electrically connected to the TES electrode 415. Each of the TES RF signal supply pins 413 is electrically connected to a corresponding TES RF signal filter 411, and each of the TES RF signal filters 411 is electrically connected to the TES RF signal supply lead 409. In some embodiments, each TES RF signal filter 411 is configured as an inductor. For example, in some embodiments, each TES RF signal filter 411 is configured as a coiled conductor, such as a metal coil wrapped around a dielectric core structure. In various embodiments, the metal coil may be formed, for example, of a solid copper rod, a copper tube, an aluminum rod, or an aluminum tube. Also, in some embodiments, each TES RF signal filter 411 may be configured as a combination of inductive and capacitive structures. With a view to improving uniformity of plasma processing results across the wafer W, each of the TES RF signal filters 411 has substantially the same configuration.

[0072] In some embodiments, the TES RF signal feed lead 409 is formed in a ring-like (annular) structure so as to extend to the interior of the cantilever arm assembly 115 near the open region 118, allowing physical and electrical connection between the azimuthally distributed TES RF signal filters 411 and the TES RF signal feed lead 409. In some embodiments, the TES RF signal feed lead 409 is formed in a solid (non-tubular) structure. Alternatively, in some embodiments, the TES RF signal feed lead 409 is formed in a tubular structure. In some embodiments, the TES RF signal feed lead 409 is formed of, for example, copper, aluminum, anodized aluminum, etc.

[0073] The TES RF signal feed lead 409 is electrically connected to the TES RF feed cable 407. A capacitor 408 is connected between the TES RF signal feed lead 409 and a reference ground potential, for example as in the structure of the cantilever arm assembly 115. More specifically, the capacitor 408 has a first terminal electrically connected to both the TES RF feed cable 407 and the TES RF signal feed lead 409, and the capacitor 408 has a second terminal electrically connected to the reference ground potential. In some embodiments, the capacitor 408 is a variable capacitor. In some embodiments, the capacitor 408 is a fixed capacitor. In some embodiments, the capacitor 408 is set to have a capacitance in the range of about 10 picofarads to about 100 picofarads. The TES RF feed cable 407 is connected to the TES impedance matching system 401. The TES impedance matching system 401 is connected to the TES RF signal generator 403. The RF signal generated by the TES RF signal generator 403 is transmitted through the TES impedance matching system 401 to the TES RF feed cable 407, then to the TES RF signal feed lead 409, through the TES RF signal filter 411 to the respective TES RF signal feed pin 413, and to the TES electrode 415 in the coupling ring 161. In some embodiments, the TES RF signal generator 403 is configured and operative to generate an RF signal within a frequency range of about 50 kilohertz to about 27 MHz. In some embodiments, the TES RF signal generator 403 provides RF power within a range of about 50 watts to about 10 kilowatts. The TES RF signal generator 403 is also connected to the control system 120 via one or more signal leads 405.

[0074] The TES impedance matching system 401 includes an arrangement of inductors and capacitors sized and connected to enable impedance matching so that RF power can be transmitted from the RF signal generator 403 along the TES RF feed cable 407, the TES RF signal feed conductors 409, through the TES RF signal filter 411, and through the TES RF signal feed pins 413 to the TES electrode 415 in the coupling ring 161 and into the plasma processing region 182 above the edge ring 167. FIG. 3B illustrates an example electrical schematic of the TES impedance matching system 401, according to some embodiments. The TES impedance matching system 401 includes an input line 321 electrically connected to the TES RF signal generator 403. The TES input line 321 is electrically connected to an input terminal of the first inductor 322. The output terminal of the first inductor 322 is electrically connected to the internal node 328. The second inductor 324 has an input terminal electrically connected to the internal node 328. The output terminal of the second inductor 324 is electrically connected to the second internal node 329. The first capacitor 326 has an input terminal electrically connected to the second internal node 329. The output terminal of the first capacitor 326 is electrically connected to the input terminal of the third inductor 327. The output terminal of the third inductor 327 is electrically connected to the TES RF supply cable 407. The input terminal of the second capacitor 323 is electrically connected to the first internal node 328. The output terminal of the second capacitor 323 is electrically connected to the reference ground potential. In some embodiments, the second capacitor 323 is a variable capacitor. The input terminal of the third capacitor 325 is electrically connected to the second internal node 329. The output terminal of the third capacitor 325 is electrically connected to the reference ground potential. It is noted that the electrical configuration of the TES impedance matching system 401 as shown in FIG. 3B is shown as an example. In other embodiments, the TES impedance matching system 401 may have a different inductor and / or capacitor configuration than the example shown in FIG. 3B. The TES impedance matching system 401 is also connected to the control system 120 via one or more signal conductors 404 .

[0075] By transmitting an RF signal / power through the TES electrode 415 disposed (embedded) in the coupling ring 161, the TES system can control the characteristics of the plasma 180 near the periphery of the wafer W. For example, in some embodiments, the TES system operates to control the plasma 180 sheath characteristics near the edge ring 167, such as by controlling the shape and / or size (either increasing or decreasing the sheath thickness) of the plasma 180 sheath. Also, in some embodiments, by controlling the shape of the plasma 180 sheath near the edge ring 167, various characteristics of the bulk plasma 180 above the wafer W can be controlled. Also, in some embodiments, the TES system operates to control the density of the plasma 180 near the edge ring 167. For example, in some embodiments, the TES system operates to increase or decrease the density of the plasma 180 near the edge ring 167. Also, in some embodiments, the TES system operates to control a bias voltage present on the edge ring 167, thereby controlling or influencing the movement of ions and other charged components in the plasma 180 near the edge ring 167. For example, in some embodiments, the TES system operates to control a bias voltage present on the edge ring 167 to attract more ions from the plasma 180 toward the edge of the wafer W. Additionally, in some embodiments, the TES system operates to control a bias voltage present on the edge ring 167 to repel ions from the plasma 180 away from the edge of the wafer W. It is noted that the TES system can be operated to perform a variety of different functions, either separately or in combination, as specifically described above.

[0076] 9A illustrates a vertical cross-sectional close-up view of a connection between coupling ring 161 and edge ring 167, according to some embodiments. In some embodiments, coupling ring 161 is formed of a dielectric material, such as, for example, quartz, ceramic, alumina (Al2O3), or a polymer.

[0077] The bottom surface of the edge ring 167 has a portion P1 that is coupled to the top surface of the coupling ring 161 through a layer of thermally conductive gel 903 to thermally sink the coupling ring 161 into the edge ring 167. The bottom surface of the edge ring 167 also has another portion P2 that is coupled to the top surface of the electrode 109 through a layer of thermally conductive gel 905. Examples of thermally conductive gels 903, 905 include polyimide, polyketone, polyetherketone, polyethersulfone, polyethylene terephthalate, fluoroethylene propylene copolymer, cellulose, triacetate, silicone, and the like. In some embodiments, the thermally conductive gels 903, 905 are formed as double-sided tape. In some embodiments, the edge ring 167 has an inner diameter sized to be close to the outer diameter of the ceramic layer 110.

[0078] The edge ring 167 is secured to the coupling ring 161 by a number of fasteners 901 distributed azimuthally around the edge ring 167. In some embodiments, a threaded hole is formed in the edge ring 167 to receive each fastener 901. In some embodiments, a threaded insert is disposed in the edge ring 167 to receive each fastener 901. For example, the threaded insert may be configured as a tubular sleeve having a threaded inner wall surface to receive the threads of the fastener 901, the tubular sleeve of the threaded insert having an outer wall surface that is secured (mechanically and / or chemically) to a corresponding hole formed in the edge ring 167. Also, the coupling ring 161 is formed with holes for inserting the fasteners 901. In some embodiments, the fasteners 901 are formed of a metal, such as, for example, steel, aluminum, an alloy of steel, or an alloy of aluminum. Alternatively, in some embodiments, the fasteners 901 are formed of a plastic. In some embodiments, the holes formed in the coupling ring 161 into which the fasteners 901 are disposed are formed to precisely correspond to the size of the fasteners 901. In some embodiments, the holes formed in edge ring 167 to receive fasteners 901 are drilled to a depth such that when fasteners 901 are fully seated in the holes, there is a vertical space 907 (measured in the z-direction) between the ends of fasteners 901 and the portions of edge ring 167 that overlie them. Vertical space 907 is sized to prevent arcing within space 907. Also, in some embodiments, the heads of fasteners 901 are countersunk within coupling ring 161.

[0079] In various embodiments, the TES electrode 415 is formed of a conductive material such as, for example, platinum, steel, aluminum, or copper. During operation, capacitive coupling occurs between the TES electrode 415 and the edge ring 167, thereby powering the edge ring 167 and influencing the processing of the wafer W near the periphery of the wafer W.

[0080] In some embodiments, multiple hold-down rods 911 are used to secure the coupling ring 161 to the ceramic support 113. FIG. 9B shows a vertical cross-sectional close-up of a hold-down rod 911 connected to the coupling ring 161 according to some embodiments. The hold-down rod 911 extends through a hole formed in the ceramic support 113 and is secured within a receptacle formed in the coupling ring 161. In some embodiments, the receptacle formed in the coupling ring 161 for the hold-down rod 911 has a threaded wall formed to engage with a thread present on the end of the hold-down rod 911. In some embodiments, a threaded insert is disposed within the coupling ring 161 to receive a corresponding threaded end of the hold-down rod 911. The hold-down rod 911 is secured to a hold-down control mechanism 913 disposed within a mounting structure 915 within the open area 118 in the cantilever arm assembly 115. The mounting structure 915 is secured to the cantilever arm assembly 115. In some embodiments, an O-ring 917 is disposed between the mounting structure 915 and the ceramic support 113 such that the atmospheric environment in the open region 118 in the cantilever arm assembly 115 is kept separated from the plasma processing region 182 (and vice versa).

[0081] In some embodiments, the hold-down control mechanism 913 is configured and operated to pull the coupling ring 161 downward toward the ceramic support 113 such that any seals (O-rings) disposed between the coupling ring 161 and the ceramic support and / or between the edge ring 167 and the coupling ring 161 are fully engaged. In some embodiments, the hold-down control mechanism 913 uses air pressure to pull the coupling ring 161 downward toward the ceramic support 113. In other embodiments, the hold-down control mechanism 913 uses an electromechanically generated and applied force to pull the coupling ring 161 downward toward the ceramic support 113. In some embodiments, three hold-down rods 911 are connected to the coupling ring 161 at substantially equally spaced azimuthal positions around the circumference of the coupling ring 161. However, in other embodiments, more than three hold-down rods 911 are connected to the coupling ring 161. Also, in various embodiments, a plurality of hold-down rods 911 connected to the coupling ring 161 are disposed at substantially equally or non-equally spaced azimuthal positions around the circumference within the coupling ring 161. In some embodiments, the hold-down rods 911 are formed of a rigid material that is not electrically conductive, such as, for example, plastic.

[0082] FIG. 9C illustrates a top perspective view of the coupling ring 161, according to some embodiments. In the exemplary embodiment of FIG. 9C, three hold-down rods 911A, 911B, 911C are connected to the coupling ring 161 at locations L1, L2, and L3, respectively. In some embodiments, locations L1, L2, and L3 are vertices of an equilateral triangle that is coplanar with the bottom surface of the coupling ring 161. The exemplary embodiment of FIG. 9C also illustrates three TES RF signal supply pins 413A, 413B, and 413C that are connected to the coupling ring 161 at locations L4, L5, and L6, respectively. In some embodiments, locations L4, L5, and L6 are vertices of an equilateral triangle that is coplanar with the bottom surface of the coupling ring 161. The exemplary embodiment of FIG. 9C also illustrates a temperature probe feed-through sleeve 919 that is connected to the bottom surface of the coupling ring 161. The temperature probe feedthrough sleeve 919 extends through a hole formed in the ceramic support 113 and provides a channel into which a temperature probe is inserted to measure the temperature of the coupling ring 161 and / or the edge ring 167. The exemplary embodiment of FIG. 9C also shows a number of holes 921 formed through the coupling ring 161 into which fasteners 901 are positioned to secure the coupling ring 161 to the edge ring 167.

[0083] FIG. 10A illustrates a bottom perspective view of a portion of a TES system 1000 disposed within a cantilever arm assembly 115, according to some embodiments. The TES RF feed cable 407 is electrically connected to a capacitor 408. The TES RF feed cable 407 is also electrically connected to a TES RF signal feed lead 409 by a conductive strap 1001. The TES RF signal filter 411A has an input terminal electrically connected to the TES RF signal feed lead 409. The TES RF signal filter 411A has an output terminal electrically connected to a TES RF signal feed pin 413A. The TES RF signal filter 411B has an input terminal electrically connected to the TES RF signal feed lead 409 by a conductive strap 1001. The TES RF signal filter 411B has an output terminal electrically connected to the TES RF signal feed lead 409 by a conductive strap 1001. The TES RF signal filter 411B has an output terminal electrically connected to the TES RF signal feed pin 413B. The TES RF signal filter 411C has an input terminal electrically connected to the TES RF signal feed lead 409. The TES RF signal filter 411C has an output terminal electrically connected to the TES RF signal supply pin 413C. Each of the TES RF signal supply pins 413A, 413B, 413C is electrically connected to the TES RF signal supply conductor 409 via a corresponding TES RF signal filter 411A, 411B, 411C. In this manner, each of the TES RF signal supply pins 413A, 413B, 413C includes a corresponding TES RF signal filter 411A, 411B, 411C, thereby blocking a high-frequency RF signal, such as a 60 MHz signal, that attempts to be coupled to the TES system 1000 via the TES RF signal supply pins 413A, 413B, 413C.

[0084] FIG. 10B illustrates a bottom perspective view of the TES system 1000 as shown in FIG. 10A with the TES RF signal filters 411A, 411B, 411C each configured as a conductive coil, according to some embodiments. In some embodiments, substantially similarly configured conductive coils are used for each of the TES RF signal filters 411A, 411B, 411C. In some embodiments, each of the conductive coils forming the TES RF signal filters 411A, 411B, 411C has a substantially same inductance value. In some embodiments, each of the conductive coils forming the TES RF signal filters 411A, 411B, 411C has an inductance value in the range of about 1 microhenry to about 5 microhenry. Note that each of the TES RF signal supply pins 413A, 413B, 413C is directly electrically connected to a corresponding one of the TES RF signal filters 411A, 411B, 411C, respectively. In some embodiments, no other electrical components are connected between each of the TES RF signal supply pins 413A, 413B, 413C and their respective corresponding TES RF signal filters 411A, 411B, 411C. Furthermore, each of the TES RF signal supply pins 413A, 413B, and 413C is not directly connected to either the TES RF supply cable 407 or the TES RF signal supply conductor 409, but is electrically connected to the TES RF supply cable 407 and / or the TES RF signal supply conductor 409 via its respective corresponding TES RF signal filter 411A, 411B, and 411C. In this manner, high frequency RF signals (e.g., 60 MHz signals) reaching TES RF signal supply pins 413A, 413B, and 413C from within plasma processing region 182 are substantially blocked by TES RF signal filters 411A, 411B, and 411C, respectively, thereby preventing these signals from reaching either TES RF supply cable 407 or TES RF signal supply conductor 409.

[0085] 11 illustrates a bottom perspective view of an alternative TES system 1100 that uses a single TES RF signal filter 1108 for all TES RF signal supply pins 413A, 413B, and 413C, according to some embodiments. In the alternative TES system 1100, the TES RF supply cable 407 is electrically connected to a first terminal of a capacitor 408. The first terminal of the single TES RF signal filter 1108 is also electrically connected to the first terminal of the capacitor 408. The second terminal of the capacitor 408 is also electrically connected to a reference ground potential. The second terminal of the single TES RF signal filter 1108 is electrically connected to the TES spider structure 1102 at location 1110. The TES spider structure 1102 includes a ring portion 1102D and three legs 1102A, 1102B, and 1102C that extend from the ring portion 1102D to the locations of the TES RF signal supply pins 413A, 413B, and 413C, respectively. The three legs 1102A, 1102B, and 1102C of the TES spider structure 1102 are electrically connected to corresponding ones of the TES RF signal supply pins 413A, 413B, and 413C, as shown at locations 1112A, 1112B, and 1112C, respectively. The TES spider structure 1102 is formed of a conductive material, such as aluminum, stainless steel, an alloy of aluminum, an alloy of steel, or copper.

[0086] Unlike the TES system 1000 of Figures 1A, 1B, 3B, 9A, 9B, 9C, 10A, and 10B, the alternative TES system 1100 of Figure 11 has the TES RF signal supply pins 413A, 413B, and 413C electrically connected directly to the TES spider structure 1102, rather than being directly and exclusively electrically connected to the corresponding TES RF signal filters 411A, 411B, and 411C, respectively. Thus, in the alternative TES system 1100 of Figure 11, high frequency signals (e.g., 60 MHz signals) arriving at the TES RF signal supply pins 413A, 413B, 413C from within the plasma processing region 182 are able to circulate within and around the TES spider structure 1102 without being blocked by the single TES RF signal filter 1108. However, the single TES RF signal filter 1108 is effective to prevent high frequency signals from reaching the TES RF supply cable 407. In some embodiments, high frequency signals coupling into the TES RF signal supply pins 413A, 413B, and 413C and circulating in and around the TES spider structure 1102 can undesirably affect the uniformity of plasma processing results across the wafer W.

[0087] The TES system 1000 described with respect to FIGS. 1A, 1B, 3B, 9A, 9B, 9C, 10A, and 10B provides better azimuthal uniformity of plasma processing results across the wafer W compared to the TES system 1100 described with respect to FIG. 11. As an example, FIG. 12A illustrates a wafer map of plasma processing results across the wafer W obtained using the TES system 1100 of FIG. 11 according to some embodiments. The plasma processing results of FIG. 12A were obtained by performing a prescribed etch plasma process on a test wafer having a blank oxide film deposited thereover. The wafer map of FIG. 12A illustrates the thickness of material (e.g., layer, film, etc.) removed from the wafer W after the prescribed etch plasma process on the test wafer is completed. The wafer map of FIG. 12A illustrates the uniformity characteristics of the process results across the wafer W using a color scale or gray scale.

[0088] In general, a set of data measurement points z i is the position (x i , y i ) and the area of ​​the wafer W is x 2 +y 2 <=R 2 where R is the radius of the wafer W. Each data measurement point z i represents a corresponding portion of the total area of ​​the wafer W. In some embodiments, various points z i Coordinates (x i , y i ) for each point z i are selected to represent substantially equal portions of the entire area of ​​the wafer W. Note, however, that the various points z i The measured data values ​​at various points z are used to calculate the wafer-level metrics. i The wafer-level uniformity criterion shown in FIG. 12A is a weighted uniformity criterion for all points z across the wafer W. i The average film thickness based on measurements taken at all points z across the wafer W i The three standard deviation (3σ) values ​​of the film thickness based on measurements taken at all points z across the wafer W i and a calculation of the film thickness variation across the wafer W based on the measurements taken in 2. The three standard deviation (3σ) value of the film thickness across the wafer W is sometimes referred to as the within-wafer non-uniformity (WIWNU) criterion.

[0089] As shown in Figure 12A, a significantly higher non-uniformity in plasma processing results exists in the azimuthal region near where the TES RF signal supply pin 413 connects to the TES electrode 415 in the coupling ring 161. Figure 12A also shows that the non-uniformity of plasma processing results throughout the volume of the wafer W correlates significantly to the peripheral azimuthal region of higher non-uniformity of plasma processing results that exists where the TES RF signal supply pin 413 connects to the TES electrode 415 in the coupling ring 161. The significantly higher non-uniformity of plasma processing results on the wafer W near where the TES RF signal supply pin 413 connects to the TES electrode 415 in the coupling ring 161 is caused by the high frequency RF signal (60 MHz) transmitted from the electrode 109 to the plasma processing region 182 (from the first RF signal generator 147) via the coupling of the TES electrode 415 to the TES spider structure 1102. A single TES RF signal filter 1108 in the TES system 1100 cannot prevent high frequency RF signals (60 MHz) from coupling into the TES spider structure 1102 in the TES system 1100.

[0090] In contrast to the TES system 1100, the TES system 1000, having separate TES RF signal filters 411A, 411B, 411C electrically connected directly and exclusively to each TES RF signal supply pin 413A, 413B, 413C, respectively, provides a high impedance at each TES RF signal supply pin 413 to block the coupling into the TES system 1000 of the much higher radio frequency RF signal used to generate the plasma 180 in the plasma processing region 182. The radio frequency RF signal used to generate the plasma 180 in the plasma processing region 182 is a signal having one or more frequencies in the range of about 1 megahertz to about 100 megahertz, such as 60 megahertz. Thus, the radio frequency RF signal arriving at the TES RF signal supply pins 413A, 413B, 413C cannot circulate in or around the TES RF signal supply lead 409 in the TES system 1000.

[0091] FIG. 12B illustrates a wafer map of plasma processing results across a wafer W obtained using the TES system 1000 of FIGS. 1A, 1B, 3B, 9A, 9B, 9C, 10A, and 10B, according to some embodiments. The plasma processing results of FIG. 12B were obtained by performing a predetermined etch plasma process (the same as was performed to obtain the results of FIG. 12A) on a test wafer having a blank oxide film deposited thereover using the TES system 1100. Thus, the plasma processing results of FIG. 12B are directly comparable to the plasma processing results of FIG. 12A, i.e., the TES apparatus 1000 and the TES apparatus 1100 can be directly compared. As shown in FIG. 12B, by having separate TES RF signal filters 411A, 411B, 411C electrically connected directly and exclusively to each TES RF signal supply pin 413A, 413B, 413C, respectively, there are no noticeable azimuthal non-uniformities in the plasma processing results near the locations where the TES RF signal supply pins 413A, 413B, 413C electrically and physically connect to the TES electrode 415 within the coupling ring 161.

[0092] As a further comparison, Figure 12C shows a wafer map of plasma processing results across a wafer W obtained with the TES RF signal supply pins 413A, 413B, and 413C disconnected from their corresponding TES RF signal filters 411A, 411B, and 411C, respectively, according to some embodiments. The plasma processing results in Figure 12C were obtained by performing a predetermined etch plasma process (the same as was performed to obtain the results in Figures 12A and 12B) on a test wafer that had a blank oxide film deposited across it. Thus, Figure 12C essentially represents plasma processing results across a wafer W without either the TES system 1000 or the TES system 1100 connected. 12C with the results shown in FIGS. 12A and 12B indicates that the uniformity of plasma processing results across the wafer W obtained using TES system 1000 with separate TES RF signal filters 411A, 411B, and 411C connected exclusively and directly to TES RF signal supply pins 413A, 413B, and 413C, respectively, is comparable to that obtained without TES system 1000. Thus, it can be seen that having separate TES RF signal filters 411A, 411B, and 411C connected directly and exclusively to TES RF signal supply pins 413A, 413B, and 413C, respectively, effectively blocks the coupling of high frequency RF signals from plasma 180 to TES system 1000.

[0093] FIG. 13A illustrates a perspective view of edge ring 167 according to some embodiments. Edge ring 167 has a top surface 167A and a bottom surface 167B. As described with respect to FIG. 9A, a plurality of holes 167C are formed through bottom surface 167B to receive fasteners 901. Note that the plurality of holes 167C do not reach top surface 167A of edge ring 167. Note that while three holes 167C are shown in the example of FIG. 13A, in other embodiments, the number of holes 167C for receiving fasteners 901 may be more than three, such as six or nine. In some embodiments, edge ring 167 is a consumable component, such that after a certain number of plasma processing operations are performed in plasma processing system 100, material of edge ring 167 may be lost due to plasma induced erosion, effectively wearing away. Thus, edge ring 167 is a replaceable component within plasma processing system 100.

[0094] 13B illustrates a top view of edge ring 167, according to some embodiments. Edge ring 167 has an inner diameter ID1 and an outer diameter OD1. Inner diameter ID1 corresponds to the diameter of the inner periphery of edge ring 167, and outer diameter OD1 is the diameter of the outer periphery of edge ring 167. In various embodiments, the size of inner diameter ID1 is determined by the diameter of ceramic layer 110 such that the inner periphery of edge ring 167 is proximate to the outer periphery of ceramic layer 110.

[0095] 13C illustrates a vertical cross-sectional view of the edge ring 167 shown at (section line) AA in FIG. 13B, according to some embodiments. The edge ring 167 has an inner surface 167D that resides on the inner periphery of the edge ring 167. The edge ring 167 also has an outer surface 167E that resides on the outer periphery of the edge ring 167. In some embodiments, when the edge ring 167 is disposed in the plasma processing system 100, each of the top surface 167A and the bottom surface 167B of the edge ring 167 has a horizontal orientation (orientation substantially parallel to the xy plane), and each of the inner surface 167D and the outer surface 167E has a vertical orientation (orientation substantially parallel to the z direction). It should be noted that the edge ring 167 has an annular shape, which may also be referred to as, for example, a ring shape or a dish shape.

[0096] The edge ring 228 has a step portion 1622 that has an inclined inner surface 1606 and a horizontally facing inner surface 1608. The inclined inner surface 1606 is at an angle A2 with respect to the vertically facing inner surface 167D. 1606 is continuous with top surface 167A. In some embodiments, the edge between inclined inner surface 1606 and top surface 167A is formed with a radius R3. Horizontally facing inner surface 1608 is continuous with inclined inner surface 1606. In some embodiments, the edge between horizontally facing inner surface 1608 and inclined inner surface 1606 is formed with a radius R4. The edge between horizontally facing inner surface 1608 and inclined inner surface 1606 is disposed according to a mid-diameter (MD) that is concentric with inner diameter ID1 and outer diameter OD1. Inner surface 167D is continuous with horizontally facing inner surface 1608. In some embodiments, the edge between inner surface 167D and horizontally facing inner surface 1608 is formed with a radius R5.

[0097] Inner surface 167D is continuous with beveled inner surface 1618. In some embodiments, the edge between inner surface 167D and beveled inner surface 1618 is formed to have a radius R6. Beveled inner surface 1618 is continuous with bottom surface 167B. In some embodiments, the edge between beveled inner surface 1618 and bottom surface 167B is formed to have a radius R7. In some embodiments, radius R7 has a value that is approximately twice the value of radius R6.

[0098] The outer surface 167E is continuous with the bottom surface 167B. In some embodiments, the edge between the outer surface 167E and the bottom surface 167B is formed with a radius R2. The outer surface 167E is continuous with the top surface 167A. In some embodiments, the edge between the outer surface 167E and the top surface 167A is formed with a radius R1. The curvature of the edge ring 167 with the radius R1 reduces the probability of arcing of RF power between the edge ring 167 and the cover ring 165.

[0099] FIG. 14 illustrates an exemplary schematic diagram of the control system 120 of FIG. 1A according to some embodiments. In some embodiments, the control system 120 is configured as a process controller for controlling a semiconductor manufacturing process performed in the plasma processing system 100. In various embodiments, the control system 120 includes a processor 1401, a storage hardware unit (HU) 1403 (e.g., memory), an input HU 1405, an output HU 1407, an input / output (I / O) interface 1409, an I / O interface 1411, a network interface controller (NIC) 1413, and a data communication bus 1415. The processor 1401, the storage HU 1403, the input HU 1405, the output HU 1407, the I / O interface 1409, the I / O interface 1411, and the NIC 1413 are in data communication with each other via the data communication bus 1415. The input HU 1405 is configured to receive data communication from a number of external devices. Examples of the input HU 1405 include a data acquisition system, a data acquisition card, and the like. The output HU 1407 is configured to transmit data to a number of external devices. An example of the output HU 1407 includes a device controller. An example of the NIC 1413 includes a network interface card, a network adapter, etc. Each of the I / O interfaces 1409 and 1411 is defined to provide compatibility between different hardware units coupled to the I / O interface. For example, the I / O interface 1409 may be defined to convert signals received from the input HU 1405 to a format, amplitude, and / or speed compatible with the data communication bus 1415. Also, the I / O interface 1407 may be defined to convert signals received from the data communication bus 1415 to a format, amplitude, and / or speed compatible with the output HU 1407.Note that although various operations are described herein as being performed by processor 1401 of control system 120, in some embodiments, various operations may be performed by multiple processors of control system 120 and / or by multiple processors of multiple computing systems in data communication with control system 120.

[0100] In some embodiments, the control system 120 is used to control devices in various wafer fabrication systems based in part on the sensed values. For example, the control system 120 can control one or more of the valves 1417, the filter heater 1419, the wafer support structure heater 1421, the pump 1423, and other devices 1425 based on the sensed values ​​and other control parameters. The valves 1417 can include valves associated with controlling the backside gas supply system 129, the process gas supply system 191, and the temperature control fluid circulation system 125. The control system 120 receives sensed values ​​from, for example, a pressure gauge 1427, a flow meter 1429, a temperature sensor 1431, and / or other sensors 1433, such as, for example, voltage sensors, current sensors, etc. The control system 120 can also be used to control process conditions in the plasma processing system 100 while performing plasma processing operations on the wafer W. For example, the control system 120 can control the type and amount of process gas supplied from the process gas supply system 191 to the plasma processing region 182. The control system 120 may also control the operation of the first RF signal generator 147, the second RF signal generator 149, the impedance matching system 143, the TES RF signal generator 403, and the TES impedance matching system 401. The control system 120 may also control the operation of the DC power supply 117 for the clamp electrode 112. The control system 120 may also control the operation of the lift device 133 for the lift pins 132 and the operation of the door 107. The control system 120 also controls the operation of the backside gas supply system 129 and the temperature control fluid circulation system 125. The control system 120 also controls the vertical movement of the cantilever arm assembly 115. The control system 120 also controls the operation of the throttle member 196 and the pump that controls the suction at the exhaust port 105. The control system 120 also controls the operation of the hold-down control mechanism 913 of the hold-down rod 911 of the TES system 1000. Control system 120 also receives input from a temperature probe of TES system 1000. It is noted that control system 120 is equipped to allow programmatic and / or manual control of any function within plasma processing system 100.

[0101] In some embodiments, the control system 120 is configured to execute computer programs including sets of instructions for controlling process timing, process gas delivery system temperature, pressure differentials, valve positions, process gas mixture, process gas flow rates, backside cooling gas flow rates, chamber pressure, chamber temperature, wafer support structure temperature (wafer temperature), RF power levels, RF frequency, RF pulses, impedance match system 143 settings, cantilever arm assembly position, bias power, and other parameters of a particular process. In some embodiments, other computer programs stored in a memory device associated with the control system 120 may be used. In some embodiments, there is a user interface associated with the control system 120. The user interface may include a display 1435 (e.g., a display screen and / or a graphical software representation of the apparatus and / or process conditions) and user input devices 1437, such as a pointing device, keyboard, touch screen, microphone, etc.

[0102] The software directing the operation of the control system 120 can be designed or configured in many different ways. The computer programs directing the operation of the control system 120 to perform the various wafer fabrication processes in a process sequence can be written in any conventional computer readable programming language, such as assembly language, C, C++, Pascal, Fortran, etc. The compiled object code or script is executed by the processor 1401 to perform the tasks identified in the program. The control system 120 can be programmed to control various process control parameters related to process conditions, such as filter pressure differential, process gas composition and flow rate, backside cooling gas composition and flow rate, plasma conditions such as temperature, pressure, RF power level and RF frequency, bias voltage, cooling gas / fluid pressure, chamber wall temperature, etc. Examples of sensors that may be monitored during the wafer fabrication process include, but are not limited to, mass flow control modules, pressure sensors such as pressure gauge 1427, and temperature sensor 1431. Appropriately programmed feedback and control algorithms can be used with data from these sensors to control / adjust one or more process control parameters to maintain the desired process conditions.

[0103] In some implementations, the control system 120 is part of a broader manufacturing control system. Such manufacturing control systems may include semiconductor processing equipment, including processing tools, chambers, and / or platforms for wafer processing, and / or specific processing components such as wafer pedestals, gas flow systems, etc. These manufacturing control systems may be integrated with electronics for controlling their operation before, during, and after wafer processing. The control system 120 may control various components or subparts of the manufacturing control system. The control system 120 may be programmed to control any of the processes disclosed herein, including delivery of process gases, delivery of backside cooling gases, temperature settings (e.g., heating and / or cooling), pressure settings, vacuum settings, power settings, radio frequency (RF) generator settings, RF matching circuit settings, frequency settings, flow settings, fluid delivery settings, position and motion settings, wafer transport in and out of tools and other transport tools and / or load locks connected or interfaced to the particular system, depending on the wafer processing requirements.

[0104] Generally, the control system 120 can be defined as electronics having various integrated circuits, logic, memory, and / or software to receive and issue instructions, control operations, enable wafer processing operations, enable endpoint measurements, etc. The integrated circuits can include chips in firmware form that store program instructions, digital signal processors (DSPs), chips defined as application specific integrated circuits (ASICs), and / or one or more microprocessors or microcontrollers that execute the program instructions (e.g., software). The program instructions can be instructions communicated to the control system 120 in the form of various individual settings (or program files) that define operational parameters for performing a particular process on the wafer W within the system 100. In some embodiments, the operational parameters can be part of a recipe defined by a process engineer to accomplish one or more processing steps during the manufacture of one or more layers, materials, metals, oxides, silicon, silicon dioxide, surfaces, circuits, and / or dies of the wafer.

[0105] In some implementations, the control system 120 may be integrated or coupled with the plasma processing system 100, or may be part of or coupled to a computer that is networked to the system 100, or a combination thereof. For example, the control system 120 may be in the "cloud" of all or part of a fab host computer system that allows remote access to the wafer processing. The computer may allow remote access to the system 100 to monitor the current progress of a manufacturing operation, examine the history of past manufacturing operations, examine trends or performance metrics from multiple manufacturing operations, change parameters of a current process, set processing steps to follow a current process, or start a new process. In some examples, a remote computer (e.g., a server) may provide process recipes to the system 100 over a network, which may include a local network or the Internet.

[0106] The remote computer may include a user interface that allows for entry or programming of parameters and / or settings, which are then communicated from the remote computer to the system 100. In some examples, the control system 120 receives instructions in the form of data, where the instructions specify parameters for each of the processing steps to be performed during one or more operations. It should be noted that the parameters may be specific to the type of process being performed within the plasma processing system 100. Thus, as noted above, the control system 120 may be distributed, such as with one or more discrete controllers, which are networked together and operate for a common purpose, such as the processing and control described herein. One example of a distributed controller for such purposes is one or more integrated circuits in the plasma processing system 100 that communicate with one or more integrated circuits located remotely (e.g., at the platform level or as part of the remote computer) and are coupled to control the processes performed on the plasma processing system 100.

[0107] Examples of systems with which control system 120 may interface include, without limitation, plasma etch chambers or modules, deposition chambers or modules, spin rinse chambers or modules, metal plating chambers or modules, clean chambers or modules, bevel edge etch chambers or modules, physical vapor deposition (PVD) chambers or modules, chemical vapor deposition (CVD) chambers or modules, atomic layer deposition (ALD) chambers or modules, atomic layer etch (ALE) chambers or modules, ion implantation chambers or modules, track chambers or modules, and any other semiconductor processing systems that may be associated with or used in the fabrication and / or manufacture of semiconductor semiconductor wafers. As noted above, depending on the process step or steps performed by the tool, control system 120 may communicate with one or more other tool circuits or modules, other tool components, cluster tools, other tool interfaces, adjacent tools, neighboring tools, tools located throughout the factory, a main computer, another controller, or tools used in material transport to or from tool locations and / or loading docks in a semiconductor manufacturing factory.

[0108] The embodiments described herein may be practiced with a variety of computer system configurations, including handheld hardware units, microprocessor systems, microprocessor-based or program-controlled consumer electronics, minicomputers, mainframe computers, and the like. The embodiments described herein may also be practiced with distributed computing environments in which tasks are performed by remote processing hardware units connected over a network. It should be noted that the embodiments described herein, particularly those relating to the control system 120, may employ various computer-implemented operations with data stored in computer systems. These operations involve physical manipulation of physical quantities. Any operations described herein that are part of the embodiments are useful machine operations. The embodiments also relate to hardware units or apparatus for performing these operations. An apparatus may be specially configured for a special purpose computer. When defined as a special purpose computer, it may perform other processes, program executions, or routines that are not part of the special purpose while still allowing operations for that special purpose. In some embodiments, operations may be processed by a general purpose computer selectively activated or configured by one or more computer programs stored in a computer memory, cache, or retrieved from a network. When data is obtained from the network, it may be processed by other computers on the network, for example, a cloud of computing resources.

[0109] Various embodiments described herein may be implemented via process control instructions instantiated as computer readable code on a non-transitory computer readable medium. A non-transitory computer readable medium is any data storage hardware unit that can store data and subsequently read the data by a computer system. Examples of non-transitory computer readable media include hard disks, network attached storage (NAS), ROM, RAM, compact disk ROM (CD-ROM), recordable CD (CD-R), rewritable CD (CD-RW), magnetic tape, and other optical and non-optical data storage hardware units. A non-transitory computer readable medium may include a computer readable tangible medium distributed over a network-coupled computer system, allowing the storage and execution of computer readable code in a distributed manner.

[0110] The above disclosure includes detailed descriptions for a clearer understanding, but it is clear that certain changes and modifications are permitted within the scope of the appended claims. For example, one or more features from any embodiment disclosed herein can be combined with one or more features from any other embodiment disclosed herein. Therefore, it should be recognized that the present embodiment is merely illustrative and not restrictive, and the claims are not limited to the details described herein, but can be modified within the scope of the described embodiments and equivalents. The present disclosure may be realized in the following forms. [Form 1] 1. A variable edge sheath system, comprising: a coupling ring configured to couple to a bottom surface of an edge ring surrounding a wafer support region within the plasma processing chamber; an electrode having an annular shape embedded within the coupling ring; a plurality of RF signal supply pins coupled to the electrodes embedded within the coupling ring, each of the RF signal supply pins extending through a corresponding hole formed through a bottom surface of the coupling ring; a plurality of RF signal filters, each connected to the plurality of RF supply pins and configured to present a high impedance to a corresponding RF signal used to generate a plasma within the plasma processing chamber; Variable edge sheath system including. [Form 2] A variable edge sheath system as described in claim 1, wherein the corresponding RF signal used to generate the plasma in the plasma processing chamber has one or more frequencies within a range of about 1 megahertz to about 100 megahertz. [Form 3] A variable edge sheath system as described in claim 1, wherein each of the plurality of RF supply pins is exclusively connected to a corresponding one of the plurality of RF signal filters. [Form 4] The variable edge sheath system according to claim 1, a variable edge sheath system further comprising an RF signal generator electrically connected via an impedance matching system to supply an RF signal to the electrode embedded within the coupling ring via the plurality of RF signal filters and the plurality of RF supply pins. [Form 5] The variable edge sheath system according to claim 1, The variable edge sheath system further comprising an RF signal feed conductor to which each of the plurality of RF signal filters is electrically connected. [Form 6] The variable edge sheath system according to claim 5, A variable edge sheath system, wherein the connection locations of the plurality of RF signal filters to the RF signal feed conductor are substantially equally spaced circumferentially within the RF signal feed conductor. [Form 7] A variable edge sheath system as described in claim 5, wherein the plurality of RF signal filters and the RF signal supply conductor are disposed in an atmospheric environment isolated from the plasma in the plasma processing chamber. [Form 8] The variable edge sheath system according to claim 5, The variable edge sheath system further includes an RF signal feed line electrically connected between an RF signal output of the impedance matching system and the RF signal feed conductor. [Form 9] The variable edge sheath system according to claim 8, The variable edge sheath system further includes a capacitor having a first terminal electrically connected to both the RF signal supply conductor and the RF signal supply line, and a second terminal electrically connected to a reference ground potential. [Form 10] A variable edge sheath system as described in claim 1, wherein each of the plurality of RF signal filters is formed as a conductive coil. [Form 11] 11. A variable edge sheath system as described in claim 10, wherein the conductive coil is formed of aluminum or copper. [Form 12] 2. A variable edge sheath system as described in claim 1, wherein each of the plurality of RF signal filters has substantially the same configuration. [Form 13] A variable edge sheath system as described in claim 1, wherein the connection positions of the multiple RF signal supply pins to the electrodes in the coupling ring are arranged substantially equally spaced around the circumference of the electrodes in the coupling ring. [Form 14] A variable edge sheath system as described in embodiment 1, wherein the number of the plurality of RF signal supply pins is three, and the number of the plurality of RF signal filters is three. [Form 15] 1. A plasma processing system comprising: a primary electrode having a substantially cylindrical shape defined by a top surface, a bottom surface and an exterior surface; a ceramic layer disposed on the top surface of the primary electrode, the ceramic layer being configured to receive and support a semiconductor wafer; an RF signal generator electrically connected to the primary electrode through an impedance matching system and configured to generate and provide an RF signal to the primary electrode; an edge ring formed of a conductive material and configured to surround the ceramic layer and disposed radially adjacent the ceramic layer; a coupling ring coupled to a bottom surface of the edge ring, the coupling ring being formed of an electrically insulating material and including a recessed electrode; a plurality of RF signal supply pins electrically and physically connected to the recessed electrodes, each extending through a corresponding hole formed through a bottom surface of the coupling ring; a plurality of RF signal filters, each connected to the plurality of RF supply pins and configured to present a high impedance to the RF signal provided by the RF signal generator to the primary electrode; 1. A plasma processing system comprising: [Form 16] 16. A plasma processing system as recited in claim 15, wherein each of the plurality of RF supply pins is exclusively connected to a corresponding one of the plurality of RF signal filters. [Form 17] A plasma processing system as described in claim 15, wherein the RF signal generator is a first RF signal generator, the impedance matching system is a first impedance matching system, and the plasma processing system includes a second RF signal generator electrically connected via a second impedance matching system and supplying an RF signal to the embedded electrode via the multiple RF signal filters and the multiple RF supply pins. [Form 18] 18. The plasma processing system of claim 17, further comprising: The plasma processing system further comprising an RF signal supply conductor to which each of the plurality of RF signal filters is electrically connected. [Form 19] 19. A plasma processing system according to claim 18, wherein the connection positions of the plurality of RF signal filters to the RF signal supply conductor are substantially equally spaced around the periphery of the RF signal supply conductor. [Form 20] 20. The plasma processing system of claim 18, wherein the plurality of RF signal filters and the RF signal supply conductor are disposed in an atmospheric environment isolated from a plasma processing region overlying the ceramic layer. [Form 21] 19. The plasma processing system of claim 18, further comprising: The plasma processing system further includes an RF signal supply line electrically connected between an RF signal output of the second impedance matching system and the RF signal supply conductor. [Form 22] 22. The plasma processing system of claim 21, further comprising: The plasma processing system further includes a capacitor having a first terminal electrically connected to both the RF signal supply conductor and the RF signal supply line, and a second terminal electrically connected to a reference ground potential. [Form 23] 16. The plasma processing system of claim 15, wherein each of the plurality of RF signal filters is formed as a conductive coil. [Form 24] 24. The plasma processing system of claim 23, wherein the conductive coil is formed from aluminum or copper. [Form 25] 16. The plasma processing system of claim 15, wherein each of the plurality of RF signal filters has substantially the same configuration. [Form 26] A plasma processing system as described in claim 15, wherein the buried electrode has a substantially annular shape, and the connection positions of the multiple RF signal supply pins to the buried electrode are substantially equally spaced around a circumference of the buried electrode. [Form 27] 16. A plasma processing system according to claim 15, wherein a number of the plurality of RF signal supply pins is three, and a number of the plurality of RF signal filters is three.

Claims

1. 1. A variable edge sheath system, comprising: a coupling ring configured to couple to a bottom surface of an edge ring surrounding a wafer support region within the plasma processing chamber; an electrode having an annular shape embedded within the coupling ring; a plurality of RF signal supply pins coupled to the electrodes embedded within the coupling ring, each of the RF signal supply pins extending through a corresponding hole formed through a bottom surface of the coupling ring; a plurality of RF signal filters, each connected to the plurality of RF signal supply pins and configured to present a high impedance to a corresponding RF signal used to generate a plasma within the plasma processing chamber; a ring-shaped RF signal supply conductor, each of the plurality of RF signal filters being electrically connected between a respective one of the plurality of RF signal supply pins and the ring-shaped RF signal supply conductor; Variable edge sheath system including.

2. 2. The variable edge sheath system of claim 1, wherein the corresponding RF signal used to generate the plasma in the plasma processing chamber has one or more frequencies within a range of about 1 megahertz to about 100 megahertz.

3. 2. The variable edge sheath system of claim 1, wherein each of the plurality of RF signal supply pins is exclusively connected to a corresponding one of the plurality of RF signal filters.

4. 2. The variable edge sheath system of claim 1, a variable edge sheath system further comprising an RF signal generator electrically connected via an impedance matching system to supply an RF signal to the electrode embedded within the coupling ring via the plurality of RF signal filters and the plurality of RF signal supply pins.

5. 2. The variable edge sheath system of claim 1, The variable edge sheath system further comprising an RF signal feed conductor to which each of the plurality of RF signal filters is electrically connected.

6. 6. The variable edge sheath system of claim 5, A variable edge sheath system, wherein the connection locations of the plurality of RF signal filters to the RF signal feed conductor are substantially equally spaced circumferentially within the RF signal feed conductor.

7. 6. The variable edge sheath system of claim 5, wherein the plurality of RF signal filters and the RF signal feed conductor are disposed in an atmospheric environment isolated from the plasma in the plasma processing chamber.

8. 6. The variable edge sheath system of claim 5, The variable edge sheath system further includes an RF signal feed line electrically connected between an RF signal output of the impedance matching system and the RF signal feed conductor.

9. 9. The variable edge sheath system of claim 8, The variable edge sheath system further includes a capacitor having a first terminal electrically connected to both the RF signal feed conductor and the RF signal feed line, and a second terminal electrically connected to a reference ground potential.

10. 10. The variable edge sheath system of claim 1, wherein each of the plurality of RF signal filters is formed as a conductive coil.

11. 11. The variable edge sheath system of claim 10, wherein the conductive coil is formed from aluminum or copper.

12. 10. The variable edge sheath system of claim 1, wherein each of the plurality of RF signal filters has substantially the same configuration.

13. 2. The variable edge sheath system of claim 1, wherein the connection locations of the plurality of RF signal supply pins to the electrodes in the coupling ring are substantially equally spaced around the circumference of the electrodes in the coupling ring.

14. 2. The variable edge sheath system of claim 1, wherein the number of said plurality of RF signal supply pins is three, and the number of said plurality of RF signal filters is three.

15. 1. A plasma processing system comprising: a primary electrode having a substantially cylindrical shape defined by a top surface, a bottom surface and an exterior surface; a ceramic layer disposed on the top surface of the primary electrode, the ceramic layer being configured to receive and support a semiconductor wafer; an RF signal generator electrically connected to the primary electrode through an impedance matching system and configured to generate and provide an RF signal to the primary electrode; an edge ring formed of a conductive material and configured to surround the ceramic layer and disposed radially adjacent the ceramic layer; a coupling ring coupled to a bottom surface of the edge ring, the coupling ring being formed of an electrically insulating material and including a recessed electrode; a plurality of RF signal supply pins electrically and physically connected to the recessed electrodes, each extending through a corresponding hole formed through a bottom surface of the coupling ring; a plurality of RF signal filters, each connected to the plurality of RF signal supply pins and configured to present a high impedance to the RF signal provided by the RF signal generator to the primary electrode; a ring-shaped RF signal supply conductor, each of the plurality of RF signal filters being electrically connected between a respective one of the plurality of RF signal supply pins and the ring-shaped RF signal supply conductor; 1. A plasma processing system comprising:

16. 16. The plasma processing system of claim 15, wherein each of the plurality of RF signal supply pins is exclusively connected to a corresponding one of the plurality of RF signal filters.

17. 16. The plasma processing system of claim 15, wherein the RF signal generator is a first RF signal generator, the impedance matching system is a first impedance matching system, and the plasma processing system includes a second RF signal generator electrically connected through a second impedance matching system and supplying an RF signal to the recessed electrode through the plurality of RF signal filters and the plurality of RF signal supply pins.

18. 20. The plasma processing system of claim 17, further comprising: The plasma processing system further includes an RF signal supply conductor to which each of the plurality of RF signal filters is electrically connected.

19. 20. The plasma processing system of claim 18, wherein connection locations of the plurality of RF signal filters to the RF signal supply conductor are substantially equally spaced circumferentially within the RF signal supply conductor.

20. 20. The plasma processing system of claim 18, wherein the plurality of RF signal filters and the RF signal feed conductors are disposed in an atmospheric environment isolated from a plasma processing region overlying the ceramic layer.

21. 20. The plasma processing system of claim 18, further comprising: The plasma processing system further includes an RF signal supply line electrically connected between an RF signal output of the second impedance match system and the RF signal supply conductor.

22. 22. The plasma processing system of claim 21, further comprising: The plasma processing system further includes a capacitor having a first terminal electrically connected to both the RF signal supply conductor and the RF signal supply line, and a second terminal electrically connected to a reference ground potential.

23. 16. The plasma processing system of claim 15, wherein each of the plurality of RF signal filters is formed as a conductive coil.

24. 24. The plasma processing system of claim 23, wherein the conductive coil is formed from aluminum or copper.

25. 16. The plasma processing system of claim 15, wherein each of the plurality of RF signal filters has substantially the same configuration.

26. 16. The plasma processing system of claim 15, wherein the recessed electrode has a substantially annular shape, and the connection locations of the plurality of RF signal supply pins to the recessed electrode are substantially equally spaced around a circumference within the recessed electrode.

27. 16. The plasma processing system of claim 15, wherein a number of the plurality of RF signal supply pins is three, and a number of the plurality of RF signal filters is three.

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