Backside illuminated sensor having a boron layer deposited using plasma-enhanced atomic layer deposition - Patents.com

Abstract

In the fabrication of back-illuminated DUV / VUV / EUV radiation or charged particle image sensors, a method is used that utilizes a plasma-enhanced atomic layer deposition (plasma-enhanced ALD) process to generate a thin, pinhole-free pure boron layer above an active sensor area. Circuit elements are formed on the front surface of a semiconductor film, and an optional preliminary hydrogen plasma cleaning process is performed on the back surface of the film. The plasma-enhanced ALD process includes performing a plurality of plasma-enhanced ALD cycles, each of which forms an adsorbed boron precursor layer during a first cycle phase and then generates a hydrogen plasma during a second cycle phase to convert the precursor layer into an associated boron nanolayer. After each cycle phase, gas is purged from the plasma-enhanced ALD process chamber. The plasma-enhanced ALD cycles are repeated until the resulting cumulative stack height (thickness) of the boron nanolayer stack is equal to a specified target thickness.

Description

[Technical field]

[0001] [Related Applications / Patents] This application claims priority to U.S. Provisional Patent Application No. 63 / 146001, filed February 5, 2021, entitled “BACK-ILLUMINATED SENSOR WITH BORON LAYER DEPOSITED USING PLASMA ATOMIC LAYER DEPOSITION.”

[0002] [Field of Disclosure] This application relates to image sensors suitable for sensing radiation at deep UV (DUV), vacuum UV (VUV) and extreme UV (EUV) wavelengths, and methods for making / producing such image sensors. The sensors in certain embodiments are suitable for sensing electrons and other charged particles. Any of the sensors are suitable for use in photomask, reticle or wafer inspection systems. [Background technology]

[0003] The integrated circuit industry requires inspection tools with higher and higher resolution to resolve smaller and smaller features on integrated circuits, photomasks, reticles, solar cells, charge-coupled devices, etc., and to detect defects whose size is comparable to or smaller than the size of the features.

[0004] Inspection systems operating at short wavelengths, e.g., wavelengths less than about 250 nm, can often provide such resolution. In some cases, electrons or other charged particles, e.g., helium (He) nuclei (i.e., alpha particles), can be used. In particular, for photomask or reticle inspection, it is desirable to inspect at wavelengths that are the same as or close to those that will be used in lithography, i.e., near 193.4 nm for current generation lithography and near 13.5 nm for future EUV lithography, because the phase shifts of the inspection light caused by the patterns will be the same as or very similar to those caused during lithography. For inspection of semiconductor patterned wafers, an inspection system operating over a relatively wide wavelength range, e.g., including wavelengths in the near UV, DUV, and / or VUV ranges, may be advantageous because a wider wavelength range may reduce sensitivity to small changes in layer thickness or pattern dimensions that can cause large reflectivity changes at individual wavelengths.

[0005] A high signal-to-noise (S / N) ratio is required to detect small defects or particles on photomasks, reticles, and semiconductor wafers. To ensure a high S / N ratio during high speed inspection, a high photon or particle flux density is required, since statistical fluctuations in the number of detected photons (Poisson noise) are the fundamental limit to the S / N ratio. In many cases, about 100,000 or more photons per pixel are required. Inspection systems are typically used 24 / 7 with only short outages, resulting in detectors being exposed to a large amount of radiation after only a few months of operation.

[0006] Photons with a vacuum wavelength of 250 nm have an energy of about 5 eV. The band gap of silicon dioxide is about 10 eV. At first glance, photons with such wavelengths would not be likely to be absorbed by silicon dioxide, but since the silicon dioxide structure cannot perfectly match that of the silicon crystal, silicon dioxide grown on a silicon surface necessarily exhibits some dangling bonds at the interface with the silicon. Furthermore, since silicon dioxide is amorphous, there are likely to be some dangling bonds within the material as well. In practice, there will be a non-negligible density of defects and impurities within the oxide and at the interface with the underlying semiconductor that can absorb photons with deep UV wavelengths, especially those with wavelengths less than about 250 nm. Furthermore, under high radiation flux density, two high energy photons can arrive near the same location with very short time intervals (a few nanoseconds or picoseconds) and thus excite an electron to the conduction band of silicon dioxide by two absorption events in rapid succession or by two-photon absorption. EUV photons have very high energy (13.5 nm wavelength corresponds to photon energy of around 92 eV) and can break silicon-oxygen bonds and interact strongly with defects and contaminants in the oxide. Electron and charged particle detectors must usually be able to detect electrons or charged particles with energies of several hundred eV or more. At energies above 10 eV, silicon-oxygen bonds can be easily broken.

[0007] As mentioned above, high energy photons and particles can break bonds and ionize atoms in the silicon dioxide layer. Because silicon dioxide is a good insulator, free electrons created in the silicon dioxide can have a lifetime of 1 ms or more before recombining. Some of these electrons can migrate into the semiconductor material. These electrons create electric fields in the silicon dioxide and between the silicon dioxide and the semiconductor. These fields can cause electrons created in the semiconductor by lattice absorption to migrate to the semiconductor surface and recombine, resulting in loss of signal and a decrease in detector quantum efficiency. The near-continuous use of the device means that there is little or no time to recover the detector, since new free charges are created faster than they can recombine.

[0008] High energy particles and photons can also induce irreversible changes in silicon dioxide. These changes can include rearrangements of atomic bonds and movements of small atoms within the silicon dioxide. These changes are irreversible, as the normal operating temperature of the detector is usually in the range from near room temperature to about 50°C. In particular, conventional silicon photodiodes used as EUV detectors are known to lose efficiency with use.

[0009] Silicon dioxide layers on the surface of semiconductor detectors significantly reduce the efficiency of those detectors for low energy (less than about 2 keV) electrons. Some low energy electrons are absorbed by the silicon dioxide, causing it to become charged and deflecting later incoming electrons. Because native oxide always forms on exposed silicon surfaces, silicon detectors must necessarily have some oxide on their surface. Growing or depositing alternative dielectric materials (instead of oxide) on the semiconductor surface results in a significant increase in the density of defect states at the semiconductor-silicon dioxide interface. These defects reduce the quantum efficiency of the detector, especially for photons and charged particles absorbed near the semiconductor surface.

[0010] An additional source of degradation for EUV sensors is the development over time of a thin carbon layer on all EUV radiation-exposed surfaces in EUV systems, including the image sensor and optical elements. As this carbon layer thickens, it absorbs EUV radiation, reducing the sensitivity of the sensor and reducing the reflectivity of the optical elements in the light path. In EUV systems, all EUV-exposed surfaces are periodically cleaned to remove this carbon. This cleaning is typically performed with activated hydrogen (a mixture of hydrogen atoms and hydrogen radicals), which is very effective at removing carbon. However, hydrogen radicals can also attack the oxides on silicon detector surfaces, causing degradation of the performance of these sensors.

[0011] Diode-type detectors suitable for detecting EUV and / or electrons are known in the art. Examples of diode-type detectors are described in U.S. Pat. No. 6,399,433 issued to Nihtianov on March 20, 2012, U.S. Pat. No. 6,399,433 issued to Nihtianov on September 8, 2009, U.S. Pat. No. 6,399,433 issued to Nihtianov on April 23, 2013, and U.S. Pat. No. 6,399,433 issued to Nanver on May 28, 2012. These diode-type detectors have a thin (1 nm to 20 nm) boron layer directly on the silicon surface. U.S. Pat. No. 6,399,433 further describes an open mesh of metal conductors on the surface of such detectors.

[0012] These conventional detectors have contacts on their top surface (light or electron incidence surface). One of the disadvantages of having contacts and conductors on the illuminated surface is that it is not possible to create detectors with a large number (thousands or millions) of detector elements (pixels) while maintaining high detector efficiency. Each detector element requires multiple control signals, which are usually shared with other detector elements. For full well capacities of 100,000 electrons or more, detector element dimensions will usually be in the range of about 10 μm to 20 μm. Hundreds or thousands of interconnects connecting these control signals to each other and to the driving circuitry cannot be made without covering a significant portion of the surface area. DUV, VUV and EUV photons and low energy particles do not penetrate layers of conductors, such as metal and polysilicon, so the areas covered by these conductors have low or no sensitivity.

[0013] US Pat. Nos. 5,299,303; 5,303,633; and 5,433,663, all to Chern et al., disclose image sensor structures and methods for fabricating an image sensor in which a boron layer is deposited on at least the exposed backside surface of the image sensor. Various boron deposition temperature ranges are disclosed, including a range of about 400-450° C. and a range of about 700-800° C. The inventors have discovered that one advantage of higher boron deposition temperatures, such as deposition temperatures of about 600° C. to about 900° C., is that at such temperatures boron diffuses into silicon, resulting in an extremely thin, highly p-doped silicon layer on the photosensitive backside surface. This p-doped silicon layer is important in ensuring high quantum efficiency for DUV and VUV radiation, since an electrostatic field generated near the surface accelerates electrons away from the surface and toward the silicon layer. The p-type silicon also increases the silicon backside surface conductivity, which is important for high speed operation of the image sensor because a return path is required for ground currents induced by signal switching on the electrodes on the front surface of the sensor.

[0014] However, processing temperatures above 450°C cannot be used with semiconductor wafers containing conventional CMOS circuits, since 450°C is close to the melting points of metals commonly used in CMOS device fabrication, such as aluminum and copper. At high temperatures, such as above 450°C, these metals can expand, soften, and delaminate. Furthermore, at high temperatures, copper can easily diffuse into silicon, altering the electrical properties of the CMOS circuits. If the wafer is thinned and then a metal is deposited thereon, a boron layer can be deposited on the backside surface at temperatures between 600 and 900°C as described in the above-mentioned patent documents, and boron can be diffused into the surface during or after the deposition of the boron layer. Metal interconnects can then be formed on the frontside surface. After the image sensor region of the wafer is thinned to a thickness of, for example, about 25 μm or less, the thinned region can sag significantly and the peak-to-valley non-flatness can be tens of μm or more. Therefore, it is necessary to use relatively wide metal interconnect lines and vias, e.g., several microns wide or more, to ensure that the lines and vias connect despite any misalignment caused by the non-planarity. Such wide metal interconnects and vias increase the capacitance per unit area associated with the lines and vias. Furthermore, wide interconnects and vias may make it difficult or impossible to interconnect all the signals on a large area sensor having about a million or more pixels. In some cases, polysilicon jumpers may be required to connect the metal interconnects together, but polysilicon has a much higher resistivity than any metal, so using such jumpers may limit the maximum operating speed of the sensor.

[0015] The delta doping technique for image sensors described in US Patent No. 5,999,333 to Hoenk et al. can be performed at temperatures below 450° C. The technique involves the application of a 1.5 nm cap layer of nominally undoped silicon. This cap layer can be oxidized intentionally or by water and oxygen in the environment. This oxide layer can degrade under high intensity DUV, VUV, EUV or charged particle radiation, causing degradation of the sensor.

[0016] In a backside illuminated sensor fabrication method described in US Patent Publication 9, issued to Chuang et al. on September 7, 2021, a heavily p-doped epitaxial silicon layer provided on the sensor backside surface prior to boron deposition is used as an alternative electrostatic field acquisition means to improve the sensor quantum efficiency in DUV and VUV as described above. The low temperature heavily doped p-type epitaxial silicon layer can be grown at a temperature of 450° C. or less. A pure boron deposit at 450° C. or less can be deposited on the low temperature epitaxial layer to provide a backside surface electrostatic field and improve the quantum efficiency in DUV and VUV at low temperatures. The method allows the front side metal interconnects of the backside thinned image sensor to be created prior to the backside thinning and backside epitaxial silicon and boron processes, thereby enabling the sensor to be realized with finer design rules (0.35 μm or less). This allows the metal lines connecting critical features, such as the floating diffusion, to be thinner, thus allowing for smaller floating diffusion capacitance and higher charge-to-voltage conversion ratios.

[0017] The pure boron layer in the above methods is deposited by a chemical vapor deposition (CVD) process. The boron layer becomes rougher as the CVD deposition temperature is reduced. This increased surface roughness increases the tendency for pinholes, especially for very thin (2-5 nm) boron layers, since typical boron layers are 2-10 nm thick. The inventors also discovered that since boron absorbs a significant portion of DUV radiation, thinning the boron layer further increases the quantum efficiency of these backside-thinned sensors. According to the method described in US Pat. No. 6,299,333, published on June 3, 2021, the backside surface of the sensor can be textured to reduce reflections, which in turn further improves the quantum efficiency of these backside-thinned sensors. Although the CVD boron deposition process can deposit boron conformally on slightly rough surfaces (Ra~5 nm), as the aspect ratio of the surface texture increases, the boron thickness at the peaks of the texture differs significantly from that at the valleys.This non-uniformity can be exacerbated, especially at temperatures below 450 °C, as the CVD boron deposition becomes increasingly rough and therefore more prone to pinhole formation. [Prior art documents] [Patent documents]

[0018] [Patent Document 1] U.S. Patent No. 8,138,485 [Patent Document 2] U.S. Patent No. 7,586,108 [Patent Document 3] U.S. Patent No. 8,426,831 [Patent Document 4] U.S. Patent No. 8,450,820 [Patent Document 5] U.S. Patent No. 9,496,425 [Patent Document 6] U.S. Pat. No. 9,818,887 [Patent Document 7] U.S. Patent No. 10,121,914 [Patent Document 8] U.S. Patent No. 5,376,810 [Patent Document 9] U.S. Pat. No. 1,111,491 [Patent Document 10] US Patent Application Publication No. 2021 / 0164917 (A1) [Patent Document 11] US Patent Application Publication No. 2021 / 0320144 (A1) [Patent Document 12] U.S. Pat. No. 7,705,331 [Patent Document 13] U.S. Patent No. 9,723,703 [Patent Document 14] U.S. Pat. No. 9,865,447 [Patent Document 15] U.S. Patent No. 9,891,177 [Patent Document 16] U.S. Patent No. 9,279,774 [Patent Document 17] U.S. Patent No. 7,957,066 [Patent Document 18] U.S. Patent No. 7,817,260 [Patent Document 19] U.S. Patent No. 5,999,310 [Patent Document 20] U.S. Patent No. 7,525,649 [Patent Document 21] U.S. Patent No. 9,080,971 [Patent Document 22] U.S. Patent No. 7,474,461 [Patent Document 23] U.S. Pat. No. 9,470,639 [Patent Document 24] U.S. Patent No. 9,228,943 [Patent Document 25] U.S. Pat. No. 5,608,526 [Patent Document 26] U.S. Patent No. 6,297,880 Summary of the Invention [Problem to be solved by the invention]

[0019] Therefore, there is a need for a backside illuminated sensor fabrication method that includes a boron deposition process that can create a thin (2 nm to 20 nm) pinhole-free boron layer by deposition over flat and textured surfaces at temperatures ranging from room temperature to 800° C. Such a boron deposition process could benefit from ultra-thin, pinhole-free boron and / or boron deposited on textured surfaces to increase quantum efficiency, especially in the deep UV. Additionally, a boron deposition process capable of depositing pinhole-free pure boron layers at temperatures below 450° C. would allow for tighter design rules for sensor fabrication, thus increasing the flexibility of the image sensor's front side circuitry and increasing quantum efficiency. [Means for solving the problem]

[0020] The present invention is directed to a method of fabricating a back-illuminated image sensor that utilizes a plasma-enhanced atomic layer deposition (plasma-enhanced ALD) boron layer formation process to generate a thin, pinhole-free pure boron layer over an active area of ​​the image sensor. The present invention is also directed to a back-illuminated image sensor incorporating at least one pure boron layer formed by the plasma-enhanced ALD process, and an inspection system that utilizes such a back-illuminated image sensor. By fabricating a back-illuminated image sensor having a pure boron layer, and forming the pure boron layer by the plasma-enhanced ALD process described herein, the present invention provides an image sensor that exhibits a significantly longer operational lifetime (compared to image sensors having a boron layer formed using conventional processes) when used in an inspection system configured to sense deep ultraviolet (DUV) radiation, vacuum ultraviolet (VUV) radiation, extreme ultraviolet (EUV) radiation, or charged particles.

[0021] In one generalized embodiment of a method, circuitry is first formed on a front surface of a semiconductor film (e.g., using standard CMOS processing technology), the semiconductor film is then flipped over and a pure boron layer is formed on the back surface of the film by performing a plasma ALD boron layer formation process in which multiple plasma ALD cycles are performed, each of which produces a corresponding boron nanolayer, and the stack of boron nanolayers produced by the multiple plasma ALD cycles collectively forms the pure boron layer. Each plasma-enhanced ALD cycle includes two broad phases: a first cycle phase forms an adsorbed boron precursor layer over the backside (second) surface of the film, and a second cycle phase generates a hydrogen plasma over the boron precursor layer, which then reacts with the adsorbed boron precursor to create an associated boron nanolayer, ideally approximately one atomic layer thick, or less if precursor coverage is insufficient. In some embodiments, after the film is placed in a plasma-capable ALD deposition chamber and before the boron layer formation process begins, a preliminary hydrogen plasma cleaning process is performed to remove surface oxides from the backside surface, further enhancing the quality and purity of the pure boron layer produced by the plasma-enhanced ALD process. In one embodiment, the cleaning process involves exposing the film surface to hydrogen radicals in a plasma until the surface is saturated with hydrogen radicals, then switching off the plasma power supply and purging excess hydrogen radicals and gaseous reaction products (i.e., those produced by the reaction of the film material with hydrogen radicals) from the plasma-capable ALD deposition chamber. In a first cycle phase, a selected boron precursor is delivered into the deposition chamber using a gas flow system while keeping the plasma generation system of the deposition chamber inactive. In some embodiments, the boron precursor is selected from the group including B2H6, BX3 (X=Cl / Br), B2F4, trimethylborane (TMB), tris(dimethylamido)borane (TDMAB), and triethylborane (TEB).The film is left exposed to the boron precursor until all portions of the film surface are saturated with boron precursor molecules. In a second cycle phase, while the plasma generation system is activated, hydrogen gas is delivered into the deposition chamber using the gas flow system, which generates a hydrogen plasma that converts the adsorbed boron precursor formed in the first cycle phase into an associated boron nanolayer. Between the first and second cycle phases, a first purge is performed to remove the gaseous reaction products of the boron precursor and residual boron precursor gas from the deposition chamber, and after the second cycle phase and before the start of the subsequent plasma ALD cycle, a second purge is performed to remove residual reaction gas from the deposition chamber. Each plasma ALD cycle results in a corresponding boron nanolayer having a fixed thickness that is deposited on or above the backside surface of the film. The plasma ALD cycle is repeated multiple times until a stack of boron nanolayers is produced with a cumulative stack height (thickness) equal to a specified target thickness. In one practical embodiment, the semiconductor film has an epitaxial silicon thickness in the range of 10 μm to 40 μm and a pure boron layer thickness in the range of 2 nm to 20 nm. This plasma ALD boron deposition method provides reliable conformal deposition of ultra-thin (2 nm to 20 nm) and smooth boron layers on high aspect ratio textured film surfaces, facilitating the fabrication of image sensors for sensing DUV / VUV / EUV radiation or charged particles that are superior to image sensors with boron layers formed using traditional chemical vapor deposition (CVD) methods, especially at low temperatures (below 450° C.). One distinct advantage offered by this plasma-enhanced ALD boron deposition method over older CVD methods is the reliable formation of ultra-thin (2 nm to 5 nm), conformal, pinhole-free boron layers for use in DUV / VUV / EUV radiation or charged particle imaging sensors.

[0022] In a specific embodiment, when forming the front side circuit structure group, a lightly p-doped (p -After the epitaxial silicon layer is formed, front-end processing is performed to form circuit elements (but not metal or metal interconnects) on the front surface of the epitaxial layer. The substrate is then thinned while protecting the circuit elements to expose portions of the back surface of the epitaxial layer above the sensor active area, and the exposed back surface is then optionally textured. A pure boron layer is then formed directly over the exposed portions of the epitaxial layer using a modified plasma-enhanced ALD process, and a high temperature drive-in (>800°C) integrated into the process dissolves the pure boron layer and the p - A highly p-doped (p + ) epitaxial silicon layer regions are created, then back-end processing is performed to complete the front-end circuitry, an optional anti-reflective layer is formed over the boron layer, and the image sensor is packaged for use.

[0023] In accordance with another specific embodiment, a method for fabricating an image sensor on an SOI wafer (structure) using a low temperature ALD process includes first heavily p-doping a thin top silicon substrate / layer of the SOI wafer, and then doping the thin top silicon substrate / layer with a high p-doping concentration. + On the top silicon layer - The epitaxial layer is then formed. The complete front side circuitry (i.e., both the front end circuitry and the back end metal interconnects) is then fabricated on the p - After being formed on the front side surface of the epitaxial layer, a back side (second) handle wafer and / or a protective layer is formed over the front side circuit elements to facilitate back side processing. The SOI handle substrate is then thinned / removed, thereby removing the p +After the backside surface of the top silicon layer (i.e., at least above the active area of ​​the sensor) is exposed, optional cleaning and processing (e.g., texturing) of the backside surface is performed. A low temperature plasma ALD process (at 450° C. or less) is then performed to grow a pure boron layer on the exposed backside surface. Maintaining a low temperature (below 450° C.) during the plasma ALD process is important in this case to avoid expansion and / or diffusion of metallic components of the front side circuit elements. An anti-reflective and / or conductive coating can be formed on the boron layer to increase transmission of wavelengths of interest through the backside surface into the image sensor and / or to protect the image sensor.

[0024] It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not necessarily restrictive of the invention as claimed. The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and, together with the general description, serve to explain the principles of the invention. [Brief description of the drawings]

[0025] [Figure 1] FIG. 1 is a flow diagram illustrating an example plasma-enhanced ALD boron deposition method according to an embodiment of the invention. [Figure 2A] FIG. 2 is a cross-sectional view illustrating a schematic example of a plasma-capable ALD deposition chamber during a first phase of a plasma-activated ALD cycle of the plasma-activated ALD boron deposition method of FIG. [Figure 2B] FIG. 2 is a cross-sectional view illustrating a schematic example of a plasma-capable ALD deposition chamber during a second phase of a plasma-activated ALD cycle of the plasma-activated ALD boron deposition method of FIG. [Figure 3A] FIG. 2 is a timing diagram illustrating an example of gas flows utilized in a plasma-enhanced ALD cycle of the plasma-enhanced ALD boron deposition method of FIG. [Figure 3B] FIG. 2 is a timing diagram illustrating an example of gas flows utilized in a plasma-enhanced ALD cycle of the plasma-enhanced ALD boron deposition method of FIG. [Figure 3C]FIG. 2 is a timing diagram illustrating an example of gas flows utilized in a plasma-enhanced ALD cycle of the plasma-enhanced ALD boron deposition method of FIG. [Figure 3D] FIG. 2 is a timing diagram illustrating example plasma power levels utilized in a plasma ALD cycle of the plasma ALD boron deposition method of FIG. [Figure 4A] FIG. 2 is an exploded perspective view illustrating a schematic of an image sensor fabricated by the plasma-enhanced ALD boron deposition method of FIG. [Figure 4B] FIG. 2 is an exploded perspective view illustrating a schematic of an image sensor fabricated by the plasma-enhanced ALD boron deposition method of FIG. [Diagram 5] FIG. 1 is a flow diagram illustrating an example plasma-assisted ALD boron deposition method utilizing high temperature drive-in in accordance with another embodiment of the invention. [Figure 6] FIG. 1 is a flow diagram illustrating an example plasma ALD boron deposition method utilizing a low-temperature plasma ALD process in accordance with another embodiment of the invention. [Figure 7A] FIG. 13 is a cross-sectional side view of a backside thinned film image sensor fabricated on a silicon substrate using partial wafer thinning and having a plasma ALD boron layer in accordance with another embodiment of the present invention. [Figure 7B] FIG. 13 is a cross-sectional side view of a backside thinned film image sensor fabricated on a silicon substrate using partial wafer thinning and having a plasma ALD boron layer in accordance with another embodiment of the present invention. [Figure 8] FIG. 13 is a cross-sectional side view of a plasma ALD boron backside thinned image sensor fabricated on an SOI substrate using full wafer thinning and having a plasma ALD boron layer in accordance with another embodiment of the present invention. [Figure 9] FIG. 1 is a simplified schematic diagram illustrating an inspection system utilizing an image sensor fabricated using a plasma-enhanced ALD boron deposition method in accordance with another embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0026] Figure 1 is a flow diagram illustrating a method 100 of producing an image sensor 150 configured to sense DUV / VUV / EUV radiation or charged particles using a plasma-enhanced ALD boron layer formation process in accordance with one generalized embodiment of the invention. For reference, image sensor 150 is partially illustrated in simplified form at the bottom of Figure 1. Additional details regarding method 100 and image sensor 150 are described below with reference to Figures 2A-4B.

[0027] Referring to block 110 at the top of FIG. 1 and image sensor 150 at the bottom of FIG. 1, front-end circuitry 171 is formed on front surface 161 of semiconductor film 160 using well-known integrated circuit (IC) fabrication processes, such as lithography, deposition, ion implantation, annealing, and etching. As known in the art, these well-known IC fabrication processes typically include front-end processes in which non-metallic structures are formed in or on a semiconductor material layer (e.g., on the surface of a silicon substrate or epitaxial silicon layer), and back-end processes that include the formation of metal interconnects and other back-end circuitry. As used herein, the phrase "semiconductor film" refers to one or more layers of semiconductor material (e.g., a monolithic silicon substrate and / or one or more stacked epitaxial silicon layers), and the phrase "front-end circuitry" refers to the typically non-metallic structures formed in or on the semiconductor film during the front-end portion of a typical IC fabrication process. In contrast, the phrase "front side circuitry" refers to complete circuitry that collectively performs image sensor operations, including both front-end circuitry and back-end circuitry (e.g., metal interconnects and other structures formed in the back-end portion of a typical IC manufacturing process). When completed, the front side circuitry includes light sensing devices such as charge-coupled devices (CCDs), complementary metal oxide semiconductor (CMOS) imagers and photodiodes, and other semiconductor devices such as transistors, diodes, resistors, and capacitors that collectively perform image sensor operations when the image sensor 150 is installed in an inspection system. As described in specific embodiments below with reference to Figures 5 and 6, the process of block 110 may produce only front-end circuitry or may produce back-end circuitry in addition to the front-end circuitry to provide complete front side circuitry. Thus, the process of block 110 produces at least front-end circuitry that is made up of front side circuitry.After front side processing is complete, membrane 160 is typically thoroughly cleaned using a dilute HF or BHF dip in conjunction with standard cleans RCA1 and RCA2 to remove surface contaminants and surface oxides from its surface, ensuring that only silicon or hydrogenated silicon surfaces are available for the plasma ALD process described below.

[0028] In a currently preferred embodiment, after the front side circuit structure formation process (block 110) is performed in a processing equipment optimized for performing selected semiconductor processes, the partially formed sensor (i.e., film 160 with circuit elements 171 formed thereon) is placed in a plasma capable deposition chamber (block 120). As used herein, the phrase "plasma capable deposition chamber" refers to any deposition chamber configured to expose film 160 (or other substrate) to the set of gases and plasmas required to perform plasma ALD processes. With brief reference to FIG. 2A, an example plasma capable deposition chamber 210 generally includes a chamber wall 211 surrounding a processing compartment 212, a gas flow system 220 having an electrically insulated gas manifold 221 at least partially disposed within the processing compartment 212, and a plasma generation system 230 having a plasma generator 231 disposed within the processing compartment 212 and connected to a plasma controller 235 via an insulated conductor 233. As described below, these structures and systems are operatively configured to perform a plasma ALD boron layer formation process. As shown in FIG. 2A, when the film 160 is placed in the plasma capable deposition chamber 210, the film 160 is typically placed on the stage (support structure) 213 with the first surface 161 facing downward (i.e., the circuitry 171 is disposed between the film 160 and the stage 213) and the second surface 162 facing upward, i.e., toward the outlet orifice 223 of the gas manifold 221 and toward the plasma generator 231. The illustrated plasma capable deposition chamber 210 is highly simplified and is presented solely for descriptive purposes, and the features of the chamber 210 described below are not intended to be limiting unless expressly recited in the claims. That is, as will be appreciated by those skilled in the art, a plasma-capable deposition chamber suitable for carrying out the plasma-enhanced ALD boron layer formation process described below may have features (e.g., heat removal / cooling systems) in addition to those depicted in FIG. 2A.

[0029] Referring to block 125 (FIG. 1), after the film 160 is placed inside the deposition chamber 210, an optional hydrogen plasma clean is performed. Because of the delay between completing the standard clean (described above) and loading the film 160 into the deposition chamber 210, the backside film surface 162 sometimes has some native oxide even after the above-described standard clean process. In such cases, an initial hydrogen plasma can be used to remove the surface oxide and hydrogenate the backside surface 162 before the plasma ALD boron layer formation process can begin. In this hydrogen plasma clean process, hydrogen gas is flowed with or without an inert gas (e.g., argon) while the plasma generator 231 is switched on. The inert gas, e.g., Ar, helps strike and maintain the plasma at the required pressure in the deposition chamber 210. The duration for which the plasma is generated is determined by the amount of time required to maximize hydrogenation of the backside surface 162 and / or remove any surface oxide. At the end of the cleaning process, the plasma generator 231 is deactivated and the excess hydrogen radicals in the plasma and any other gases used to maintain the chamber pressure, such as Ar or any other inert gas radicals, are removed (purged). In this purge process, the inert gas is pumped through the deposition chamber with or without some hydrogen to ensure the removal of reactive radicals. The duration of this post-clean purge process is determined by the amount of time required to remove the radicals and reaction products from the deposition chamber 210.

[0030] As shown in the central region of FIG. 1, the plasma ALD process includes a number of plasma ALD cycles 130, which collectively form a pure boron layer 180 on the backside surface 162 of the membrane 160, at least on the surface portion facing the active sensor area defined by the location of the front-end circuitry structures 171. Each plasma ALD cycle 130 includes two phases, a first phase (P1) for forming an adsorbed boron precursor layer (block 132) above the backside surface 162, as described below with reference to FIG. 2A, and a second phase (P2) for converting the adsorbed boron precursor layer into a corresponding boron nanolayer (block 136) using a hydrogen plasma, as described below with reference to FIG. 2B. Two purge processes (blocks 134 and 138) are also performed at the end of each phase. The timing of gas flow and plasma generation will be described below with reference to FIGS. 3A-3D. As indicated by decision block 139 and described below with reference to FIG. 4A, the plasma-enhanced ALD cycle 130 is repeated until the thickness of pure boron layer 180 achieves a thickness target (e.g., within the range of 2 nm to 20 nm).

[0031] 2A and 3A, during phase P1, between cycle initial time T0 and first intermediate time T1, a boron precursor BP is disposed in the processing chamber 212 to form an adsorbed boron precursor layer 240 above the backside surface 162. In this exemplary embodiment, a portion of the boron precursor gas BP is then formed above the backside surface 162 by activating the gas flow distribution controller 225 to flow a boron precursor gas from a suitable source 226-1 through the manifold 221 into the processing compartment 212 and otherwise controlling process conditions within the deposition chamber 210. The dominant reaction in the first plasma ALD cycle is one in which the boron in the boron precursor bonds to exposed silicon at the backside surface 162, and the dominant reaction in subsequent cycles is one in which the boron in the precursor bonds to exposed boron of the most recently formed boron nanolayer while a reaction product is released. In either case, the hydrogenated or protonated surface reacts with the boron precursor BP, thereby bonding boron atoms to exposed material above the backside surface 162. It is noted that the plasma generation system 230 is deactivated in phase P1 (as shown in FIG. 3D). The length of phase P1 is determined by the amount of time required to maximize the reaction of the boron precursor with the substrate surface. According to alternative embodiments, the boron precursor BP includes one or more of B2H6, BX3 (X=Cl / Br), B2F4, trimethylborane (TMB), tris(dimethylamido)borane (TDMAB), and triethylborane (TEB). In some embodiments, an amount of H2 is flowed into the deposition chamber 210 with the boron precursor BP during phase P1, as shown by the dashed line between times T0 and T1 in FIG. 3C for one embodiment.

[0032] 1, a first purge phase (block 134) is performed at the end of phase P1 to ensure that the plasma-capable deposition chamber 210 is cleared of unreacted boron precursor and gaseous reaction products, and to prepare the film 160 for plasma ignition. As shown in FIG. 3B, in one embodiment, this first purge phase PP1 is performed from the first intermediate time T1 to the second intermediate time T2 (i.e., after phase P1 ends and before phase P2 begins) by flowing argon (or some other inert) gas into the processing compartment 212 (e.g., using the gas flow system 220 shown in FIG. 2A) to evacuate the deposition chamber 210 of unreacted boron precursor gas and gaseous reaction products. In some embodiments, H2 is also flowed into deposition chamber 210 during the first purge phase PP1, as indicated by the dashed line between times T1 and T2 in FIG. 3C for some embodiments.

[0033] 2B, in phase P2, a hydrogen plasma 237 is generated above the boron precursor layer formed in phase P1, thus creating an associated boron nanolayer 181 by gas reaction of the adsorbed boron precursor. As shown in FIG. 3C, in the second phase, hydrogen gas H2 is delivered into the processing compartment 212 (e.g., by controlling the gas delivery controller 225 to flow gas from source 226-1 as shown in FIG. 2B) to provide reactive protons for hydrogenation of the exposed / top film surface. As shown in FIGS. 2B and 3D, in one embodiment, the second phase also activates the plasma generation system 230; for example, by transmitting a plasma power signal V from the plasma controller 235 to the plasma generator 231. PThis is accomplished by asserting / transmitting a current between the electrodes, generating high acceleration, which generates energetic / hot electrons and ions 236, which in turn generate and maintain a plasma 237 in the portion of the hydrogen gas H2 disposed above the film 160. As shown by the dashed lines at times T2-T3 in FIG. 3B, in some embodiments, argon gas (Ar) is also flowed into the deposition chamber 210 during phase P2 to help maintain the process pressure and upon ignition of the plasma 237. Depending on the boron precursor used, possible reaction products include dihydrogen gas, gaseous hydrogen halides such as HCl, HF or HBr, CH4 or C2H6, NH3 or mono- or dimethyl ammonia, as well as other potential gaseous reaction intermediates that may be liberated during the reaction.

[0034] Referring back to FIG. 1, a second purge phase (block 138) is performed at the end of phase P2 to remove unreacted species and reaction products from the plasma-capable deposition chamber 210 and prepare the film 160 for a subsequent plasma-enhanced ALD cycle. As shown in FIG. 3B, in one embodiment, a second purge phase PP2 is performed between intermediate time T3 and end time T4 (i.e., at the end of the most recent plasma-enhanced ALD cycle) by flowing argon gas into the processing compartment. In some embodiments, H2 is also flowed into the deposition chamber 210 in the second purge phase PP2, as shown by the dashed line between times T3 and T4 in FIG. 3C for one embodiment.

[0035] 1, cycle 130 of these two phases and associated purge phases is repeated (usually several times) until the resulting stack of boron nanolayers has a cumulative stack height (thickness) equal to a specified target thickness for boron layer 180. With reference to FIG. 4A, in generating this cumulative stack height, a plurality of boron nanolayers 181-0 through 181-n are sequentially formed one on top of the other as described above, with each successive nanolayer adding a corresponding amount to the cumulative stack height, thus resulting in a certain cumulative stack height / thickness T (as shown in FIG. 4B). 180 That is, a bottom boron nanolayer 181-0 is formed directly on the upper surface 162 of the film 160 at the end of the first plasma ALD cycle, a second boron nanolayer 181-1 is produced on the upper surface 181-0U of the first boron nanolayer 181-0 at the end of a subsequently performed plasma ALD cycle, a third boron nanolayer 181-2 is produced on the upper surface 181-1U of the second boron nanolayer 181-1 at the end of the third plasma ALD cycle, and so on until a final boron nanolayer 181-n is produced on the upper surface of the penultimate boron nanolayer at the end of the last plasma ALD cycle. The plasma ALD cycle 130 results in a resulting pure boron layer thickness T 180 This is repeated until the target thickness value is reached. In one exemplary practical embodiment, the thickness T of the semiconductor film 160 is 160 is in the range of 10 μm to 40 μm, and the plasma-enhanced ALD cycle 130 is repeated until the thickness of the pure boron layer 180 is in the range of 2 nm to 20 nm. Because the molecular structure of a pure boron layer deposited using plasma-enhanced ALD may contain some fractional contaminants of carbon or nitrogen or halogens or inert carrier gases such as Ar, the phrase "pure boron layer" is defined herein as a molecular structure in which at least 80% are boron atoms.

[0036] 1, additional processing (block 140) may be performed after the formation of the pure boron layer 180 to complete the fabrication of the image sensor 150. As described below, some post-boron-deposition processing may be performed while the partially completed sensor 150 is still located in the plasma-capable ALD deposition chamber utilized to form the pure boron layer 180 (e.g., after the plasma cleaning and plasma-enhanced ALD boron deposition processes described above have been performed). Other post-boron-deposition processing may be performed after the sensor 150 has been removed from the plasma-capable ALD deposition chamber. For example, as shown in FIG. 4B, in some embodiments, the additional processing may complete the creation of the front side circuit elements 170, and may be performed by forming back-end interconnects 172 on the front-end circuit structures 171 and / or by forming an anti-reflective coating or conductive capping layer 185 on the top surface 181 of the pure boron layer 180.

[0037] FIG. 5 illustrates a method 500 for producing an image sensor 150A (partially depicted in simplified form at the bottom of FIG. 5 for reference) using a high temperature plasma ALD boron layer formation process according to another embodiment. Referring to block 510 at the top of FIG. 5, front-end circuit structures 171A (without metal interconnects 172A) are created on the front surface 161A of the lightly p-doped epitaxial silicon layer 163A using standard semiconductor processing steps, such as lithography, deposition, ion implantation, annealing, and etching (e.g., one or more dielectric layers, such as silicon dioxide and / or silicon nitride, are formed as a gate layer on the front surface 161A, and then the circuit structures are completed by forming polysilicon and dielectric structures rather than metal structures). Charge-coupled device (CCD) and / or CMOS sensor elements can also be created during the creation of the front-end circuit structures 171A. In preferred embodiments, the epitaxial layer 163A has a thickness of about 10 to 40 μm. In preferred embodiments, the epitaxial layer 163A is very lightly p-doped (p -) is formed on the semiconductor substrate. In some embodiments, one or more protective (wax) layers are then deposited (block 512) on the front-end circuitry structures 171A for protection during backside thinning, and the semiconductor substrate is then thinned (e.g., using mechanical polishing and wet etching) to expose the backside surface of the epitaxial layer 163A above the active sensor area (block 514). Once the backside surface of the epitaxial layer 163A is exposed, it can be textured using wet or dry etching to improve the quantum efficiency of the sensor, as described in U.S. Patent No. 5,399,313 to Chuang et al., entitled "Low-reflectivity back-illuminated sensor," which is incorporated herein by reference in its entirety. The or each of the frontside protective layers can then be removed (block 518) by dissolving the composite wax material using a solvent, such as acetone and / or ethanol. The exposed backside surface is then cleaned and prepared for plasma-enhanced ALD boron deposition (block 525). In one embodiment, at least a portion of the cleaning is performed before placing the wafer / film (i.e., the backside thinned substrate with frontside circuitry features) in a plasma-capable ALD deposition chamber, where standard silicon cleaning procedures, e.g., RCA1 and RCA2, are performed, followed by immersion of the wafer / film in a dilute HF or BHF solution to remove surface oxides. A pure boron layer 180A is then deposited / grown (formed) on the backside surface of epitaxial layer 163A, e.g., using a plasma-enhanced ALD procedure performed as described above with reference to FIG. 1. After the thickness of the pure boron layer 180A reaches the target thickness, a high temperature (i.e., greater than 800° C.) thermal drive-in process is performed (block 535) to induce boron atomic diffusion from the pure boron layer 180A into the epitaxial layer material adjacent to the pure boron layer 180A, thereby increasing the p-doping concentration therein to p - A highly p-doped (p +) epitaxial silicon layer region 165A is effectively formed (block 535). By controlling the drive-in process, p - A part of the epitaxial layer portion 163A is a front-end circuit structure group 171A·p + The epitaxial silicon layer regions 165A are disposed between the epitaxial silicon layer regions 165A. - The resistivity of the epitaxial layer portion 163A is less than 10 Ωcm, p + The resistivity of the epitaxial layer region 165A is greater than 0.01 Ω cm, and + The nominal p-type doping concentration of the epitaxial layer region 165A is p - It is at least twice the nominal p-type doping concentration of epitaxial layer portion 163A. + The formation of the (second) epitaxial silicon layer portion 165A results in backside surface accumulation, which improves the quantum efficiency of the sensor, especially for DUV, VUV, and EUV illumination. In one embodiment, this drive-in is performed by heating the wafers in the plasma ALD deposition chamber to 850° C. for 5 minutes in an H2 or N2 ambient. The wafers are then removed from the plasma ALD deposition chamber, and metal interconnects 172A are fabricated above the front-end circuit structures 171A using known techniques, thereby completing the fabrication of the front-side circuit elements 170A (block 541). After the front-side circuit elements 170A are completed, an optional anti-reflective coating 185A, such as Al2O3 and / or HfO2 or other dielectric oxide, is deposited on the pure boron layer 180A (block 543). The choice of the dielectric material deposited and its thickness depends on the operating wavelength of the sensor being fabricated. Finally, the wafer is diced and the individual sensors 150A are packaged for operation (block 545).

[0038] FIG. 6 illustrates a method 600 for fabricating an image sensor 150B (see FIG. 6, bottom) on an SOI wafer (structure / substrate) using a plasma-enhanced ALD boron layer formation process at low temperature (i.e., below 450° C.) according to another embodiment. As known in the art, an SOI wafer typically includes a thin top epitaxial silicon substrate mounted on an SOI (first) handle substrate with an intervening oxide layer. Referring to block 605 at the top of FIG. 6, the thin top epitaxial silicon substrate of the SOI wafer is heavily boron doped (or heavily doped with another p-type dopant) and then a thin p-type oxide is deposited on the thin epitaxial silicon substrate. - At least a portion of the semiconductor film 160B is formed by growing a (lightly p-doped) epitaxial silicon layer over the upper silicon substrate. - Epi layer 163B and p + The thickness of both the upper silicon substrate 165B and the lower silicon substrate 165C is within the range of 10 to 40 μm, and - The layer resistivity of the epitaxial layer 163B is less than 10 Ωcm, + The resistivity of the upper silicon substrate 165B is set to be greater than 0.01 Ω cm, and + The nominal p-type doping concentration of the upper silicon substrate 165B is p - The doping concentration of the epitaxial silicon (epi) layer 165B is at least twice the nominal doping concentration of the epi layer 163B. If the SOI structure is provided with a fully p-doped upper silicon substrate, the process of p-doping the upper silicon substrate 165B can be omitted. Referring to image sensor 150B, the downward facing surface of epitaxial silicon (epi) layer 165B defines the front surface of semiconductor film 160B, and the upward facing surface of the heavily p-doped upper silicon substrate 165B defines the back surface 162B of film 160B. Next, as shown in block 610, standard semiconductor processing steps such as lithography, deposition, ion implantation, annealing, and etching are used to p-do the upper silicon substrate 165B. -On the front side surface 161B of the epi layer 163B, the complete front side circuit elements 170B (i.e., both the front end circuit structures 171B and the metal interconnects 172B) are produced. Charge-coupled device (CCD) and / or CMOS sensor elements and devices can also be formed during the creation of the front side circuit elements 170B. In some embodiments, one or more protective layers are then deposited on the front side circuit elements 170B (block 612), and then a front side (second) handle wafer is attached above the front side circuit elements 170B (e.g., attached to the membrane 160B above the circuit elements 170B with an intervening protective layer, block 613). The SOI (first) handle substrate is then backside thinned by a combination of polishing and / or wet etching until the back side surface 162B is fully or partially exposed (block 614). The exposed backside surface is then optionally processed (e.g., textured using wet or dry etching to improve the quantum efficiency of the sensor) and then cleaned using standard silicon cleaning procedures, such as an RCA1 clean and HF or BHF dip, to prepare the exposed first epitaxial layer backside surface for low temperature epitaxial silicon growth (block 616). In one embodiment, the partially formed image sensor is then placed in a plasma capable ALD deposition chamber and a pure boron layer 180B is deposited / grown (formed) on the backside surface 162B using a plasma ALD procedure performed using known techniques such that at least the circuitry 170B is kept at a temperature of 450° C. or less (block 630). In some embodiments, the low temperature plasma ALD process is performed as described above with reference to FIG. 1. Forming the pure boron layer 180B at low temperature avoids damage to the metal layers forming the front side circuitry 170B due to thermal expansion and diffusion that would occur at higher temperatures. An optional anti-reflective coating 185B, such as Al2O3 and / or HfO2 or other dielectric oxides, is then deposited (block 643) on the pure boron layer 180B. The choice of the dielectric material deposited and its thickness depends on the operating wavelength of the sensor being fabricated.Finally, the front handle substrate and protective layer are removed (block 644), the wafer is diced, and the individual image sensors 150B are packaged for operation using known techniques (block 645).

[0039] 7A and 7B show schematic cross-sections of partially backside thinned image sensors 150C and 150D fabricated using the methods described in FIGS. 5 and 6, respectively.

[0040] Referring to FIG. 7A, the image sensor 150C is a lightly p-doped (p - ) epitaxial silicon layer 163C. Front-end circuitry 171C is fabricated on front surface 161C of epitaxial layer 163C and then covered with a protective layer (not shown). Portions of silicon substrate 167C above the active sensor area are then backside thinned to expose backside surface 162C. A pure boron layer 180C is then formed on backside surface 162C using the plasma-enhanced ALD process described herein, followed by a high temperature drive-in process to form a heavily boron doped (p + ) backside (second) epitaxial regions 165C are then formed. Metal interconnects 172C are then formed on front-end circuit structures 171C to complete front-side circuit elements 170C, followed by formation of an anti-reflective layer 185C over pure boron layer 180C to reduce reflections and thereby enhance the quantum efficiency of image sensor 150C at the operating wavelength. Additional details relating to the formation of image sensor 150C (i.e., without the pure boron layer formed by plasma ALD) are described in U.S. Patent No. 5,399,323 to Chern et al., entitled “Back illuminated sensor with boron layer,” which is incorporated herein by reference.

[0041] Referring to Figure 7B, an image sensor 150D is fabricated on a silicon-on-insulator (SOI) structure using the low temperature plasma ALD process of Figure 6. Due to the low temperature processes used during subsequent processing, complete front side circuit elements 170D (i.e., both front end circuit structures 171D and metal interconnects 172D) are formed on the front side surface 161D of a lightly p-doped epitaxial layer 163D grown on a thin upper silicon substrate 165D of the SOI. Notably, the upper silicon substrate 165D is p - Prior to growing the epitaxial layer 163D, it is heavily boron doped to enhance backside surface conductivity. A partial backside thinning of the SOI handle substrate 167D is then performed to expose portions of the backside surface 162D of the upper silicon substrate 165D. A pure boron layer 180D is then formed on the exposed backside surface 162D using a low temperature (<450° C.) plasma ALD boron layer formation process to extend exposure lifetime, followed by an anti-reflective coating 185D on the pure boron layer 180D to enhance quantum efficiency. The essential difference between sensor 150D and sensor 150C (FIG. 7A) is that in sensor 150D, a portion of the oxide layer 169D of the original SOI structure is in contact with the remaining portion of the handle layer 167D and the p-type oxide layer 185D. + The point is located between the silicon substrate 165D. - Epitaxial layer 163D and p +Silicon substrate 165D forms the effective semiconductor membrane 160D of image sensor 150D, and in-dwell oxide portion 169D and in-dwell handle substrate portion 167D are attached to membrane 160D above the non-active sensor area. Details of step-by-step manufacturing schematics for producing sensor 150D are provided, for example, in U.S. Patent No. 6,393,363 to Haddidi et al., entitled “Back-illuminated image sensor and method of manufacturing a sensor using a silicon on insulator wafer,” which is incorporated herein by reference in its entirety.

[0042] 8 shows another image sensor 150E having a pure plasma ALD boron layer 180E formed on a SOI substrate using the low temperature fabrication method of FIG. 6 according to another specific embodiment. As with the example described above with reference to FIG. 7B, a SOI top silicon substrate 165E is heavily boron doped to provide high backside surface conductivity, and then a lightly p-doped epitaxial layer 163E is grown thereon. Complete front side circuit elements 170E (i.e., both front end circuit structures 171E and metal interconnects 172e) are formed on the front side surface 161E of the epitaxial layer 163E. In this embodiment, through silicon vias 198E are formed with p + Layer upper silicon substrate 165E and p - By forming in the epi layer 163E, electrical connections are made between the backside surface 162E and the frontside circuit elements 170E. A full wafer thinning process is then performed to remove the entire SOI handle substrate and oxide layer (not shown), thus forming the semiconductor film 160E of the image sensor 150E. - Epitaxial layers 163E and p +The image sensor 150E is formed by a silicon substrate 165E. Since full wafer thinning is utilized to fabricate the image sensor 150E, the method involves creating the front side circuit elements 170E, forming a protective layer 197E over the circuit elements 170E, and then bonding a handle substrate 195E to the front side surface. The handle substrate 195E and protective layer 197E are removed after completing back side processing to form a pure boron layer 180E on the heavily p-doped epitaxial layer 163E using a plasma-enhanced ALD boron layer formation process at low temperature (<450° C.) and then forming an anti-reflective coating layer 185E over the pure boron layer 180E for long term stability and improved quantum efficiency at the wavelength of interest. In some embodiments, portions of the pure boron layer 180E and the heavily doped epitaxial layer 163E are etched / removed to expose the bottom of the through silicon via 198E to facilitate making frontside / backside connections. Details of the fabrication procedures used to form the image sensor 150E using an SOI substrate are described, for example, in the above-referenced U.S. Patent No. 6,233,663. Alternatively, the sensor 150E can be formed on a silicon substrate, for example, as described in the above-referenced U.S. Patent No. 6,233,663.

[0043] 9 illustrates an example inspection or metrology system 900 configured to inspect or measure a semiconductor manufacturing related specimen 908, such as a silicon wafer, a reticle, or a photomask. System 900 generally includes an illumination (light) source 902, a detector assembly 904, and a stage 912.

[0044] The illumination source 902 emits deep UV (DUV) and / or vacuum UV (VUV) incident light (radiation) L having a wavelength in the range of 100 nm to 300 nm. IN Preferably, the illumination source 902 is configured to generate (emit) light having a wavelength of less than 100 nm (e.g., 13.5 nm for future EUV lithography) or greater than 300 nm. In some embodiments, the illumination source 902 uses one or more light sources LS and one or more optical elements (e.g., a frequency converter) to convert the incident light L INis generated. In one embodiment, the illumination source 902 may comprise a continuous light source, such as an arc lamp, a laser-pumped plasma source, or a continuous wave (CW) laser. In another embodiment, the illumination source 902 may comprise a pulsed light source, such as a mode-locked laser, a Q-switched laser, or a plasma source pumped by a mode-locked or Q-switched laser. Suitable light sources that may be incorporated into the illumination source 902 are described in U.S. Pat. No. 5,399,433 to Kirk et al., entitled "Methods and systems for providing illumination of a specimen for a process performed on the specimen," U.S. Pat. No. 5,399,433 to Bezel et al., entitled "System and method for transverse pumping of laser-sustained plasma," and U.S. Pat. No. 5,399,433 to Chuang et al., entitled "High brightness laser-sustained plasma broadband source," all of which are incorporated herein by reference.

[0045] The stage 912 is adapted to receive the specimen 908 and effect movement of the specimen 908 relative to the optical system 903 (i.e., to reflect the incident light L by the optical system 903). IN The stage 912 may include an XY stage or an Rθ stage. In one embodiment, the stage 912 allows the height of the specimen 908 to be adjusted during inspection to maintain focus. In another embodiment, the optics 903 may be adjusted to maintain focus.

[0046] The optical system 103 includes a number of optical elements and other optical components, which receive the incident light L IN 908 and to focus reflected (e.g., scattered) light L R / S 9 includes an illumination tube lens 903-1, an objective lens 903-2, a collection tube lens 903-3, a condenser lens 903-4, and a beam splitter 903-5. During operation of the system 900, incident light L emitted from the illumination source 902 is IN is directed by the condenser lens 903-4 and the illumination tube lens 903-1 to the beam splitter 903-5, from where the incident light L IN is directed downwards onto the specimen 908 via the objective lens 903-2. R / S is the incident light L IN 903-3 is a portion of the incident light that is reflected and / or scattered upward by surface features of the specimen 908 into the objective lens 903-2 and then directed by the objective lens 903-2 and collection tube lens 903-3 towards the detector assembly 904.

[0047] The detector assembly 904 includes one or more image sensors 150 fabricated by any of the methods described herein. Alternative embodiments of the sensor 150 include a plasma ALD boron coated backside illuminated CCD sensor, a plasma ALD boron coated backside illuminated CMOS sensor, and an electron bombarded image sensor incorporating a plasma ALD boron coated backside thinned solid-state image sensor. The image sensor 150 can include a two-dimensional array sensor or a one-dimensional line sensor. In some embodiments, the output of the detector assembly 904 is provided to an information processing system 914, which analyzes the output. The information processing system 914 can be configured by program instructions 918, which can be stored on a carrier medium 916. In some embodiments, the inspection system 900 includes a Q-switched laser, and one or more image sensors 150 in the detector assembly 904 are synchronized with the laser pulses. In such an embodiment, the image sensor 150 can be operated in TDI mode during the laser pulses and the data can be read out through multiple outputs on either side of the sensor during the intervals between the laser pulses. In certain embodiments of the inspection system, a line on the specimen is illuminated and scattered and / or reflected light is collected in one or more darkfield and / or brightfield collection channels. In such an embodiment, the image sensor 150 can be a line sensor or an electron bombarded line sensor. In certain embodiments of the inspection system, multiple spots on the specimen are illuminated and scattered and / or reflected light is collected in one or more darkfield and / or brightfield collection channels. In such an embodiment, the image sensor 150 can be a two-dimensional array sensor or an electron bombarded two-dimensional array sensor.

[0048] Additional details regarding various embodiments of the inspection or metrology system 900 may be found in U.S. Patent No. 6,393,433 to Vazhaeparambil et al., entitled “TDI Sensor in a Darkfield System,” U.S. Patent No. 6,393,433 to Romanovsky et al., entitled “Wafer inspection,” U.S. Patent No. 6,393,433 to Armstrong et al., entitled “Split field inspection system using small catadioptric objectives,” U.S. Patent No. 6,393,433 to Chuang et al., entitled “Beam delivery system for laser dark-field illumination in a catadioptric optical system,” U.S. Patent No. 6,393,433 to Shafer et al., entitled “Ultra-broadband UV microscope imaging system with wide range zoom capability,” and U.S. Patent No. 6,393,433 to Shafer et al., entitled “Surface inspection system using laser line illumination and two-dimensional imaging.” U.S. Patent No. 5,393,433 to Leong et al. entitled “Metrology systems and methods”; U.S. Patent No. 5,393,433 to Kandel et al. entitled “Broad band objective having improved lateral color performance”; and U.S. Patent No. 5,393,433 to Chuang et al. entitled “Broad band objective having improved lateral color performance.”No. 5,393,633 to Zhuang et al. entitled "Optical metrology with reduced sensitivity to grating anomalies," U.S. Pat. No. 5,493,633 to Wang et al. entitled "Dynamically Adjustable Semiconductor Metrology System," U.S. Pat. No. 5,493,633 to Wang et al. entitled "Dynamically Adjustable Semiconductor Metrology System," U.S. Pat. No. 5,493,633 to Piwonka-Corle et al. entitled "Focused Beam Spectroscopic Ellipsometry Method and System," issued on March 4, 1997 to Piwonka-Corle et al., and U.S. Pat. No. 5,493,633 to Rosencwaig et al. entitled "Apparatus for Analyzing Multi-Layer Thin Film Stacks on Semiconductors," issued on October 2, 2001 to Rosencwaig et al., all of which are incorporated herein by reference.

[0049] The various embodiments of the structures and methods of the present invention described above are merely illustrative of the principles of the present invention and are not intended to limit the scope of the present invention to the described embodiments. For example, additional steps may be added or the order of steps may be changed from those depicted in the flow charts of Figures 5 and 6. Thus, the present invention is limited only by the following claims and their equivalents.

Claims

1. 1. A method of manufacturing an image sensor configured to sense at least one of deep ultraviolet (DUV) radiation, vacuum ultraviolet (VUV) radiation, extreme ultraviolet (EUV) radiation, and charged particles, comprising: forming front-end circuit structures on the first surface of the semiconductor film; and a method of performing a plurality of plasma-enhanced atomic layer deposition (ALD) cycles to assemble a pure boron layer on the second surface of the semiconductor film with successively produced nanolayers of boron, each of the plasma-enhanced ALD cycles comprising: disposing a boron precursor above the second surface of the semiconductor film during a first phase of each of the plasma-enhanced ALD cycles such that an adsorbed portion of the boron precursor forms a boron precursor layer above the second surface of the semiconductor film; and A method of generating a hydrogen plasma above the boron precursor layer during a second phase of each of the plasma-enhanced ALD cycles such that the associated boron nanolayer is created by gas reaction of adsorbed portions of the boron precursor.

2. The method of claim 1, further comprising: placing the semiconductor film in a deposition chamber; cleaning the second surface of the semiconductor film by generating a hydrogen plasma above the second surface; and performing said plurality of plasma ALD cycles immediately following said cleaning; A method for performing the cleaning and the multiple plasma ALD cycles while continuously maintaining the semiconductor film in the deposition chamber.

3. 3. The method of claim 2, the deposition chamber having a gas flow system configured to selectively deliver the boron precursor and the hydrogen into the deposition chamber and a plasma generation system configured to generate a plasma adjacent the second surface of the semiconductor film; and Upon depositing the boron precursor, the method includes controlling the gas flow system to deliver the boron precursor into the deposition chamber while the plasma generation system is deactivated.

4. 4. The method of claim 3, wherein the gas flow system is controlled to flow one of B2H6, BX3 (X=Cl / Br), B2F4, trimethylborane (TMB), tris(dimethylamido)borane (TDMAB), and triethylborane (TEB) into the deposition chamber.

5. 4. The method of claim 3, wherein the gas flow system is controlled to deliver hydrogen gas into the deposition chamber while the plasma generation system is activated to generate the hydrogen plasma.

6. 3. The method of claim 2, further comprising, in each said plasma ALD cycle: purging residual boron precursor gas from the deposition chamber during a first period between the first and second phases; and A method for purging residual reactant gas from the deposition chamber during a second period after the second phase.

7. 2. The method of claim 1, wherein the semiconductor film comprises an epitaxial layer having a thickness in the range of 10 μm to 40 μm, and wherein during the execution of the plurality of plasma ALD cycles, depositing the boron precursor and generating the hydrogen plasma are repeated until the thickness of the pure boron layer is in the range of 2 nm to 20 nm.

8. 2. The method of claim 1, further comprising forming one of an anti-reflective coating and a capping layer on said pure boron layer.

9. 2. The method of claim 1, The method of forming the front-end circuitry structures includes forming the front-end circuitry structures on a p-doped epitaxial silicon layer having a first p-type doping concentration, the method further comprising: A high temperature drive-in process is performed to form a heavily p-doped epitaxial silicon layer region between the pure boron layer and the remaining portion of the p-doped epitaxial silicon layer.

10. 10. The method of claim 9, further comprising forming metal interconnects over said front-end circuit structures after said heavily p-doped epitaxial silicon layer regions are formed.

11. 2. The method of claim 1, further comprising performing one of a wet etch and a dry etch to texture said second surface before said pure boron layer is formed.

12. 2. The method of claim 1, further comprising forming the semiconductor film by forming a p-doped epitaxial silicon layer having a first p-type doping concentration on a top silicon substrate of a silicon-on-insulator (SOI) wafer, the top silicon substrate having a second p-type doping concentration higher than the first p-type doping concentration.

13. 13. The method of claim 12, further comprising the step of forming the semiconductor film further comprising: heavily p-doping the top silicon substrate of the SOI wafer before forming the p-doped epitaxial silicon layer.

14. 13. The method of claim 12, the SOI wafer having a first handle wafer and an oxide layer located between the first handle wafer and the top silicon substrate; forming the front-end circuitry structure group, the front-end circuitry structure group being disposed on a front-side surface of the p-doped epitaxial silicon layer, and a metal interconnect group being disposed above the front-end circuitry structure group, the method further comprising: attaching a second handle wafer to the semiconductor film above the front-side circuit element group; backside thinning the first handle wafer to expose at least a portion of the top silicon substrate, the exposed portion of the top silicon substrate forming the second surface of the semiconductor membrane.

15. 15. The method of claim 14, wherein the front side circuit elements are maintained at a temperature of less than 450° C. during the plasma ALD cycle.

16. 13. The method of claim 12, further comprising forming a through silicon via in said semiconductor film before said pure boron layer is formed.

17. 17. The method of claim 16, further comprising etching portions of said pure boron layer to expose said through silicon vias.

18. 2. The method of claim 1, wherein forming the front-end circuitry structures comprises fabricating one of a charge coupled device (CCD) and a complementary metal oxide semiconductor (CMOS) device.

19. 13. An image sensor for sensing at least one of deep ultraviolet (DUV) radiation, vacuum ultraviolet (VUV) radiation, extreme ultraviolet (EUV) radiation, and charged particles, the image sensor comprising: a semiconductor film; a group of circuit elements formed on a first surface of the semiconductor film; and a pure boron layer formed on a second surface of the semiconductor film, the pure boron layer being formed according to the method of claim 1.

20. 13. An inspection system comprising: an illumination source; and a set of optics including an objective lens configured to direct and focus incident light from the illumination source onto a specimen and to collect, direct and focus reflected / scattered light from the specimen onto a detector, the detector having one or more image sensors configured to sense at least one of deep ultraviolet (DUV) radiation, vacuum ultraviolet (VUV) radiation, extreme ultraviolet (EUV) radiation and charged particles, each of the image sensors comprising a semiconductor film, a group of circuit elements formed on a first surface of the semiconductor film, and a pure boron layer formed on a second surface of the semiconductor film, the pure boron layer being formed according to the method of claim 1.

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