Semiconductor Device

Abstract

To provide a technique capable of detecting a substrate bias voltage with low power consumption.SOLUTION: A technology includes a booster circuit (CP1) that outputs a boosted voltage on the basis of a first clock signal (CLKP) of a first frequency (FCLKP), a step-down circuit (CP2) that outputs a step-down voltage on the basis of a second clock signal (CLKN) of a second frequency (FCLKN), and a logic circuit block (CL) that compares the first frequency and the second frequency and outputs a comparison result (CMPOUT) between the first frequency and the second frequency according to a predetermined standard.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present disclosure relates to a semiconductor device, and to a technique that is effective when applied to a semiconductor device including a MISFET that uses SOTB. [Background technology]

[0002] A semiconductor device configured with a MISFET using SOTB (Silicon on Thin Buried oxide) has a substrate bias generating circuit that generates a substrate bias voltage (VBP) for a P-channel MISFET and a substrate bias voltage (VBN) for an N-channel MISFET. For example, U.S. Patent Application Publication No. 2018 / 000568 proposes this type of semiconductor device.

[0003] It may be necessary to check whether a substrate bias voltage such as a substrate bias voltage (VBP) for a P-channel MISFET or a substrate bias voltage (VBN) for an N-channel MISFET is a normal voltage. For example, one voltage can be checked using two comparators (comparison circuits). A proposal for this type of inspection is given in, for example, U.S. Patent Application Publication No. 2019 / 0310699. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] US Patent Application Publication No. 2018 / 000568 [Patent Document 2] US Patent Application Publication No. 2019 / 0310699 Summary of the Invention [Problem to be solved by the invention]

[0005] In a substrate bias generating circuit that generates a substrate bias voltage (VBP) for a P-channel MISFET and a substrate bias voltage (VBN) for an N-channel MISFET, four comparators are required to detect two substrate bias voltages (VBP, VBN). However, the current consumption of the semiconductor device increases by the amount of the current consumption of the four comparators.

[0006] An object of the present disclosure is to provide a technique capable of detecting a substrate bias voltage with low power consumption.

[0007] Other objects and novel features will become apparent from the description of this specification and the accompanying drawings. [Means for solving the problem]

[0008] A brief summary of representative aspects of this disclosure is as follows.

[0009] According to one embodiment, a boost circuit (CP1) that outputs a boosted voltage based on a first clock signal (CLKP) having a first frequency (FCLKP); a step-down circuit (CP2) that outputs a step-down voltage based on a second clock signal (CLKN) having a second frequency (FCLKN); a logic circuit block (CL) for comparing a first frequency with a second frequency and outputting a comparison result (CMPOUT) between the first frequency and the second frequency according to a predefined criterion. Effect of the Invention

[0010] According to the above embodiment, the substrate bias voltage can be detected with low power consumption. [Brief description of the drawings]

[0011] [Figure 1] FIG. 1 is a diagram for explaining a substrate bias generating circuit according to a first embodiment. [Diagram 2]FIG. 2 is a diagram showing an example of the configuration of the counter logic circuit block CL shown in FIG. [Diagram 3] FIG. 3 is a diagram for explaining the operation of the counter logic circuit block CL in FIG. [Figure 4] FIG. 4 is a cross-sectional view of a MISFET using SOTB. [Diagram 5] FIG. 5 is a diagram for explaining the current consumption of the counter logic circuit block CL. [Figure 6] FIG. 6 is a block diagram illustrating a configuration example of a semiconductor device according to application example 1 of the first embodiment. [Figure 7] FIG. 7 is a diagram for explaining an example of the operation of the semiconductor device of FIG. [Figure 8] FIG. 8 is a block diagram illustrating a configuration example of a semiconductor device according to the second application example of the first embodiment. [Figure 9] FIG. 9 is a diagram for explaining an example of the operation of the semiconductor device of FIG. [Figure 10] FIG. 10 is a diagram illustrating the operation of the oscillator circuit. [Figure 11] FIG. 11 is a diagram illustrating a configuration example of a substrate bias generating circuit according to the second embodiment. [Figure 12] FIG. 12 is a diagram showing the relationship between the frequency FOSC, the first frequency FCLKP, and the second frequency FCLKN. [Figure 13] FIG. 13 is a diagram illustrating a configuration example of a substrate bias generating circuit according to the third embodiment. [Figure 14] FIG. 14 is a diagram showing the relationship between the first frequency FCLKP and the second frequency FCLKN. [Figure 15] FIG. 15 is a diagram illustrating a configuration example of a substrate bias generating circuit according to the fourth embodiment. [Figure 16] FIG. 16 is a diagram illustrating a configuration example of a substrate bias generating circuit according to the fifth embodiment. [Figure 17] FIG. 17 is a diagram showing the characteristics of the substrate bias generating circuit of FIG. [Figure 18] FIG. 18 is a diagram showing the dependency of the second substrate bias voltage on the set value of the first substrate bias voltage. [Figure 19] FIG. 19 is a diagram for explaining a case where an abnormal current (leak) flows from the first substrate bias voltage to the second substrate bias voltage. [Figure 20] FIG. 20 is a diagram for explaining the layout arrangement of the terminal pads for the first substrate bias voltage and the terminal pads for the second substrate bias voltage. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0012] Hereinafter, the embodiments will be described with reference to the drawings. However, in the following description, the same components are given the same reference numerals and the repeated description may be omitted. Note that the drawings may be shown more diagrammatically than the actual embodiment in order to clarify the description, but they are merely examples and do not limit the interpretation of the present disclosure. EXAMPLES

[0013] FIG. 1 is a diagram for explaining a substrate bias generating circuit according to a first embodiment. FIG. 2 is a diagram for explaining a configuration example of a counter logic circuit block CL in FIG. 1. FIG. 3 is a diagram for explaining the operation of the counter logic circuit block CL in FIG. 2. FIG. 4 is a cross-sectional view of a MISFET using SOTB. FIG. 5 is a diagram for explaining the current consumption of the counter logic circuit block CL.

[0014] In FIG. 1, the substrate bias generating circuit BBG includes a first oscillation circuit OSC1, a second oscillation circuit OSC2, a first charge pump CP1 which is a step-up circuit, a second charge pump CP2 which is a step-down circuit, and a counter logic circuit block CL which is a logic circuit block.

[0015] The first oscillator circuit OSC1 outputs a first clock signal CLKP having a first frequency FCLKP, and the second oscillator circuit OSC2 outputs a second clock signal CLKN having a second frequency FCLKN.

[0016] The first charge pump CP1 outputs a first substrate bias voltage VBP, which is a boosted voltage, based on a first clock signal CLKP of a first frequency FCLKP. The second charge pump CP2 outputs a second substrate bias voltage VBN, which is a stepped-down voltage, based on a second clock signal CLKN of a second frequency FCLKN. The first substrate bias voltage VBP is, for example, a positive voltage. The second substrate bias voltage VBN is, for example, a negative voltage.

[0017] The first substrate bias voltage VBP and the second substrate bias voltage VBN are substrate bias voltages selectively supplied to the substrate gate of the P-channel MISFET2 and the substrate gate of the N-channel MISFET3 constituting a large-scale logic circuit (also called a core logic circuit) CLC, such as a microcontroller unit MCU, a central processing unit CPU, and a memory circuit provided in the semiconductor device 1. The substrate bias voltage VBP is the substrate bias voltage of the P-channel MISFET2, and the substrate bias voltage VBN is the substrate bias voltage of the N-channel MISFET3. The source-drain path of the P-channel MISFET2 and the source-drain path of the N-channel MISFET3 are connected in series between the second power supply potential VDD2 and the ground potential VSS (for example, 0V). Therefore, the large-scale logic circuit CLC can be said to be a supply region of the second power supply potential VDD2. On the other hand, the substrate bias generating circuit BBG is supplied with the first power supply potential VDD1 (VDD1>VDD2) and the ground potential VSS. Therefore, the substrate bias generating circuit BBG can be said to be a supply region of the first power supply potential VDD2.

[0018] Here, selectively means that, for example, in a case where the operation mode of the large scale logic circuit CLC has a normal operation mode and a standby operation mode, when the normal operation mode is switched to the standby operation mode, the first substrate bias voltage VBP and the second substrate bias voltage VBN are selectively supplied to the substrate gate of the P channel MISFET2 and the substrate gate of the N channel MISFET3, respectively. As a result, the respective threshold voltages of the P channel MISFET2 and the N channel MISFET3 become larger than the respective threshold voltages of the P channel MISFET2 and the N channel MISFET3 in the normal operation mode. As a result, the leakage current of the large scale logic circuit CLC in the standby operation mode can be reduced. When the semiconductor device 1 is driven by a power supply potential from a battery or the like, the leakage current of the semiconductor device 1 can be reduced, which has the effect of allowing the power supply potential of the battery or the like to be used for a long period of time.

[0019] As shown in Fig. 4, each of the P-channel MISFET 2 and the N-channel MISFET 3 can be, for example, a MISFET (Metal Insulator Semiconductor Field Effect Transistor) using SOTB (Silicon on Thin Buried oxide). Fig. 2 shows a cross-sectional view of the P-channel MISFET 2 and the N-channel MISFET 3. In Fig. 2, the P-channel MISFET 2 and the N-channel MISFET 3 are shown as a p-type SOTB transistor PT and an n-type SOTB transistor NT as SOTB transistors. In the SOTB transistor, a deep n-type well region DNW is formed on a p-type substrate SU such as single crystal silicon.

[0020] In the p-type SOTB transistor PT, an n-type well region NW is formed on the n-type well region DNW. An insulating film BOX is formed on the n-type well region NW. A semiconductor layer SL1 is formed on the n-type well region NW so as to sandwich the insulating film BOX. In the semiconductor layer SL1, a p+ type region SR1 that serves as the source region of the p-type SOTB transistor PT and a p+ type region DR1 that serves as the drain region are formed. In addition, in the semiconductor layer SL1, a channel region CH1 that does not substantially contain impurities is formed between the p+ type region SR1 and the p+ type region DR1. The impurity concentration of the channel region CH1 is, for example, 3×10 17 cm -3 The gate electrode G1 of the p-type SOTB transistor PT is formed on the channel region CH1 via the gate insulating film DL1.

[0021] In the n-type SOTB transistor NT, a p-type well region PW is formed on the n-type well region DNW. An insulating film BOX is formed on the p-type well region PW. A semiconductor layer SL2 is formed on the p-type well region PW so as to sandwich the insulating film BOX. In the semiconductor layer SL2, an n+ type region SR2 that serves as the source region of the n-type SOTB transistor NT and an n+ type region DR2 that serves as the drain region are formed. In addition, in the semiconductor layer SL2, a channel region CH2 that does not substantially contain impurities is formed between the n+ type region SR2 and the n+ type region DR2. The impurity concentration of the channel region CH2 is 3×10 17 cm -3 The gate electrode G2 of the n-type SOTB transistor NT is formed on the channel region CH2 via the gate insulating film DL2.

[0022] The thickness of the insulating film BOX is, for example, about 10 nm. In the p-type SOTB transistor PT, an n+ type region NR is formed on the n-type well region NW, through which the substrate bias generating circuit BBG supplies a first substrate bias voltage (also called a back bias voltage) VBP to the n-type well region NW. In the n-type SOTB transistor NT, a p+ type region PR is formed on the p-type well region PW, through which the substrate bias generating circuit BBG supplies a second substrate bias voltage (also called a back bias voltage) VBN to the p-type well region PW. In addition, the p-type SOTB transistor PT, the n-type SOTB transistor NT, the p+ type region PR, and the n+ type region NR are isolated by an element isolation film STI.

[0023] In the case of an n-type SOTB transistor NT, the absolute value of the threshold voltage can be increased and the leakage current can be reduced by setting the back bias voltage VBN to a negative voltage. On the other hand, in the case of a p-type SOTB transistor PT, the absolute value of the threshold voltage can be increased and the leakage current can be reduced by setting the back bias voltage VBP to a positive voltage. The leakage current changes exponentially with respect to the change in the back bias voltage.

[0024] Therefore, the threshold voltages of the p-type SOTB transistor PT and the n-type SOTB transistor NT are controlled by the back bias voltages VBN and VBP, and the leakage current is suppressed. As a result, the power consumption of the large scale logic circuit CLC having the p-type SOTB transistor PT and the n-type SOTB transistor NT can be reduced.

[0025] In the p-type SOTB transistor PT and the n-type SOTB transistor NT, the short channel effect can be suppressed by thinning the film thickness of the channel layer formed on the insulating film BOX. In addition, the threshold voltage can be controlled by adjusting the impurity concentration of the N-type well region NW and the P-type well region PW under the insulating film BOX. Therefore, the variation in the threshold voltage can be suppressed by lowering the impurity concentration of the channel layer. In addition, in the SOTB transistor, the threshold voltage of each transistor can be adjusted by applying a voltage from the substrate (i.e., applying the first substrate bias voltage VBP and the second substrate bias voltage VBN) using the thin insulating film BOX. In other words, the substrate bias voltage VBP is set to the well potential VNW of the N-type well region NW under the insulating film BOX, and the substrate bias voltage VBN is set to the well potential VPW of the P-type well region PW under the insulating film BOX. In this case, the provision of the thin insulating film BOX has the advantage that the junction leakage current between the source or drain and the bulk substrate is almost no problem.

[0026] The counter logic circuit block CL compares the first frequency FCLKP with the second frequency FCLKN, and outputs a comparison result CMPOUT between the first frequency FCLKP and the second frequency FCLKN according to a predefined standard.

[0027] The first oscillator circuit OSC1 generates a first clock signal CLKP to be supplied to the first charge pump CP1, and the first frequency FCLKP of the first clock signal CLKP changes so that the voltage value of the first substrate bias voltage VBP becomes a target voltage.

[0028] The second oscillator circuit OSC2 generates a second clock signal CLKN to be supplied to the second charge pump CP2, and the second frequency FCLKN of the second clock signal CLKN changes so that the voltage value of the second substrate bias voltage VBN becomes a target voltage.

[0029] These two clock signals CLKP and CLKN are counted by a counter in the counter logic circuit block CL. When the count value is within a specified range, the counter logic circuit block CL sets the comparison result CMPOUT to, for example, a high level H (CMPOUT=H). When the count value is outside the specified range, the counter logic circuit block CL sets the comparison result CMPOUT to, for example, a low level L (CMPOUT=L). The comparison result CMPOUT can be used as a detection signal for detecting whether the respective voltage values ​​of the first substrate bias voltage VBP and the second substrate bias voltage VBN are normal or abnormal.

[0030] The comparison result CMPOUT is supplied to, for example, a system control logic circuit SL. Based on the value of the comparison result CMPOUT (for example, high level H), the system control logic circuit SL can generate a control signal to apply the first substrate bias voltage VBP to the N-type well region NW and the second substrate bias voltage VBN to the P-type well region PW. Based on the value of the comparison result CMPOUT (for example, low level L), the system control logic circuit SL can generate a control signal to notify that the first substrate bias voltage VBP and the second substrate bias voltage VBN are abnormal.

[0031] Next, a configuration example and operation of the counter logic circuit block CL in Fig. 1 will be described with reference to Fig. 2 and Fig. 3. In Fig. 3, t indicates time.

[0032] The counter logic circuit block CL includes a counter circuit constituted by D-FFs (D-type flip-flops) 20-30 with reset terminals, an AND circuit 31, and the like. In the D-FFs 20-23, the Q terminal and the D terminal of each D-FF are coupled by an inverter circuit, and an inverted signal of the Q terminal is input to the D terminal. The clock terminal of the D-FF20 is connected so as to receive a first clock signal CLKP having a first frequency FCLKP. The clock terminals of the D-FFs 21, 22, and 23 are connected so as to receive signals of the Q terminals of the preceding D-FFs 20, 21, and 22. The reset terminals of the D-FFs 20-23 are configured so as to receive a first reset signal RST1. The signal of the G terminal of the D-FF23 is set as the second reset signal RST2. The signal of the D terminal of the D-FF23 is set as the FCLK_8 signal.

[0033] In D-FFs 24 to 28, the Q terminal and D terminal of each D-FF are coupled by an inverter circuit IV, and an inverted signal at the Q terminal is input to the D terminal. The clock terminal of D-FF 24 is connected so as to receive a second clock signal CLKN having a second frequency FCLKN. The clock terminals of D-FFs 25, 26, 27, and 28 are connected so as to receive signals from the Q terminals of the preceding D-FFs 24, 25, 26, and 27. The reset terminals of D-FFs 20 to 28 are connected so as to receive a second reset signal RST2.

[0034] D-FF29 is connected to the D terminal of D-FF26, and has a clock terminal to which the signal VCMPL is input, and a reset terminal to which the second reset signal RST2 is input. The Q terminal of D-FF29 is connected to the first input of the AND circuit 31. The Q terminal of D-FF28 is connected as the signal VCMPH to the second input of the AND circuit 31. The Q terminal of D-FF29 operates to change from L to H on the 4th count, and the Q terminal of D-FF28 operates to change from L to H on the 16th count.

[0035] The output of the AND circuit 31 is connected to the D terminal of D-FF30. The first reset signal RST1 is input to the reset terminal of D-FF30. The inverted signal of the second reset signal RST2 is input to the clock terminal of D-FF30 via an inverter circuit. The Q terminal of D-FF30 is supplied with the signal of the comparison result CMPOUT.

[0036] 3, when the second clock signal CLKN of the second frequency FCLKN is 4 to 16 (4 to 16 pulses) during an 8 count period of the first clock signal CLKP of the first frequency FCLKP (period of high level H of the FCLK_8 signal), the value of the comparison result CMPOUT is output as high level H (CMPOUT=H). In addition, in FIG. 3, the period of high level H of the second reset signal RST2 is set as a comparison period TCMP, and the period of low level H of the second reset signal RST2 is set as a reset period TRST.

[0037] The current consumption of the counter logic circuit block CL will be explained using FIG. 5. In FIG. 5, the vertical axis indicates frequency (Freq) and the horizontal axis indicates time (t). The frequency FVBP indicated by the solid line is the change in the oscillation frequency of the first oscillation circuit OSC1, and the frequency FVBN indicated by the dashed line is the change in the oscillation frequency of the second oscillation circuit OSC2. The frequencies FVBP and FVBN are counted by the counter logic circuit block CL. As shown in FIG. 5, the counter logic circuit block CL operates at high speed (several MHz) during the charging period of the first charge pump CP1 and the second charge pump CP2. When the charging is completed and the voltages (VBP, VBN) generated by the first charge pump CP1 and the second charge pump CP2 are stabilized, the counter logic circuit block CL operates at several tens of kHz. Therefore, the current consumption of the counter logic circuit block CL can be considered to be negligible. This can also be understood from the fact that the current consumption of a counter circuit that counts a 32 kHz clock is about 3 nA. The relationship between the frequencies FVBP and FVBN when charging is completed is a fixed relationship such as FVBP / FVBN≈A (where A is a predetermined constant).

[0038] According to the first embodiment, in the substrate bias generating circuit BBG which generates a substrate bias voltage (VBP) for a P-channel MISFET and a substrate bias voltage (VBN) for an N-channel MISFET, when detecting two substrate bias voltages (VBP, VBN), it is possible to detect whether each of the voltage values ​​of the first substrate bias voltage VBP and the second substrate bias voltage VBN is normal or abnormal by the counter logic circuit block CL without using four comparators. In other words, it is possible to detect the substrate bias voltages (VBP, VBN) with low power consumption without increasing the current consumption of the semiconductor device 1.

[0039] (Application Example 1 of Example 1) Fig. 6 is a block diagram showing a configuration example of a semiconductor device 1a according to application example 1 of embodiment 1. Fig. 7 is a diagram for explaining an operation example of the semiconductor device 1a of Fig. 6.

[0040] The following mainly describes the differences between the semiconductor device 1a in FIG. 6 and the semiconductor device 1 in FIG.

[0041] 1) In the substrate bias generating circuit BBG, a first resistor R1 and a second resistor R2 are connected in series between the output of the first charge pump CP1 and the ground potential VSS. A potential VFBN at a connection point (midpoint) between the first resistor R1 and the second resistor R2 is configured to be supplied to the first oscillator circuit OSC1. The oscillation frequency (first frequency FCLKP) of the first oscillator circuit OSC1 is determined based on a difference voltage between a reference voltage VFER and the potential VFBN. The potential VFBN is a potential obtained by dividing the output voltage of the first charge pump CP1 by the first resistor R1 and the second resistor R2.

[0042] 2) In the substrate bias generating circuit BBG, a third resistor element R3 and a fourth resistor element R4 are connected in series between the output of the first charge pump CP1 and the output of the second charge pump CP2. A potential VFBP at a connection point (midpoint) between the third resistor element R3 and the fourth resistor element R4 is configured to be supplied to the second oscillation circuit OSC2. The oscillation frequency (second frequency FCLKN) of the second oscillation circuit OSC2 is determined based on a difference voltage between a reference voltage VFER and the potential VFBP. The potential VFBP is a potential obtained by dividing the output voltage of the first charge pump CP1 and the output voltage of the second charge pump CP2 by the third resistor element R3 and the fourth resistor element R4.

[0043] 3) In the semiconductor device 1a, a switch circuit SWC is provided between a substrate bias generating circuit BBG and a substrate gate of a P-channel MISFET2 and a substrate gate of an N-channel MISFET3 which constitute a large-scale logic circuit (also called a core logic circuit) CLC. The switch circuit SWC is configured to select a substrate bias voltage to be supplied to the substrate gate of the P-channel MISFET2 and the substrate gate of the N-channel MISFET3. The semiconductor device 1a (or the large-scale logic circuit CLC) has, for example, three operation modes (normal operation mode, standby operation mode, and boost operation mode). Note that the boost operation mode does not have to be provided.

[0044] In the standby operation mode, the second switch element SW2 of the switch circuit SWC is turned on by, for example, a high level (selection level) of the control signal CNT2. At this time, the first switch element SW1 of the switch circuit SWC is turned off by, for example, a low level (non-selection level) of the control signal CNT1, and the third switch element SW3 of the switch circuit SWC is turned off by, for example, a low level (non-selection level) of the control signal CNT3. As a result, the first substrate bias voltage VBP and the second substrate bias voltage VBN are selectively supplied to the substrate gate of the P-channel MISFET2 and the substrate gate of the N-channel MISFET3, respectively.

[0045] In the normal operation mode, the first switch element SW1 is turned on by, for example, a high level (selection level) of the control signal CNT1. At this time, the second switch element SW2 is turned off by, for example, a low level (non-selection level) of the control signal CNT2, and the third switch element SW3 is turned off by, for example, a low level (non-selection level) of the control signal CNT3. As a result, the power supply potential VDD2 and the ground potential VSS are selectively supplied to the substrate gate of the P-channel MISFET2 and the substrate gate of the N-channel MISFET3, respectively. The threshold voltages of the P-channel MISFET2 and the N-channel MISFET3 in the normal operation mode are made smaller than the threshold voltages of the P-channel MISFET2 and the N-channel MISFET3 in the standby operation mode.

[0046] In the boost operation mode, the third switch element SW3 is turned on by, for example, a high level (selection level) of the control signal CNT3. At this time, the first switch element SW1 is turned off by, for example, a low level (non-selection level) of the control signal CNT1, and the second switch element SW2 is turned off by, for example, a low level (non-selection level) of the control signal CNT2. As a result, the second substrate bias voltage VBN and the first substrate bias voltage VBP are selectively supplied to the substrate gate of the P-channel MISFET2 and the substrate gate of the N-channel MISFET3, respectively. That is, in the boost operation mode, the substrate gate of the P-channel MISFET2 and the substrate gate of the N-channel MISFET3 are forward biased, and the threshold voltage of the P-channel MISFET2 and the threshold voltage of the N-channel MISFET3 are made smaller than the threshold voltage of the P-channel MISFET2 and the threshold voltage of the N-channel MISFET3 in the normal operation mode. The boost operation mode is an operation mode that places importance on the operation speed.

[0047] 4) The semiconductor device 1a is provided with a power management circuit (also called a power management unit) PMU. The system logic circuit SL can control the signal levels (high level and low level) of the control signals CNT1, CNT2, and CNT3 based on signals from the power management circuit (also called a power management unit) PMU. The power management circuit PMU can select the operation mode of the large scale logic circuit CLC from a normal operation mode, a standby operation mode, and a boost operation mode.

[0048] 5) The system logic circuit SL generates a start-up signal VBB_EN for the substrate bias generating circuit BBG based on the power-on reset signal POR supplied from the power management circuit PMU, and supplies the generated start-up signal VBB_EN to the substrate bias generating circuit BBG. The substrate bias generating circuit BBG is configured to start generating the first substrate bias voltage VBP and the second substrate bias voltage VBN based on the start-up signal VBB_EN.

[0049] 6) The system logic circuit SL generates the control signals CNT1, CNT2, and CNT3 and controls the switch circuit SWC based on the comparison result CMPOUT of high level H from the substrate bias generating circuit BBG. The comparison result CMPOUT of high level H can also be regarded as a setup completion signal for the substrate bias generating circuit BBG.

[0050] Next, an example of the operation of the semiconductor device 1a will be described with reference to FIG.

[0051] When the power-on reset signal POR supplied from the power management circuit PMU changes from high level to low level, the system logic circuit SL changes the activation signal VBB_EN of the substrate bias generating circuit BBG from low level to high level.

[0052] The substrate bias generating circuit BBG starts generating the first substrate bias voltage VBP and the second substrate bias voltage VBN based on the high level start signal VBB_EN.

[0053] The frequency FVBP is the change in the oscillation frequency FCLKP of the first oscillation circuit OSC1, and the frequency FVBN is the change in the oscillation frequency FCLKN of the second oscillation circuit OSC2. The frequencies FVBP and FVBN are counted by the counter logic circuit block CL. The counter logic circuit block CL operates at high speed (several MHz) during the charging period of the first charge pump CP1 and the second charge pump CP2. When charging is completed and the voltages (VBP, VBN) generated by the first charge pump CP1 and the second charge pump CP2 stabilize, the counter logic circuit block CL operates at several tens of kHz.

[0054] When the second clock signal CLKN of the second frequency FCLKN is 4 to 16 (4 to 16 pulses) during an 8 count period of the first clock signal CLKP of the first frequency FCLKP (the period of the high level H of the FCLK_8 signal) (i.e., when the voltage values ​​of the first substrate bias voltage VBP and the second substrate bias voltage VBN are normal), the value of the comparison result CMPOUT changes from low level L to high level H (CMPOUT=H).

[0055] In this example, the time from when the activation signal VBB_EN changes to high level to when the comparison result CMPOUT changes to high level H (the time from when the substrate bias generating circuit BBG starts up to when charging is completed, or the time until the voltages (VBP, VBN) stabilize) is set to 40 ms to 300 ms, depending on the value of the parasitic capacitance CEXT.

[0056] In response to the change in the value of the comparison result CMPOUT from low level L to high level H (CMPOUT=H), the control signal CNT2 changes from low level to high level, causing voltages (VBP, VBN) to be supplied to the substrate gates of the P-channel MISFET2 and N-channel MISFET3 constituting the large scale logic circuit CLC.

[0057] (Application Example 2 of Example 1) Fig. 8 is a block diagram showing a configuration example of a semiconductor device 1b according to application example 2 of embodiment 1. Fig. 9 is a diagram for explaining an operation example of the semiconductor device 1b of Fig. 8.

[0058] The following mainly describes the differences between the semiconductor device 1b in FIG. 8 and the semiconductor device 1a in FIG.

[0059] 1) The second resistor element R2 is composed of a variable resistor element, and is configured so that the value of the second resistor element R2 can be determined based on the code value of the trim signal (also called the trimming signal) TRIM output from the system logic circuit SL.

[0060] 2) A resistor (shunt resistor) RSH is provided at each of node N1 at the output of the first charge pump CP1 and node N2 at the output of the second charge pump CP2 via a switch element SW4. The switch element SW4 is controlled by a control signal CNT4 output from the system logic circuit SL. For example, when transitioning from a boost operation mode (operation mode prioritizing speed) to a normal operation mode (operation mode capable of suppressing leakage current at a medium speed), the operation of the switch element SW4 is controlled so that it is temporarily turned on.

[0061] Next, an operation example of the semiconductor device 1b will be described with reference to Fig. 9. Here, a case where the operation mode of the semiconductor device 1b transitions from the boost operation mode to the normal operation mode will be described as an operation example.

[0062] In the boost operation mode, it is assumed that the second resistor element R2 is set to a resistance value according to the code value (code 1) of the trim signal TRIM output from the system logic circuit SL.

[0063] To transition from the boost operation mode to the normal operation mode, the system logic circuit SL changes the code value of the trim signal TRIM from code 1 to code 2. As a result, the first oscillation circuit OSC1 and the second oscillation circuit OSC2 stop operating, and the frequency FVBP of the first oscillation circuit OSC1 and the frequency FVBN of the second oscillation circuit OSC2 temporarily become 0 Hz.

[0064] The system logic circuit SL also sets the control signal CNT4 to a high level to turn on the switch element SW4. As a result, the output potentials VBP, VBN of the first charge pump CP1 and the second charge pump CP2 change toward 0V. Here, the comparison result CMPOUT of high level H is not updated until the oscillation operations of the first oscillation circuit OSC1 and the second oscillation circuit OSC2 are resumed, even if the frequency FVBP of the first oscillation circuit OSC1 and the frequency FVBN of the second oscillation circuit OSC2 become 0Hz.

[0065] The first oscillation circuit OSC1 and the second oscillation circuit OSC2 resume the oscillation operation when the voltage falls below a voltage determined by the resistance value of the second resistor element R2 specified by the code value (code 2) of the trim signal TRIM. When the oscillation operation of the first oscillation circuit OSC1 and the second oscillation circuit OSC2 resumes, the level of the comparison result CMPOUT changes from high level H to low level L. Accordingly, the system logic circuit SL sets the control signal CNT4 to low level to turn off the switch element SW4.

[0066] The frequencies FVBP and FVBN are counted by the counter logic circuit block CL. The counter logic circuit block CL operates at high speed (several MHz) during the charging period of the first charge pump CP1 and the second charge pump CP2. When charging is completed and the voltages (VBP, VBN) generated by the first charge pump CP1 and the second charge pump CP2 stabilize, the counter logic circuit block CL operates at several tens of kHz.

[0067] When the second clock signal CLKN of the second frequency FCLKN is 4 to 16 (4 to 16 pulses) during an 8-count period of the first clock signal CLKP of the first frequency FCLKP (period of high level H of the FCLK_8 signal) (that is, when the voltage values ​​of the first substrate bias voltage VBP and the second substrate bias voltage VBN are normal), the value of the comparison result CMPOUT changes from low level L to high level H (CMPOUT=H). As a result, the operation mode of the semiconductor device 1b transitions from the boost operation mode to the normal operation mode.

[0068] In this way, in the boost operation mode, a high forward bias (FB) is set in order to reduce the threshold voltage of the P-channel MISFET2 and the N-channel MISFET3 constituting the large scale logic circuit CLC to increase the speed. At this time, in a state where high speed operation is not required (normal operation mode other than the boost operation mode or standby operation mode), it is necessary to reduce the voltage of the forward bias (FB) in order to suppress the leakage current, and this can be determined including the control timing of the shunt switch (SW4). Therefore, this embodiment is effective in order to perform a high speed transition of the operation mode.

[0069] In the above embodiment 1, both abnormal voltage and abnormal current of the substrate bias voltages (VBP, VBN) can be detected, and an alarm can be issued before a malfunction occurs. Examples of abnormal current include when the insulating film box is broken, when a foreign object adheres to the wiring of either of the substrate bias voltages (VBP, VBN) (or to the terminal if it is an external output), and when the current consumption specification of the microcontroller unit MCU is exceeded and the guaranteed period of battery operation falls short. When leakage occurs in both substrate bias voltages (VBP, VBN), it can be detected if there is a difference in the amount of leakage.

[0070] It is possible to detect malfunctions of the P-channel MISFET2 and N-channel MISFET3 caused by destruction of the insulating film box. It is also possible to issue an alarm before malfunction occurs. This makes it possible to send an alarm to the host from edge terminals in the IoT (Internet of Things) field.

[0071] It is necessary to secure an offset voltage due to mismatches in the comparators, and the dead band of the voltage to be detected is large (for example, a difference of ±30 mV). As the power supply voltage becomes lower, it is necessary to further increase the dead band, and the required voltage precision may not be satisfied. On the other hand, in this embodiment, the circuit that converts the voltage used for feedback into a frequency (i.e., the first oscillator circuit OSC1 and the second oscillator circuit OSC2) is common, so the mismatch can be ignored.

[0072] Fig. 10 is a diagram for explaining the operation of the oscillator circuits (OSC1, OSC2). In Fig. 10, the vertical axis indicates frequency (Freq) and the horizontal axis indicates the input potential difference. As shown in Fig. 10, the slope Kvco allows for high gain, and the dead band of the detection level can be set to ±1mV or less.

[0073] Since the frequency is determined by the input difference between the oscillator circuits (OSC1, OSC2), it is not affected by the high and low set voltages of the first substrate bias voltage VBP and the second substrate bias voltage VBN. This embodiment has the following advantages, and the counter logic circuit block CL can be used as a detection circuit, regardless of the high and low set voltages of the first substrate bias voltage VBP and the second substrate bias voltage VBN.

[0074] 1) The feedback oscillator circuits (OSC1, OSC2) convert the potential difference into a frequency, and the converted frequency is used in the detection circuit (counter logic circuit block CL), so there is no mismatch like in a comparator.

[0075] 2) The voltage difference between the inputs of the oscillator circuits (OSC1, OSC2) is multiplied by 1 / Kvco, so the dead band is small. The dead band can be made less than ±1mV.

[0076] 3) The frequency of the oscillator circuits (OSC1, OSC2) is determined by (I = C × V × Freq), and the variation in capacitance C and voltage V is generally around ±20%, so the frequency variation is small.

[0077] 4) The completion of charging the first substrate bias voltage VBP and the second substrate bias voltage VBN can be detected in several μs. EXAMPLES

[0078] Fig. 11 is a diagram illustrating an example of the configuration of a substrate bias generating circuit BBG2 according to Example 2. Fig. 12 is a diagram illustrating the relationship between the frequency FOSC, the first frequency FCLKP, and the second frequency FCLKN.

[0079] In the first embodiment shown in FIG. 1, two oscillator circuits (OSC1, OSC2) are used, but in the substrate bias generating circuit BBG2 of the second embodiment, as shown in FIG. 11, one oscillator circuit OSC1 is used. For this purpose, a first gating circuit (first gate circuit) GT1 and a second gating circuit (second gate circuit) GT2 are provided in the front stage of the first charge pump CP1, which is a step-up circuit, and in the front stage of the second charge pump CP2, which is a step-down circuit, respectively, to gate and stop the clock signal CLK with the frequency FOSC oscillated from the oscillator circuit OSC1. The first gating circuit GT1 outputs a first clock signal CLKP with a first frequency FCLKP. The second gating circuit GT2 outputs a second clock signal CLKN with a second frequency FCLKN.

[0080] 12 shows the relationship between the frequency FOSC of the clock signal CLK oscillated by the oscillator circuit OSC1, the first frequency FCLKP of the first clock signal CLKP output by the first gating circuit GT1, and the second frequency FCLKN of the second clock signal CLKN output by the second gating circuit GT2. In this example, the first gating circuit GT1 generates the first frequency FCLKP by gating the four consecutive clocks of the frequency FOSC so as to pass the first two clocks (first and second) and not pass the last two clocks (third and fourth). In this example, the second gating circuit GT2 generates the second frequency FCLKN by gating the four consecutive clocks of the frequency FOSC so as to pass the first clock (first) and the last clock (fourth) and not pass the two clocks (second and third) between the first clock (first) and the last clock (fourth).

[0081] According to the second embodiment, there is an advantage that the number of oscillation circuits provided in the substrate bias generating circuit BBG2 can be reduced to one. EXAMPLES

[0082] Fig. 13 is a diagram illustrating an example of the configuration of a substrate bias generating circuit BBG3 according to Example 3. Fig. 14 is a diagram illustrating the relationship between the first frequency FCLKP and the second frequency FCLKN.

[0083] The third embodiment is an example of the configuration of a substrate bias generating circuit BBG3 in which one gating circuit is further deleted from the configuration of the substrate bias generating circuit BBG2 in the second embodiment. By utilizing the fact that the clock required for the second frequency FCLKN is lower than the first frequency FCLKP, a second gating circuit (second gate circuit) GT2 having a function of gating and stopping the first clock signal CLKP of the first frequency FCLKP can be inserted, and the number of oscillation circuits can be reduced to one.

[0084] The first oscillator circuit OSC1 generates a first clock signal CLKP having a first frequency FCLKP. The second gating circuit GT2 gates the first clock signal CLKP having the first frequency FCLKP and outputs a second clock signal CLKN having a second frequency FCLKN.

[0085] 14 shows the relationship between the first frequency FCLKP of the first clock signal CLKP oscillated by the oscillator circuit OSC1 and the second frequency FCLKN of the second clock signal CLKN output by the second gating circuit GT2. In this example, the second gating circuit GT2 generates the second frequency FCLKN by gating the first four (first, second, third, and fourth) clocks of the five consecutive clocks of the first frequency FCLKP to pass and not to pass the last clock (the fifth clock).

[0086] According to the third embodiment, there is an advantage that the number of oscillation circuits provided in the substrate bias generating circuit BBG3 can be reduced to one, and the number of gating circuits can also be reduced to one. EXAMPLES

[0087] FIG. 15 is a diagram showing a configuration example of a substrate bias generating circuit BBG4 according to the fourth embodiment.

[0088] The substrate bias generating circuit BBG4 of the embodiment 4 is a configuration example in which a resistive element R5 is provided between the first substrate bias voltage VBP and the second substrate bias voltage VBN of the embodiments 1 to 3. That is, the resistive element R5 is connected between the output of the first charge pump CP1 (or the first output signal line connected to the output terminal of the first charge pump CP1) and the output of the second charge pump CP2 (or the second output signal line connected to the output terminal of the second charge pump CP2).

[0089] In an environment where leakage is extremely small, such as at low temperatures, the leakage current in the first charge pump CP1 and second charge pump CP2, which are step-up / step-down circuits, becomes dominant, and the relationship IVBP / IVBN ≒ A > 1 may not be maintained. To suppress this occurrence, a resistive element R5 is provided between the first substrate bias voltage VBP and the second substrate bias voltage VBN, making it possible to set a minimum current for IVBP / IVBN. Here, IVBP is the current that flows from the output of the first charge pump CP1 to the substrate gate side of the P-channel MISFET2. IVBN is the current that flows from the output of the second charge pump CP2 to the substrate gate side of the N-channel MISFET3. EXAMPLES

[0090] FIG. 16 is a diagram showing a configuration example of a substrate bias generating circuit BBG5 according to a fifth embodiment. FIG. 17 is a diagram showing characteristics of the substrate bias generating circuit BBG5 of FIG. 16. FIG. 18 is a diagram showing the dependency of the second substrate bias voltage VBN on the set value of the first substrate bias voltage VBP. FIG. 19 is a diagram explaining the case where an abnormal current (leak) flows from the first substrate bias voltage VBP to the second substrate bias voltage VBN. FIG. 20 is a diagram explaining the layout arrangement of the terminal pad of the first substrate bias voltage VBP and the terminal pad of the second substrate bias voltage VBN.

[0091] 16, in the substrate bias generating circuit BBG5 according to the fifth embodiment, the resistive element R5 in the fourth embodiment is changed to resistive elements R3 and R4. In the substrate bias generating circuit BBG5 according to the first and fourth embodiments, the voltage (VFBN) used for feedback control of the second oscillation circuit OSC2 is taken from the intermediate voltage Vi between the resistive elements R3 and R4.

[0092] Generally, the second substrate bias voltage VBN is a negative potential, so the intermediate voltage Vi(VFBN) generated by the resistor elements R3 and R4 is compared with the reference voltage VREF by the second oscillator circuit OSC2 to determine the set voltage of the second substrate bias voltage VBN.

[0093] By adopting the configuration of the fifth embodiment, the second substrate bias voltage VBN has a characteristic that depends on the first substrate bias voltage VBP (see formula 1).

[0094] VBN=VBP-((R3+R4) / R3)×(VBP-VREF) Equation 1 17, due to this characteristic, the second substrate bias voltage VBN does not depend on the capacity of the step-down side second charge pump CP2, and the charging start time of the first substrate bias voltage VBP is delayed, and the charging completion timing is also delayed. Therefore, it is possible to prevent the frequency ratio from erroneously falling within the specified range during the transition.

[0095] Moreover, as shown in FIG. 18, by utilizing this characteristic and changing the set value of the target voltage on the side of the first substrate bias voltage VBP, the second substrate bias voltage VBN can be changed in conjunction therewith.

[0096] 19, when an abnormality is detected, if an abnormal current (leak) flows from the first substrate bias voltage VBP to the second substrate bias voltage VBN (leakage in the path from VBP to VBN), the leakage current increases equally, and the output clocks (FVBP, FVBN) of the first oscillation circuit OSC1 and the second oscillation circuit OSC2 also change at the same rate. For this reason, even in the present invention, it is not possible to detect leakage in the path from VBP to VBN.

[0097] Therefore, in the layout arrangement of the substrate bias generating circuit BBG5, it is effective to eliminate adjacent arrangement locations. For example, as shown in Fig. 20, in the layout arrangement of the terminal pad Pad_VBP of the first substrate bias voltage VBP and the terminal pad Pad_VBN of the second substrate bias voltage VBN, it is effective to arrange the terminal pad Pad_GND of the ground potential GND (VSS) or another terminal pad Pad_X between the terminal pad Pad_VBP and the terminal pad Pad_VBN, rather than arranging the terminal pad Pad_VBP and the terminal pad Pad_VBN adjacent to each other.

[0098] The invention made by the present inventor has been specifically described above based on examples. However, it goes without saying that the present invention is not limited to the above-mentioned embodiments and examples, and various modifications are possible. [Explanation of symbols]

[0099] 1: Semiconductor device 2: P-channel MISFET 3: N-channel MISFET BBG: Substrate bias generation circuit OSC1: First oscillator circuit OSC2: Second oscillator circuit CP1: 1st charge pump (boost circuit) CP2: Second charge pump (step-down circuit) CL: Counter logic circuit block (logic circuit block) CLC: Large scale logic circuit (core logic circuit)

Claims

1. a boost circuit that outputs a boosted voltage based on a first clock signal having a first frequency; a step-down circuit that outputs a step-down voltage based on a second clock signal having a second frequency; a logic circuit block that compares the first frequency with the second frequency and outputs a comparison result between the first frequency and the second frequency in accordance with a predefined criterion; 13. A semiconductor device comprising:

2. 2. The semiconductor device according to claim 1, a first oscillator circuit that outputs the first clock signal having the first frequency; a second oscillator circuit that outputs the second clock signal having the second frequency; 13. A semiconductor device comprising:

3. 2. The semiconductor device according to claim 1, a first oscillator circuit that outputs the first clock signal having the first frequency; a first gating circuit that gates the first clock signal of the first frequency to output the second clock signal of the second frequency.

4. 2. The semiconductor device according to claim 1, A first oscillator circuit; a first gating circuit that gates an output of the first oscillation circuit to output the first clock signal having the first frequency; a second gating circuit that gates the output of the first oscillation circuit to output the second clock signal of the second frequency.

5. 3. The semiconductor device according to claim 2, The semiconductor device further comprises a resistor element provided between an output of the step-up circuit and an output of the step-down circuit.

6. 6. The semiconductor device according to claim 5, the resistive element includes a first resistive element and a second resistive element; The second oscillator circuit generates the second frequency of the second clock signal based on a comparison between a reference voltage and an intermediate voltage at a connection point between the first resistive element and the second resistive element.

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