Semiconductor device and its manufacturing method

Abstract

A semiconductor device according to the present disclosure is provided with: a substrate; a bonding member that is arranged on the surface of the substrate; a first chip that is superposed on the bonding member, with a first adhesive piece being interposed therebetween; and a second chip that is superposed on the first chip, with a second adhesive piece being interposed therebetween. The bonding member has a multilayer structure which contains a pair of surface layers that are formed of a cured product of a thermosetting resin composition, and an intermediate layer that is arranged between the pair of surface layers.

Description

[Technical field]

[0001] The present disclosure relates to a semiconductor device and a manufacturing method thereof. [Background technology]

[0002] A semiconductor device is manufactured through the following steps: First, a semiconductor wafer is fixed with a dicing adhesive sheet, and then the semiconductor wafer is divided into individual semiconductor chips in this state. Then, an expanding step, a pick-up step, a die bonding step, a reflow step, and the like are performed.

[0003] One of the important characteristics required for semiconductor devices is connection reliability. In order to improve connection reliability, film-like adhesives for die bonding that take into consideration properties such as heat resistance, moisture resistance, and reflow resistance have been developed. For example, Patent Document 1 discloses an adhesive sheet that contains a resin containing a high molecular weight component and a thermosetting component mainly composed of an epoxy resin, and a filler. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] International Publication No. 2005 / 103180 Summary of the Invention [Problem to be solved by the invention]

[0005] The present inventors are developing a process for efficiently manufacturing semiconductor devices (e.g., 3D NAND type memories) with high capacity by stacking semiconductor chips (hereinafter, simply referred to as "chips") in multiple stages. 3D NAND wafers consist of a complex circuit layer and a relatively thin semiconductor layer (e.g., about 15 to 25 μm), and therefore have the problem that the semiconductor elements obtained by dicing the wafers are prone to warping.

[0006] Fig. 17(a) is a cross-sectional view showing a structure in a manufacturing process of a semiconductor device. The structure 30 shown in Fig. 17(a) includes a substrate 10 and four chips T1, T2, T3, and T4 stacked on the substrate. The four chips T1, T2, T3, and T4 are stacked at positions shifted from each other in the horizontal direction (direction perpendicular to the stacking direction) for electrical connection by wires. The chip T1 is adhered to the substrate 10 by an adhesive piece A1, and adhesive pieces A2, A3, and A4 are interposed between the semiconductor elements T1, T2, T3, and T4.

[0007] According to the inventors' study, when the chips T1, T2, T3, and T4 each have a complex circuit layer (upper surface side) and a relatively thin semiconductor layer (lower surface side), peeling is likely to occur between the first-stage chip T1 and the adhesive piece A2, as shown in Fig. 17(b). The inventors speculate on the cause of this as follows. Due to the complex circuit layers and thin semiconductor layers, as described above, the semiconductor elements T1, T2, T3, and T4 have a tendency to be easily warped (warping stress). Overhang H is formed by stacking multiple chips with their positions shifted laterally. Since it has been confirmed that peeling will not occur when the second-tier chip T2 is mounted, mounting the third and fourth-tier chips T2 and T3 increases the upward force on the overhang portion H of the second-tier chip T2 (warping stress in the direction that causes peeling between the chip T1 and the first-tier chip T1).

[0008] The present disclosure provides a semiconductor device including a plurality of stacked chips, in which peeling caused by warping of the chips inside the semiconductor device can be sufficiently suppressed, and a method for efficiently manufacturing the same. [Means for solving the problem]

[0009] A first aspect of the semiconductor device of the present disclosure comprises a substrate, an adhesive member disposed on a surface of the substrate, a first chip laminated to the adhesive member via a first adhesive piece, and a second chip laminated to the first chip via a second adhesive piece, the adhesive member having a multilayer structure including a pair of surface layers made of a cured product of a thermosetting resin composition and an intermediate layer disposed between the pair of surface layers.

[0010] According to the semiconductor device of the first aspect, the interface where the warpage stress is likely to concentrate is constituted by the adhesive member and the first adhesive piece, so that a sufficiently high adhesive strength can be obtained, and peeling at this interface can be suppressed. In addition, as described above, the adhesive member has a multilayer structure including a pair of surface layers made of a cured product of a thermosetting resin composition and an intermediate layer disposed between the pair of surface layers, so that the warpage of the chip itself can be suppressed even if the adhesive member is made relatively thick. That is, compared to the case where the entire adhesive member is made of a thermosetting resin composition, the presence of the intermediate layer in the thickness direction can suppress the thickness of the adhesive member from becoming uneven due to the warpage stress of the chip in the process of stacking multiple chips.

[0011] A second aspect of the semiconductor device of the present disclosure comprises a substrate, a chip (e.g., a controller chip) arranged on a surface of the substrate, a plurality of support pieces arranged around the chip on the surface of the substrate, an adhesive member supported by the plurality of support pieces and arranged to cover the chip, and a first chip laminated to the adhesive member via a first adhesive piece, wherein the adhesive member has a multilayer structure including a pair of surface layers made of a cured product of a thermosetting resin composition and an intermediate layer arranged between the pair of surface layers.

[0012] According to the semiconductor device of the second aspect, the interface where warpage stress is likely to concentrate is formed by the adhesive member and the first adhesive piece, so that a sufficiently high adhesive strength can be obtained and peeling can be suppressed at this interface. Also, according to the semiconductor device of the second aspect, the first chip is arranged so as to cover a chip (e.g., a controller chip), so that space can be saved. Furthermore, as in the first aspect, the adhesive member has a multi-layer structure, so that warpage of the chip itself can be suppressed. This semiconductor device may further include a second chip stacked on the first chip via the second adhesive piece.

[0013] A third aspect of the semiconductor device of the present disclosure includes a substrate, a chip with a first adhesive piece arranged on the surface of the substrate, an adhesive member arranged on the surface of the adhesive piece of the chip with the first adhesive piece, and a chip with a second adhesive piece arranged on the surface of the adhesive member, and the adhesive member has a multi-layer structure including a pair of surface layers made of a cured product of a thermosetting resin composition and an intermediate layer arranged between the pair of surface layers. According to this semiconductor device, the interface where the warping stress is likely to concentrate is composed of the adhesive member and the adhesive piece, so that a sufficiently high adhesive strength can be obtained and peeling can be suppressed at this interface. Also, as in the first aspect, the adhesive member has a multi-layer structure, so that the warping of the chip itself can be suppressed.

[0014] The manufacturing method of a semiconductor device according to the present disclosure includes a step of stacking a first chip on a surface of an adhesive member via a first adhesive piece, and a step of stacking a second chip on the surface of the first chip via a second adhesive piece, wherein the first and second adhesive pieces are made of a thermosetting resin composition, the adhesive member has a multilayer structure including a pair of surface layers made of the thermosetting resin composition and an intermediate layer disposed between the pair of surface layers, and a curing process of the adhesive member, the first adhesive piece, and the second adhesive piece is performed simultaneously.

[0015] According to the above manufacturing method, the first chip is stacked on the surface of the adhesive member via the first adhesive piece, so that the interface where warping stress is likely to concentrate can be formed by the adhesive member and the first adhesive piece. Therefore, when stacking chips above the first chip, even if the adhesive piece is not cured each time a chip is stacked, but a predetermined number of chips are stacked and then cured all at once, peeling at the interface can be sufficiently suppressed. The ability to cure multiple adhesive pieces between multiple stacked chips all at once contributes to improving the manufacturing efficiency of semiconductor devices.

[0016] In the present disclosure, the intermediate layer of the adhesive member is, for example, a polyimide layer or a metal layer from the standpoint of strength, heat resistance, and the like. Effect of the Invention

[0017] According to the present disclosure, there is provided a semiconductor device having a plurality of stacked chips, in which peeling caused by warping of the chips within the semiconductor device can be sufficiently suppressed, and a method for efficiently manufacturing the same is provided. [Brief description of the drawings]

[0018] [Figure 1] FIG. 1 is a cross-sectional view illustrating a schematic diagram of a first embodiment of a semiconductor device according to the present disclosure. [Diagram 2] FIG. 2(a) is a plan view that shows a schematic diagram of one example of the laminated film for forming an adhesive member, and FIG. 2(b) is a cross-sectional view taken along line bb in FIG. 2(a). [Diagram 3] FIG. 3 is a cross-sectional view that typically illustrates a step of bonding an adhesive layer and an adhesive member-forming laminate film together. [Figure 4] 4(a) to 4(d) are cross-sectional views that typically show the process of producing an adhesive member. [Diagram 5] FIG. 5 is a cross-sectional view showing a schematic example of a chip with an adhesive piece. [Figure 6] 6A to 6C are cross-sectional views that diagrammatically show the process of manufacturing the semiconductor device shown in FIG. [Figure 7] 7A to 7C are cross-sectional views that diagrammatically show the process of manufacturing the semiconductor device shown in FIG. [Figure 8] 8A to 8C are cross-sectional views that diagrammatically show the process of manufacturing the semiconductor device shown in FIG. [Figure 9] 9A to 9C are cross-sectional views that diagrammatically show the process of manufacturing the semiconductor device shown in FIG. [Figure 10] FIG. 10 is a cross-sectional view illustrating a schematic diagram of a second embodiment of a semiconductor device according to the present disclosure. [Figure 11] 11(a) and 11(b) are plan views each showing a schematic example of the positional relationship between a chip and a plurality of support pieces. [Figure 12] 12A to 12C are cross-sectional views that diagrammatically show the process of manufacturing the semiconductor device shown in FIG. [Figure 13] 13A to 13C are cross-sectional views that diagrammatically show the process of manufacturing the semiconductor device shown in FIG. [Figure 14] 14A to 14C are cross-sectional views that diagrammatically show the process of manufacturing the semiconductor device shown in FIG. [Figure 15] 15A to 15C are cross-sectional views that diagrammatically show the process of manufacturing the semiconductor device shown in FIG. [Figure 16] FIG. 16 is a cross-sectional view illustrating a schematic diagram of a third embodiment of a semiconductor device according to the present disclosure. [Figure 17] FIG. 17(a) is a cross-sectional view showing a schematic diagram of a process for manufacturing a semiconductor device, and FIG. 17(b) is a cross-sectional view showing a structure in which peeling has occurred between a first-stage semiconductor element and a second-stage semiconductor element. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0019] Hereinafter, the embodiments of the present disclosure will be described in detail with reference to the drawings. In the following description, the same or equivalent parts are given the same reference numerals, and duplicated descriptions will be omitted. Furthermore, unless otherwise specified, the positional relationships such as up, down, left, and right are based on the positional relationships shown in the drawings. Furthermore, the dimensional ratios of the drawings are not limited to the ratios shown in the drawings. In this specification, the term "(meth)acrylic" means "acrylic" and the corresponding "methacrylic".

[0020] First Embodiment [Semiconductor Devices] FIG. 1 is a cross-sectional view showing a schematic diagram of a semiconductor device according to the present embodiment. The semiconductor device 100 shown in this figure is, for example, a three-dimensional NAND type memory. The semiconductor device 100 includes a substrate 10, a controller chip Tc arranged on the surface of the substrate 10, an adhesive member 15 arranged on the surface of the substrate 10, five chips T1, T2, T3, T4, and T5 stacked on the surface of the adhesive member 15, wires Wa and Wb that electrically connect the electrodes 10a and 10b on the surface of the substrate 10 to the chips, and a sealing layer 50 that seals them. An adhesive piece A1 (first adhesive piece) is arranged between the adhesive member 15 and the chip T1 (first chip). An adhesive piece A2 (second adhesive piece) is arranged between the chip T1 and the chip T2 (second chip). An adhesive piece A3 is arranged between the chip T2 and the chip T3. An adhesive piece A4 is arranged between the chip T3 and the chip T4. An adhesive piece A5 is arranged between the chip T4 and the chip T5. 1, the side (part of the periphery) of chip T1 protrudes laterally beyond adhesive member 15. Also, the side (part of the periphery) of an upper chip (e.g., chip T2) protrudes laterally beyond the chip below it (e.g., chip T1). These constitute overhang portion H.

[0021] The substrate 10 may be an organic substrate or a metal substrate such as a lead frame. From the viewpoint of suppressing warpage of the semiconductor device 100, the thickness of the substrate 10 is, for example, 90 to 300 μm, and may be 90 to 210 μm.

[0022] The controller chip Tc is adhered to the substrate 10 by an adhesive piece Ac and is electrically connected to the electrodes 10a by wires Wa. The shape of the controller chip Tc in a plan view is, for example, a rectangle (square or oblong). The length of one side of the controller chip Tc is, for example, 5 mm or less and may be 2 to 5 mm or 1 to 5 mm. The thickness of the controller chip Tc is, for example, 10 to 150 μm and may be 20 to 100 μm. The thickness of the adhesive piece Ac is, for example, 5 to 40 μm and may be 10 to 25 μm. The sum of the thickness of the controller chip Tc and the thickness of the adhesive piece Ac (the distance from the upper surface of the substrate 10 to the upper surface of the controller chip Tc) is, for example, 25 to 190 μm and may be 30 to 125 μm.

[0023] The adhesive member 15 has a three-layer structure including a pair of surface layers 15a, 15a and an intermediate layer 15b disposed therebetween. The pair of surface layers 15a, 15a are both made of a cured product of a thermosetting resin composition having adhesive properties. The surface layer 15a bonds the chip T1 to the substrate 10 via the adhesive piece A1. In this embodiment, since the interface where warping stress is likely to occur is composed of the adhesive member 15 and the adhesive piece A1, peeling at this interface can be sufficiently suppressed. Since the adhesive member 15 has a multi-layer structure, even if the adhesive member 15 is made relatively thick, the warping of the chip itself can be suppressed. In other words, compared to the case where the entire adhesive member is made of a thermosetting resin composition, the presence of the intermediate layer 15b in the thickness direction can suppress the thickness of the adhesive member 15 from becoming uneven due to the warping stress of the chips T1, T2, T3, T4, T5 in the process of sequentially stacking the chips T1, T2, T3, T4, T5.

[0024] The total thickness of the adhesive member 15 is, for example, 35 to 150 μm, and may be 70 to 90 μm or 40 to 60 μm. The adhesive member 15 is preferably thicker than the sum of the thickness of the controller chip Tc and the thickness of the adhesive piece Ac. This allows the controller chip Tc to be disposed on the surface of the substrate 10 near the overhang portion H side of the chips T1, T2, T3, T4, and T5, and to be connected to the electrode 10a by the wire Wa.

[0025] The thickness of the surface layer 15a is, for example, 5 to 40 μm, and may be 5 to 25 μm or 5 to 20 μm. The thicknesses of the two surface layers 15a may be the same or different. The surface layer 15a is made of a thermosetting resin composition. The thermosetting resin composition can be in a semi-cured (B stage) state and then in a completely cured (C stage) state by a subsequent curing process. The thermosetting resin composition contains an epoxy resin, a curing agent, and an elastomer (e.g., acrylic resin), and further contains an inorganic filler, a curing accelerator, and the like, as necessary. The compositions of the two surface layers 15a may be the same or different.

[0026] The thickness of the intermediate layer 15b is, for example, 5 to 75 μm, and may be 10 to 75 μm or 10 to 50 μm. The intermediate layer 15b is preferably made of a material having a sufficiently high mechanical strength. Specific examples of the material include resins such as polyimide and polyethylene terephthalate (PET), and metals such as copper and aluminum. The tensile modulus of the material constituting the intermediate layer 15b is, for example, 8.0 MPa or more, and may be 9.0 MPa or more or 10.0 MPa or more. When the intermediate layer 15b is made of a resin material, the intermediate layer 15b is made of a material different from the resin material constituting the surface layer 15a. By having a plurality of layers made of different materials, the adhesive member 15 can be assigned a function to each layer, and the adhesive member can have a higher function than one made of a plurality of layers made of the same material.

[0027] (Method of manufacturing adhesive member) An example of a method for producing an adhesive member will be described. Note that the surface layer 15a shown in Fig. 1 is in a state after the thermosetting resin composition constituting it has hardened. On the other hand, the surface layer 15P and the surface layer 15p obtained by cutting it into individual pieces are in a state before the thermosetting resin composition contained therein has completely hardened (see Figs. 2(b) and 4(b)).

[0028] First, a laminated film 20 for forming an adhesive member (hereinafter, sometimes referred to as "laminated film 20") shown in Fig. 2(a) and Fig. 2(b) is prepared. The laminated film 20 includes a base film 1, an adhesive layer 2, and an adhesive film 15F. The base film 1 is, for example, a polyethylene terephthalate film (PET film). The adhesive layer 2 is formed into a circle by punching or the like (see Fig. 2(a)). The adhesive layer 2 is made of, for example, an ultraviolet-curing adhesive. This adhesive layer 2 has a property that its adhesiveness decreases when irradiated with ultraviolet light. The adhesive film 15F is formed into a circle by punching or the like, and has a smaller diameter than the adhesive layer 2 (see Fig. 2(a)).

[0029] The adhesive film 15F is composed of a pair of surface layers 15P made of a thermosetting resin layer and an intermediate layer 15B sandwiched between them. The thickness of the surface layer 15P is substantially the same as that of the above-mentioned surface layer 15a, and may be, for example, 5 to 40 μm, 5 to 25 μm, or 5 to 20 μm. The thickness of the intermediate layer 15B is the same as that of the above-mentioned intermediate layer 15b, and may be, for example, 5 to 75 μm, 10 to 75 μm, or 10 to 50 μm. The tensile modulus of the intermediate layer 15B may be, for example, 8.0 MPa or more, 9.0 MPa or more, or 10.0 MPa or more. When the tensile modulus of the intermediate layer 15B is 8.0 MPa or more, the intermediate layer 15b plays a role like a spring plate in the step of picking up the adhesive member 15 (see FIG. 4(d)), and excellent pick-up properties can be achieved. The upper limit of the tensile modulus of the intermediate layer 15B is about 15 MPa in terms of ease of material availability. Examples of materials constituting the intermediate layer 15B include polyimide and polyethylene terephthalate (PET). The intermediate layer 15B may be a layer made of a thermosetting resin composition or a photocurable resin composition that has been cured so that the tensile modulus of elasticity falls within the above range.

[0030] The laminated film 20 can be produced, for example, by bonding a first laminated film having a base film 1 and an adhesive layer 2 on its surface, and a second laminated film having a cover film 3 and an adhesive film 15F on its surface (see FIG. 3). The first laminated film is obtained through a process of forming an adhesive layer on the surface of the base film 1 by coating, and a process of processing the adhesive layer into a predetermined shape (for example, a circle) by punching or the like. The second laminated film is obtained through a process of forming a surface layer 15P on the surface of the cover film 3 (for example, a PET film or a polyethylene film) by coating, a process of forming an intermediate layer 15B on the surface of the surface layer 15P, a process of forming the surface layer 15P on the surface of the intermediate layer 15B by coating, and a process of processing the adhesive film formed through these processes into a predetermined shape (for example, a circle) by punching or the like. When using the laminated film 20, the cover film 3 is peeled off at an appropriate timing.

[0031] As shown in FIG. 4(a), a dicing ring DR is attached to the laminated film 20. That is, the dicing ring DR is attached to the adhesive layer 2 of the laminated film 20, and the adhesive film 15F is arranged inside the dicing ring DR. The adhesive film 15F is divided into individual pieces by dicing (see FIG. 4(b)). As a result, a large number of adhesive members 15 are obtained from the adhesive film 15F. Thereafter, for example, the adhesive layer 2 is irradiated with ultraviolet light to reduce the adhesive force between the adhesive layer 2 and the adhesive members 15. After the ultraviolet light irradiation, the base film 1 is expanded as shown in FIG. 4(c), so that the adhesive members 15 are separated from each other. That is, the inner region of the dicing ring DR in the base film 1 is pushed up by the ring Ra to impart tension to the base film 1, and the adhesive members 15 are separated from each other. As shown in FIG. 4(d), the adhesive member 15 is pushed up by a push-up jig 42 to peel off the adhesive member 15 from the adhesive layer 2, and the adhesive member 15 is picked up by sucking with a suction collet 44. The adhesive film 15F before dicing or the adhesive member 15 before picking up may be heated to allow the curing reaction of the thermosetting resin to proceed. When the adhesive member 15 is picked up, it is possible to achieve excellent pick-up properties by appropriately curing the adhesive member 15. It is preferable that the cut for individualization is formed up to the outer edge of the adhesive member 15. The diameter of the adhesive film 15F may be, for example, 300 to 310 mm or 300 to 305 mm. The shape of the adhesive film 15F in a plan view is not limited to the circle shown in FIG. 2(a) and may be rectangular (square or oblong).

[0032] The chips T1, T2, T3, T4, and T5 shown in FIG. 1 are, for example, memory chips. The shape of the chips T1, T2, T3, T4, and T5 in a plan view is, for example, rectangular (square or oblong). The length of one side of the chips T1, T2, T3, T4, and T5 is, for example, 12 mm or less, and may be 6 to 10 mm or 2 to 4 mm. When the shape of these chips is rectangular, the ratio B / A of the length B of the long side to the length A of the short side is, for example, 1.5 to 4, and may be 1.8 to 3.5, or 2.1 to 3.2. The thickness of the chips T1, T2, T3, T4, and T5 is, for example, 10 to 170 μm, and may be 10 to 30 μm. These chips have a complex circuit layer (upper surface side in FIG. 1) and a relatively thin semiconductor layer (lower surface side in FIG. 1). As the ratio of the thickness of the semiconductor layer to the total thickness of the chip decreases, the chip becomes more susceptible to warping on the smile side (see Figure 17). For example, when this ratio is 80% or less, warping on the smile side is likely to occur. The lengths of each side of the five chips T1, T2, T3, T4, and T5 may be the same or different, and the same applies to their thicknesses. Warping in the smile direction means that the chip warps in a downward convex shape.

[0033] The chips T1, T2, T3, T4, and T5 can be produced, for example, by attaching a dicing-die bonding integrated film to a semiconductor wafer having a circuit surface, and then going through a dicing process and a pick-up process. In this case, a large number of laminates (chips with adhesive pieces) are obtained, each of which is an adhesive piece obtained by singulating the die bonding and a chip obtained by singulating the semiconductor wafer. FIG. 5 is a cross-sectional view showing an example of a chip with adhesive pieces. The chip with adhesive pieces 31 shown in this figure is composed of a chip T1 and an adhesive piece A1 (before hardening) laminated on the surface of the chip T1 opposite to the circuit surface. The lower surface of the chip T1 in FIG. 5 corresponds to the back surface of the chip. In recent years, the back surface of the chip is often formed with unevenness. By substantially covering the entire back surface of the chip T1 with the adhesive piece A1, it is possible to suppress the occurrence of cracks or breakage in the chip T1.

[0034] [Method of manufacturing semiconductor device] The semiconductor device 100 is manufactured through the following steps. (A1) Step of placing a controller chip Tc on the surface of a substrate 10 (see FIG. 6). (B1) Step of disposing an adhesive member 15 on the surface of the substrate 10 (see FIG. 7). Note that the step (B1) may be performed after the step (A1), or the step (A1) may be performed after the step (B1). (C1) Step of laminating an adhesive piece-attached chip 31 on the surface of an adhesive member 15 (see FIG. 8). (D1) Step of stacking multiple chips with adhesive pieces 32, 33, 34, 35 on the surface of chip T1 (see FIG. 9). As described above, the presence of adhesive member 15 can suppress the warping of the chip itself. Therefore, when the chip with adhesive pieces is pressure-bonded onto the surface of the chip, the generation of trap voids due to the warping of the chip can be sufficiently suppressed. (E1) A step of collectively carrying out a hardening treatment on the adhesive member 15 and the plurality of adhesive pieces A1, A2, A3, A4, and A5. (F1) A step of sealing the chips, wires, etc. on the surface of the substrate 10 with a sealing material (see FIG. 1).

[0035] According to the above manufacturing method, the first chip is stacked on the surface of the adhesive member via the first adhesive piece, so that the interface where warping stress is likely to concentrate can be formed by the adhesive member and the first adhesive piece. Therefore, when stacking chips above the first chip, even if the adhesive piece is not cured each time a chip is stacked, but a predetermined number of chips are stacked and then cured all at once, peeling at the interface can be sufficiently suppressed. The ability to cure multiple adhesive pieces between multiple stacked chips all at once contributes to improving the manufacturing efficiency of semiconductor devices.

[0036] (Thermosetting resin composition) The thermosetting resin composition used to form the surface layer 15p of the adhesive member 15 will be described below. As described above, the thermosetting resin composition contains an epoxy resin, a curing agent, and an elastomer, and further contains an inorganic filler and a curing accelerator, etc., as necessary. The surface layer 15p and the surface layer 15a after curing preferably have the following properties. Characteristic 1: When the adhesive member 15 is thermocompression-bonded to a predetermined position on the substrate 10, displacement is unlikely to occur (the melt viscosity of the surface layer 15p at 120°C is, for example, 4300 to 50000 Pa·s or 5000 to 40000 Pa·s). Characteristic 2: The surface layer 15a exhibits stress relaxation properties in the semiconductor device 100 (the thermosetting resin composition contains an elastomer (rubber component)). Characteristic 3: The surface layer 15a has high adhesive strength to the adhesive piece A1 (the die shear strength of the surface layer 15a to the adhesive piece A1 is, for example, 2.0 to 7.0 MPa or 3.0 to 6.0 MPa). Property 4: Shrinkage rate during hardening is sufficiently small Property 5: The adhesive member 15 has good visibility by a camera in the pick-up process (the thermosetting resin composition contains, for example, a coloring agent). Property 6: The surface layer 15a has sufficient mechanical strength.

[0037] [Epoxy resin] The epoxy resin is not particularly limited as long as it has an adhesive action when cured. Bifunctional epoxy resins such as bisphenol A type epoxy resin, bisphenol F type epoxy resin, and bisphenol S type epoxy resin, novolac type epoxy resins such as phenol novolac type epoxy resin and cresol novolac type epoxy resin can be used. In addition, generally known epoxy resins such as multifunctional epoxy resins, glycidylamine type epoxy resins, heterocyclic epoxy resins, and alicyclic epoxy resins can be applied. These may be used alone or in combination of two or more.

[0038] [Hardening agent] Examples of the curing agent include phenolic resins, ester compounds, aromatic amines, aliphatic amines, and acid anhydrides. Among these, phenolic resins are preferred from the viewpoint of achieving high die shear strength. Examples of commercially available phenolic resins include LF-4871 (trade name, BPA novolac type phenolic resin) manufactured by DIC Corporation, HE-100C-30 (trade name, phenylarakyl type phenolic resin) manufactured by Air Water Inc., Phenolite KA and TD series manufactured by DIC Corporation, Milex XLC-series and XL series (e.g., Milex XLC-LL) manufactured by Mitsui Chemicals Inc., HE series (e.g., HE100C-30) manufactured by Air Water Inc., MEHC-7800 series (e.g., MEHC-7800-4S) manufactured by Meiwa Kasei Co., Ltd., and JDPP series manufactured by JEF Chemical Co., Ltd. These may be used alone or in combination of two or more types.

[0039] From the viewpoint of achieving high die shear strength, the blending amounts of the epoxy resin and the phenol resin are preferably such that the equivalent ratio of the epoxy equivalent to the hydroxyl equivalent is 0.6 to 1.5, more preferably 0.7 to 1.4, and even more preferably 0.8 to 1.3. By having the blending ratio within the above range, it is easy to achieve both sufficiently high levels of curability and fluidity.

[0040] [Elastomer] Examples of the elastomer include acrylic resin, polyester resin, polyamide resin, polyimide resin, silicone resin, polybutadiene, acrylonitrile, epoxy-modified polybutadiene, maleic anhydride-modified polybutadiene, phenol-modified polybutadiene, and carboxy-modified acrylonitrile.

[0041] From the viewpoint of achieving high die shear strength, acrylic resins are preferred as elastomers, and more preferably, acrylic resins such as epoxy group-containing (meth)acrylic copolymers obtained by polymerizing functional monomers having an epoxy group or a glycidyl group as a crosslinkable functional group, such as glycidyl acrylate or glycidyl methacrylate. Among the acrylic resins, epoxy group-containing (meth)acrylic acid ester copolymers and epoxy group-containing acrylic rubbers are preferred, and epoxy group-containing acrylic rubbers are more preferred. The epoxy group-containing acrylic rubber is a rubber having an epoxy group, mainly composed of an acrylic acid ester as a main component, and mainly composed of a copolymer of butyl acrylate and acrylonitrile, or the like, a copolymer of ethyl acrylate and acrylonitrile, or the like. The acrylic resin may have not only an epoxy group, but also a crosslinkable functional group such as an alcoholic or phenolic hydroxyl group, or a carboxyl group.

[0042] Commercially available acrylic resins include SG-70L, SG-708-6, WS-023 EK30, SG-280 EK23, and SG-P3 solvent-modified product (product name, acrylic rubber, weight-average molecular weight: 800,000, Tg: 12°C, solvent: cyclohexanone) manufactured by Nagase Chemtec Corporation.

[0043] The glass transition temperature (Tg) of the acrylic resin is preferably -50 to 50°C, more preferably -30 to 30°C, from the viewpoint of achieving high die shear strength. The weight average molecular weight (Mw) of the acrylic resin is preferably 100,000 to 3,000,000, more preferably 500,000 to 2,000,000, from the viewpoint of achieving high die shear strength. Here, Mw means a value measured by gel permeation chromatography (GPC) and converted using a calibration curve of standard polystyrene. By using an acrylic resin with a narrow molecular weight distribution, there is a tendency that a highly elastic adhesive piece can be formed.

[0044] From the viewpoint of achieving high die shear strength, the amount of the acrylic resin contained in the thermosetting resin composition is preferably 10 to 200 parts by mass, and more preferably 20 to 100 parts by mass, per 100 parts by mass of the epoxy resin and the epoxy resin curing agent in total.

[0045] [Inorganic filler] Examples of inorganic fillers include aluminum hydroxide, magnesium hydroxide, calcium carbonate, magnesium carbonate, calcium silicate, magnesium silicate, calcium oxide, magnesium oxide, aluminum oxide, aluminum nitride, aluminum borate whiskers, boron nitride, crystalline silica, and amorphous silica. These may be used alone or in combination of two or more.

[0046] From the viewpoint of achieving high die shear strength, the average particle size of the inorganic filler is preferably 0.005 μm to 1.0 μm, more preferably 0.05 to 0.5 μm. From the viewpoint of achieving high die shear strength, the surface of the inorganic filler is preferably chemically modified. A silane coupling agent is suitable as a material for chemically modifying the surface. Examples of the types of functional groups of the silane coupling agent include vinyl groups, acryloyl groups, epoxy groups, mercapto groups, amino groups, diamino groups, alkoxy groups, and ethoxy groups.

[0047] From the viewpoint of achieving high die shear strength, the content of the inorganic filler is preferably 20 to 200 parts by mass, and more preferably 30 to 100 parts by mass, per 100 parts by mass of the resin component of the thermosetting resin composition.

[0048] [Cure accelerator] Examples of the hardening accelerator include imidazoles and their derivatives, organic phosphorus compounds, secondary amines, tertiary amines, and quaternary ammonium salts. From the viewpoint of achieving high die shear strength, imidazole compounds are preferred. Examples of imidazoles include 2-methylimidazole, 1-benzyl-2-methylimidazole, 1-cyanoethyl-2-phenylimidazole, and 1-cyanoethyl-2-methylimidazole. These may be used alone or in combination of two or more.

[0049] The content of the curing accelerator in the thermosetting resin composition is preferably 0.04 to 3 parts by mass, and more preferably 0.04 to 0.2 parts by mass, per 100 parts by mass of the epoxy resin and the epoxy resin curing agent in total, from the viewpoint of achieving high die shear strength.

[0050] Second Embodiment [Semiconductor Devices] FIG. 10 is a cross-sectional view showing a schematic diagram of a semiconductor device according to this embodiment. The semiconductor device 200 shown in this figure includes a substrate 10, a controller chip Tc arranged on the substrate 10, a plurality of support pieces S arranged around the controller chip Tc on the substrate 10, an adhesive member 15 supported by the plurality of support pieces S and arranged to cover the controller chip Tc, five chips T1, T2, T3, T4, and T5 stacked on the surface of the adhesive member 15, wires Wa and Wb that electrically connect the electrodes 10a and 10b on the surface of the substrate 10 to the chips, and a sealing layer 50 that seals them. An adhesive piece A1 is arranged between the adhesive member 15 and the chip T1. An adhesive piece A2 is arranged between the chip T1 and the chip T2. An adhesive piece A3 is arranged between the chip T2 and the chip T3. An adhesive piece A4 is arranged between the chip T3 and the chip T4. An adhesive piece A5 is arranged between the chip T4 and the chip T5.

[0051] According to the semiconductor device 200, the interface where warpage stress is likely to concentrate is formed by the adhesive member 15 and the adhesive piece A1, so that a sufficiently high adhesive strength can be obtained and peeling at this interface can be suppressed. Also, according to the semiconductor device 200, the chip T1 is arranged so as to cover the controller chip Tc, so that space can be saved. Below, the semiconductor device 200 will be described mainly with respect to the differences from the semiconductor device 100 according to the first embodiment.

[0052] In this embodiment, a dolmen structure is formed on the substrate 10 by a plurality of support pieces S and an adhesive member 15. A dolmen is a type of stone tomb, and comprises a plurality of supporting stones and a slab-shaped rock placed on the supporting stones. In the semiconductor device 200, the support pieces S correspond to the "support stones", and the adhesive member 15 corresponds to the "slab-shaped rock".

[0053] The support piece S plays the role of a spacer that forms a space around the controller chip Tc. The support piece S is, for example, entirely made of a cured product of a thermosetting resin composition. The support piece S may be a laminate (dummy chip) of a chip and an adhesive piece provided on one surface of the chip, or may have a multi-layer structure similar to that of the adhesive member 15. By having multiple layers made of different materials, the support piece S can be assigned a function to each layer, and the support piece can have higher functionality than one made of multiple layers of the same material.

[0054] As shown in Fig. 11(a), two support pieces S (rectangular shape) may be arranged at positions spaced apart on both sides of the controller chip Tc, or as shown in Fig. 11(b), one support piece S (square shape, total of four) may be arranged at each position corresponding to the corner of the chip T1. The length of one side of the support piece S in a plan view is, for example, 20 mm or less, and may be 1 to 20 mm or 1 to 12 mm. The thickness (height) of the support piece S is, for example, 10 to 180 µm, and may be 20 to 120 µm.

[0055] The chip T1 is spaced apart from the adhesive member 15. By appropriately setting the thickness of the support piece S, it is possible to ensure a space for the wire Wa that connects the upper surface of the chip T1 to the substrate 10. As shown in FIG. 10, the adhesive member 15 covers the region R of the adhesive piece A1 that faces the controller chip Tc, and extends continuously to the upper surfaces of the multiple support pieces S.

[0056] [Method of manufacturing semiconductor device] The semiconductor device 200 is manufactured through the following steps. (A2) A step of arranging a controller chip Tc and a plurality of support pieces S around the controller chip Tc on the surface of the substrate 10 (see FIG. 12). Note that the plurality of support pieces S may be arranged after the controller chip Tc is arranged, or the plurality of support pieces S may be arranged before the controller chip Tc is arranged. (B2) A step of arranging an adhesive member 15 so as to be supported by a plurality of support pieces S and to cover the controller chip Tc (see FIG. 13). (C2) A step of laminating an adhesive piece-attached chip 31 on the surface of adhesive member 15 (see FIG. 14). (D2) A process of stacking a plurality of chips with adhesive pieces 32, 33, 34, 35 on the surface of the chip with adhesive pieces 31 (see FIG. 15). As shown in FIG. 15, the chip with adhesive pieces 32 is arranged at a position shifted in the horizontal direction (to the right in FIG. 15) from the chip T1, and the chip with adhesive pieces 33 is arranged at a position shifted in the same horizontal direction (to the right in FIG. 15) from the chip T2. Then, the chip with adhesive pieces 34 is arranged at a position shifted in the opposite horizontal direction (to the left in FIG. 15) from the chip T3, and the chip with adhesive pieces 35 is arranged at a position shifted in the same horizontal direction (to the left in FIG. 15) from the chip T4. This makes it possible to secure a space for connecting wires to the chips and to achieve space saving. (E2) A step of collectively carrying out a hardening treatment on the adhesive member 15 and the plurality of adhesive pieces A1, A2, A3, A4, and A5. (F2) A process of sealing the chips, wires, etc. on the surface of the substrate 10 with a sealing material (see FIG. 10).

[0057] <Third embodiment> Fig. 16 is a cross-sectional view showing a schematic diagram of a semiconductor device according to this embodiment. The semiconductor device 300 shown in this figure includes a substrate 10, two chips 31 and 32 with adhesive pieces stacked on the surface of the substrate 10, an adhesive member 15 arranged between the two chips 31 and 32 with adhesive pieces, wires Wa and Wb electrically connecting the electrodes 10a on the surface of the substrate 10 to the chips T1 and T2, and a sealing layer 50 sealing them. An adhesive piece A2 is arranged between the adhesive member 15 and the chip T2.

[0058] The sides (part of the peripheral edges) of the chips 31, 32 with adhesive pieces protrude laterally beyond the adhesive member 15. In a plan view, the adhesive member 15 has a smaller area than the chips 31, 32 with adhesive pieces, and the sides of the upper surface of the chip T1 are not covered by the adhesive member 15. The sides of the lower surface of the adhesive piece A2 are also not covered by the adhesive member 15. According to the semiconductor device 300, the interface at which warping stress is likely to concentrate is formed by the adhesive member 15 and the adhesive piece A2, so that a sufficiently high adhesive strength can be obtained and peeling at this interface can be suppressed.

[0059] Although the embodiments of the present disclosure have been described in detail above, the present invention is not limited to the above embodiments. For example, in the first and second embodiments, the chip 31 with adhesive piece (a laminate of the adhesive piece A1 and the chip T1) is arranged at a position shifted laterally (to the right in FIG. 8 and FIG. 14) with respect to the adhesive member 15, but the chip 31 with adhesive piece may be arranged directly on the adhesive member 15. By arranging the chip T1 on the surface of the adhesive member 15, it is easy to ensure the distance from the surface of the substrate 10 to the chip T1. Therefore, it is possible to sufficiently prevent the chip T1 from contacting other members (for example, the controller chip Tc shown in FIG. 8) arranged on the surface of the substrate 10. Note that the above distance can also be ensured when an adhesive member made of an adhesive layer (single layer) having a thickness equivalent to that of the three-layer adhesive member 15 is used instead of the three-layer adhesive member 15. However, such an adhesive member is inferior in machinability and handleability to the adhesive member 15, and therefore the productivity of the semiconductor device is also reduced. [Industrial Applicability]

[0060] According to the present disclosure, there is provided a semiconductor device having a plurality of stacked chips, in which peeling caused by warping of the chips within the semiconductor device can be sufficiently suppressed, and a method for efficiently manufacturing the same is provided. [Explanation of symbols]

[0061] 1...base film, 2...adhesive layer, 3...cover film, 10...substrate, 10a, 10b...electrodes, 15...adhesive member, 15a, 15p, 15P...surface layer, 15b, 15B...intermediate layer, 15F...adhesive film, 20...laminated film for forming adhesive member, 31, 32, 33, 34, 35...chip with adhesive piece, 42...push-up jig, 44...suction collet, 50...sealing layer, 100, 200, 300...semiconductor device, A1, A2, A3, A4, A5, Ac...adhesive piece, DR...dicing ring, H...overhang portion, R...area, S...support piece, T1, T2, T3, T4, T5...chip, Tc...controller chip, Wa, Wb...wire

Claims

1. A substrate; an adhesive member disposed on a surface of the substrate; a first chip laminated to the adhesive member via a first adhesive piece; a second chip laminated to the first chip via a second adhesive piece; Equipped with The semiconductor device, wherein the adhesive member has a multi-layer structure including a pair of surface layers made of a cured product of a thermosetting resin composition, and an intermediate layer disposed between the pair of surface layers.

2. A substrate; a chip disposed on a surface of the substrate; A plurality of support pieces arranged around the chip on the surface of the substrate; an adhesive member supported by the plurality of support pieces and disposed so as to cover the chip; a first chip laminated to the adhesive member via a first adhesive piece; Equipped with The semiconductor device, wherein the adhesive member has a multi-layer structure including a pair of surface layers made of a cured product of a thermosetting resin composition, and an intermediate layer disposed between the pair of surface layers.

3. The semiconductor device according to claim 2 , further comprising a second chip laminated to the first chip via a second adhesive piece.

4. 4. The semiconductor device according to claim 1, wherein at least a part of a peripheral portion of said second chip protrudes laterally beyond said first chip.

5. 5. The semiconductor device according to claim 1, wherein at least a part of a peripheral portion of said first chip protrudes laterally beyond said adhesive member.

6. A substrate; a first adhesive chip disposed on a surface of the substrate; an adhesive member disposed on a surface of the adhesive piece of the first adhesive piece-attached chip; a second adhesive chip disposed on a surface of the adhesive member; Equipped with The semiconductor device, wherein the adhesive member has a multi-layer structure including a pair of surface layers made of a cured product of a thermosetting resin composition, and an intermediate layer disposed between the pair of surface layers.

7. 7. The semiconductor device according to claim 6, wherein at least a part of a peripheral edge of said second adhesive piece-attached chip protrudes laterally beyond said adhesive member.

8. 8. The semiconductor device according to claim 1, wherein the intermediate layer is a polyimide layer.

9. 8. The semiconductor device according to claim 1, wherein the intermediate layer is a metal layer.

10. 10. The semiconductor device according to claim 1, which is a three-dimensional NAND memory.

11. laminating a first chip on a surface of an adhesive member on a substrate via a first adhesive piece; laminating a second chip on a surface of the first chip via a second adhesive piece; Including, the first and second adhesive pieces are made of a thermosetting resin composition; the adhesive member has a multilayer structure including a pair of surface layers made of a thermosetting resin composition and an intermediate layer disposed between the pair of surface layers, A method for manufacturing a semiconductor device, comprising the steps of: curing the adhesive member, the first adhesive piece, and the second adhesive piece all at once.

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