Semiconductor module and method for manufacturing the same

Abstract

The present invention improves bonding strength between a semiconductor element and a metal wiring board, while ensuring the thickness of a joining member. The semiconductor module (1) comprises a multi-layer substrate (2) having a plurality of circuit boards (22) arranged on the upper surface of an insulating plate (20), a semiconductor element (3) arranged on the upper surface of at least one circuit board, and a metal wiring board (4) arranged on the upper surface of the semiconductor element. The metal wiring board has a first junction (40) joined to the upper surface of the semiconductor element via a first joining member (S3). The first junction includes a tabular portion having an upper surface and a lower surface, and has a boss (45) formed on the lower surface of the tabular portion and protruding toward the semiconductor element, a first recess (46) that is formed in the upper surface of the tabular portion at a location corresponding to directly above the boss, and a plurality of second recesses (49) that are formed in the upper surface and are smaller than the first recess.

Description

[Technical field]

[0001] The present invention relates to a semiconductor module and a method for manufacturing the semiconductor module. [Background technology]

[0002] 2. Description of the Related Art Semiconductor modules have substrates on which semiconductor elements such as IGBTs (Insulated Gate Bipolar Transistors), power MOSFETs (Metal Oxide Semiconductor Field Effect Transistors), FWDs (Free Wheeling Diodes), etc. are provided, and are used in inverter devices and the like.

[0003] In this type of semiconductor module, for example, in Patent Documents 1-3, a semiconductor element is disposed on an insulating substrate (which may be called a laminated substrate), and a metal wiring board (which may be called a lead frame) for wiring is disposed on the upper electrode of the semiconductor element. The metal wiring board is formed into a predetermined shape, for example, by pressing a metal plate. One end of the metal wiring board is electrically joined to the upper electrode via a bonding material such as solder. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] JP 2018-088448 A [Patent Document 2] JP 2016-139635 A [Patent Document 3] JP 2015-176871 A Summary of the Invention [Problem to be solved by the invention]

[0005] In this type of semiconductor module, the power semiconductor element generates heat during switching operations. In the structure in which the metal wiring plate is soldered to the surface of the power semiconductor element as described above, there is a risk of distortion at the joint due to fluctuations in internal stress caused by temperature changes. In addition, it is possible that the plate-shaped joint facing the upper electrode of the semiconductor element may tilt during soldering, resulting in a partial thinning of the solder thickness.

[0006] The present invention has been made in consideration of these points, and one of its objectives is to provide a semiconductor module that can improve the bonding strength between a semiconductor element and a metal wiring board while ensuring the thickness of the bonding material. [Means for solving the problem]

[0007] A semiconductor module of one embodiment of the present invention comprises a laminated substrate having a plurality of circuit boards arranged on an upper surface of an insulating plate, a semiconductor element arranged on the upper surface of at least one of the circuit boards, and a metal wiring board arranged on the upper surface of the semiconductor element, wherein the metal wiring board has a first bonding portion joined to the upper surface of the semiconductor element via a first bonding material, the first bonding portion including a plate-shaped portion having an upper surface and a lower surface, and having a boss formed on the lower surface of the plate-shaped portion and protruding toward the semiconductor element, a first recess formed on the upper surface of the plate-shaped portion at a location corresponding to directly above the boss, and a plurality of second recesses formed on the upper surface and smaller than the first recesses.

[0008] Moreover, a method for manufacturing a semiconductor module according to one aspect of the present invention is the method for manufacturing the semiconductor module described above, which includes forming the boss and the first recess by press working in the process of manufacturing the metal wiring board. Effect of the Invention

[0009] According to the present invention, it is possible to improve the bonding strength between a semiconductor element and a metal wiring board while ensuring the thickness of the bonding material. [Brief description of the drawings]

[0010] [Figure 1] 1 is a schematic diagram showing a semiconductor device according to an embodiment of the present invention as viewed from above; [Diagram 2] 2 is a cross-sectional view of the semiconductor device shown in FIG. 1 taken along line AA. [Diagram 3] 2 is an enlarged view of a metal wiring board according to the present embodiment; FIG. [Figure 4] 4 is a plan view of the metal wiring board shown in FIG. 3 as viewed in the direction of arrow B. FIG. [Diagram 5] 4 is an enlarged view of a portion C of the metal wiring board shown in FIG. [Figure 6] 5 is a plan view of the metal wiring board shown in FIG. 4 as viewed in the direction of arrow D. FIG. [Figure 7] 11A and 11B are schematic diagrams showing modified examples of recesses formed on the surface of a metal wiring board. [Figure 8] 10A and 10B are schematic diagrams showing other examples of the arrangement of recesses formed on the surface of a metal wiring board. [Figure 9] 1A to 1C are schematic diagrams showing variations of bosses and recesses formed on a metal wiring board. [Figure 10] 1 is a plan view showing a specific example of a semiconductor module to which a metal wiring board according to an embodiment of the present invention is applied. [Figure 11] 1 is an equivalent circuit diagram of a semiconductor device according to an embodiment of the present invention; [Figure 12] 4 is a flow diagram showing an example of a method for manufacturing a semiconductor module according to the present embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011] A semiconductor module and a semiconductor device to which the present invention can be applied will be described below. Fig. 1 is a schematic diagram of a semiconductor device according to the present embodiment as viewed from above. Fig. 2 is a cross-sectional view of the semiconductor device shown in Fig. 1 taken along line AA. Fig. 3 is an enlarged view of a metal wiring board according to the present embodiment. Fig. 10 is a plan view showing a specific example of a semiconductor module to which the metal wiring board according to the present embodiment is applied. Fig. 11 is an equivalent circuit diagram of the semiconductor device according to the present embodiment. Here, a configuration is adopted in which an inverse-parallel circuit of an IGBT and an FWD is connected in series as the semiconductor element 3.

[0012] In the following figures, the longitudinal direction of the semiconductor module (cooler) is defined as the X direction, the short side direction of the semiconductor module (cooler) as the Y direction, and the height direction (thickness direction of the board) as the Z direction. The longitudinal direction of the semiconductor module indicates the direction in which multiple circuit boards are arranged. The illustrated X, Y, and Z axes are mutually orthogonal and form a right-handed system. In some cases, the X direction may be called the left-right direction, the Y direction as the front-back direction, and the Z direction as the up-down direction. These directions (front-back, left-right, up-down directions) are terms used for convenience of explanation, and the corresponding relationship with each of the XYZ directions may change depending on the mounting posture of the semiconductor module. For example, the heat dissipation surface side (cooler side) of the semiconductor module is called the bottom side, and the opposite side is called the top side. In this specification, plan view means the top or bottom side of the semiconductor module as seen from the Z direction. The aspect ratios and the size relationships between the various members in each drawing are merely schematic diagrams, and therefore do not necessarily match. For the sake of convenience, the size relationships between the components may be exaggerated.

[0013] A semiconductor device 100 according to this embodiment is applied to a power conversion device such as an inverter for an industrial or vehicle-mounted motor. As shown in Fig. 1 and Fig. 2, the semiconductor device 100 is configured by disposing a semiconductor module 1 on the upper surface of a cooler 10. Note that the cooler 10 may have any configuration relative to the semiconductor module 1.

[0014] The cooler 10 dissipates heat from the semiconductor module 1 to the outside and has an overall rectangular parallelepiped shape. Although not shown in the figures, the cooler 10 is configured by providing a plurality of fins on the lower surface side of a base plate and housing these fins in a water jacket. However, the cooler 10 is not limited to this and can be modified as appropriate.

[0015] The semiconductor module 1 is configured by arranging a laminated substrate 2, a semiconductor element 3, a metal wiring board 4, etc. within a case 11.

[0016] The laminated substrate 2 is, for example, a DCB (Direct Copper Bonding) substrate, an AMB (Active Metal Brazing) substrate, or a metal-based substrate. The laminated substrate 2 is configured by laminating an insulating plate 20, a heat sink 21, and a plurality of circuit boards 22, and is formed into a rectangular shape as a whole in a plan view.

[0017] Specifically, the insulating plate 20 is formed of a plate-like body having an upper surface and a lower surface, and has a rectangular shape in a plan view that is long in the X direction. The insulating plate 20 may be formed of a ceramic material such as aluminum oxide (Al2O3), aluminum nitride (AlN), silicon nitride (Si3N4), aluminum oxide (Al2O3), and zirconium oxide (ZrO2).

[0018] The insulating plate 20 may be formed of, for example, a thermosetting resin such as an epoxy resin or a polyimide resin, or a composite material in which a thermosetting resin is filled with glass or a ceramic material. The insulating plate 20 is preferably flexible and may be formed of, for example, a material containing a thermosetting resin. The insulating plate 20 may be called an insulating layer or an insulating film.

[0019] The heat sink 21 has a predetermined thickness in the Z direction and a rectangular shape in plan view that is long in the Y direction. The heat sink 21 is formed of a metal plate with good thermal conductivity, such as copper or aluminum. The heat sink 21 is disposed on the lower surface of the insulating plate 20. The lower surface of the heat sink 21 is a surface to be attached to the cooler 10 to which the semiconductor module 1 is attached, and also functions as a heat dissipation surface (heat dissipation area) for dissipating heat from the semiconductor module 1. The heat sink 21 is bonded to the upper surface of the cooler 10 via a bonding material S1 such as solder. The heat sink 21 may be disposed on the upper surface of the cooler 10 via a thermal conductive material such as thermal grease or thermal compound.

[0020] The multiple circuit boards 22 each have a predetermined thickness and are arranged on the upper surface of the insulating plate 20. Each circuit board 22 is formed in an electrically independent island shape. For example, the circuit boards 22 have a rectangular shape in a plan view and are arranged side by side in the X direction on the insulating plate 20. The number of circuit boards 22 is not limited to two as shown in FIG. 1 and can be changed as appropriate. As shown in FIG. 10, three or more circuit boards 22 may be arranged on the insulating plate 20. The shape, arrangement location, etc. of the circuit boards 22 are also not limited to these and can be changed as appropriate. These circuit boards 22 are formed of a metal plate with good thermal conductivity, such as copper or aluminum. The circuit boards 22 may be called a circuit layer or a circuit pattern.

[0021] A semiconductor element 3 is disposed on the upper surface of a predetermined circuit board 22 (circuit board 22 on the negative side in the X direction) via a bonding material S such as solder. The semiconductor element 3 is formed in a rectangular shape in a plan view from a semiconductor substrate made of, for example, silicon (Si) or silicon carbide (SiC). The semiconductor element 3 may be a power semiconductor element. For the semiconductor element 3, a switching element such as an IGBT (Insulated Gate Bipolar Transistor) or a power MOSFET (Metal Oxide Semiconductor Field Effect Transistor), or a diode such as an FWD (Free Wheeling Diode) is used.

[0022] In this embodiment, the semiconductor element 3 is configured as an RC (Reverse Conducting)-IGBT element that integrates the functions of an IGBT (Insulated Gate Bipolar Transistor) element and an FWD (Free Wheeling Diode) element.

[0023] The semiconductor element 3 is not limited to this, and may be configured by combining the above-mentioned switching elements, diodes, etc. For example, an IGBT element and an FWD element may be configured separately. Also, an RB (Reverse Blocking)-IGBT or the like having a sufficient withstand voltage against reverse bias may be used as the semiconductor element 3. Also, the shape, number, and location of the semiconductor element 3 may be changed as appropriate.

[0024] Furthermore, electrodes (not shown) are formed on the upper and lower surfaces of the semiconductor element 3. For example, the electrode on the upper surface side (upper surface electrode) is composed of an emitter electrode (source electrode) or a gate electrode, and the electrode on the lower surface side (lower surface electrode) is composed of a collector electrode (drain electrode).

[0025] The semiconductor element 3 in this embodiment is a so-called vertical switching element in which the above-mentioned functional elements are formed on a semiconductor substrate, but is not limited to this and may be a horizontal switching element.

[0026] A metal wiring board 4 is disposed on the upper surface of the semiconductor element 3. The metal wiring board 4 is configured as a plate-like body having an upper surface and a lower surface, and is formed from a metal material such as a copper material, a copper alloy material, an aluminum alloy material, or an iron alloy material. The metal wiring board 4 is formed into a predetermined shape, for example, by press working. Note that the shape of the metal wiring board 4 shown below is merely an example, and can be modified as appropriate. The metal wiring board may also be called a lead frame.

[0027] The metal wiring board 4 according to this embodiment is an elongated body extending in the X direction so as to straddle a plurality of circuit boards 22 in a plan view, and has a crank shape bent a plurality of times in a side view. Specifically, as shown in Fig. 2 and Fig. 3, the metal wiring board 4 includes a first bonding portion 40 bonded to the upper surface (upper electrode) of the semiconductor element 3 via a bonding material S3 (first bonding material), a second bonding portion 41 bonded to the upper surface of the circuit board 22 on the positive side in the X direction via a bonding material S4 (second bonding material), and a connecting portion 42 connecting the first bonding portion 40 and the second bonding portion 41.

[0028] The width of the metal wiring board 4 in the Y direction is uniform from the first joint portion 40 to the second joint portion 41. The first joint portion 40, the second joint portion 41, and the connecting portion 42 are arranged in a line along the X direction in a plan view. The width of the metal wiring board 4 in the Y direction does not need to be uniform from the first joint portion 40 to the second joint portion 41, and may have different widths as shown in FIG. 10. The first joint portion 40, the second joint portion 41, and the connecting portion 42 do not need to be arranged in a line, and may be arranged so as to be shifted obliquely from each other as shown in FIG. 10.

[0029] The first joint 40 is formed in a rectangular shape smaller than the outer shape of the semiconductor element 3 in a plan view, and includes a plate-like portion having an upper surface and a lower surface. A first bent portion 43 that is bent at a substantially right angle and rises upward is formed at the end of the first joint 40 on the positive side in the X direction (the connecting portion 42 side). One end (left end) of the connecting portion 42 is connected to the upper end of the first bent portion 43. Although details will be described later, a plurality of bosses 45 that protrude toward the semiconductor element 3 are formed on the lower surface of the first joint 40. In addition, a first recess 46 is formed on the upper surface of the first joint 40 at a position directly above the boss 45.

[0030] The second joint portion 41 is formed in a rectangular shape smaller than the outer shape of the circuit board 22 in a plan view, and includes a plate-like portion having an upper surface and a lower surface. A second bent portion 44 that is bent at a substantially right angle and rises upward is formed at the end of the second joint portion 41 on the negative side in the X direction (the connecting portion 42 side). The other end (right end) of the connecting portion 42 is connected to the upper end of the second bent portion 44. Although details will be described later, a plurality of bosses 47 that protrude toward the circuit board 22 are formed on the lower surface of the second joint portion 41. In addition, a third recess 48 is formed on the upper surface of the second joint portion 41 at a position directly above the boss 47.

[0031] The connecting portion 42 extends in the horizontal direction, and as described above, one end is connected to the first bent portion 43 and the other end is connected to the second bent portion 44.

[0032] The length of the first bent portion 43 in the Z direction is shorter than that of the second bent portion 44 by the thickness of the semiconductor element 3. That is, the first bonding portion 40 and the second bonding portion 41 are provided at positions with different heights. More specifically, the first bonding portion 40 is provided at a higher position than the second bonding portion 41.

[0033] The shape, number, arrangement, etc. of the metal wiring boards 4 described above are merely examples, and are not limited to these and can be appropriately changed. As will be described in detail later, a plurality of (for example, four) metal wiring boards 4 may be arranged for one semiconductor module, as shown in Fig. 10. In this embodiment, the semiconductor element 3, the metal wiring boards 4, and main terminals, etc. described later form an inverter circuit, for example, as shown in Fig. 11.

[0034] The laminated substrate 2, the semiconductor element 3, and the metal wiring board 4 are surrounded by a case 11. The case 11 has a cylindrical or frame shape that is rectangular in plan view, and is made of, for example, a synthetic resin. The case 11 may be made of a thermosetting resin material such as epoxy resin or silicone rubber. The lower end of the case 11 is bonded to the upper surface of the cooler 10 via an adhesive (not shown), and the upper end extends to a position sufficiently higher than the upper surface of the metal wiring board 4. In this way, the case 11 surrounds the laminated substrate 2, the semiconductor element 3, and the metal wiring board 4, and defines a space that accommodates the laminated substrate 2, the semiconductor element 3, and the metal wiring board 4.

[0035] The internal space defined by the case 11 is filled with sealing resin 5. The sealing resin 5 may be filled so that the upper surface reaches the upper end of the case 11. This seals the laminated substrate 2, the semiconductor element 3, and the metal wiring board 4. The metal wiring board 4 is entirely covered with the sealing resin 5.

[0036] The sealing resin 5 may be made of, for example, a thermosetting resin. The sealing resin 5 preferably contains at least one of epoxy, silicone, urethane, polyimide, polyamide, and polyamideimide. For example, an epoxy resin mixed with a filler is suitable for the sealing resin 5 in terms of insulation, heat resistance, and heat dissipation.

[0037] As shown in a specific example in Fig. 10, the case 11 may be provided with a plurality of main terminals 60 for main current and a plurality of control terminals 64 for control. The main terminals 60 are formed of long, plate-like bodies and embedded in the side walls of the case 11. In Fig. 10, two main terminals 60 constituting an N terminal and a P terminal are arranged side by side in the X direction on the side wall of the case 11 located on the negative side in the Y direction. Also, a main terminal 60 constituting an M terminal is arranged on the side wall of the case 11 located on the positive side in the Y direction.

[0038] As described above, in this embodiment, the semiconductor element 3, the metal wiring board 4, the main terminals 60, etc. form an inverter circuit as shown in Fig. 11, for example. These main terminals 60 (N terminal, P terminal, M terminal) correspond to IN(N) (which may be called a low potential side input terminal or a negative terminal), IN(P) (which may be called a high potential side input terminal or a positive terminal), and OUT(M) (which may be called an output terminal or an intermediate terminal) in Fig. 11, respectively.

[0039] Moreover, the control terminal 61 is formed of a long plate-like body, and is embedded in the side wall of the case 11 located on the positive side in the Y direction. The control terminal 61 is electrically connected to a predetermined control electrode of the semiconductor element 3 via a wiring member such as a bonding wire. These main terminals 60 and control terminals 61 are formed of a metal material such as a copper material, a copper alloy material, an aluminum alloy material, an iron alloy material, or the like, and have a predetermined electrical conductivity and a predetermined mechanical strength. The shapes, numbers, locations, etc. of the main terminals 60 and control terminals 61 are not limited to these and can be changed as appropriate.

[0040] When a semiconductor module is subjected to a power cycle test and operated until it fails, most of the failures are due to electrode failures of the semiconductor elements. The following events, for example, can be considered as factors that can cause early failure of a semiconductor module.

[0041] (1) As the thickness of the bonding material between the semiconductor element and the metal wiring board becomes thinner, electrode distortion increases, resulting in a decrease in the resistance. (2) Thermal stress causes peeling at the interface between the bonding material between the semiconductor element and the metal wiring board and the encapsulation resin. The peeling progresses along the interface between the metal wiring board and the encapsulation resin. If the thermal deformation of the metal wiring board increases as the peeling progresses, the electrode distortion increases, resulting in a decrease in the resistance.

[0042] Therefore, in order to improve the resistance of semiconductor modules, (i) Ensuring the thickness of the bonding material between the semiconductor element and the metal wiring board; (ii) It is necessary to suppress peeling at the interface between the metal wiring board and the sealing resin.

[0043] Regarding (i) above, in the past, in the bonding process (soldering process), the shape and center of gravity of the metal wiring board may cause the metal wiring board to tilt with respect to the upper electrode of the semiconductor element. As a result, the thickness of the bonding material (solder) directly below the metal wiring board may become uneven, and there may be places where the thickness is not secured locally. In other words, it is difficult to secure the thickness of the bonding material between the semiconductor element and the metal wiring board.

[0044] Regarding (ii) above, a possible method for reducing peeling is, for example, increasing the surface area of ​​the metal wiring board and improving the adhesion (anchor effect) between the metal wiring board and the sealing resin. One method for increasing the surface area of ​​the metal wiring board is to form an uneven shape on the surface of the metal wiring board. However, if the lower surface of the metal wiring board (the surface facing the semiconductor element) has an uneven shape, voids and sink marks are likely to occur in the bonding material. As a result, there is a risk of affecting the mounting quality of the metal wiring board.

[0045] In addition, methods for roughening the surface of a metal wiring board include laser processing and wet methods using chemicals. However, these methods not only increase costs, but also make the lower surface of the metal wiring board rough, which makes it easier for voids and sink marks to occur in the bonding material. In other words, it is difficult to roughen the metal wiring board without affecting the quality of the bonding material directly below the metal wiring board.

[0046] Therefore, the present inventors have conceived of the present invention in order to achieve both of the above (i) and (ii). Specifically, in this embodiment, the first joint portion 40 of the metal wiring board 4 is recessed from the upper surface side to form a first recess 46, and a boss 45 is made to protrude from the lower surface side. In addition, a plurality of second recesses 49 smaller than the first recess 46 are formed on the upper surface of the first joint portion 40. The boss 45, the first recess 46, and the second recess 49 are formed by pressing.

[0047] Moreover, the bosses 45 are disposed in positions close to the four corners of the rectangular first joint portion 40 in a plan view. In this manner, by forming a plurality of bosses 45, the first joint portion 40 does not tilt with respect to the upper surface of the semiconductor element 3 in the bonding process of the metal wiring board 4. Therefore, the posture of the metal wiring board 4 (first joint portion 40) can be stabilized.

[0048] In particular, by providing the boss 45 on the lower surface of the metal wiring board 4, a gap at least the height of the boss 45 can be secured between the first bonding portion 40 and the semiconductor element 3. By filling the gap with the bonding material S3, it is possible to ensure the thickness of the bonding material S3.

[0049] In addition, the upper surface of the first bonding portion 40 is roughened by forming a plurality of second recesses 49. As a result, the surface area of ​​the upper surface of the first bonding portion 40 is increased, and it is possible to improve the adhesion (anchor effect) between the upper surface of the first bonding portion 40 and the sealing resin. Therefore, it is possible to suppress the progress of peeling of the upper surface of the metal wiring plate 4 caused by thermal stress above the semiconductor element 3.

[0050] In addition, because the structure that realizes these effects is obtained by press processing, it is less expensive and has a cost advantage compared to conventional roughening methods using laser processing or wet methods using chemicals. Thus, according to this embodiment, it is possible to improve the bonding strength between the semiconductor element and the metal wiring board while ensuring the thickness of the bonding material.

[0051] In addition, a boss 47 protruding toward the circuit board 22 is also formed on the back surface side of the second joint portion 41. This makes it possible to secure a gap at least the height of the boss 47 between the second joint portion 41 and the circuit board 22. By filling the gap with the joint material S4, it is possible to ensure the thickness of the joint material S4.

[0052] Next, a detailed structure of metal wiring board 4 according to this embodiment will be described with reference to Fig. 1 to Fig. 6. Fig. 4 is a plan view of the metal wiring board shown in Fig. 3 as viewed in the direction of arrow B. Fig. 5 is an enlarged view of part C of the metal wiring board shown in Fig. 3. Fig. 6 is a plan view of the metal wiring board shown in Fig. 4 as viewed in the direction of arrow D.

[0053] As shown in Figs. 1 to 6, a plurality of bosses 45 are provided on the lower surface of the first joint 40. In this embodiment, a total of four bosses 45 are provided, two in each of the X direction and two in each of the Y direction. The four bosses 45 are arranged along the outer periphery of the first joint 40 at positions corresponding to the four corners of the first joint 40. For example, as shown in Fig. 4, a predetermined boss 45 may be provided at a position spaced apart from one corner of the first joint 40 by a distance X1 in the X direction and a distance Y1 in the Y direction. The distances X1 and Y1 may be 0.25 mm to 2.5 mm, and preferably 0.5 mm to 2.0 mm. The distance X1 may be the same as the distance Y1.

[0054] The boss 45 has a cylindrical shape with an outer diameter D1, for example. The boss 45 protrudes from the lower surface of the first bonding portion 40 toward the semiconductor element 3 with a protruding height Z1. The side surface (cylindrical surface) of the boss 45 may be perpendicular to the lower surface of the first bonding portion 40. The outer diameter D1 of the boss 45 may be, for example, 0.4 mm to 1.5 mm, and preferably 0.6 mm to 1.2 mm. The protruding height Z1 of the boss 45 may be 50 μm or more and 300 μm or less, and preferably 100 μm to 200 μm. If the protruding height Z1 is too large, voids are likely to occur in the bonding material S3, and if the protruding height Z1 is small, the bonding material S3 becomes thin and a sufficient thickness cannot be ensured.

[0055] A first recess 46 is formed on the upper surface of the first joint portion 40 at a position directly above the boss 45. The first recess 46 may have a shape complementary to the boss 45, and may have, for example, a cylindrical shape with the same diameter (inner diameter D1) as the boss 45. The inner diameter of the first recess 46 may be smaller than the outer diameter D1 of the boss 45. The depth of the first recess 46 may be the same as the protruding height Z1 of the boss 45, or may be smaller than Z1. The outer diameter D1 of the first recess 46 may be, for example, 0.4 mm to 1.5 mm, and preferably 0.6 mm to 1.2 mm. The depth of the first recess 46 may be 50 μm or more and 300 μm or less, and preferably 100 μm to 200 μm.

[0056] Further, a plurality of bosses 47 (second bosses) are provided on the lower surface of the second joint portion 41. In the present embodiment, two bosses 47 are provided side by side in the Y direction. The shape of the boss 47 may be the same as or different from the shape of the boss 45 described above.

[0057] Furthermore, a third recess 48 is formed on the upper surface of the second joint portion 41 at a position directly above the boss 47. The third recess 48 may have a shape complementary to the boss 47, and may have, for example, a cylindrical shape with the same diameter as the boss 47. The third recess 48 may also have the same shape and size as the first recess 46.

[0058] The shapes, arrangements, and numbers of the bosses 45, 47, the first recesses 46, and the third recesses 48 described above are not limited to those described above and can be changed as appropriate. For example, the bosses 45, 47 are not limited to a cylindrical shape, and may be a prismatic shape, a truncated cone shape tapering downward, or a hemispherical shape. Details will be described later.

[0059] Further, a plurality of second recesses 49 are formed on the upper surface of the first joint portion 40. The second recesses 49 are smaller than the first recesses 46 in a plan view. For example, the second recesses 49 may have a polygonal shape (including a triangle, a rectangle, a pentagon, etc.) in a plan view. The second recesses 49 may be square in a plan view. The length D2 of one side of the square-shaped second recesses 49 may be, for example, 50 μm or more and 600 μm or less, and is preferably 80 μm or more and 200 μm or less.

[0060] Moreover, the second recess 49 may have a quadrangular pyramid shape. The depth Z2 of the second recess 49 may be 25% or more and 150% or less of the length D2 of one side of the second recess 49, and is preferably 50% or more and 110% or less. This shape allows the press die to have a simple shape. For example, the depth Z2 of the second recess 49 may be smaller than the depth of the first recess 46. The depth Z2 of the second recess 49 may be 30% or more and 90% or less of the depth of the first recess 46, and is preferably 50% or more and 75% or less.

[0061] The plurality of second recesses 49 thus formed may be arranged in a lattice pattern at a predetermined pitch P, for example, spaced apart in the X and Y directions. The predetermined pitch may be, for example, 100 μm or more and 900 μm or less, and preferably 200 μm or more and 600 μm or less. The plurality of second recesses 49 may be formed on the upper surface of the second joint portion 41, or may be formed only on the upper surface of the first joint portion 40. That is, the second recesses 49 may not be formed in the connecting portion 42, the first bent portion 43, and the second bent portion 44 that constitute the other parts of the first joint portion 40.

[0062] Since the semiconductor element 3, which is a heat source, is disposed directly below the first joint portion 40, it is possible to make it more susceptible to the influence of the anchor effect due to roughening. Further, by roughening only the portion where the anchor effect is to be improved, it is not necessary to incur unnecessary processing costs. That is, it can be said that the second joint portion 41, the connecting portion 42, the first bent portion 43, and the second bent portion 44 have less influence on the peeling of the sealing resin 5 than the first joint portion 40. In this case, the surfaces of the second joint portion 41, the connecting portion 42, the first bent portion 43, and the second bent portion 44 may be flat, and the surface roughness thereof may be equivalent to the surface roughness of the lower surface of the first joint portion 40.

[0063] Further, it is preferable that the portion of the lower surface of the first joint portion 40 excluding the boss 45 is a flat surface. That is, it is preferable that the second recess 49 is not formed on the lower surface of the first joint portion 40. For example, it is preferable that the surface roughness of the lower surface of the first joint portion 40 is smaller than the surface roughness of the upper surface of the first joint portion 40. Since the lower surface of the first joint portion 40 is flat, voids and sink marks are less likely to occur in the bonding material S3.

[0064] More specifically, the surface roughness of the upper surface and the lower surface of the first joint portion 40 in the present embodiment was compared by the interface developed area ratio (Sdr). Here, the interface developed area ratio is a value measured in accordance with ISO25178.

[0065] For example, on the lower surface of the first joint portion 40, the interface developed area ratio is 0 < Sdr < 0.2, and more preferably, 0.02 < Sdr < 0.15. If the lower surface of the first joint portion 40 is too rough, the solder wettability deteriorates, and voids and sink marks are likely to occur. On the other hand, for the upper surface of the first joint portion 40, 0.10 ≤ Sdr < 1.0, and more preferably, 0.2 ≤ Sdr < 1.0. If the interface developed area ratio on the upper surface of the first joint portion 40 is too small, there is a risk that peeling cannot be sufficiently suppressed. Also, if the interface developed area ratio is too large, warping and undulation may occur during processing, resulting in deformation.

[0066] The area of ​​the second recess 49 in plan view may be 0.5% to 75% of the area of ​​the boss 45 or the first recess 46, and is preferably 1.0% to 2.5%. By setting it in this range, it is possible to effectively increase the surface area of ​​the upper face of the first bonding portion 40.

[0067] 5 and 6, an annular convex portion 49a surrounding the second recess 49 may be formed on the upper surface of the first joint portion 40. The annular convex portion 49a may have a square ring shape in a plan view. The width D3 of the annular convex portion 49a is preferably, for example, 10 μm or more and 100 μm or less. The width D3 of the annular convex portion 49a is preferably 10% or more and 30% or less of the length D2 of one side of the square-shaped second recess 49. The height Z3 of the annular convex portion 49a is preferably 10% or more and 20% or less of the depth Z2 of the second recess 49. In addition, it is preferable that adjacent multiple annular convex portions 49a do not overlap each other. In other words, it is preferable that there is a flat portion 49b between at least two adjacent annular convex portions 49a. The flat portion 49b is continuous with the adjacent annular convex portions 49a. By forming such an annular protrusion 49a, the surface area of ​​the upper face of the first bonding portion 40 is further increased, and the anchor effect can be further improved.

[0068] Furthermore, the upper surface of the first bonding portion may be covered with the sealing resin 5. In this case, it is preferable that the sealing resin 5 fills the first recess 46 and the second recess 49. This can be expected to provide a further anchor effect.

[0069] 5, a coating film F may be interposed at the interface between the upper surface of the first bonding portion 40 and the sealing resin 5. The coating film enhances the degree of chemical bonding with the sealing resin 5, and may be made of, for example, polyamide resin, polyamideimide resin, polyetheramide resin, or silica. The thickness of the coating film F is 0.1 μm or more and 20 μm or less, and more preferably 1 μm to 10 μm. In this case, it is preferable that the first recess 46 and the second recess 49 (their inner side surfaces and inner bottom surfaces) are covered with the coating film F.

[0070] Furthermore, the second recess 49 may not be formed on the inner bottom surface and inner side surface of the first recess 46. In this case, it is preferable that the inner surface of the first recess 46 (the inner bottom surface and inner side surface described above) is flat. It is also preferable that the surface roughness of the inner surface of the first recess 46 is smaller than the surface roughness of the upper surface of the first bonding portion 40 excluding the first recess 46. For example, the surface roughness of the inner surface of the first recess 46 may be equal to the surface roughness of the lower surface of the first bonding portion 40.

[0071] The manufacture of the metal wiring board 4 configured as above preferably includes the steps shown below: Fig. 12 is a flow diagram showing an example of a method for manufacturing a semiconductor module (metal wiring board) according to this embodiment.

[0072] As shown in FIG. 12, the method for manufacturing semiconductor module 1 according to the present embodiment includes the following steps ST101-ST105 in the process of manufacturing metal wiring board 4.

[0073] In step ST101, first, a roughening process is performed. In this process, a plurality of second recesses 49 are formed on the upper surface of the first joint portion 40. Here, a metal plate that is the material of the metal wiring board 4 is prepared. Then, the metal plate is arranged so that the lower surface of the metal plate that corresponds to the lower surface of the metal wiring board 4 contacts a lower mold having a flat surface. Then, an upper mold having a predetermined convex shape is pressed against the upper surface of the metal plate that corresponds to the upper surface of the metal wiring board 4. In this way, a plurality of second recesses 49 are formed in a predetermined area on the upper surface of the metal plate. In addition, the lower surface of the metal plate becomes flat. Note that the roughening process may be performed only on the area that corresponds to the upper surface of the first joint portion 40. Furthermore, the area that corresponds to the first recess 46 may be excluded from the roughening process.

[0074] In step ST102, a punching process is carried out. In this step, the metal plate is punched into a predetermined shape. The predetermined shape may be an external shape in which a plurality of metal wiring plates 4 are partially connected by a connection bar (not shown).

[0075] In step ST103, a bending process is performed. In this process, predetermined portions of the metal wiring board 4 are bent into a crank shape. As a result, the metal wiring board 4 is formed with a first joint portion 40, a second joint portion 41, a connecting portion 42, a first bent portion 43, and a second bent portion 44.

[0076] In step ST104, a boss forming process is performed. In this process, a first recess 46 is formed on the upper surface and a boss 45 is formed on the lower surface at a predetermined location (e.g., first joint 40) of metal wiring board 4. For example, a lower mold having a recess corresponding to boss 45 is disposed so that the lower surface of metal wiring board 4 comes into contact with the lower surface of metal wiring board 4. Then, an upper mold having a convex shape corresponding to first recess 46 is pressed against the upper surface of metal wiring board 4. In this way, a plurality of first recesses 46 are formed on the upper surface of metal wiring board 4, and a plurality of bosses 45 are formed on the lower surface of metal wiring board 4.

[0077] In step ST105, a connection bar cutting process is performed. In this process, the connection bars of the metal wiring boards 4 connected together by the connection bars are cut to separate the metal wiring boards 4 into individual metal wiring boards 4. This process may also be performed by pressing using two dies, one above and one below.

[0078] The above steps ST101-105 are all realized by press processing. Therefore, it is possible to realize boss formation and surface roughening with a cheaper configuration than when laser processing or chemicals are used. Note that each step is merely an example, and the order of each step can be changed as appropriate within the scope of not causing any contradiction. In addition, other steps such as plating and rust prevention treatment may be included.

[0079] As described above, according to this embodiment, it is possible to improve the bonding strength between the semiconductor element and the metal wiring board while ensuring the thickness of the bonding material.

[0080] Next, modified examples will be described with reference to Fig. 7 to Fig. 9. Fig. 7A and Fig. 7B are schematic diagrams showing modified examples of recesses formed on the surface of a metal wiring board. Fig. 7A is a plan view, and Fig. 7B is a perspective view. Fig. 8A and Fig. 8B are schematic diagrams showing other arrangement examples of recesses formed on the surface of a metal wiring board. Fig. 9A and Fig. 9B are schematic diagrams showing variations of bosses and recesses formed on a metal wiring board. In the following modified examples, the previously mentioned configurations are indicated by the same names and the same symbols, and the description will be omitted as appropriate.

[0081] In the above embodiment, a case has been described in which one side of the second recess 49 having a polygonal shape in a plan view is parallel to the X direction or the Y direction, but the present invention is not limited to this configuration. For example, as shown in Fig. 7A and Fig. 7B, one side of the second recess 49 may form a predetermined angle θ with one side of the first bonding portion 40. The predetermined angle θ may be, for example, 45°.

[0082] In the above embodiment, the second recesses 49 are arranged in a lattice pattern with equal pitches in a plan view, but the present invention is not limited to this configuration. For example, as shown in FIG. 8A, the second recesses 49 may be arranged in a staggered pattern. Here, the staggered pattern refers to a pattern in which a row of the second recesses 49 is formed by a plurality of second recesses 49 arranged in a predetermined direction (e.g., the X direction), and the row of the second recesses 49 is shifted by half a pitch (1 / 2P) from the adjacent rows of the second recesses 49. In the staggered pattern, the rows of the second recesses 49 are alternately arranged with a half pitch shift.

[0083] Also, as shown in FIG. 8B, the density of the second recesses 49 arranged on the outer periphery side of the first recesses 46 may be higher than the density of the second recesses 49 arranged on the inner periphery side of the first recesses 46. The first recesses 46 are arranged at locations corresponding to the four corners of the first joint portion 40. Each of the first recesses 46 is provided at a position away from one corner of the first joint portion 40 by a distance X1 in the X direction and a distance Y1 in the Y direction. As described above, the distances X1 and Y1 may be 0.25 mm to 2.5 mm, and preferably 0.5 mm to 2.0 mm. The distance X1 may be the same as the distance Y1. In addition, in a region between the outer edge corresponding to the tip of the first joint portion 40 and the range of X1, the second recesses 49 may be arranged at a higher density than in a region on the first bent portion 43 side from X1. In addition, in a region between the outer edge corresponding to the side edge of the first joint portion 40 and the range of Y1, the second recesses 49 may be arranged at a higher density than in a region on the central side from Y1. In the high density region, there may be two or more times as many second recesses 49 per unit area as in the low density region.

[0084] 8C, the second recesses 49 may be disposed only on the outer periphery side of the first recesses 46. In this case, the first recesses 46 may be disposed at locations corresponding to the four corners of the first joint portion 40. Each of the first recesses 46 is provided at a position away from one corner of the first joint portion 40 by a distance X1 in the X direction and a distance Y1 in the Y direction. The second recesses 49 may be disposed in a region between the outer edge corresponding to the tip of the first joint portion 40 and the range X1, and in a region between the outer edge corresponding to the side edge of the first joint portion 40 and the range Y1.

[0085] In the above embodiment, a case where the second recess 49 is not formed on the inner bottom surface and the inner side surface of the first recess 46 has been described. However, this is not limited thereto, and the second recess 49 may be formed on the bottom surface of the first recess 46 as shown in Fig. 9A, for example. In this case, it is preferable that the second recess 49 formed on the bottom surface of the first recess 46 is also filled with sealing resin. This can be expected to provide a further anchor effect.

[0086] 9B, the side surface of the boss 45 and the inner surface of the first recess 46 may have a tapered shape that narrows downward. Furthermore, a second recess 49 may be formed on the inner surface of the first recess 46. In this case, it is preferable that the second recess 49 formed on the inner surface of the second recess 46 is also filled with sealing resin. This can be expected to provide a further anchoring effect.

[0087] Furthermore, in the above embodiment, the number and locations of the semiconductor elements 3 are not limited to the above configuration and can be changed as appropriate.

[0088] In addition, in the above embodiment, the number and layout of the circuit boards are not limited to the above configuration, and can be changed as appropriate.

[0089] In the above embodiment, the laminated substrate 2 and the semiconductor element 3 are configured to be rectangular or square in plan view, but are not limited to this configuration. These configurations may be formed into polygonal shapes other than those described above.

[0090] Furthermore, although the present embodiment and modifications have been described, other embodiments may be combinations of the above-described embodiments and modifications in whole or in part.

[0091] In addition, the present embodiment is not limited to the above-mentioned embodiment and modification, and may be modified, substituted, or altered in various ways without departing from the spirit of the technical idea. Furthermore, if the technical idea can be realized in a different way due to technological progress or a different derived technology, it may be implemented using that method. Therefore, the claims cover all embodiments that may be included in the scope of the technical idea.

[0092] The features of the above embodiment are summarized below. The semiconductor module of the above embodiment comprises a laminated substrate having a plurality of circuit boards arranged on an upper surface of an insulating plate, a semiconductor element arranged on the upper surface of at least one of the circuit boards, and a metal wiring board arranged on the upper surface of the semiconductor element, wherein the metal wiring board has a first bonding portion joined to the upper surface of the semiconductor element via a first bonding material, and the first bonding portion includes a plate-shaped portion having an upper surface and a lower surface, and has a boss formed on the lower surface of the plate-shaped portion and protruding toward the semiconductor element, a first recess formed on the upper surface of the plate-shaped portion at a location corresponding to directly above the boss, and a plurality of second recesses formed on the upper surface and smaller than the first recesses.

[0093] In the semiconductor module according to the above embodiment, the lower surface of the first joint portion excluding the boss is a flat surface.

[0094] In the semiconductor module according to the above embodiment, the surface roughness of the lower surface of the first joint portion is smaller than the surface roughness of the upper surface of the first joint portion.

[0095] In the semiconductor module according to the above embodiment, the area of ​​the second recess in a plan view is 0.5% to 75% of the area of ​​the boss or the first recess.

[0096] In the semiconductor module according to the above embodiment, the depth of the second recess is smaller than the depth of the first recess.

[0097] In the semiconductor module according to the above embodiment, the boss and the first recess have a circular shape in a plan view, and the second recess has a polygonal shape in a plan view.

[0098] In the semiconductor module according to the above embodiment, an annular convex portion is formed on the upper surface of the first joint portion so as to surround the second concave portion.

[0099] In the semiconductor module according to the above embodiment, a flat portion is formed on the upper surface of the first joint portion and is disposed between at least two adjacent annular protrusions.

[0100] In addition, in the semiconductor module of the above embodiment, the semiconductor module further includes a sealing resin that seals the laminated substrate, the semiconductor element, and the metal wiring plate, the sealing resin covering an upper surface of the first joint portion and penetrating into the first recess and the second recess.

[0101] In addition, the semiconductor module according to the above embodiment further includes a coating film interposed at the interface between an upper surface of the first joint portion and the sealing resin, the coating film having a thickness of 0.1 μm or more and 20 μm or less, and the first recess and the second recess are covered by the coating film.

[0102] In the semiconductor module according to the above embodiment, the second recesses are arranged in a staggered manner.

[0103] In addition, in the semiconductor module of the above embodiment, the density of the multiple second recesses arranged on the outer periphery side of the first recess is greater than the density of the multiple second recesses arranged on the inner periphery side of the first recess.

[0104] In the semiconductor module according to the above embodiment, the second recess is formed in the bottom surface of the first recess.

[0105] In addition, in the semiconductor module according to the above embodiment, the side surface of the boss and the inner side surface of the first recess have a tapered shape that narrows in diameter as it extends downward, and the second recess is formed on the inner side surface of the first recess.

[0106] Furthermore, in the semiconductor module according to the above embodiment, the metal wiring board has a second bonding portion bonded to an upper surface of the other circuit board via a second bonding material, the second bonding portion includes a plate-shaped portion having an upper surface and a lower surface, a second boss formed on the lower surface of the plate-shaped portion and protruding toward the other circuit board, and a third recess formed on the upper surface of the plate-shaped portion at a location corresponding to directly above the second boss, and the second recess is formed only on the upper surface of the first bonding portion.

[0107] Furthermore, in the semiconductor module of the above embodiment, the metal wiring plate has a connecting portion connecting the first joint portion and the second joint portion, a first bent portion connecting the first joint portion and one end of the connecting portion and bent, and a second bent portion connecting the second joint portion and the other end of the connecting portion and bent, and the second recess is formed only on the upper surface of the first joint portion.

[0108] Furthermore, the method for manufacturing a semiconductor module in the above embodiment is a method for manufacturing the above semiconductor module, which includes a step of forming the boss, the first recess, and the second recess by press processing in the process of manufacturing the metal wiring board. [Industrial Applicability]

[0109] As described above, the present invention has the effect of improving the bonding strength between a semiconductor element and a metal wiring board while ensuring the thickness of the bonding material, and is particularly useful for semiconductor modules for industrial or electrical equipment use and methods for manufacturing semiconductor modules.

[0110] This application is based on Japanese Patent Application No. 2021-173308 filed on October 22, 2021, the contents of which are incorporated herein in their entirety.

Claims

1. a laminated substrate having a plurality of circuit boards disposed on an upper surface of an insulating plate; a semiconductor device disposed on a top surface of at least one of the circuit boards; a metal wiring board disposed on an upper surface of the semiconductor element; the metal wiring board has a first bonding portion bonded to an upper surface of the semiconductor element via a first bonding material; The first joint portion includes a plate-like portion having an upper surface and a lower surface, a plurality of bosses formed on a lower surface of the plate-like portion and protruding toward the semiconductor element; a first recess formed on an upper surface of the plate-like portion at a position directly above each of the plurality of bosses; a plurality of second recesses formed on the top surface, the second recesses being smaller than the first recesses.

2. The semiconductor module according to claim 1 , wherein a lower surface of the first joint portion excluding the bosses is flat.

3. The semiconductor module according to claim 2 , wherein a surface roughness of the lower surface of the first joint portion is smaller than a surface roughness of the upper surface of the first joint portion.

4. 4. The semiconductor module according to claim 1, wherein an area of ​​the second recess in a plan view is 0.5% to 75% of an area of ​​the boss or the first recess.

5. 4. The semiconductor module according to claim 1, wherein a depth of the second recess is smaller than a depth of the first recess.

6. 4. The semiconductor module according to claim 1, wherein the boss and the first recess have a circular shape in a plan view, and the second recess has a polygonal shape in a plan view.

7. 4. The semiconductor module according to claim 1, wherein an annular convex portion surrounding the second concave portion is formed on an upper surface of the first joint portion.

8. The semiconductor module according to claim 7 , wherein a flat portion is formed on an upper surface of the first joint portion and is disposed between at least two of the annular protrusions adjacent to each other.

9. a sealing resin that seals the laminated substrate, the semiconductor element, and the metal wiring board; 4. The semiconductor module according to claim 1, wherein the sealing resin covers an upper surface of the first joint portion and fills the first recess and the second recess.

10. a coating film disposed at an interface between an upper surface of the first bonding portion and the sealing resin; The thickness of the coating film is 0.1 μm or more and 20 μm or less, The semiconductor module according to claim 9 , wherein the first recess and the second recess are covered with the coating film.

11. The semiconductor module according to claim 1 , wherein the second recesses are arranged in a staggered manner.

12. 4. The semiconductor module according to claim 1, wherein a density of the second recesses arranged on an outer circumferential side of the first recess is greater than a density of the second recesses arranged on an inner circumferential side of the first recess.

13. 4. The semiconductor device according to claim 1, wherein the second recess is formed on a bottom surface of the first recess. The semiconductor module according to any one of claims 1 to 5.

14. a side surface of the boss and an inner surface of the first recess have a tapered shape that decreases in diameter downward, The semiconductor module according to claim 13 , wherein the second recess is formed on an inner side surface of the first recess.

15. the metal wiring board has a second bonding portion bonded to an upper surface of the other circuit board via a second bonding material; The second joint portion includes a plate-like portion having an upper surface and a lower surface, a second boss formed on a lower surface of the plate-like portion and protruding toward the other circuit board; a third recess formed on the upper surface of the plate-like portion at a location directly above the second boss, The semiconductor module according to claim 1 , wherein the second recess is formed only in an upper surface of the first joint portion.

16. The metal wiring board is A connecting portion that connects the first joint portion and the second joint portion; a first bent portion that connects the first joint portion and one end of the connecting portion and is bent; a second bent portion that connects the second joint portion and the other end of the connecting portion and is bent, The semiconductor module according to claim 15 , wherein the second recess is formed only in an upper surface of the first joint portion.

17. A method for manufacturing a semiconductor module according to any one of claims 1 to 3, comprising the steps of: A method for manufacturing a semiconductor module, comprising the step of forming the plurality of bosses, the plurality of first recesses, and the plurality of second recesses by press working in a process of manufacturing the metal wiring board.

18. A laminated substrate having a plurality of circuit boards disposed on an upper surface of an insulating plate; a semiconductor device disposed on a top surface of at least one of the circuit boards; a metal wiring board disposed on an upper surface of the semiconductor element; Equipped with the metal wiring board has a first bonding portion bonded to an upper surface of the semiconductor element via a first bonding material; The first joint portion includes a plate-like portion having an upper surface and a lower surface, a boss formed on a lower surface of the plate-like portion and protruding toward the semiconductor element; a first recess formed on an upper surface of the plate-like portion at a position directly above the boss; a plurality of second recesses formed on the top surface and smaller than the first recesses; having A semiconductor module, wherein a density of the second recesses arranged on an outer circumferential side of the first recesses is greater than a density of the second recesses arranged on an inner circumferential side of the first recesses.

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