Improved current sensing and regulation for stepper motor drivers - Patents.com

Abstract

The integrated circuit (100A) includes an H-bridge circuit (102) having a first output node (OUT1) for coupling to a high-side terminal of an inductor (103) and a second output node (OUT2) for coupling to a low-side terminal of the inductor. A current sense FET (SNS-DRV) is coupled between a current source (110) and a lower supply voltage to provide a reference current (Itrip) including a peak current limit at the sense node. A current sense comparator (104) has a first input coupled to the sense node, a second input coupled to a second output node, and an output (113) coupled to send an output signal to a driver control circuit. A FET linear detection circuit (112) is coupled to receive a gate voltage (LS2) of an active low-side power FET (Mls2) and has an output (CMP_EN) coupled to enable the current sense comparator when the active low-side power FET is operating in its linear region.

Description

[Background technology]

[0001] In a stepper motor, motor position is controlled by regulating the current in two or more motor windings. Different stepper motor designs may have different numbers of windings, with the current waveform in each winding leading or lagging the current waveform associated with the other windings. Although many aspects of current regulation are well understood, there remain areas where control is problematic. Summary of the Invention

[0002] The disclosed embodiments provide a FET linearity detection circuit that tracks the gate voltage on the active low-side power FET to determine when to turn off blanking and when to enable a current sense comparator. The current sense comparator can be enabled when the active low-side power FET is in a linear region. In one embodiment, the current sense comparator is enabled when the voltage on the gate of the active low-side power FET is greater than one threshold voltage below the digital upper supply voltage.

[0003] In one aspect, an integrated circuit embodiment is disclosed that includes an H-bridge circuit including a first high-side power field effect transistor (FET) coupled in series with a first low-side power FET between a motor supply voltage and a lower supply voltage, a second high-side power FET coupled in series with a second low-side power FET between the motor supply voltage and the lower supply voltage, a first output node between the first high-side power FET and the first low-side power FET for coupling to a high-side terminal of an inductor, and a second output node between the second high-side power FET and the second low-side power FET for coupling to a low-side terminal of the inductor; a current sense FET coupled between a current source and a lower supply voltage, the current sense FET providing a reference current including a peak current limit at a sense node between the current source and the current sense FET; a current sense comparator including a first input coupled to the sense node, a second input coupled to a second output node, and an output coupled to send an output signal to a driver control circuit; and a FET linearity detection circuit coupled to receive a gate voltage of the second low side power FET, the FET having an output coupled to enable the current sense comparator when the second low side power FET is operating in a linear region.

[0004] In another aspect, a system embodiment is disclosed that includes a stepper motor having a first inductor and a second inductor, a first H-bridge circuit including a first high-side power FET coupled in series with a first low-side power FET between a motor supply voltage and a lower supply voltage, a second high-side power FET coupled in series with a second low-side power FET between the motor supply voltage and a lower supply voltage, a first output node between the first high-side power FET and the first low-side power FET for coupling to a high-side terminal of the first inductor, and a second output node between the second high-side power FET and the second low-side power FET for coupling to a low-side terminal of the first inductor; a first current sense FET coupled between a current source and a lower supply voltage, the first current sense FET providing a reference current including a peak current limit at a first sense node between the current source and the first current sense FET; a first current sense comparator including a first input coupled to the first sense node, a second input coupled to the second output node, and an output coupled to send an output signal to a driver control circuit; and a first FET linearity detection circuit coupled to receive a gate voltage of the second low-side power FET and having an output coupled to enable the first current sense comparator when the second low-side power FET is operating in a linear region.

[0005] In yet another aspect, an embodiment of a method of operating a stepper motor is disclosed, the method including: attaching a first output node in an H-bridge circuit to a high-side terminal of an inductor, attaching a second output node in the H-bridge circuit to a low-side terminal of the inductor, tracking a gate voltage on a second low-side power FET when the H-bridge circuit is operating in a drive mode to determine when the second low-side power FET is operating in a linear region, and enabling a first current sense comparator coupled to compare a current at the second output node to a peak current limit when the second low-side power FET is operating in a linear region, the first output node being between the first high-side power FET coupled to a motor supply voltage and the first low-side power FET coupled to a lower supply voltage, and the second output node being between the second high-side power FET coupled to the motor supply voltage and the second low-side power FET coupled to the lower supply voltage.

[0006] Embodiments of the present disclosure are illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings. In the drawings, like references indicate like elements. It should be noted that different references to "a" or "an" embodiment in the present disclosure are not necessarily to the same embodiment, and such references may mean at least one. Also, when a particular feature, structure, or characteristic is described in connection with an embodiment, it is submitted that it is within the knowledge of one skilled in the art to achieve such feature, structure, or characteristic in connection with other embodiments, whether or not explicitly described. As used herein, the term "couple" is intended to mean an indirect or direct electrical connection, unless otherwise limited to "communicatively coupled," which may include a wireless connection. Thus, when a first device couples to a second device, such connection may be through a direct electrical connection or through an indirect electrical connection via other devices and connections.

[0007] The accompanying drawings are incorporated in and form a part of this specification to illustrate one or more exemplary embodiments of the present disclosure. Various advantages and features of the present disclosure can be understood by reference to the following detailed description in conjunction with the appended claims and by reference to the accompanying drawing figures. [Brief description of the drawings]

[0008] [Figure 1A] 1 illustrates an integrated circuit having an H-bridge circuit and a FET linear detection circuit that provides adaptive blanking in accordance with an embodiment of the present disclosure.

[0009] [Figure 1B] 1 illustrates an example of a FET linear detection circuit according to an embodiment of the present disclosure.

[0010] [Figure 1C] 1 shows both the gate voltage on the active low-side power FET and the voltage on the second output node OUT2 when the drive mode is initiated.

[0011] [Figure 1D] 1 illustrates an example of a FET linear detection circuit according to an embodiment of the present disclosure.

[0012] [Figure 1E] 1B illustrates the timely termination of the blanking period and the absence of overshoot provided by the current regulation arrangement of FIG. 1A.

[0013] [Figure 2A] 1 illustrates a method of operating a stepper motor according to an embodiment of the present disclosure. [Figure 2B] 1 illustrates a method of operating a stepper motor according to an embodiment of the present disclosure. [Figure 2C] 1 illustrates a method of operating a stepper motor according to an embodiment of the present disclosure.

[0014] [Figure 3A] 1 illustrates an H-bridge and current sense circuit with current sensing during fast decay mode according to an embodiment of the present disclosure.

[0015] [Figure 3B] 1 illustrates an H-bridge and current sense circuit with current sensing during drive mode and fast decay mode, illustrating drive mode operation, according to an embodiment of the present disclosure.

[0016] [Figure 3C] 1 illustrates an H-bridge and current sensing circuit with current sensing during drive mode and fast decay mode, showing fast decay mode operation, according to an embodiment of the present disclosure.

[0017] [Figure 4A] 13 illustrates improvements to inductor current in several example scenarios using the disclosed current sensing circuitry in accordance with certain embodiments of the present disclosure. [Figure 4B] 13 illustrates improvements to inductor current in several example scenarios using the disclosed current sensing circuitry in accordance with certain embodiments of the present disclosure.

[0018] [Figure 5A] 1 illustrates a method of operating a stepper motor according to an embodiment of the present disclosure.

[0019] [Figure 5B] 1 illustrates additional elements in a method of operating a stepper motor, according to an embodiment of the present disclosure. [Figure 5C] 1 illustrates additional elements in a method of operating a stepper motor, according to an embodiment of the present disclosure.

[0020] [Figure 6] 1 is a schematic illustrating a system including a current regulation device according to an embodiment of the present disclosure.

[0021] [Figure 7A]1 shows the current through each of the two coils of a stepper motor and an example of the current control at each step.

[0022] [Figure 7B] 7B shows an example of current control at each step in the current diagram of FIG. 7A.

[0023] [Figure 8] 1 shows a baseline implementation of a current regulation circuit that may be used with a stepper motor.

[0024] [Figure 9] 1 shows an H-bridge circuit illustrating the current flow in each of the three phases.

[0025] [Figure 10] 13 shows the inductor current and voltage on the second output node OUT2 when the H-bridge is switched from the fast decay mode to the drive mode, illustrating the need for blanking when the drive mode begins.

[0026] [Figure 11A] 3 shows the overshoot that can occur when the blanking time is too long.

[0027] [Figure 11B] 1 illustrates one potential consequence of overshoot.

[0028] [Figure 12A] 1 illustrates a potential problem that can occur with a constant decay time. [Figure 12B] 1 illustrates a potential problem that can occur with a constant decay time. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0029] Next, specific embodiments of the present invention will be described in detail with reference to the accompanying drawings. In the following detailed description of the embodiments of the present invention, numerous specific details are set forth in order to provide a more thorough understanding of the present invention. However, it will be apparent to those skilled in the art that the present invention may be practiced without these specific details. In other instances, well-known features are not described in detail to avoid unnecessarily complicating the description.

[0030] Stepper motor operation Stepper motors typically have two coils, or inductors, with a 90 degree angle between them. For smooth operation, the current through each coil must have a 90 degree phase separation to create a rotating magnetic field for the rotor to follow. The current in the coils can be regulated with a square wave or a sine wave, with current regulation using a sine wave profile having smoother operation and increased position resolution. For the purposes of this disclosure, current regulation in a single winding will be referenced as an example of current regulation in each winding.

[0031] In a current implementation, the current waveform in a given motor winding is shaped by the output of a digital-to-analog converter (sine DAC). When the DAC output waveform is viewed at sufficient magnification, it is formed into a staircase shape. For each digital input code ("DAC code"), an ideal DAC would maintain a corresponding analog output voltage level. FIG. 7A shows a graph 700A of the output current in two coils of a stepper motor, with the "A" coil providing a current Aout that follows a sine wave and the "B" coil providing a current Bout that follows a cosine wave. In the example shown, each quadrant of the current signal is divided into 16 steps. Applications requiring greater position accuracy may utilize more steps, for example 256, 1024 or 4096 microsteps.

[0032] In the case of a stepper motor, each DAC input code results in a different mechanical rotational position of the stepper motor rotor. Thus, any particular section of the waveform is stepped upward to increase current and stepped downward to decrease current. Once a DAC input code is applied and the winding current reaches a level corresponding to the top of a DAC step-up or the bottom of a DAC step-down, that level of winding current is regulated to avoid any further mechanical rotation or oscillation of the rotor until a different DAC input code is applied. Without such regulation, factors such as supply voltage fluctuations or changes in the mechanical load on the stepper motor could cause the winding current to change during the desired step.

[0033] At each step in the waveform, such as circled step 705 in graph 700A, multiple pulse width modulation cycles may occur as illustrated by graph 700B in FIG. 7B. Graph 700B shows the current when current regulation is provided by the driver control, e.g., current Bout, which in this example uses a peak current regulation scheme. When the coil has a new rising step, the current Bout rises in drive mode until the current regulation circuit can detect that the current has reached a new peak current limit identified as Itrip. The current then decays in either fast or slow decay mode for a period of time, and then continues alternating between drive and decay cycles to maintain the desired current.

[0034] 8 shows a baseline implementation of a current regulation circuit 800 that may be used to drive one inductor of a stepper motor. The current regulation circuit 800 includes an H-bridge circuit 802 including a first high-side power FET Mhs1 coupled in series with a first low-side power FET Mls1 between the motor supply voltage Vm and a lower supply voltage, which may be ground. A first output node OUT1 is located between the first high-side power FET Mhs1 and the first low-side power FET Mls1. The H-bridge circuit 802 also includes a second high-side power FET Mhs2 coupled in series with a second low-side power FET Mls2 between the motor supply voltage Vm and the lower supply voltage, and a second output node OUT2 is located between the second high-side power FET Mhs2 and the second low-side power FET Mls2. During operation, an inductor 803 is coupled between the first output node OUT1 and the second output node OUT2, and the current through the inductor 803 is used to drive, for example, a stepper motor. Respective gate control signals HS1, LS1, HS2, and LS2 are provided for the power FETs Mhs1, Mls1, Mhs2, and Mls2.

[0035] The current regulation circuit 800 further includes a digital-to-analog (sine DAC) circuit 808, a voltage-to-current (V2I) operational amplifier 810, a drive mode current sense FET SNS-DRV, a current sense comparator 804, and a driver control circuit 806. A microstepping indexer 807 has an output coupled to the DAC circuit 808, which is also coupled to receive an analog reference voltage VREF. The output of the DAC circuit 808 is coupled to an input to the V2I operational amplifier 810. The drive mode current sense FET SNS-DRV is coupled between the V2I operational amplifier 810 and a lower supply voltage, and the gate of the drive mode current sense FET SNS-DRV is coupled to the gate of the second low-side power FET Mls2. A sense node 812 is located between the V2I operational amplifier 810 and the drive mode current sense FET SNS-DRV. A current sense comparator 804 has a first input coupled to the second output node, a second input coupled to a sense node 812 , and an output coupled to the driver control circuit 806 .

[0036] In the example shown in FIG. 8, the current regulation circuit 800 is operating in drive mode, with the first high-side power FET Mhs1 and the second low-side power FET Mls2 turned on. An inductor current Iout flows from the motor supply voltage Vm through the first high-side power FET Mhs1, the inductor 803, and the second low-side power FET Mls2 to the lower supply voltage, causing the inductor current Iout through the inductor 803 to increase. During operation, the microstepping indexer 807 provides microstepping indexer bits, which are a sequence of DAC codes that correspond to the desired shape of a current waveform associated with one or more stepper motor position commands. The DAC circuit 808 receives these microstepping indexer bits and an analog reference voltage VREF. The DAC circuit 808 converts the current DAC code to an analog voltage set point Vtrip, which is provided to a V2I operational amplifier 810, which provides a peak current limit Itrip corresponding to the current microstep. The drive mode current sense FET SNS-DRV is also turned on during the drive mode, so that the sense node 812 reflects the value of the peak current limit Itrip. The current sense comparator 804 compares the current on the second output node OUT2 to the peak current limit Itrip to determine when to turn off the drive mode. Such comparison is sent to the driver control circuit 806, which provides the gate control signals HS1, HS2, LS1, and LS2 to control the power FETs in the H-bridge circuit. When the current sense comparator 804 detects that the inductor current Iout is greater than the peak current limit Itrip, the drive mode ends and the decay mode begins.

[0037] 9 shows an H-bridge circuit 900 illustrating three conduction modes, drive mode DRV, fast decay mode FD, and slow decay mode SD, that may be used to drive a stepper motor. In the drive mode, a first high-side power FET Mhs1 and a second low-side power FET Mls2 are turned on to drive current from the motor supply voltage Vm through the first high-side power FET Mhs1, inductor 903, and second low-side power FET Mls2 to the lower supply voltage, as shown by the solid arrow. This current ramps up in inductor 903 at a rate of Vm / L, where L is the inductance of inductor 903. After an initial blanking period at the start of the drive mode, which is described further below, the current through inductor 903 is compared to a peak current limit Itrip using a comparator, such as, for example, current sense comparator 804 of current regulation circuit 800. As described above, when the inductor current Iout exceeds the value of the peak current limit Itrip, the driving mode is turned off, and then the H-bridge circuit is controlled to be in either the fast decay mode or the slow decay mode.

[0038] In the fast decay mode, the second high-side FET Mhs2 and the first low-side power FET Mls1 are turned on. Due to the inductance of inductor 903, current flows from the lower supply voltage through the first low-side power FET Mls1, inductor 903, and the second high-side power FET Mhs2 to the motor supply voltage Vm, as shown by the dotted arrow, but decays with a slope of -Vm / L. In one embodiment, the fast decay mode operates for a fixed time before re-entering the drive mode.

[0039] In the slow decay mode, both the first high side power FET Mhs1 and the second high side power FET Mhs2 are turned off and both the first low side power FET Mls1 and the second low side power FET Mls2 are turned on so that current travels in a loop from the lower supply voltage, through the first low side power FET Mls1, inductor 903, the second low side power FET Mls2, and back to the lower supply voltage, as shown by the curved arrow. As the name suggests, in the slow decay mode, the current through inductor 903 does not decay as quickly as in the fast decay mode.

[0040] Adaptive Blanking Time Although it is possible to start comparing the inductor current Iout with the peak current limit Itrip as soon as the drive mode begins, an accurate comparison cannot be obtained quickly due to noise in the circuit. Figure 10 illustrates this problem. Graph 1000 shows both the inductor current Iout and the voltage on the second output node OUT2 during the end of the fast decay mode and the start of the drive mode. During the end of the fast decay mode, the inductor current Iout decreases at a steady rate while the voltage on the output node stabilizes at approximately the motor supply voltage Vm.

[0041] When the fast decay mode is turned off at time T1, the voltage on the second output node OUT2 drops quickly towards zero while the inductor current Iout continues to move downwards briefly and then starts to rise again as the drive mode takes effect. When the voltage on the second output node OUT2 reaches zero, there may be ringing in the signal before the voltage starts to rise.

[0042] 8 provides an accurate measurement, the second low-side power FET Mls2 needs to operate in its linear region with the voltage on the second output node near zero. After drive mode begins, it is necessary to wait for the second output node OUT2 to slew from the motor supply voltage Vm to zero, for example around time T2, before attempting to sense the current in the inductor 803 through the second low-side power FET Mls2. This means that the blanking time must always be longer than the driver's slew time.

[0043] Determining the appropriate amount of blanking time has proven difficult, especially when the current regulation system is expected to operate over a range of motor voltages and inductances. Providing a higher blanking time, i.e., waiting a longer time before sensing after the drive mode begins, may in some cases result in the inductor current Iout exceeding the value of the peak current limit Itrip. FIG. 11A shows a graph 1100A including an example of this occurrence. When the blanking time Tblank is completed, the inductor current Iout has already exceeded the peak current limit Itrip. In some embodiments, for example, when the decay time Toff is a constant value, a blanking time that is too high may lead to loss of regulation and runaway current in subsequent cycles. This problem is more pronounced during regulation at lower current levels and higher ratios of motor supply voltage to inductance, i.e., Vm / L. On the other hand, providing too little blanking time may result in premature turn-off of the drive mode and unregulated inductor current Iout. This current distortion causes the stepper motor to move more roughly, resulting in vibration, audible noise, and angular error. An example of this non-uniform motion is shown in graph 1100B of FIG.

[0044] While the blanking time of a driver for a stepper motor is largely dependent on the slew rate of the switching node, drivers for stepper motors supporting the automotive and industrial markets are expected to offer a wide range of programmable slew rates, for example, from 10V / μs to 150V / μs, to meet criteria such as less electromagnetic interference (EMI), additionally optimal power dissipation, etc. Such slew rates can vary by approximately 30% over process and temperature.

[0045] Many driver circuits for stepper motors use a certain blanking time. This blanking time is derived from the maximum of simulation data and depends on the slew rate variations with process, temperature, device type, and to some extent the motor supply voltage Vm. Typically, this blanking time is chosen for the worst case and is therefore higher than necessary in many other situations. Choosing the blanking time according to the worst case scenario can result in current distortion problems and / or current runaway. Some driver circuits have programmable blanking times for lower and higher currents. At lower current levels, much less noise is created and therefore a low blanking time is desirable to prevent current runaway. However, making the blanking time programmable puts the burden on the customer to select the blanking time based on the motor being used.

[0046] Many problems can arise by trying to have a certain blanking time, since different slew rate options require different blanking times. For some part families, the design time and digital logic modifications are extensive to support different blanking times for multiple slew rates. For some devices, customers can change the slew rate by adjusting a resistor provided to a pin. In such cases, it is difficult to program the blanking time. Although the blanking time limit can be selected to meet the worst rare case to prevent false trips, the result of this selection is generally a blanking time that is higher than necessary, which can lead to the current distortion problems and / or current runaway mentioned above.

[0047] Also, due to device modeling limitations, if the slew rate in silicon does not match the simulated slew rate, the result may be functional failure during current sensing. When a higher blanking time is chosen, it imposes limitations on the maximum step frequency and maximum rotation speed for the stepper motor. Therefore, it is essential to optimize the blanking time.

[0048] 1A illustrates an H-bridge and current sense circuit 100A with a FET linear sense circuit 112 providing adaptive blanking in accordance with an embodiment of the present disclosure. The H-bridge and current sense circuit 100A includes an H-bridge circuit 102 having an inductor 103 coupled between a first output node OUT1 and a second output node OUT2. The H-bridge and current sense circuit 100A further includes a microstepping indexer 107, a DAC circuit 108, a V2I operational amplifier 110, a drive mode current sense FET SNS-DRV, and a current sense comparator 104. Although not specifically illustrated in the current sense circuit 100A, except for the H-bridge receiving the motor voltage Vm, the indexer 107, the DAC 108, the V2I operational amplifier 110, the drive mode current sense FET SNS-DRV, the current sense comparator 104, and the FET linear sense circuit 112 are each powered by a digital upper supply voltage DVDD, which in one embodiment is 5V. The microstepping indexer 107 and an analog reference voltage VREF are coupled to provide inputs to a DAC circuit 108. An output of the DAC circuit 108 is coupled to an input of a V2I operational amplifier 110. A drive mode current sense FET SNS-DRV is coupled between the V2I operational amplifier 110 and a lower supply voltage, and a gate of the drive mode current sense FET SNS-DRV is coupled to a gate of a second low-side power FET Mls2. A sense node 111 is located between the V2I operational amplifier 110 and the drive mode current sense FET SNS-DRV. A current sense comparator 104 has a first input coupled to a second output node OUT2, a second input coupled to the sense node 111, and an output coupled to provide an output signal 113 to a driver control circuit (not specifically shown).

[0049] When the H-bridge and current sense circuit 100A is operating in drive mode, the first high-side power FET Mhs1 and the second low-side power FET Mls2 are turned on and the inductor current Iout flows as shown by arrow 114. Operation in drive mode continues as described above with the microstepping indexer 107 providing indexer bits that are a sequence of DAC codes corresponding to the desired shape of the current waveform. The DAC circuit 108 receives these microstepping indexer bits and an analog reference voltage VREF, converts the current DAC codes to an analog voltage set point Vtrip, and provides the analog voltage set point Vtrip to the V2I operational amplifier 110. During drive mode, the drive mode current sense FET SNS-DRV is turned on so that the V2I operational amplifier 110 is coupled to the lower supply voltage to provide a peak current limit Itrip corresponding to the current microsteps. The sense node 111 provides the value of the peak current limit Itrip to a second input node of the current sense comparator 104, which compares the current on the second output node OUT2 with the peak current limit Itrip. When the current sense comparator 104 detects that the inductor current Iout is greater than the peak current limit Itrip, the current sense comparator 104 sends a high value to the driver control circuit, so that the drive mode is terminated and the decay mode is initiated.

[0050] The FET linear detection circuit operates with the active low-side power FET in the H-bridge circuit, or with the second low-side power FET when both low-side power FETs are active. The operation of the FET linear detection circuit during drive mode is described herein. However, as further described below, embodiments of the FET linear detection circuit may also operate during fast decay mode or slow decay mode. In the H-bridge and current sense circuit 100A, the FET linear detection circuit 112 is coupled to receive as an input the second low-side gate control signal LS2 and to provide a comparator enable signal CMP_EN to the current sense comparator 104. The FET linear detection circuit 112 provides adaptive blanking by enabling current sensing in the current sense comparator 104 after the transition of the second low-side power FET Mls2 from the “saturation region” to the “linear region”. In one embodiment, the FET linear detection circuit 112 makes this determination by detecting when the gate of the second low-side power FET LS2 is more than one threshold voltage below the digital upper supply voltage DVDD.

[0051] 1C shows a graph 100C of the voltage on the second low-side gate control signal LS2 and the voltage on the second output node OUT2 when the second low-side power FET Mls2 is turned on. This short period is divided into three separate time periods. In the first time period, the voltage on the second low-side gate control signal LS2 starts to rise and passes the threshold voltage Vth, so the second low-side power FET Mls2 starts to turn on. In the second time period, the second low-side gate control signal LS2 is at the Miller plateau and does not rise. During the third time period, the second low-side gate control signal LS2 starts to rise again.

[0052] In drive mode, the voltages of both the first high-side gate control signal HS1 and the second low-side gate control signal LS2 go high, causing the voltage on the second output node OUT2 to transition from high to low. As can be seen in graph 100C, the second low-side gate control signal LS2 remains in the Miller plateau region during the transition of the second output node OUT2. The FET linearity detection circuit 112 detects that the voltage has passed the end of the Miller plateau. This indicates that the second low-side power FET Mls2 has entered its linear region, and therefore the end of the need for a blanking time.

[0053] 1B illustrates an embodiment of a FET linear detection circuit 100B that may use the knowledge shown in graph 100C to determine when to turn on a comparator enable signal CMP_EN. In the FET linear detection circuit 100B, a detection P-type field effect transistor (PFET) M3 is coupled in series with a current sink 115 between a digital upper supply voltage DVDD and a lower supply voltage. During a drive mode, when used for adaptive blanking, the gate of the detection PFET M3 is coupled to the gate of a second low-side power FET Mls2 to receive a second low-side gate control signal LS2. Also, a Schmitt trigger 116 is coupled between the digital upper supply voltage DVDD and the lower supply voltage. The Schmitt trigger has an input coupled to a gate sense node 118 between the detection PFET M3 and the current sink 115, and has an output coupled to provide a comparator enable signal CMP_EN that enables the current sense comparator 104.

[0054] During operation of the H-bridge and current sense circuit 100A, when the H-bridge circuit 102 is in fast decay mode, the second low-side gate control signal LS2 is low so that the sense PFET M3 is turned on and provides a current to the current sink 115 that keeps the voltage on the gate sense node 118 high. The Schmitt trigger 116 generates a low signal on the comparator enable signal CMP_EN so that the current sense comparator 104 is not enabled. When the H-bridge circuit 102 starts driving mode, the second low-side gate control signal LS2 starts to rise and when it reaches a threshold voltage Vt below the digital supply voltage DVDD, the sense PFET M3 is turned off. As the current sink 115 continues to sink current from the gate sense node 118, the voltage on the gate sense node 118 goes low and the Schmitt trigger 116 provides a high signal on the comparator enable signal CMP_EN to trigger a comparison of the inductor current Iout to the peak current limit Itrip.

[0055] FIG. 1D shows the second low-side control signal LS2 and the comparator enable signal CMP_EN during the drive mode. Initially, both the second low-side control signal LS2 and the comparator enable signal CMP_EN are low, but when the second low-side power FET Mls2 is turned on, the second low-side control signal LS2 ramps upward. When the second low-side control signal LS2 is greater than the value of DVDD-Vt, the comparator enable signal CMP_EN goes high, ending blanking and starting current sensing. When the drive mode ends, the second low-side control signal LS2 falls below DVDD-Vt, the comparator enable signal CMP_EN goes off, and the current sense comparator 104 is disabled until the next time the second low-side power FET Mls2 is turned on. Thus, the FET linear detection circuit 100B as an example of the FET linear detection circuit 112 provides an adaptive blanking period that is independent of the slew rate. The blanking time can be optimal, preventing premature sensing or current runaway.

[0056] 1E shows an example graph 100E of the inductor current Iout when the FET linear detection circuit 112 is used with the H-bridge circuit 102. Instead of having too long blanking period as shown in graph 1100A, the inductor current Iout in graph 100E has a shortened blanking period Tblank. This shorter blanking period enables the current sense comparator 104 in time to detect that the inductor current Iout reaches the peak current limit Itrip and trigger the start of the fast decay mode. Therefore, problems such as current runaway can be prevented.

[0057] 2A illustrates a method 200 of operating a stepper motor according to an embodiment of the disclosure. The method begins with attaching a first output node of an H-bridge circuit to a high-side terminal of an inductor (205) and attaching a second output node of the H-bridge circuit to a low-side terminal of the inductor (210). The first output node is between a first high-side power FET coupled to the motor supply voltage and a first low-side power FET coupled to the lower supply voltage. The second output node is between a second high-side power FET coupled to the motor supply voltage and a second low-side power FET coupled to the lower supply voltage. When the H-bridge circuit is operating in a drive mode, the gate voltage on the second low-side power FET is tracked (215) to determine when the second low-side power FET is operating in a linear region. When the second low-side power FET is operating in a linear region, a first current sense comparator is enabled (220). The first current sensing comparator is coupled to compare the inductor current Iout at the second output node OUT2 to the peak current limit Itrip.

[0058] Although described above with respect to operation in the drive mode, adaptive blanking may also be utilized in both the slow decay mode and the fast decay mode. Operation in the slow decay mode is illustrated in FIG. 2B. When the H-bridge circuit is operating in the slow decay mode, the gate voltage on the second low-side power FET is tracked (225) to determine when the second low-side power FET is operating in a linear mode. When the second low-side power FET is operating in a linear mode, a first current sense comparator is enabled (230). The first current sense comparator is now coupled to compare the current at the second output node to a first valley current limit.

[0059] As shown in FIG. 2C, when the H-bridge circuit is operating in a fast decay mode, the gate voltage on the first low-side power FET is tracked (235) to determine when the first low-side power FET is operating in a linear mode. When the first low-side power FET is operating in a linear mode, a second current sense comparator is enabled (240). The second current sense comparator is coupled to compare the current at the first output node combined with the first valley current limit to the lower supply voltage. It will be appreciated that the method shown in FIG. 2B and FIG. 2C is operable when the reference current used by the comparator is a hysteresis reference current that carries both the peak current limit Itrip and the valley current limit Ivalley.

[0060] The disclosed FET linear sensing circuits and related methods for operating a stepper motor may provide one or more of the following advantages. Driver slew rate agnostic. · Independent of algorithms used for current regulation, e.g., constant off-time, constant frequency, ripple control, etc. Eliminates fixed timers for each of several different slew rates, allowing for simplified circuitry, reduced area, reduced digital complexity, and faster design time for product families. · No pessimistic blanking time is selected, thus preventing average motor current errors and current runaway problems. Automatically adjusts minimum drive time with output current. Limiting drive time at low current steps can help reduce zero-crossing distortion. When the H-bridge circuit transitions from drive mode to slow decay mode, the second output node OUT2 already has a value of zero, therefore there is no slew of the second output node OUT2. In this case, the FET linear detection circuit 112 already provides a high value, so there is no blanking time. This response is ideal. The prior art does not track the gate voltage, so the prior art circuit adds blanking time regardless of the transition.

[0061] Current Sensing in Fast Decay Mode When the desired waveform requires step reduction, the inductor current Iout needs to be dropped to the next lower level in each step. In a ripple control scheme, when a step reduction occurs, a fast decay mode is initiated to reach the lower level as quickly as possible. However, existing designs do not have current sensing during fast decay mode. Instead, after a certain time in fast decay mode, the driver goes into drive mode to sense the current.

[0062] FIG. 12A shows a graph 1200A illustrating this problem in a motor with a high inductance. Graph 1200A shows the peak current limit Itrip, the inductor current Iout, and the stepping indicator Step. First, the inductor current Iout shows the current when successive drive modes drive the current up to the value of the peak current limit Itrip and then allow the current to decay for a fixed amount of time. At time Ta, the stepping indicator Step provides a pulse to indicate that a new step is desired, which in the illustrated embodiment is a downward step. As the value of the peak current limit Itrip drops downward, the inductor current Iout is set to decay in fast decay mode for a fixed period of time of 2 μs, and then the H-bridge circuit is placed in drive mode for a period of time long enough to allow the blanking time to elapse and measure the inductor current Iout. Thus, alternating fast decay cycles with drive mode increases the overall time it takes to reach the next lower level, rather than the desired quick drop to the next lower level. This creates torque ripple.

[0063] A different problem may arise for a low inductance motor, as shown by graph 1200B in FIG. 12B. In this situation, a fast decay period of 2 μs is again utilized. However, instead of taking a long period to decay to the next level, the inductor current Iout drops further than desired during the fast decay mode each time the stepping indicator Step provides a pulse to drop the value of the peak current limit Itrip. This excessive drop results in a large current ripple that distorts the current waveform. As shown by graphs 1200A and 1200B, the delay-based approach to the fast decay time cannot be optimized across motor parameters.

[0064] The problem shown in graphs 1200A and 1200B is due to the fact that the inductor current Iout cannot be sensed in fast decay mode. If the current through the motor could be reliably sensed in fast decay mode, the use of a time-based approach could be eliminated and the current could be more accurately regulated. The problem with sensing the inductor current Iout during fast decay mode is that the inductor voltage is negative, which poses a problem for current detection.

[0065] 3A shows an H-bridge and current sense circuit 300A including an H-bridge circuit 301 receiving the motor supply voltage Vm as an upper supply voltage and a current sense circuit 303 receiving the digital supply voltage DVDD as an upper supply voltage. The current sense circuit 303 is coupled to detect a valley current limit during a fast decay mode and includes a microstepping indexer 307, a DAC circuit 308, a V2I operational amplifier 310, a fast decay mode current sense FET SNS-FD, and a current sense comparator 304. The microstepping indexer 307 and an analog reference voltage VREF are coupled to provide inputs to the DAC circuit 308. The DAC circuit 308 is coupled to an input of the V2I operational amplifier 310. The fast decay mode current sense FET SNS-FD is coupled between the V2I operational amplifier 310 and a first output node OUT1, and a gate of the fast decay mode current sense FET SNS-FD is coupled to a gate of a first low-side power FET Mls1. A sense node 311 is located between the V2I operational amplifier 310 and the fast decay mode current sense FET SNS-FD. A current sense comparator 304 has a first input coupled to the sense node 311, a second input coupled to the lower supply voltage, and an output coupled to provide an output signal 313 to a driver control circuit (not specifically shown).

[0066] During the fast decay mode, the current at the first output node OUT1 is negative, so that the current at the first output node OUT1 is added to a valley current limit Ivalley and provided to a first input of the current sense comparator 304. The combined current sensed on the sense node 311 is compared to a lower supply voltage, e.g., 0V, to detect when the combined current crosses zero. In one embodiment, the H-bridge and current sense circuit 300A may be combined with a current regulation circuit 800 such that the current sense comparator 804 is a first current sense comparator used to regulate the current during the drive mode and the current sense comparator 304 is a second current sense comparator used to regulate the current during the fast decay mode. Also, in a situation where both the peak current limit Itrip and the valley current limit Ivalley are utilized, the current sense comparator 804 may be utilized to sense the current during the slow decay mode when both the first low-side power FET Mls1 and the second low-side power FET Mls2 are on.

[0067] Another embodiment of an H-bridge and current sense circuit 300B is shown in both FIG. 3B and FIG. 3C. An H-bridge and current sense circuit 300B1 is shown in FIG. 3B in a drive mode configuration, and an H-bridge and current sense circuit 300B2 is shown in FIG. 3C in a fast decay mode configuration. With the H-bridge and current sense circuit 300B, current sensing can be performed using a single current sense comparator 320 in both drive and fast decay modes. As shown in FIG. 3B and FIG. 3C, the H-bridge and current sense circuit 300B is part of an integrated circuit (IC) chip 321 that includes an H-bridge circuit 322 and a current sense circuit 324. Four pins on the IC chip 321, namely pins P1-P4, are shown on the H-bridge and current sense circuit 300B. A first pin P1 can be coupled to a motor supply voltage Vm to provide the motor supply voltage to the H-bridge. A second pin P2 is coupled to the first output node OUT1 and may be coupled to a high side terminal of a first inductor 326 of the stepper motor 328. A third pin P3 is coupled to the second output node OUT2 and may be coupled to a low side terminal of the first inductor 326. A fourth pin P4 is coupled to provide a lower supply voltage and, in one embodiment, may be coupled to ground. A second copy of the H-bridge and current sense circuit 300B (not specifically shown), typically on the IC chip 321, may be coupled to a terminal of a second inductor 330 in the stepper motor 328, but receives a control signal providing a waveform that is offset from the waveform of the H-bridge and current sense circuit 300B.

[0068] The current sense circuit 324 includes a current source CS1 coupled in series with a sense node SNS-DUAL between a digital upper supply voltage DVDD and a first switchable node SW1. The first switchable node SW1 can be switchably coupled to a first output node OUT1 or a lower supply voltage. A sense node 332 is between the current source CS1 and the first switchable node SW1 and is coupled to a first input of a current sense comparator 320. A second input of the current sense comparator 320 is coupled to a second switchable node SW2. The second switchable node SW2 can be switchably coupled to a lower supply voltage or a second output node OUT2. As will be further described below, the current source CS1 provides a hysteresis reference current. At each step in the desired waveform, the current source CS1 can provide both a corresponding peak current limit and a corresponding valley current limit.

[0069] As shown in FIG. 3B, the H-bridge and current sense circuit 300B1 is operating in drive mode, and current is traveling through the H-bridge circuit 322 and the first inductor 326, as indicated by the arrow 334. The second output node OUT2 provides a second output voltage V2 equal to Iout×Rds(on), where Iout is the inductor current and Rds(on) is the source-drain on resistance for the main FET, which in drive mode is the second low-side power FET Mls2. In drive mode, the second output node OUT2 is coupled to a second input of the current sense comparator 320 via the second switchable node SW2, and the first switchable node SW1 is coupled to the lower supply voltage. During drive mode, the current source CS1 provides a peak current limit Itrip. Thus, the current sense comparator 320 compares the current on the second output node OUT2 with the peak current limit Itrip, and when the current on the second output node OUT2 becomes greater than the peak current limit Itrip, an output signal 319 is sent to a driver circuit (not specifically shown) to terminate the drive mode. Although not specifically shown, the settings in the H-bridge and current sense circuit 300B1 can also be used to provide adaptive blanking during the slow decay mode when both the first low-side FET Mls1 and the second low-side FET Mls2 are active. In this case, the current source CS1 provides a current representing the valley current limit.

[0070] 3C, the H-bridge and current sense circuit 300B2 is operating in a fast decay mode, with current traveling through the H-bridge circuit 322 and the first inductor 326, as indicated by arrow 336. The first output node OUT1 provides a first output voltage V1 equal to −Iout×Rds(on), where Iout is again the inductor current and Rds(on) is the source-drain on resistance for the main FET, which in the fast decay mode is the first low-side power FET Mls1. In the fast decay mode, the first output node OUT1 is coupled to the sense node 332 and the first input of the current sense comparator 320 via the first switchable node SW1, and the second switchable node SW2 is coupled to the lower supply voltage. During the fast decay mode, current source CS1 provides a valley current limit Ivalley and a current sensing comparator 320 compares the current on the first output node OUT1 combined with the valley current limit Ivalley to zero, and when the combined current crosses zero, an output signal 319 is sent to a driver circuit (not specifically shown) to terminate the fast decay mode.

[0071] Although not specifically shown in these figures, each of the H-bridge and current sense circuits 300A, 300B may include a FET linear detection circuit for determining when to enable the respective current sense comparator 304, 320. In Figure 3A, the FET linear detection circuit may be coupled to receive the gate voltage on the first low-side power FET Mls1 and may be coupled to the comparator 304 to provide a comparator enable signal. In Figure 3B, the FET linear detection circuit may be switchably coupled to receive the gate voltage on the first low-side power FET Mls1 during the fast decay mode and to receive the gate voltage on the second low-side power FET Mls2 during the drive mode and during the slow decay mode.

[0072] Figures 12A and 12B show the problems that can occur when the current cannot be sensed in fast decay mode. Figures 4A and 4B show the inductor current Iout when using current sensing in fast decay mode. Figure 4A shows a situation similar to Figure 12A, and Figure 4B shows a situation similar to Figure 12B. In both Figures 4A and 12A, the motor has a high inductance. 2 μs is used for each fast decay period, after which a slow drop to the new setting occurs when the switch to the drive mode continues. In Figure 4A, since current sensing was used in fast decay mode, the inductor current Iout can remain in fast decay mode until the valley current limit Ivalley is reached, resulting in a faster drop to the new level.

[0073] In both Figures 4B and 12B, the motor has a low inductance. When current sensing is not available for a certain fast decay period, the inductor current Iout may fall far below the peak current limit Itrip before the motor switches to drive mode to determine the value of the inductor current Iout. By using valley current limit and current sensing in the fast decay mode in Figure 4B, the inductor current Iout may not fall below the desired value, providing a smoother operation.

[0074] 5A illustrates a method 500A of operating a stepper motor according to an embodiment of the present disclosure. The method 500A begins with attaching a first output node of an H-bridge circuit to a high-side terminal of an inductor (505) and attaching a second output node of the H-bridge circuit to a low-side terminal of the inductor (510). The first output node is between a first high-side power FET coupled to the motor supply voltage and a first low-side power FET coupled to the lower supply voltage, and the second output node is between a second high-side power FET coupled to the motor supply voltage and a second low-side power FET coupled to the lower supply voltage.

[0075] The method 500A further includes coupling (515) a current source to provide a valley current limit during the fast decay mode, the current source coupled to the current sense node and the current sense node coupled to a first input of the current sense comparator. The method further includes coupling (520) the current sense node to the first output node and a second input of the current sense comparator to a lower supply voltage.

[0076] Method 500A may be used when the H-bridge and current sense circuit is configured as in H-bridge and current sense circuit 300A or as in H-bridge and current sense circuit 300B. Figures 5B and 5C add additional elements to method 500A. However, Figures 5B and 5C may only be used when current sensing during both drive mode and fast decay mode is performed with a single current sense comparator. In this case, during drive mode, the current source is coupled to provide a peak current limit (525). The current sense node is coupled to the lower supply voltage and the second input of the current sense comparator is coupled to the second output node (530). During slow decay mode, the current source is coupled to provide a valley current limit (535), the current sense node is coupled to the second output node and the second input of the current sense comparator is coupled to the lower supply voltage (540).

[0077] The use of fast decay current sensing may provide good current regulation over all variations in motor supply voltage Vm and inductance L. Also, improved ripple accuracy may be provided by the use of a single comparator to measure both the peak and valley current limits.

[0078] 6 shows a system 600 that may include one or more of the H-bridge and current sense circuits 100A, 300A, 300B1, 300B2. The system 600 includes an IC chip 602 that is coupled to drive a stepper motor 604 by controlling an inductor current through a first inductor 606 and a second inductor 608. Alternatively, the IC chip may be used to drive a bidirectional current through two external loads. In one alternative embodiment, the two external loads are a first brushed DC motor 603 and a second brushed DC motor 605.

[0079] Many pins provide inputs and outputs to the IC chip 602, but only some of these pins are described in this application. Some first pins P1 are coupled to a motor supply voltage Vm, and some fourth pins P4 are coupled to ground to provide a lower supply voltage. A second pin P2 is coupled to a high-side terminal of a first inductor 606, and a pin P3 is coupled to a low-side terminal of the first inductor 606. Similarly, a fifth pin P5 is coupled to a high-side terminal of a second inductor 608, and a sixth pin P6 is coupled to a low-side terminal of the second inductor 608.

[0080] Within the IC chip 602, a power supply circuit 610 receives the motor voltage Vm and distributes power to other circuits on the IC chip 602. The power supply circuit 610 may include, for example, a charge pump and a regulator for a digital upper supply voltage DVDD. A control input circuit 612 receives logic control signals used to control the H-bridge circuit. These logic control signals may include, for example, an enable signal and a pulse width modulation (PWM) control. Both the power supply circuit 610 and the control input circuit 612 are coupled to a digital core circuit 616. The digital core circuit 616 is coupled to send control signals to a first gate driver circuit 620 and a second gate driver circuit 622.

[0081] The first gate driver 620 is coupled to an H-bridge and current sense circuit 624 to provide control signals for the H-bridge FETs and to receive current sense information. The H-bridge and current sense circuit 624 is coupled to a high-side terminal of the first inductor 606 via a second pin P2 and to a low-side terminal of the first inductor 606 via a third pin P3. The current sense element in the H-bridge and current sense circuit 624 is also coupled to a current sense comparator 625 for comparison to a first reference voltage Vref1.

[0082] Similarly, the second gate driver 622 is coupled to an H-bridge and current sense circuit 626 to provide control signals for the associated H-bridge FETs and to receive current sense information. The H-bridge and current sense circuit 626 is coupled to the high side terminal of the second inductor 608 via a fifth pin P5 and to the low side terminal of the second inductor 608 via a sixth pin P6. The current sensing element in the H-bridge and current sense circuit 626 is also coupled to a current sense comparator 627 for comparison to a second reference voltage Vref2.

[0083] The IC chip 602 also includes an analog voltage reference input circuit 614 coupled to receive a voltage reference signal for each gate driver, a protection circuit 628 that monitors, for example, overcurrent, undervoltage, and overtemperature conditions, and a fault output circuit 630 that provides notification of any faults detected by the protection circuit 628. The IC chip 602, more specifically, the H-bridge and current sense circuits 624, 626 may incorporate a FET linear detection circuit, for example, the FET linear detection circuit 100B, to provide adaptive blanking. The IC chip may also incorporate current sensing during the fast decay mode, either alone or in combination with adaptive blanking. The comparator used for current sensing during the fast decay mode may be dedicated to current sensing in the fast decay mode, as shown in current sense circuit 303, or may be shared between the drive mode and the fast decay mode, as shown in current sense circuit 324.

[0084] Applicant has disclosed methods, circuits, systems, and IC chips that provide adaptive blanking that is agnostic to the driver slew rate and independent of the algorithm used for current regulation. Applicant has also disclosed methods, circuits, systems, and IC chips that provide current sensing in a fast decay mode that allows for faster drop to lower steps without dropping lower than desired. Adaptive blanking and current sensing in fast decay mode can be utilized individually or in conjunction with each other to provide more robust current sensing. With these tools, motor operation can be smoother and less noisy.

[0085] Although various embodiments have been shown and described in detail, the claims are not limited to any particular embodiment or example. Nothing in the above detailed description should be construed as implying that any particular component, element, step, act, or function is essential and therefore should be included in the claims. Reference to a singular element does not mean "one and only one" unless expressly stated to be so, but rather means "one or more." All structural and functional equivalents of the elements of the above-described embodiments known to those skilled in the art are expressly incorporated herein by reference and are intended to be encompassed by the claims of this application. Thus, those skilled in the art will recognize that the exemplary embodiments described herein can be made with various modifications and alterations within the spirit and scope of the appended claims below.

Claims

1. 1. An integrated circuit comprising: An H-bridge circuit, a first low side power field effect transistor (FET); a first high side power FET coupled in series with the first low side power FET between a motor supply voltage and a lower side supply voltage; a second low side power FET; and a second high side power FET coupled in series with the second low side power FET between the motor supply voltage and the lower side supply voltage; a first output node between the first high side power FET and the first low side power FET, the first output node being coupled to a high side terminal of an inductor; a second output node between the second high side power FET and the second low side power FET, the second output node being coupled to a low side terminal of the inductor; The H-bridge circuit includes: a current sense FET coupled between a current source and the lower supply voltage, the current sense FET providing a reference current having a peak current limit to a sense node between the current source and the current sense FET; a current sense comparator including a first input coupled to the sense node, a second input coupled to the second output node, and an output coupled to a driver control circuit; 1. A FET linear detection circuit, comprising: a sense P-type field effect transistor (PFET) coupled in series with a current sink between a digital upper supply voltage and the lower supply voltage, the sense PFET having a gate coupled to a gate of the second low side power FET to receive a gate voltage of the second low side power FET; a Schmitt trigger coupled between the digital upper supply voltage and the lower supply voltage, the Schmitt trigger having an input coupled to a gate sense node between the sense PFET and the current sink and an output coupled to enable the current sense comparator when the second low side power FET is operating in a linear region; the FET linear detection circuit comprising: [0023] An integrated circuit including

2. 2. The integrated circuit of claim 1, an integrated circuit, wherein the FET linear detection circuit is configured to enable the current sense comparator when the gate voltage rises above a value that is one threshold voltage below the digital upper supply voltage.

3. 2. The integrated circuit of claim 1, an integrated circuit wherein a gate of the current sense FET is coupled to a gate of the second low-side power FET.

4. 2. The integrated circuit of claim 1, The current source is a digital-to-analog converter (DAC); a voltage to current operational amplifier coupled to the DAC, the voltage to current operational amplifier coupled to provide the reference current; 4. An integrated circuit comprising:

5. 2. The integrated circuit of claim 1, The integrated circuit wherein the reference current is a hysteretic current reference further including a valley current limit.

6. 6. An integrated circuit according to claim 5, the FET linearity detection circuit is switchably coupled to a gate of the first low side power FET to enable the current sense comparator when the first low side power FET is operating in a linear region.

7. 1. A system comprising: A stepper motor; A first H-bridge circuit, a first low side power FET; a first high side power FET coupled in series with the first low side power FET between a motor supply voltage and a lower side supply voltage; a second low side power FET; and a second high side power FET coupled in series with the second low side power FET between the motor supply voltage and the lower side supply voltage; a first inductor including a high side terminal coupled to a first output node between the first high side power FET and the first low side power FET and a low side terminal coupled to a second output node between the second high side power FET and the second low side power FET; the first H-bridge circuit comprising: A first current source; a first current sense FET coupled between the first current source and the lower supply voltage, the first current sense FET providing a reference current including a peak current limit to a first sense node between the current source and the first current sense FET; a first current sense comparator having a first input coupled to the first sense node, a second input coupled to the second output node, and an output coupled to a driver control circuit; 1. A first FET linear detection circuit, comprising: A current sink; a sense P-type field effect transistor (PFET) coupled in series with the current sink between a digital upper supply voltage and the lower supply voltage, the sense PFET having a gate coupled to a gate of the second low side power FET to receive a gate voltage of the second low side power FET; a Schmitt trigger coupled between the digital upper supply voltage and the lower supply voltage, the Schmitt trigger having an input coupled to a gate sense node between the sense PFET and the current sink and an output coupled to enable the first current sense comparator when the second low side power FET is operating in a linear region; the first FET linear detection circuit, Including, the system.

8. 8. The system of claim 7, The first current source is a first digital-to-analog converter (DAC) coupled to provide a first reference voltage; a first operational amplifier coupled to receive the first reference voltage and to provide a first reference current; Including, the system.

9. 9. The system of claim 8, The system wherein the first reference current is a hysteretic reference current further including a valley current limit.

10. 8. The system of claim 7, a second H-bridge circuit, a third low side power FET; and a third high side power FET coupled in series with the third low side power FET between the motor supply voltage and the lower side supply voltage; a fourth low side power FET; and a fourth high side power FET coupled in series with the fourth low side power FET between the motor supply voltage and the lower side supply voltage; a second inductor including a high side terminal coupled to a third output node between the third high side power FET and the third low side power FET, and a low side terminal coupled to a fourth output node between the fourth high side power FET and the fourth low side power FET; the second H-bridge circuit comprising: A second current source; and a second current sense FET coupled between the second current source and the lower supply voltage, the second current sense FET providing a second reference current including a second peak current limit at a second sense node between the second current source and the second current sense FET; a second current sense comparator having a first input coupled to the second sense node, a second input coupled to the fourth output node, and an output coupled to the driver control circuit; a second FET linearity detection circuit coupled to receive a gate voltage of the fourth low side power FET, the second FET linearity detection circuit having an output coupled to enable the second current sense comparator when the fourth low side power FET is operating in the linear region; The system further comprises:

11. 1. A method of operating a stepper motor, comprising the steps of: Attaching a first output node in an H-bridge circuit to a high side terminal of an inductor, the first output node being between a first high side power FET coupled to a motor supply voltage and a first low side power FET coupled to a lower side supply voltage; attaching a second output node in the H-bridge circuit to a low side terminal of the inductor, the second output node being between a second high side power FET coupled to the motor supply voltage and a second low side power FET coupled to the lower side supply voltage; enabling a first current sense comparator coupled to track a gate voltage on the second low side power FET to determine when the second low side power FET is operating in a linear region when the H-bridge circuit is operating in a drive mode and to compare a current at the second output node to a peak current limit when the second low side power FET is operating in the linear region; tracking a gate voltage of a selected one of the first low side power FET and the second low side power FET to determine when the selected one of the first low side power FET and the second low side power FET is operating in a linear region when the H-bridge circuit is operating in a decay mode; A method comprising:

12. 12. The method of claim 11, the decay mode is a slow decay mode, and a selected one of the first low side power FET and the second low side power FET is the second low side power FET; The method further includes enabling the first current sense comparator coupled to compare a current at the second output node to a valley current limit.

13. 12. The method of claim 11, the decay mode is a fast decay mode, and a selected one of the first low side power FET and the second low side power FET is the first low side power FET; The method further includes enabling a second current sense comparator coupled to compare a current at the first output node in combination with a valley current limit to the lower supply voltage.

14. 14. The method of claim 13, The method, wherein the first current sensing comparator and the second current sensing comparator are a single comparator.

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