Highly linear phase interpolator

Abstract

A phase interpolator and method for performing phase interpolation that has high linearity over the entire range of operation is provided. The fractional frequency divider (FFD) includes a high linearity phase interpolator (PI) 107 including control logic for generating a phase value parameter indicative of a desired phase difference between an output signal and an input clock signal edge, a first capacitor C1 that is charged for a first time period with a current proportional to the phase value parameter from a first current source 401 to generate a first voltage on the capacitor that is proportional to the phase value parameter, and that is further charged for a second time period with a current having a constant value from a second current source 402 to form a voltage ramp offset by the first voltage, and a reference voltage V REF and PI generated by the charging capacitor C1 during the second time period. OUT and a comparator 110 that compares the voltage ramp of the input voltage to the output clock signal 120.

Description

[Technical field]

[0001] The present invention relates generally to phase interpolators, and more particularly to phase interpolators that have high linearity over their entire range of operation. [Background technology]

[0002] A phase interpolator (PI) can be used to generate a clock signal that is phase shifted from a reference clock signal by interpolating a specified amount of time from an edge of the reference clock signal.

[0003] For example, a phase interpolator can be used in the clock and data recovery (CDR) loop of a serializer / deserializer (SerDes) communication interface. A PI can be interposed between a phase-locked loop (PLL) and a data sampler to shift the recovered clock phase to the appropriate position in the data sampling window. A PI can receive two clocks of the same frequency, in-phase and quadrature (IQ), respectively, and generate a clock output whose phase is the weighted sum of the two input phases. An ideal PI would be capable of generating a large number of equally spaced phase steps for a full cycle from 0 to 360 degrees.

[0004] Typically, SerDes applications do not require a highly linear PI to operate properly. Summary of the Invention

[0005] In a described example of a high linearity phase interpolator, the control logic may generate a phase value parameter indicative of a desired phase difference between the output signal and the input clock edges. A first capacitor may be charged for a first period of time with a first current proportional to the phase value parameter to generate a first voltage on the first capacitor proportional to the phase value parameter. The first capacitor may further be charged for a second period of time with a second current having a constant value to form a voltage ramp offset by the first voltage. A reference voltage may be compared to the voltage ramp during the second period of time. The output signal may be asserted once when the voltage ramp equals the reference voltage. [Brief description of the drawings]

[0006] [Figure 1A] FIG. 2 is a block diagram illustrating the operation of an example fractional frequency divider. [Figure 1B] FIG. 2 is a timing diagram illustrating the operation of an example fractional frequency divider.

[0007] [Diagram 2] FIG. 1 is a block diagram of an example clock generator system including multiple fractional frequency dividers.

[0008] [Diagram 3] 1 is a schematic diagram of a conventional phase interpolator.

[0009] [Figure 4] FIG. 1 is a schematic diagram illustrating an embodiment of an improved phase interpolator. [Diagram 5] FIG. 1 is a timing diagram illustrating an embodiment of an improved phase interpolator. [Figure 6] 1 is a schematic illustrating an embodiment of an improved phase interpolator. [Figure 7] FIG. 1 is a timing diagram illustrating an embodiment of an improved phase interpolator.

[0010] [Figure 8] 11 is a graph illustrating further improvement in nonlinearity.

[0011] [Figure 9] FIG. 13 is a schematic diagram illustrating another embodiment of a phase interpolator.

[0012] [Figure 10] FIG. 10 is a timing diagram illustrating the operation of the PI of FIG.

[0013] [Figure 11] 10 is a graph illustrating the operation of the PI of FIG. 9.

[0014] [Figure 12] 4 is a flow chart illustrating the operation of the high linearity phase interpolator. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0015] In the drawings, like elements are designated with like reference numerals for consistency.

[0016] Exemplary embodiments may provide a high resolution, high linearity phase interpolator for applications requiring better linearity than conventional SerDes applications. For example, such applications may include high precision clock generators.

[0017] In an exemplary embodiment, the improved phase interpolator eliminates the need for quadrature input signals and in-phase feedback: the required input and control signals can be easily generated by digital logic.

[0018] In one embodiment, a phase interpolator having 11-bit resolution over a period of 200 ps (picoseconds) may be provided to produce a time resolution of approximately 97.6 fs (femtoseconds). For example, such resolution may be 40 times better than the integral nonlinearity (INL) of conventional phase interpolators used in SerDes applications.

[0019] 1A is a block diagram of an example fractional frequency divider (FFD) 100 including a high linearity phase interpolator 107. The FFD 100 may be operable to generate an output clock signal 120 having a frequency equal to a specified fraction of an input clock signal 102. The input clock signal 102 may be selected to have a value in the range of 10 MHz to 10 GHz in this example embodiment. In other embodiments, a different range of input clock frequencies may be supported. An output clock signal 120 may be generated with a frequency that may be selected from a range of approximately 100 Hz to 1 GHz in this example embodiment.

[0020] Digital control circuitry 104 may be hardwired or programmably configured to select a particular division ratio between output clock signal 120 and input clock signal 102. For example, control circuitry 104 may include registers that are loaded by software or firmware executing on a processor coupled to FFD 100.

[0021] FFD 100 operates by counting a specified number of clock periods of input clock 102 that is the approximate desired period of output clock signal 120, and then interpolating the amount of time between edges of clock signal 120 to generate the precise period length between edges of output clock signal 102. The operation of FFD 100 is briefly described herein, and a detailed description of the operation of FFDs such as FFD 100 is provided in U.S. patent application US 15 / 281,617, entitled "Fractional Frequency Clock Divider With Direct Division," filed September 30, 2016, by Hoshyar et al., which is incorporated herein by reference. [Patent Document 1] U.S. Patent Application US15 / 281,617

[0022] 1B is a timing diagram illustrating the operation of the FFD 100 for an example division ratio of 13.75. The frequency divider 103 is configured to count the number N of edges of the input clock signal 102 in response to a control parameter N 105 provided by the digital control logic 104 to generate the "Nth clock" signals VIP, V2P. In this embodiment, the frequency divider counts both rising and falling edges of the input clock signal 102. The phase interpolator 107 is configured to interpolate between two edges of the input clock 102 as specified by the phase parameter α. For example, if a division ratio of 13.75 is specified, the control logic 104 may instruct the counter 103 to count 13 edges (N=13) of the input clock 102 and may then instruct the PI 107 to interpolate 0.75 of the period of the input clock 102 (α=0.75) before asserting the intermediate clock signal CLKp 119. At the next output period, the control logic may then instruct counter 103 to count 13 input periods and may instruct PI 107 to then interpolate for half a period of the input clock 102. The intermediate clock signal 119 may then be divided in frequency by two at 111 to form an output clock signal 120 with a 50% duty cycle and a period of 13.75 periods of the input clock 102. This process is then repeated for each period of the output clock signal 120. Typically, a fractional frequency ratio will continually change the edge relationship between the output clock signal and the input clock signal, so each period may require a different amount of phase interpolation.

[0023] In this example, the parameter α is an 11-bit digital value (0 to 2047). In other examples, α may have a resolution greater than or less than 11 bits. Phase interpolator 107 generates a voltage PIout 109 that correlates to the amount of required phase shift indicated by parameter α. PIout 109 may be compared to a reference voltage Vref 108 by comparator 110. A transition on output clock signal 120 is generated by comparator 110 when PIout equals Vref, as described in more detail below.

[0024] FIG. 2 is a block diagram of an example clock generator system 200 including one or more fractional frequency dividers 100(1)-100(n). For example, the system 200 may be fabricated on a single integrated circuit (IC) using known or later developed semiconductor processing techniques. Also, for example, a phase-locked loop (PLL) circuit 210 may be used to generate a fixed frequency reference clock signal 202 under control of a crystal 214 controlled oscillator 212. In some examples, the crystal 214 may be located outside the IC 200. In other embodiments, other types of known or later developed clock generation circuits may be used, such as oscillators including, for example, MEMS resonators, multivibrators, ring oscillators, delay line oscillators, etc. In other examples, the reference clock 202 may be provided from an external source instead of from an on-chip source.

[0025] In this way, a single IC can provide multiple clock signals of different frequencies all synthesized from a single reference clock signal.

[0026] Referring again to FIG. 1, as described in more detail below, the phase interpolator 107 generates a phase shift in response to the parameter α over a range of values ​​in a highly linear manner. In this description, “nonlinearity” can be described in a manner similar to that commonly used for analog-to-digital converters (ADCs). To typically represent the nonlinearity of an ADC, manufacturers can draw a line, called a best-fit line, through the ADC transfer function. The maximum deviation from this line is called the “integral nonlinearity (INL)” which can be expressed as a percentage of full scale or in LSBs (least significant bits). INL is measured from the center of each step to a point on the line that would be the center of the step if the ADC were ideal. The term “differential” refers to the value that the ADC takes between two successive levels. In response to a charging input signal, the ADC sample signal and the output of the ADC are a stream of binary numbers. An ideal ADC can step up or down one least significant bit (LSB) without skipping any levels and without retaining the same fraction past two or three LSBs. Differential nonlinearity (DNL) is defined as the maximum deviation between two consecutive levels from one LSB over the entire transfer function.

[0027] FIG. 3 is a schematic of a conventional phase interpolator (PI) 300. The general operation of a phase interpolator is known, as described in “Phase Interpolator with Improved Linearity” by Soulioutis et al., May 2015. A conventional phase interpolator (PI) may require quadrature control signals I, Iz, Q, and Qz to control the operation of a summing circuit that provides charging current to a capacitor 304. Some implementations, such as this implementation, also require common-mode feedback (CMFB). However, some of the charging current to devices 302, 303 may be lost, thereby creating nonlinearity. A simple PI circuit such as PI 300 may have an INL error of 60 LSB or more, and when 1 LSB is 100 fs, the INL error may be greater than 6000 fs. [Non-Patent Document 1] “Phase Interpolator with Improved Linearity,”Soulioutis et al., May 2015

[0028] Referring again to FIG. 1, FIG. 4 is a schematic diagram illustrating in more detail an improved phase interpolator 400 that may be used for the PI 107. FIG. 5 is a timing diagram illustrating the operation of the PI 400. As mentioned above, the parameter α may be provided by control circuitry, such as the control circuitry 104 in FIG. 1. The parameter α may be loaded into a register in or coupled to the control logic 104, for example, by execution of an instruction, other control logic, initialization circuitry, or hardwired control logic. In this example, the parameter α is a fractional value having a value in the range of 0.0 to 1.0 that represents the percentage of the time period to shift the phase of the output clock signal 120 relative to the input clock signal 102.

[0029] During each interpolation cycle, a first current source 401 is configured to generate a current proportional to (1-α), and a second current source 402 is configured to generate a current proportional to (α). For example, current sources 401, 402 may be implemented using digital-to-analog converters (DACs). In this example, a 12-bit resolution DAC may be used, although other embodiments may use higher or lower resolution DACs. The current sources may be controlled by control circuitry, such as control circuitry 104, again referring to FIG. 1.

[0030] During a first time period 501, current from current source 401 is provided to ramp capacitor C1 through MOS device M1, while current from current source 402 is dissipated by resistor R1 through MOS device M4. The current from current source 401 charges ramp capacitor C1 and generates a voltage PIout that ramps up with a slope proportional to (1-α) during the first time period 501 to generate a PIout voltage at time 531 that is proportional to the requested phase shift.

[0031] During the second time period 502, a current proportional to (α) from the current source 402 is also provided to the ramp capacitor C1 via the MOS device M3 such that the total current provided to the capacitor C1 during the period 502 is proportional to (α)+(1-α)=1. Thus, a constant rate of charge is generated during the period 502, independent of the parameter α. Thus, during the time period 502, the voltage PIout ramps up with a slope independent of the parameter α and is offset by the PIout voltage at time 531. In this manner, a two-step voltage ramp signal is generated, with a first step generating a voltage magnitude proportional to the desired phase shift at time 531 and a second step such that an output signal having the desired phase shift is generated based on the voltage magnitude at time 531.

[0032] During the third time period 503, current from current source 401 may be diverted to resistor R1 by MOS device M2 such that ramp capacitor C1 charges at a rate proportional to (α) during time period 503. In this manner, ramp capacitor C1 is charged to the same fully charged voltage level shown at 510 during each iteration of the interpolation cycle, regardless of the value of parameter α.

[0033] A reference voltage Vref may be provided having a value of 1 / 2 the full charge voltage 510, which corresponds to the maximum voltage at 531. By comparing PIout to Vref during the second time period 502, a clock signal 120 may be generated having a phase shift relative to the input clock 102 that is highly linear with the parameter α. For example, when α=0, the clock signal 120 is asserted at time 520, which has a phase shift of 0 degrees relative to the input clock signal 102. When α=0.5, the clock signal 120 is asserted at time 521, which has a phase shift of 180 degrees relative to the input clock signal 102. Similarly, when α=1.0, the clock signal 120 is asserted at time 522, which has a phase shift of 360 degrees relative to the input clock signal 102. Thus, any phase shift amount between 0 and 360 degrees may be generated by a corresponding selection of the parameter α.

[0034] During time period 504, ramp capacitor C1 may be discharged by MOS device M7.

[0035] In this example, the reference voltage Vref is generated by a third current source 403 configured to charge a capacitor C2 for a time period 504. Capacitor C2 may be reset during the second half of the time period 503. In this way, the reference voltage Vref is generated under the same conditions as the rest of the PI circuit 400 such that mismatches caused by process variations are eliminated.

[0036] Referring again to FIG. 1, FIG. 6 is a schematic diagram illustrating another implementation of an improved phase interpolator 600 that may be used as the PI 107. FIG. 7 is a timing diagram illustrating the operation of the PI 600. The PI 600 may be implemented with a set of switch devices 630-639 controlled as shown in FIG. 7 by timing signals S1-S5. The operation of the PI 600 is similar to that of the PI 400 as described with respect to FIGS. 4 and 5. The switches 630-639 may be implemented using known or later developed devices, for example, bipolar semiconductor devices, field effect devices, etc.

[0037] During each interpolation cycle, a first current source 601 is configured to generate a current proportional to (1-α) and a second current source 602 is configured to generate a current proportional to (α). During a first time period 701, current from current source 601 is provided to ramp capacitor C2 via switch device 631, while current from current source 602 is dissipated by resistor R2 via switch devices 637 and 638. The current from current source 601 generates a voltage PIout that ramps up with a slope proportional to (1-α) during the first time period 701 to charge ramp capacitor C2 and generate a PIout voltage at the end of the period 701 that is proportional to the requested phase shift.

[0038] During the second time period 702, a current proportional to (α) from the current source 602 is also provided to the ramp capacitor C2 via the switch device 636 such that the total current provided to the capacitor C2 during the period 702 is proportional to (α)+(1-α)=1. Thus, during the period 702a, a constant rate of charge is produced regardless of the parameter α. Thus, during the time period 702a, the voltage PIout ramps up with a slope independent of the parameter α.

[0039] During the third time period 703, current from current source 601 may be diverted to resistor R1 by switch devices 632 and 633 such that capacitor C2 charges at a rate proportional to (α) during time period 703. In this manner, ramp capacitor C2 is charged to the same fully charged voltage level, as shown at 710, during each iteration of the interpolation cycle, regardless of the value of parameter α.

[0040] A reference voltage Vref may be provided having a value of 1 / 2 the full charge voltage 710. By comparing PIout to Vref during the second time period 702, a clock signal 620 may be generated having a phase shift relative to the input clock 712 that is fairly linear with respect to the parameter α. For example, when α=0, the clock signal 620 is asserted at time 720, which has a phase shift of 0 degrees relative to the input clock signal 712. When α=0.5, the clock signal 620 is asserted at time 721, which has a phase shift of 180 degrees relative to the input clock signal 712. Similarly, when α=1.0, the clock signal 620 is asserted at time 722, which has a phase shift of 360 degrees relative to the input clock signal 712. Thus, any phase shift amount between 0 and 360 degrees may be generated by a corresponding selection of the parameter α.

[0041] During time period 704 , capacitor C 2 is discharged by switch device 639 .

[0042] In this example, the reference voltage Vref is generated by current from both current sources 601 and 602 configured to charge capacitor C1 for time period 705 via switches 630 and 635. Capacitor C1 is reset for the second half of time period 704 by switch 634 in this example. In another example, capacitor C1 may be reset for the second half of time period 703 and charged for time period 704. In this manner, the reference voltage Vref is generated under the same conditions as the rest of the PI circuit 600 such that mismatches caused by process variations are eliminated.

[0043] FIG. 8 is a graph illustrating possible nonlinearities in the PI circuit 107 of FIG. 4 and the PI circuit 600 of FIG. 6. Referring again to the timing diagram of FIG. 5, when the parameter α has a value near its minimum or maximum, respectively, glitch interference caused by signal switching at timing points 531 and 532 can cause nonlinear errors. Plot line 801 represents an ideal linear response curve between timing points 531 and 532. Plot line 802 represents a possible response curve due to a signal glitch around timing points 531 and 532. An INL magnitude shown at 803 can result. The illustrative embodiment allows the phase interpolator to be operated in a more linear region, such as the region between timing points 831 and 832. In this case, the ideal linear response 804 in this region results in a much lower INL magnitude, as shown at 805.

[0044] 9 is a schematic diagram illustrating another embodiment 900 of a phase interpolator that may be used as the PI 107, referring again to FIG. 1. FIG. 10 is a timing diagram illustrating the operation of the PI 900. Referring again to FIG. 4, the PI 900 is similar to the PI 400 in that it has a first current source 901 configured to generate a current proportional to (1-α) and a second current source 902 configured to generate a current proportional to (α). However, the current sources 901 and 902 each use a reference current having a value of 0.5 I(0). To compensate for the lower current value, the first time period 1001 and the second time period 1002 span two periods of the input clock 1012.

[0045] A second set of current sources 904, 905 is included to provide a "pedestal current" that shifts the PIout voltage ramp generated by the charging capacitor C1 by an additional fixed amount. In this example, current sources 904, 905 provide a constant current of 0.25 I(0).

[0046] During a first time period 1001, current from current sources 901 and 904 is provided to ramp capacitor C1 through MOS device M1, while current from current sources 902 and 905 is dissipated by resistor R1 through MOS device M4. The current from current sources 901, 904 charges ramp capacitor C1 and generates a voltage PIout that ramps up with a slope proportional to (1-α) during the first time period 1001, which is two periods of the input clock 1012, to generate a PIout voltage at time 1031 that is proportional to the requested phase shift.

[0047] During a second time period 1002, a current proportional to (α) from current source 902 and a fixed current from current source 905 are also provided to ramp capacitor C1 through MOS device M3 such that the total current provided to ramp capacitor C1 during period 1002 is proportional to (α)+(1-α)=1. Thus, a constant rate of charge is produced during period 1002 that is independent of parameter α. Thus, voltage PIout ramps up during time period 1002 with a slope that is independent of parameter α.

[0048] A reference voltage Vref may be provided having a value of approximately 0.5 of the full charge voltage 1010. By comparing PIout to Vref during a sampling period 1030 that is only the central portion of the second time period 1002, a clock signal 920 may be generated having a phase shift relative to the falling edge of the input clock 1012 that is fairly linear with respect to the parameter α. For example, when α=0, the clock signal 920 is asserted at time 1020, which has a phase shift of 0 degrees relative to the falling edge of the input clock signal 1012. When α=0.5, the clock signal 1020 is asserted at time 1021, which has a phase shift of 180 degrees relative to the falling edge of the input clock signal 1012. Similarly, when α=1.0, the clock signal 920 is asserted at time 1022, which has a phase shift of 360 degrees relative to the falling edge of the input clock signal 102. Thus, any phase shift amount between 0 and 360 degrees may be generated by a corresponding selection of the parameter α. The reduced sampling period 1030 also avoids glitching that can occur due to switching of the control signal.

[0049] During time period 1003, capacitor C1 may be discharged by MOS device M7.

[0050] In this example, the reference voltage Vref is generated by a third current source 903 configured to charge a capacitor C2 for a time period 1004. The capacitor C2 may be reset by a MOS device M8 for a time period 1003. In this manner, the reference voltage Vref is generated under the same conditions as the rest of the PI circuit 900 such that mismatches caused by process variations are eliminated.

[0051] 11 is a graph illustrating simulated operation of the PI 900, where 1 LSB corresponds to 100 fs. In this example, the PI 900 exhibits a maximum INL of only 120 fs, which corresponds to 1.2 LSB, as illustrated in FIG 11. This compares to a maximum INL error of 6000 fs for the conventional device illustrated in FIG 3.

[0052] Figure 12 is a flow chart illustrating the operation of a high linearity phase interpolator, as described above in relation to Figures 3-10. As described in relation to Figures 1 and 2, a high linearity phase interpolator may be used to generate an accurate fractional frequency clock signal from a fixed reference frequency.

[0053] A phase value parameter indicative of a desired phase difference between the output signal and an input clock signal edge may be generated (1202) by control logic coupled to the phase interpolator.

[0054] A first capacitor may be charged with a first current proportional to the phase value parameter for a first time period to generate a first voltage on the capacitor proportional to the phase value parameter (1204). As described in more detail above, a current source controlled by a DAC may be used to generate the first current. The phase value parameter may be used to control a DAC. For example, the phase value may be a 12-bit digital value provided to a 12-bit DAC.

[0055] The first capacitor may be further charged with a second current having a constant value for a second period of time to form a voltage ramp offset with the first voltage 1206. As mentioned above, the second current source may also be implemented using a DAC for control.

[0056] During a second period of time, the reference voltage may be compared to the voltage ramp 1208. As discussed above, a comparator such as comparator 110 in FIG.

[0057] The output signal may then be asserted 1210 once the voltage ramp is equal to the reference voltage to generate an output signal that is offset from the input clock by a phase amount specified by the phase value parameter.

[0058] A reference voltage may be generated 1212 by a current source configured to charge a second capacitor for another period of time, as described in more detail above. The second capacitor may be reset at the end of each interpolation cycle. In this manner, the reference voltage may be generated under the same conditions as the rest of the PI circuit, such that process variations caused by mismatches are eliminated.

[0059] Other Examples Referring again to FIG. 4, in another example embodiment, current source 401 may have a value of (α)I0 and current source 402 may have a value of (l-α)I0.

[0060] In another embodiment, current source 401 may have a current value proportional to parameter α and current source 402 may have a constant current value of I1. In this case, current from current source 401 may be directed to resistor R1 during time period 502 such that a ramp voltage of fixed slope is generated by current source 402 alone during sample period 502.

[0061] In another embodiment, various combinations of current sources can be configured to generate a voltage ramp proportional to the amount of phase shift required during a first time period, and an additional voltage ramp having a fixed slope during the sampling time period.

[0062] In various embodiments, the lump capacitor may be implemented as a discrete capacitor, a MOS device, multiple devices, and the like.

[0063] In another embodiment, the two-step ramp signal for determining the phase shift can be generated using another type of device characteristic, such as generating a current having a two-step ramp using an inductive device.

[0064] Although a fractional frequency clock generator system is described in this application, other systems may embody the high linearity phase interpolator disclosed herein for functions such as clock recovery for SerDes interfaces, frequency control of PLLs, and the like.

[0065] In this description, the term "couple" and its derivatives refer to an indirect, direct, optical, and / or wireless electrical connection. Thus, when a first device couples to a second device, such connection may be via a direct electrical connection, via an indirect electrical connection via other devices or connections, via an optical electrical connection, and / or via a wireless electrical connection.

[0066] Although method steps may be illustrated and / or described herein as sequential, one or more of the illustrated and / or described steps may be omitted, repeated, performed simultaneously, and / or performed in a different order.

[0067] Modifications may be made to the exemplary embodiments described, and other embodiments are possible, within the scope of the invention.

Claims

1. 1. An apparatus comprising: a first current source having a first current output, the first current source being configured to provide a first current at the first current output; a second current source having a second current output, the second current source configured to provide a second current at the second current output; a third current source having a third current output, the third current source being configured to provide a third current at the third current output; a first capacitor having a first capacitor terminal coupled to the power terminal and a second capacitor terminal; a second capacitor having a third capacitor terminal and a fourth capacitor terminal coupled to the power terminal; a first switch having a first switch control input coupled between the first current output and the second capacitor terminal; a second switch having a second switch control input coupled between the second current output and the second capacitor terminal; and a third switch having a third switch control input coupled between the third current output and the fourth capacitor terminal; 1. A clock divider circuit having a clock input, a first switch control output coupled to the first switch control input, a second switch control output coupled to the second switch control input, and a third switch control output coupled to the third switch control input, receiving an input clock signal at said clock input; determining a first period, a second period and a third period in response to a state of the input clock signal; enabling the first switch and disabling the second switch during the first period; enabling the first and second switches during the second time period; disabling the first switch and enabling the second switch during the third period; the clock divider circuit configured as follows: a clock generation circuit having a ramp input coupled to the second capacitor terminal, a reference input coupled to the fourth capacitor terminal, and a clock output, the clock generation circuit including a comparator having a first comparator input coupled to the ramp input, a second comparator input coupled to the reference input, and a comparator output coupled to the clock output, the clock generation circuit configured to provide an output clock signal having a phase shift from the input clock signal, an amount of the phase shift based on the first current and the second current; 13. An apparatus comprising:

2. 2. The apparatus of claim 1, the amount of phase shift, the first current, and the second current are adjustable; The amount of phase shift ranges within a cycle period of the input clock signal.

3. An apparatus comprising: a first current source having a first current output, the first current source being configured to provide a first current at the first current output; a second current source having a second current output, the second current source configured to provide a second current at the second current output; a third current source having a third current output, the third current source being configured to provide a third current at the third current output; a first capacitor having a first capacitor terminal coupled to the power terminal and a second capacitor terminal; a second capacitor having a third capacitor terminal and a fourth capacitor terminal coupled to the power terminal; a first switch having a first switch control input coupled between the first current output and the second capacitor terminal; a second switch having a second switch control input coupled between the second current output and the second capacitor terminal; and a third switch having a third switch control input coupled between the third current output and the fourth capacitor terminal; 1. A clock divider circuit having a clock input, a first switch control output coupled to the first switch control input, a second switch control output coupled to the second switch control input, and a third switch control output coupled to the third switch control input, receiving an input clock signal at said clock input; dividing the input clock signal to generate first and second control signals having respective cycle periods spanning a plurality of cycle periods of the input clock signal; providing the first control signal and the second control signal to the first switch control output and the second switch control output, respectively, such that the first switch is enabled and the second switch is disabled during a first time period, the first and second switches are enabled during a second time period, and the first switch is disabled and the second switch is enabled during a third time period; the clock divider circuit configured as follows: a clock generation circuit having a ramp input coupled to the second capacitor terminal, a reference input coupled to the fourth capacitor terminal, and a clock output, the clock generation circuit including a comparator having a first comparator input coupled to the ramp input, a second comparator input coupled to the reference input, and a comparator output coupled to the clock output, the clock generation circuit configured to provide an output clock signal having a phase shift from the input clock signal, an amount of the phase shift based on the first current and the second current; 13. An apparatus comprising:

4. 4. The apparatus of claim 3, the amount of phase shift, the first current, and the second current are adjustable; The amount of phase shift ranges within a cycle period of the input clock signal.

5. 4. The apparatus of claim 3, the first period is a first cycle period of the input clock signal, the second period is a second cycle period of the input clock signal, and the third period is a third cycle period of the input clock signal.

6. 4. The apparatus of claim 3, further comprising a digital control circuit having a first current control output and a second current control output, the digital control circuit configured to provide a first current control signal to the first current control output and a second current control signal to the second current control output; the first current source further having a first current control input coupled to the first current control output, the first current source configured to provide a first current to the first current output in response to the first current control signal; the second current source further having a second current control input coupled to the second current control output, the second current source configured to provide a second current to the second current output in response to the second current control signal.

7. 7. The apparatus of claim 6, the second current control signal represents a first ratio between an amount of the phase shift and a cycle period of the input clock signal; the first current control signal represents a second ratio, the sum of the first and second ratios being equal to one.

8. 7. The apparatus of claim 6, a fourth current source having a fourth current output, the fourth current source being configured to provide a fourth current at the fourth current output; a fifth current source having a fifth current output, the fifth current source being configured to provide a fifth current at the fifth current output, the fifth current being equal to the fourth current; Further comprising: the first switch is further coupled between the fourth current output and the second capacitor terminal; the second switch is further coupled between the fifth current output and the second capacitor terminal.

9. 9. The apparatus of claim 8, the second current control signal represents a first ratio between an amount of the phase shift and a cycle period of the input clock signal; The apparatus, wherein the first current control signal represents a second ratio, the sum of the first ratio and the second ratio being equal to 1 / 2.

10. 9. The apparatus of claim 8, the clock divider circuit is further configured to enable the third switch during a period of time after the third period of time.

11. 1. An apparatus comprising: a first current source having a first current output, the first current source being configured to provide a first current at the first current output; a second current source having a second current output, the second current source configured to provide a second current at the second current output; a first capacitor having a first capacitor terminal coupled to the power terminal and a second capacitor terminal; a first switch having a first switch control input coupled between the first current output and the second capacitor terminal; a second switch having a second switch control input coupled between the second current output and the second capacitor terminal; and 1. A clock divider circuit having a clock input, a first switch control output coupled to the first switch control input, and a second switch control output coupled to the second switch control input, receiving an input clock signal at said clock input; dividing the input clock signal to generate first and second control signals having respective cycle periods spanning a plurality of cycle periods of the input clock signal; providing the first control signal and the second control signal to the first switch control output and the second switch control output, respectively, such that the first switch is enabled and the second switch is disabled during a first time period, the first and second switches are enabled during a second time period, and the first switch is disabled and the second switch is enabled during a third time period; the clock divider circuit configured as follows: a clock generation circuit having a ramp input coupled to the second capacitor terminal, a reference input, and a clock output, the clock generation circuit including a comparator having a first comparator input coupled to the ramp input, a second comparator input coupled to the reference input, and a comparator output coupled to the clock output, the clock generation circuit configured to provide an output clock signal having a phase shift from the input clock signal, an amount of the phase shift based on the first current and the second current; a reference generator having a reference output coupled to the reference input, providing a first reference voltage to the reference output during the first and second time periods; providing a second reference voltage to the reference output after the second period of time; the reference generator configured to Including, The clock generation circuit, generating a first edge of the output clock signal in response to a first comparison between a first voltage at the second capacitor terminal and the first reference voltage; generating a second edge of the output clock signal in response to a second comparison between the first voltage at the second capacitor terminal and the second reference voltage. The apparatus, further configured as follows.

12. 12. The apparatus of claim 11, a third switch having a third switch control input coupled between the second capacitor terminal and the power terminal; the clock divider circuit further comprising a third switch control output coupled to the third switch control input; the clock divider circuit is further configured to disable the third switch during the first, second, and third time periods, and enable the third switch after the third time period.

13. 1. An apparatus comprising: a first current source having a first current output, the first current source being configured to provide a first current at the first current output; a second current source having a second current output, the second current source configured to provide a second current at the second current output; a first capacitor having a first capacitor terminal coupled to the power terminal and a second capacitor terminal; a first switch having a first switch control input coupled between the first current output and the second capacitor terminal; a second switch having a second switch control input coupled between the second current output and the second capacitor terminal; and a third switch having a third switch control input coupled between the first current output and the power terminal; and a fourth switch having a fourth switch control input coupled between the second current output and the power terminal; and 1. A clock divider circuit having a clock input, a first switch control output coupled to the first switch control input, and a second switch control output coupled to the second switch control input, receiving an input clock signal at said clock input; dividing the input clock signal to generate first and second control signals having respective cycle periods spanning a plurality of cycle periods of the input clock signal; providing the first control signal and the second control signal to the first switch control output and the second switch control output, respectively, such that the first switch is enabled and the second switch is disabled during a first time period, the first and second switches are enabled during a second time period, and the first switch is disabled and the second switch is enabled during a third time period; the clock divider circuit configured as follows: a clock generation circuit having a ramp input coupled to the second capacitor terminal, a reference input, and a clock output, the clock generation circuit including a comparator having a first comparator input coupled to the ramp input, a second comparator input coupled to the reference input, and a comparator output coupled to the clock output, the clock generation circuit configured to provide an output clock signal having a phase shift from the input clock signal, an amount of the phase shift based on the first current and the second current; 13. An apparatus comprising:

14. 14. The apparatus of claim 13, a third current source having a third current output; a second capacitor having a third capacitor terminal coupled to the power terminal and a fourth capacitor terminal coupled to the reference input; a fifth switch having a fifth switch control input coupled between the third current output and the power terminal; and a sixth switch having a sixth switch control input coupled between the third current output and the fourth capacitor terminal; a seventh switch having a seventh switch control input coupled between the third and fourth capacitor terminals; and The apparatus further comprises:

15. 15. The apparatus of claim 14, the clock divider circuit further comprising third, fourth, fifth, sixth and seventh switch control outputs coupled to the third, fourth, fifth, sixth and seventh switch control inputs of the third, fourth, fifth, sixth and seventh switches, respectively; the clock divider circuit comprises: generating third, fourth, fifth, sixth and seventh control signals having respective cycle periods spanning a plurality of cycle periods of the input clock signal; during the first period, the third switch is disabled, the fourth switch is enabled, the fifth switch is enabled, and the sixth and seventh switches are disabled; during the second period, the third and fourth switches are disabled, the fifth switch is enabled, and the sixth and seventh switches are disabled; during the third period, the third switch is enabled, the fourth switch is disabled, the fifth switch is enabled, the sixth switch is disabled, and the seventh switch is enabled; after the third period, enabling the third and fourth switches, disabling the fifth switch, enabling the sixth switch, and disabling the seventh switch; providing the third, fourth, fifth, sixth and seventh control signals to the third, fourth, fifth, sixth and seventh switch control outputs, respectively, such that The apparatus, further configured as follows.

16. 1. An apparatus comprising: a first current source having a first current output, the first current source being configured to provide a first current at the first current output; a second current source having a second current output, the second current source configured to provide a second current at the second current output; a first capacitor having a first capacitor terminal coupled to the power terminal and a second capacitor terminal; a first switch having a first switch control input coupled between the first current output and the second capacitor terminal; a second switch having a second switch control input coupled between the second current output and the second capacitor terminal; and third and fourth switches coupled in series between the second current output and the power terminal; 1. A clock divider circuit having a clock input, a first switch control output coupled to the first switch control input, and a second switch control output coupled to the second switch control input, receiving an input clock signal at said clock input; dividing the input clock signal to generate first and second control signals having respective cycle periods spanning a plurality of cycle periods of the input clock signal; providing the first control signal and the second control signal to the first switch control output and the second switch control output, respectively, such that the first switch is enabled and the second switch is disabled during a first time period, the first and second switches are enabled during a second time period, and the first switch is disabled and the second switch is enabled during a third time period; the clock divider circuit configured as follows: a clock generation circuit having a ramp input coupled to the second capacitor terminal, a reference input, and a clock output, the clock generation circuit including a comparator having a first comparator input coupled to the ramp input, a second comparator input coupled to the reference input, and a comparator output coupled to the clock output, the clock generation circuit configured to provide an output clock signal having a phase shift from the input clock signal, an amount of the phase shift based on the first current and the second current; 13. An apparatus comprising:

17. 17. The apparatus of claim 16, a second capacitor having a third capacitor terminal coupled to the power terminal and a fourth capacitor terminal coupled to the reference input; a fifth switch coupled between the second current output and the fourth capacitor terminal; a sixth switch coupled between the first current output and the fourth capacitor terminal; seventh and eighth switches coupled in series between the first current output and the power terminal; The apparatus further comprises:

18. 18. The apparatus of claim 17, the third, fourth, fifth, sixth, seventh and eighth switches having third, fourth, fifth, sixth, seventh and eighth switch control inputs, respectively; the clock divider circuit comprises: third, fourth, fifth, sixth, seventh and eighth switch control outputs coupled to the third, fourth, fifth, sixth, seventh and eighth switch control inputs, respectively; generating third, fourth, fifth, sixth, seventh and eighth control signals having respective cycle periods spanning a plurality of cycle periods of the input clock signal by dividing the input clock signal; disabling the first, second, fifth, and sixth switches and enabling the third, fourth, seventh, and eighth switches during a fourth period before the first period; during the first period, enabling the first switch, disabling the second switch, enabling at least one of the third and fourth switches, disabling the fifth and sixth switches, and disabling at least one of the seventh and eighth switches; during the second period, enabling the first and second switches, disabling at least one of the third and fourth switches, disabling the fifth and sixth switches, and disabling at least one of the seventh and eighth switches; during the third period, disabling the first switch, enabling the second switch, disabling at least one of the third and fourth switches, disabling the fifth and sixth switches, and enabling the seventh and eighth switches; providing the third, fourth, fifth, sixth, seventh and eighth control signals to the third, fourth, fifth, sixth, seventh and eighth switch control outputs, respectively, such that The apparatus, further configured as follows.

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