Semiconductor chip manufacturing method

Abstract

To suppress a crack while an identification mark is formed.SOLUTION: A method for manufacturing a semiconductor chip includes: preparing a GaN wafer 1; forming an epitaxial film 3 on one surface 1a of the GaN wafer 1 to configure a processed wafer having a plurality of chip formation regions; forming a one surface-side element component of a semiconductor element in each of the plurality of chip formation regions; forming a wafer transformation layer along a planar direction of the processed wafer by irradiating an inside of the processed wafer with a laser beam L from the other surface side of the processed wafer; dividing the processed wafer into a chip formation wafer and a recycle wafer by dividing the processed wafer at the wafer transformation layer as a boundary; extracting a semiconductor chip from the chip formation wafer; and after the preparing of the GaN wafer 1 and before the dividing of the processed wafer, irradiating an inside of the GaN wafer 1 or the processed wafer with the laser beam L to form, at the inside, a mark WM by deposition of gallium.SELECTED DRAWING: Figure 1B

Description

[Technical field]

[0001] The present invention is a semiconductor device made of gallium nitride (hereinafter also referred to as GaN). Half The present invention relates to a method for manufacturing a conductor chip. [Background technology]

[0002] It has been known that semiconductor chips are made using GaN wafers. It has been proposed to form an identification mark on the GaN wafer (see, for example, Patent Document 1). Specifically, the mark is formed by a process of forming a recess on the surface of the GaN wafer using a laser and a process of polishing the surface so that the recess remains. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2015-119087 A Summary of the Invention [Problem to be solved by the invention]

[0004] However, GaN wafers are a material that is very susceptible to cracking, so there is a concern that forming a depression in a GaN wafer may cause the wafer to crack from the depression.

[0005] In view of the above, the present invention provides a method for forming an identification mark while suppressing cracking. Half An object of the present invention is to provide a method for manufacturing a conductor chip. [Means for solving the problem]

[0006] Claim 1 for achieving the above object provides a method for manufacturing a semiconductor chip on which a semiconductor element is formed, comprising the steps of: preparing a gallium nitride wafer (1) made of gallium nitride and having one surface (1a) and another surface (1b); forming an epitaxial film (3) on one surface of the gallium nitride wafer, thereby forming a processed wafer (10) having a surface on the epitaxial film side as one surface (10a) and a surface on the gallium nitride wafer side as the other surface (10b), and having a plurality of chip formation regions (RA) on one surface side; forming one-surface-side element constituent parts (11) of semiconductor elements in the plurality of chip formation regions; By irradiating the portion with laser light (L), a wafer altered layer (15) in which nitrogen is separated from gallium is formed along the surface direction of the processed wafer, the processed wafer is divided at the wafer altered layer as a boundary, and the processed wafer is divided into a chip configuration wafer (30) on one side of the processed wafer and a recycled wafer (40) on the other side of the processed wafer, and a semiconductor chip (100) is taken out from the chip configuration wafer. After preparing the gallium nitride wafer and before dividing it, marks (WM, TM) in which gallium is precipitated are formed inside by irradiating the inside of the GaN wafer or the processed wafer with laser light (L). The mark forming step is performed by forming a wafer mark (WM) as a mark after preparing a gallium nitride wafer and before forming one-side element components, and the mark forming step is performed by forming a wafer mark in a portion to be the recycled wafer, and the formation of the wafer alteration layer and the formation of the wafer mark are performed by irradiating laser light of the same wavelength.

[0007] According to this, a mark is formed inside the processed wafer by precipitating gallium, and no recess is formed, so that it is possible to prevent the processed wafer from cracking starting from the mark.

[0012] The reference symbols in parentheses attached to each component indicate an example of the correspondence between the component and specific components described in the embodiments described below. [Brief description of the drawings]

[0013] [Figure 1A] 2A to 2C are cross-sectional views illustrating a manufacturing process of the semiconductor chip in the first embodiment. [Figure 1B] 1B is a cross-sectional view showing a manufacturing process of the semiconductor chip subsequent to FIG. 1A. [Figure 1C] 1C is a cross-sectional view showing a manufacturing process of the semiconductor chip subsequent to FIG. 1B. [Figure 1D] 1D is a cross-sectional view showing a manufacturing process of the semiconductor chip subsequent to FIG. 1C. [Figure 1E] 1D; FIG. 1E is a cross-sectional view showing a manufacturing process of the semiconductor chip subsequent to FIG. [Figure 1F] 1C is a cross-sectional view showing a manufacturing process of the semiconductor chip subsequent to FIG. 1E. [Figure 1G] 1C is a cross-sectional view showing a manufacturing process of the semiconductor chip subsequent to FIG. 1F. [Figure 1H] 1C is a cross-sectional view showing a manufacturing process of the semiconductor chip subsequent to FIG. 1G. [Figure 1I] 1C is a cross-sectional view showing a manufacturing process of the semiconductor chip subsequent to FIG. 1H. [Figure 1J] 1I is a cross-sectional view showing a manufacturing process of the semiconductor chip following FIG. 1I. [Figure 1K] 1C is a cross-sectional view showing a manufacturing process of the semiconductor chip subsequent to FIG. 1J. [Figure 1L] 1K is a cross-sectional view showing a manufacturing process of the semiconductor chip subsequent to FIG. [Figure 2A] 13 is a schematic diagram showing a case where a deteriorated layer for a wafer is formed without forming a deteriorated layer for a chip. FIG. [Figure 2B] 13 is a schematic diagram showing a case where a deteriorated layer for a wafer is formed after a deteriorated layer for a chip is formed. FIG. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0014] Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following embodiments, parts that are the same or equivalent to each other will be denoted by the same reference numerals.

[0015] (First embodiment) The first embodiment will be described with reference to the drawings. In the following, a method for manufacturing a semiconductor chip 100 in which semiconductor elements are formed on a chip substrate 110 including GaN will be described.

[0016] First, as shown in FIG. 1A, a GaN wafer 1 having one surface 1a and another surface 1b and in the form of a bulk wafer is prepared. For example, the GaN wafer 1 is doped with silicon, oxygen, germanium, etc., and has an impurity concentration of 5×10 17 ~5×10 19 cm -3 The GaN wafer 1 is prepared with a thickness of about 400 μm. The GaN wafer 1 of this embodiment has one surface 1a as a Ga surface and the other surface 1b as an N surface. After the manufacturing process of the semiconductor chip 100 described below is performed, the GaN wafer 1 is prepared by reusing a recycled wafer 40 shown in FIG. 1L, which will be described later.

[0017] Although not shown, the other surface 1b of the GaN wafer 1 is ground, polished, etc., as necessary, so that the surface roughness of the other surface 1b is 10 nm or less. This prevents the laser light L from being diffusely reflected by the other surface 1b of the GaN wafer 1 when the laser light L is irradiated from the other surface 1b of the GaN wafer 1, as described later.

[0018] 1B, laser light L is irradiated from the other surface 10b of the GaN wafer 1, and a wafer mark WM such as a lot number for identifying the wafer is formed inside the GaN wafer 1. Specifically, a laser device is prepared that has a laser light source that oscillates the laser light L, a dichroic mirror arranged to change the direction of the optical axis (i.e., optical path) of the laser light, a focusing lens (i.e., focusing optical system) for focusing the laser light, a displaceable stage, and the like. When forming the wafer mark WM, the GaN wafer 1 is placed on the stage, and the position of the stage, etc. is adjusted so that the focusing point of the laser light L is a predetermined position inside the GaN wafer 1.

[0019] As a result, gallium and nitrogen are decomposed by thermal energy, and nitrogen evaporates as a gas while gallium is precipitated to form a wafer mark WM on the GaN wafer 1. In this embodiment, the wafer mark WM is formed at a position adjusted so that the wafer mark WM remains on the recycled wafer 40 side when the processed wafer 10 described later is separated and divided into the chip configuration wafer 30 and the recycled wafer 40.

[0020] The shape of the wafer mark WM is a variety of identifiable patterns such as a line, a polygon, or a number. Although not particularly limited, in this embodiment, when forming the wafer mark WM, a solid-state laser light, a green laser with a wavelength of 532 nm, is used as the laser light L. The laser light L is irradiated with a processing point output of 2 μJ, a pulse width of 500 ps, ​​and a processing speed of 500 mm / s. However, these conditions are only an example, and the inventors have confirmed that the wafer mark WM is appropriately formed even when the processing point output of the laser light L is lower or the pulse width is shorter. The inventors have also confirmed that the wafer mark WM is appropriately formed even when the processing point output of the laser light L is higher or the pulse width is longer.

[0021] After that, although not shown, a heat treatment is performed to promote the precipitation of gallium and improve the visibility of the wafer mark WM. Note that, since the heat treatment here is performed on the GaN wafer 1 on which no semiconductor elements are formed, the temperature is set to be equal to or higher than the melting point of Ga (i.e., 29.76°C) and equal to or lower than 1000°C.

[0022] 1C, an epitaxial film 3 made of GaN and having a thickness of about 10 to 60 μm is formed on one surface 1a of the GaN wafer 1 to prepare a processed wafer 10 having a plurality of chip formation regions RA. At this time, in this embodiment, a wafer mark WM is formed inside the GaN wafer 1. Therefore, the processed wafer 10 is configured with the wafer mark WM formed therein.

[0023] In this embodiment, the epitaxial film 3 is + A type epitaxial layer 3a and an n - The n-type epitaxial layer 3b is formed in this order from the GaN wafer 1 side. For example, + The epitaxial layer 3a is doped with silicon, oxygen, germanium, etc., and has an impurity concentration of 5×10 17 ~1×10 18 cm -3 It is said to be about that level. - The epitaxial layer 3b is doped with silicon or the like and has an impurity concentration of 1×10 17 ~4×10 17 cm -3 It is said to be about that level.

[0024] In addition, n - The epitaxial layer 3b is a portion on which the one-side element components 11 such as the diffusion layer 12 described later are formed, and has a thickness of, for example, about 8 to 10 μm. + The n-type epitaxial layer 3a is a portion for ensuring the thickness of the semiconductor chip 100 described later, and has a thickness of, for example, about 40 to 50 μm. + Type epitaxial layer 3a and n - The thickness of the n-type epitaxial layer 3b may be arbitrary, but in this example, the thickness of the n-type epitaxial layer 3b is set to ensure the thickness of the semiconductor chip 100. + The epitaxial layer 3a is - The epitaxial layer 3b is thicker than the epitaxial layer 3b. In the following, the surface of the processed wafer 10 facing the epitaxial film 3 is referred to as one surface 10a of the processed wafer 10, and the surface of the processed wafer 10 facing the GaN wafer 1 is referred to as the other surface 10b of the processed wafer 10. Each chip formation region RA is formed on the one surface 10a side of the processed wafer 10.

[0025] 1D, a general semiconductor manufacturing process is performed to form one-surface element components 11 of the semiconductor element, such as diffusion layer 12, gate electrode 13, surface electrodes (not shown), wiring patterns, and passivation films, in each chip formation region RA. Note that the semiconductor elements used here may have a variety of configurations, such as power devices such as high electron mobility transistors (HEMTs) and optical semiconductor elements such as light-emitting diodes. Thereafter, a surface protection film made of resist or the like is formed on one surface 10a of the processed wafer 10 as necessary.

[0026] Next, as shown in FIG. 1E, a holding member 20 is placed on one surface 10a of the processed wafer 10. For example, a dicing tape having a base material 21 and an adhesive 22 is used as the holding member 20. The base material 21 is made of a material that is not easily warped during the manufacturing process, such as glass, a silicon substrate, or ceramics. The adhesive 22 is made of a material that can change its adhesive strength, such as a material whose adhesive strength changes depending on temperature or light. In this case, the adhesive 22 is made of, for example, an ultraviolet curing resin, wax, or double-sided tape. However, the adhesive 22 is made of a material that maintains its adhesive strength even when forming the other surface side element component part 60 of FIG. 1J, which will be described later.

[0027] Next, as shown in Fig. 1F, the other surface 10b of the processed wafer 10 is irradiated with laser light L to form a chip deterioration layer 14 on the outer edge including the boundary of each chip formation region RA. Specifically, a laser device similar to that used in the process of Fig. 1B above is prepared. When forming the chip deterioration layer 14, the processed wafer 10 is placed on a stage, and the position of the stage, etc. is adjusted so that the focal point of the laser light L is relatively scanned along the outer edge of each chip formation region RA.

[0028] As a result, a chip-use altered layer 14 is formed on the outer edge of each chip-forming region RA, where gallium and nitrogen are decomposed by thermal energy. More specifically, by irradiating the laser light L, nitrogen evaporates as a gas and gallium is precipitated to form the chip-use altered layer 14. Note that the chip-use altered layer 14 is in a state where minute voids are formed due to the separation of nitrogen. Furthermore, the chip-use altered layer 14 is shared by adjacent chip-forming regions RA at the boundaries between the chip-forming regions RA. That is, in the portion where the chip-forming regions RA are adjacent to each other, the chip-use altered layer 14 is formed along the boundaries between the chip-forming regions RA.

[0029] In addition, in this embodiment, when forming the chip deterioration layer 14, the stage or the like is moved appropriately, and the laser light L is irradiated so that the focal point moves to two or more different locations in the thickness direction of the processed wafer 10 at the outer edge of each chip formation region RA. In this case, the chip deterioration layers 14 are formed at different locations in the thickness direction of the processed wafer 10, and the chip deterioration layers 14 may be separated from each other or connected to each other. In addition, when the focal point is moved to two or more different locations in the thickness direction of the processed wafer 10, the focal point is moved from the one surface 10a side to the other surface 10b side of the processed wafer 10.

[0030] The chip-use deteriorated layer 14 is formed so that when the wafer-use deteriorated layer 15 of FIG. 1H is formed, nitrogen generated by forming the wafer-use deteriorated layer 15 can be released to the outside through the pores of the chip-use deteriorated layer 14. Although not particularly limited, in this embodiment, when the chip-use deteriorated layer 14 is formed, a solid-state laser light, a green laser having a wavelength of 532 nm, is used as the laser light L. The laser light L is irradiated with a processing point output of 2 μJ, a pulse width of 500 ps, ​​and a processing speed of 500 mm / s. However, these conditions are only an example, and the inventors have confirmed that the chip-use deteriorated layer 14 is appropriately formed even when the processing point output of the laser light L is lower or the pulse width is shorter. The inventors have also confirmed that the chip-use deteriorated layer 14 is appropriately formed even when the processing point output of the laser light L is higher or the pulse width is longer.

[0031] Next, as shown in FIG. 1G, laser light L is irradiated from the other surface 10b of the processed wafer 10, and a chip mark TM such as a lot number for identifying the semiconductor chip 100 when the semiconductor chip 100 described later is manufactured is formed inside each chip formation area RA.

[0032] Specifically, a laser device similar to that in the process of FIG. 1B is prepared. When forming the chip marks TM, the processed wafer 10 is placed on a stage, and the position of the stage and the like is adjusted so that the focal point of the laser light L is at a predetermined position in each chip formation region RA. The shape of the chip marks TM is a variety of identifiable patterns such as figures such as lines and polygons, or numbers. Although not particularly limited, in this embodiment, the conditions of the laser light L when forming the chip marks TM are the same as the conditions when forming the wafer marks WM.

[0033] After that, although not shown, a heat treatment is performed to promote the precipitation of gallium and improve the visibility of the chip mark TM. Note that, since the heat treatment is performed on the processed wafer 10 on which the one-side element component portion 11 is formed, the heat treatment is performed at a temperature equal to or higher than the melting point of Ga (i.e., 29.76°C) and equal to or lower than 200°C.

[0034] 1H, laser light L is applied from the other surface 10b of the processed wafer 10 to form a wafer-deteriorated layer 15 along the surface direction of the processed wafer 10 at a position at a predetermined depth D from the one surface 10a of the processed wafer 10. In this embodiment, the wafer-deteriorated layer 15 is formed using a laser device similar to that in the step of FIG. 1B.

[0035] When forming the wafer-use damaged layer 15, the position of a stage or the like is adjusted so that the focal point of the laser light L is scanned relatively along the surface direction of the processed wafer 10. As a result, the wafer-use damaged layer 15 is formed along the surface direction on the processed wafer 10. Note that the wafer-use damaged layer 15 is configured such that nitrogen evaporates as a gas and gallium is precipitated, similar to the chip-use damaged layer 14.

[0036] In this case, in this embodiment, the wafer deterioration layer 15 is formed so as to intersect with the chip deterioration layer 14 or pass directly below the chip deterioration layer 14. As a result, in this embodiment, it is possible to suppress the application of large distortion to each chip formation region RA when the wafer deterioration layer 15 is formed.

[0037] That is, when the chip-use deteriorated layer 14 is not formed, as shown in FIG. 2A, the nitrogen generated when the wafer-use deteriorated layer 15 is formed is difficult to be discharged to the outside, so that the distortion of the processed wafer 10 caused by the formation of the wafer-use deteriorated layer 15 may become large. On the other hand, in this embodiment, the chip-use deteriorated layer 14 is formed, and the wafer-use deteriorated layer 15 is formed so as to intersect with the chip-use deteriorated layer 14 or pass directly under the chip-use deteriorated layer 14. Therefore, as shown in FIG. 2B, the nitrogen generated when the wafer-use deteriorated layer 15 is formed is easily discharged to the outside through the pores of the chip-use deteriorated layer 14. Therefore, it is possible to suppress the distortion of the processed wafer 10 caused by the formation of the wafer-use deteriorated layer 15 from becoming large, and the distortion applied to each chip formation region RA can be reduced.

[0038] In this embodiment, when forming the deteriorated layer 15 for the wafer, a solid-state laser light having a wavelength of 532 nm is used as the laser light L, but is not particularly limited thereto. The laser light L is irradiated with a processing point output of 0.1 to 0.3 μJ, a pulse width of 500 ps, ​​and a processing speed of 50 to 500 mm / s. However, these conditions are only an example, and the inventors have confirmed that the deteriorated layer 15 for the wafer is appropriately formed even when the processing point output of the laser light is lower or the pulse width is shorter. The inventors have also confirmed that the deteriorated layer 15 for the wafer is appropriately formed even when the processing point output of the laser light L is higher or the pulse width is longer.

[0039] The predetermined depth D for forming the wafer deteriorated layer 15 is set according to the ease of handling and pressure resistance of the semiconductor chip 100, and is about 10 to 200 μm. In this case, the location where the wafer deteriorated layer 15 is formed varies according to the thickness of the epitaxial film 3, and the wafer is formed inside the epitaxial film 3, at the boundary between the epitaxial film 3 and the GaN wafer 1, or inside the GaN wafer 1. FIG. 1H shows an example in which the wafer deteriorated layer 15 is formed at the boundary between the epitaxial film 3 and the GaN wafer 1.

[0040] As described below, at least a part of the GaN wafer 1 in the processed wafer 10 is reused as a recycled wafer 40. For this reason, the wafer-use damaged layer 15 is preferably formed inside the epitaxial film 3 or at the boundary between the epitaxial film 3 and the GaN wafer 1. When the wafer-use damaged layer 15 is formed inside the GaN wafer 1, the wafer-use damaged layer 15 is preferably formed on the one surface 1a side of the GaN wafer 1.

[0041] When the wafer-use altered layer 15 is formed inside the epitaxial film 3, the wafer-use altered layer 15 is formed in the n-type semiconductor device. - The n-type epitaxial layer 3b is not + In the following description, the portion of the processed wafer 10 on the side of the wafer-deteriorated layer 15 toward the first surface 10a is referred to as a chip-configured wafer 30, and the portion of the processed wafer 10 on the side of the wafer-deteriorated layer 15 toward the second surface 10b is referred to as a recycled wafer 40.

[0042] Next, as shown in FIG. 1I, an auxiliary member 50 is placed on the other surface 10b side of the processed wafer 10. The auxiliary member 50 is composed of, for example, a base material 51 and an adhesive 52 capable of changing adhesive strength, similar to the holding member 20. In this case, the base material 51 in the auxiliary member 50 is composed of, for example, glass, a silicon substrate, ceramics, etc., and the adhesive 52 in the auxiliary member 50 is composed of, for example, ultraviolet curing resin, wax, double-sided tape, etc. Then, the holding member 20 and the auxiliary member 50 are gripped and a tensile force or the like is applied in the thickness direction of the processed wafer 10, and the wafer is divided into a chip-configured wafer 30 and a recycled wafer 40 with the wafer deterioration layer 15 as the boundary (i.e., the starting point of branching).

[0043] As described above, the wafer mark WM is preferably formed so as to remain on the recycled wafer 40. This allows the recycled wafer 40 to be used as a GaN wafer 1 as described later, starting from the process shown in FIG. 1C. In the following description, the surface of the chip-configuration wafer 30 on which the one-side element component 11 is formed is referred to as the one surface 30a, the divided surface of the chip-configuration wafer 30 is referred to as the other surface 30b, and the divided surface of the recycled wafer 40 is referred to as the one surface 40a. In addition, in each of the figures following FIG. 1I, the wafer alteration layer 15 remaining on the other surface 30b of the chip-configuration wafer 30 and the one surface 40a of the recycled wafer 40 are omitted as appropriate.

[0044] Thereafter, as shown in FIG. 1J, a typical semiconductor manufacturing process is performed to form a second surface side element component 60 of the semiconductor element, such as a metal film 61 constituting a back surface electrode, on the second surface 30b of the chip configuration wafer 30.

[0045] Before the step of forming the other surface side element component 60, a step of planarizing the other surface 30b of the chip configuration wafer 30 by a CMP (short for chemical mechanical polishing) method or the like may be performed as necessary. Fig. 1J shows a diagram of the case where the other surface 30b of the chip configuration wafer 30 is planarized. After the step of forming the other surface side element component 60 is performed, a heat treatment such as laser annealing may be performed as necessary to make the metal film 61 and the other surface 30b of the chip configuration wafer 30 into ohmic contact.

[0046] 1K, the holding member 20 is expanded, and each chip forming area RA is divided with the chip alteration layer 14 as a boundary (i.e., the starting point of branching). Thereafter, the adhesive force of the adhesive 22 is weakened by heat treatment or light irradiation, and the semiconductor chip 100 is picked up. In this way, the semiconductor chip 100 is manufactured. Before dividing each chip forming area RA, slits or the like may be formed in the metal film 61 at the boundary of each chip forming area RA as necessary, so that the metal film 61 can be easily divided for each chip forming area RA. In this case, in the step of FIG. 1J, a metal mask may be prepared to cover the divided parts, so that the metal film 61 is not formed in the divided parts.

[0047] Moreover, the semiconductor chip 100 manufactured as described above is configured to include a chip configuration substrate 110 having one surface 110a, another surface 110b opposite to the one surface, and a side surface 110c connecting the one surface 110a and the other surface 110b. The chip configuration substrate 110 has an epitaxial film 3 made of GaN, and is configured such that the one surface side element configuration portion 11 is formed on the one surface 110a side, and the other surface side element configuration portion 60 is formed on the other surface 110b side. The semiconductor chip 100 is configured in a state in which the chip mark TM is formed as described above.

[0048] In addition, the semiconductor chip 100 of this embodiment is configured by dividing the chip-use altered layer 14 as a boundary, so that the chip-use altered layer 14 remains on the side surface 110c. In this case, the chip-use altered layer 14 is a layer in which gallium and nitrogen are separated and gallium is precipitated, and is in a state in which minute irregularities are formed. Therefore, the manufacturing method of this embodiment manufactures a semiconductor chip 100 that is easy to handle.

[0049] 1L, one surface 40a of the recycled wafer 40 configured as shown in FIG. 1I is flattened by CMP using a polishing device 70 or the like. The flattened recycled wafer 40 is then used as the GaN wafer 1, and the steps from FIG. 1A onward are carried out again. This allows the GaN wafer 1 to be used multiple times to configure the semiconductor chip 100. However, if the wafer mark WM is formed on the recycled wafer 40, the steps from FIG. 1C onward are carried out without carrying out the steps of FIG. 1B again.

[0050] According to the present embodiment described above, the wafer mark WM is formed inside the processed wafer 10 by precipitating gallium. No recess is formed on the one surface 10a and the other surface 10b of the processed wafer 10. Therefore, it is possible to prevent the processed wafer 10 from cracking starting from the wafer mark WM.

[0051] According to this embodiment, the chip mark TM is formed inside the semiconductor chip 100 by precipitating gallium. No recess is formed on the one surface 110a and the other surface 110b of the chip configuration substrate 110 that configures the semiconductor chip 100. This makes it possible to prevent the semiconductor chip 100 from cracking starting from the chip mark TM.

[0052] Furthermore, by forming the wafer mark WM internally, it is possible to suppress the generation of minute dust particles, etc., when forming the wafer mark WM. Similarly, by forming the chip mark TM internally, it is possible to suppress the generation of minute dust particles, etc., when forming the chip mark TM. Therefore, it is possible to suppress the attachment of dust particles, etc., to the processed wafer 10 or the semiconductor chip 100 when forming these marks WM and TM.

[0053] (1) In this embodiment, the wafer mark WM is formed before forming the one-surface element component 11. This allows for a wider range of conditions to be selected for the heat treatment, etc., compared to the case where the wafer mark WM is formed after the one-surface element component 11 is formed.

[0054] (2) In this embodiment, when forming the wafer mark WM, the wafer mark WM is formed on the portion that will become the recycled wafer 40. As a result, when the recycled wafer 40 is used again as the GaN wafer 1, there is no need to perform a new process of forming the wafer mark WM, and the manufacturing process can be simplified.

[0055] (3) In this embodiment, the chip mark TM is formed before forming the wafer deteriorated layer 15. Therefore, compared to the case where the chip mark TM is formed after the wafer deteriorated layer 15 is formed, it is possible to suppress the laser light L when forming the chip mark TM from being scattered by the wafer deteriorated layer 15, and it is possible to preferably form the chip mark TM.

[0056] (4) In this embodiment, after the wafer mark WM is formed and after the chip mark TM is formed, a heat treatment is performed. This can promote the precipitation of gallium that constitutes each of the marks WM and TM, and can improve the visibility of each of the marks WM and TM.

[0057] (5) In this embodiment, the processed wafer 10 is divided into a chip configuration wafer 30 and a recycled wafer 40, and the recycled wafer 40 is reused as the GaN wafer 1. Therefore, it is not necessary to prepare a new GaN wafer 1 every time a semiconductor chip 100 is manufactured, and the GaN wafer 1 can be effectively used. Therefore, the productivity of the semiconductor chip 100 can be improved.

[0058] (Other embodiments) Although the present disclosure has been described based on the embodiment, it is understood that the present disclosure is not limited to the embodiment or structure. The present disclosure also encompasses various modifications and modifications within the equivalent range. In addition, various combinations and forms, as well as other combinations and forms including only one element, more than one element, or less than one element, are also within the scope and concept of the present disclosure.

[0059] For example, in the first embodiment, the epitaxial film 3 is -Alternatively, the n-type epitaxial layer 3b may be formed alone.

[0060] In the first embodiment, in the step of FIG. 1J, the metal film 61 may be formed without polishing the other surface 30b of the chip-configuration wafer 30. For example, when forming an optical semiconductor element as a semiconductor element, it is possible to effectively extract light from the other surface by forming an uneven structure on the other surface side of the semiconductor chip 100. Then, immediately after dividing the processed wafer 10 into the chip-configuration wafer 30 and the recycled wafer 40, the other surface 30b of the chip-configuration wafer 30 is in a state in which the wafer-use altered layer 15 remains, and in a state in which minute irregularities are formed. Therefore, when forming an optical semiconductor element, the other surface 30b of the chip-configuration wafer 30 may not be polished, and the unevenness of the wafer-use altered layer 15 may be used.

[0061] 1B, an epitaxial film may also be formed on the other surface 1b of the GaN wafer 1. This makes it easier to leave a predetermined thickness or more as the recycled wafer 40 even when the wafer-use altered layer 15 is formed in the GaN wafer 1, thereby increasing the number of times the wafer can be reused.

[0062] In the first embodiment, only one of the steps of forming the wafer marks WM and the step of forming the chip marks TM may be performed.

[0063] In the first embodiment, the step of forming the wafer mark WM may be performed after forming the epitaxial film 3 in Fig. 1C and before the step of forming the one-surface side element constituent portion 11 in Fig. 1D. The wafer mark WM may be formed on a portion of the processed wafer 10 that will become the chip constituent wafer 30.

[0064] Furthermore, in the first embodiment, the step of forming the chip marks TM may be performed after the step of forming the wafer altered layer 15 in FIG. 1H.

[0065] Moreover, in the above-described first embodiment, instead of forming the chip-use deteriorated layer 14, a groove may be formed in the portion where the chip-use deteriorated layer 14 is to be formed. Moreover, in the above-described first embodiment, after forming the chip-configuration wafer 30, the chip-configuration wafer 30 may be divided into chip units by a dicing saw, laser dicing, or the like to individualize the semiconductor chips 100, without forming the chip-use deteriorated layer 14 or the groove. [Explanation of symbols]

[0066] 1 GaN wafer 1a one side 1b Other side 3 Epitaxial film 10 Processed wafer 10a one side 10b Other side 11. One-side element component 30 chip configuration wafer 40 Recycled Wafers 100 Semiconductor Chips WM wafer mark TM Chip Mark L Laser light

Claims

1. A method for manufacturing a semiconductor chip having a semiconductor element formed thereon, comprising the steps of: Providing a gallium nitride wafer (1) made of gallium nitride and having one surface (1a) and another surface (1b); forming an epitaxial film (3) on one surface of the gallium nitride wafer, the surface on the epitaxial film side being one surface (10a) and the surface on the gallium nitride wafer side being the other surface (10b), thereby forming a processed wafer (10) having a plurality of chip formation areas (RA) on the one surface side; forming one-surface-side element constituent parts (11) of the semiconductor element in the plurality of chip formation regions; By irradiating the inside of the processed wafer from the other side of the processed wafer with laser light (L), a wafer alteration layer (15) in which nitrogen is separated from gallium is formed along the surface direction of the processed wafer; Dividing the processed wafer at the wafer deterioration layer as a boundary, thereby dividing the processed wafer into a chip configuration wafer (30) on one side of the processed wafer and a recycled wafer (40) on the other side of the processed wafer; and removing a semiconductor chip (100) from the chip configuration wafer; After preparing the gallium nitride wafer and before dividing, a laser beam (L) is irradiated to the inside of the gallium nitride wafer or the processed wafer to form marks (WM, TM) in which gallium is precipitated; The forming of the mark includes forming a wafer mark (WM) as the mark after preparing the gallium nitride wafer and before forming the one-surface side element component, Furthermore, forming the mark includes forming the wafer mark on the portion to be the recycled wafer, The method for manufacturing a semiconductor chip, wherein the forming of the wafer alteration layer and the forming of the wafer mark are performed by irradiating the wafer with the laser light having the same wavelength.

2. 2. The method for manufacturing a semiconductor chip as described in claim 1, wherein the mark is formed by forming a chip mark (TM) as the mark in each of the plurality of chip formation regions after forming the one-side element component portion and before forming the wafer alteration layer.

3. 3. The method for manufacturing a semiconductor chip according to claim 1, further comprising the step of: performing a heat treatment after forming the mark.

4. 4. The method for manufacturing a semiconductor chip according to claim 1, wherein the recycled wafer is reused as the gallium nitride wafer.

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