Preemptive wake-up circuitry for waking up from low-power modes

Abstract

The circuit (100) includes a power controller (150), a real-time clock (RTC) subsystem (170), and a processing subsystem (110). The RTC subsystem includes an alarm register that stores a predetermined time for a task and provides an early warning countdown (175) and a scheduled event signal (180). The processing subsystem includes a processor (120), a preemptive wakeup circuit (125), and components coupled to the processor and configured to execute tasks with the processor. The preemptive wakeup circuit includes a selector logic circuit, a comparator, and a wakeup initiation circuit. The selector logic receives a clock generator and a latency value indicating a wakeup time for the component, and outputs a maximum wakeup time to the comparator indicating when the early warning countdown and the maximum wakeup time are equal. The wakeup initiation circuit generates a clock request and disables a sleep mode indicator (140). The power controller provides a clock signal (130) to wake up the component.

Description

[Technical field]

[0001] Many electronic devices implement low power modes for components and subsystems within the device to conserve power. However, these subsystems may be scheduled to perform a task at a predetermined time in the future. Resources required to perform the scheduled real-time task, such as oscillators, clocks, static random access memory (SRAM), etc., may not be active or available from the low power mode for use by the processing subsystem to execute the time-critical task. This results in latency overhead and imprecise timing performance of the time-critical task. Therefore, for real-time tasks, it may be beneficial to wake up the subsystems and required resources from the low power mode before the scheduled real-time task.

[0002] Preemptive wakeup can be handled in software, but requires complex software sequences to manage the state of hardware resources required for the scheduled events. This can increase power consumption during wakeup sequences from low power modes. Some systems achieve precise wakeup by implementing two system real-time clock channels for each event: one for the preemptive wakeup event and one for the scheduled event itself. However, the number of channels required to handle scheduled events for multiple processing unit subsystems increases the operating and component costs for the system. Summary of the Invention

[0003] In one example, an electronic circuit includes a processing subsystem, a power controller coupled to the processing subsystem, and a real-time clock (RTC) subsystem coupled to the processing subsystem. The RTC subsystem includes an alarm register for storing a predetermined time for performing a task and is configured to provide an early warning countdown based on the predetermined time and a scheduled event signal for the predetermined time. The processing subsystem includes a processor coupled to the RTC subsystem to receive the scheduled event signal, a component coupled to the processor and configured to perform a task with the processor, and a preemptive wakeup circuit coupled to the RTC subsystem to receive the early warning countdown. The preemptive wakeup circuit is configured to generate a clock request signal and disable a sleep mode indicator based on the early warning countdown. The power controller is configured to provide a clock signal and wake up the component based on the sleep mode indicator.

[0004] In some implementations, the RTC subsystem includes a real-time clock for generating the scheduled event signal and the early warning countdown. The processor is further configured to write the predetermined time to the alarm register. In some implementations, the RTC subsystem includes a plurality of alarm registers, each of the plurality of alarm registers configured to store a predetermined time for a unique task to be performed, and the processor is further configured to write a subset of the plurality of alarm registers. In some embodiments, the RTC subsystem is further coupled to the power controller and configured to clear the alarm register, or a subset of the plurality of alarm registers, in response to a processing subsystem reset signal from the power controller. In some implementations, the early warning countdown is 12 bits wide, and the RTC subsystem decrements the countdown based on a first clock frequency for a first portion of time and based on a second, higher clock frequency for a second, shorter portion of time.

[0005] In some examples, the preemptive wake-up circuit includes a selector logic circuit, a comparator coupled to the selector logic circuit, and a wake-up initiation circuit coupled to the comparator. The selector logic circuit receives latency values ​​indicative of respective wake-up times for the components and the clock generator, and receives a selector signal indicative of which latency value is greatest corresponding to the longest wake-up time for output by the selector logic circuit. In some implementations, the selector logic circuit is a multiplexer. The comparator outputs a signal indicative of an early warning countdown value from the RTC subsystem being equal to the maximum latency value. The wake-up initiation circuit generates a clock request signal and disables the sleep mode indicator based on the comparator output. [Brief description of the drawings]

[0006] For a detailed description of various examples, reference will now be made to the accompanying drawings.

[0007] [Figure 1] 1 is an exemplary device configured for preemptive wake-up of a processing unit from a low power mode.

[0008] [Diagram 2] 2 illustrates a timing diagram for components in the example device shown in FIG. 1.

[0009] [Diagram 3] 1 illustrates an example preemptive wakeup module.

[0010] [Figure 4] 1 illustrates an example device configured for preemptive wake-up of multiple processing units from a low power mode.

[0011] [Diagram 5]1 illustrates, in flow chart form, an example process for preemptive wake-up of a processing unit from a low power mode. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0012] The exemplary system described herein provides low power, cost-effective preemptive wake-up of processing subsystems and associated resources from a low power mode. The system real-time clock included in the exemplary system includes multiple channels such that each processing unit subsystem may own and program scheduled wake-up events into multiple channels. Each unique processing unit subsystem may have multiple pending scheduled wake-up events at a time. The system real-time clock communicates with each processing unit subsystem using an early warning bus. In some examples, the same early warning bus from the system real-time clock to a particular processing unit subsystem may be used for all of the scheduled events of each processing unit subsystem, rather than a unique early warning bus for each channel owned and programmed by a particular processing unit subsystem. In one such example, a system including four processing unit subsystems includes four early warning buses, one for each processing unit subsystem, for the system real-time clock to communicate.

[0013] A preemptive wake-up circuit included in the processing unit subsystem initiates wake-up of components in response to the countdown on the early warning bus. In an example where the wake-up circuit initiates waking up components based on the component with the longest wake-up time, the circuit includes a selector logic circuit, a comparator, and a wake-up initiation subcircuit. The selector logic circuit may be a multiplexer and has inputs for receiving a latency value indicating a wake-up time for a resource used by the processing unit subsystem and a selector signal. The selector signal indicates which latency value is greatest corresponding to the longest wake-up time for the resource required to execute the scheduled event. The comparator compares the maximum latency value with a value of the early warning countdown from the system real-time clock and indicates when the countdown is equal to the maximum latency value. The wake-up initiation subcircuit generates a clock request and disables a sleep mode indicator based on the comparator output. This allows the resources required to execute a scheduled event to be fully transitioned from sleep mode to active mode prior to the scheduled event, allowing the processor to immediately execute the scheduled event.

[0014] 1 is an example device 100 configured for preemptive wake-up of a processing unit 120 from a low power mode. The device 100 includes a central processing unit subsystem (CPUSS) 110, a power reset clock manager (PRCM) 150, and a system real-time clock (RTC) 170. The CPUSS 110 includes a static random access memory (SRAM) 115, a central processing unit 120, and a preemptive wake-up module 125. The terms "central processing unit" and "CPU" (singular) are used herein to refer to either a single or multiple processing units and are used broadly to describe central processing units, digital signal processors, application specific integrated circuits, and the like. The SRAM 115 is described as a static random access memory, although any suitable non-transitory storage medium may be used.

[0015] The PRCM 150 provides power consumption control, clock control, and reset control for the CPUSS 110. The PRCM 150 receives a clock request from the CPUSS 110 via the bus 130 and provides a clock signal to the CPUSS 110. The PRCM 150 also receives a sleep mode indicator 140 from the CPUSS 110 and provides a reset signal 135 to the CPUSS 110. The PRCM 150 also controls power to the SRAM 115 via the SRAM power interface 145. The PRCM 150 also powers on or off the oscillators 155A-N according to the clock request of the device 100 and provides appropriate clock signals to the components of the device 100. For example, the PRCM 150 powers off the oscillator 155A in response to the clock signal generated by the oscillator 155A being no longer needed by any component in the device 100, and powers on the oscillator 155A in response to a request for the clock signal generated by the oscillator 155A. PRCM 150 also provides a CPUSS reset event signal over bus 160 to system RTC 170, which causes system RTC 170 to reset all scheduled alarms stored in the system RTC by CPUSS 110. After the channel is reset, system RTC 170 generates a CPUSS reset event acknowledge signal over bus 160, which PRCM 150 receives. PRCM 150 can then release CPUSS 110 from reset without subsequent interference from remaining scheduled alarms and events.

[0016] System RTC 170 operates in a real-time clock mode and provides wake-up signals and event triggers to components within device 100 in a sleep low power mode. An internal counter within system RTC 170 keeps a count of clock pulses related to real time and compares the state of this internal counter to a count stored in one or more alarm registers. In the exemplary device 100, the alarm registers are labeled as channel 1 through channel N. In response to the system RTC 170 internal counter equaling a value a period of time before the scheduled alarm time, system RTC 170 generates an early warning countdown on bus 175 that decrements based on a low frequency clock and provides it to the appropriate components within device 100. In response to the internal count equaling the scheduled alarm time, system RTC 170 generates a scheduled event signal 180 and provides it to the appropriate components within device 100.

[0017] The CPUSS 110 owns one or more channels in the system RTC 170 and programs the stored alarm time in the channel, such as by a register write operation. After scheduling an alarm, the CPUSS 110 enters a sleep mode. In the sleep mode, the clock request on the bus 130 is turned off and the PRCM 150 places the SRAM 115 in a retention state by adjusting the power via the SRAM power interface 145. The CPUSS 110 provides a sleep mode indicator 140 to the PRCM 150. The power supply to the CPUSS 110 is left intact. In response to the system RTC 170 internal counter being equal to a value a period of time before the scheduled alarm time, the system RTC 170 generates an early warning countdown decrement based on a low frequency clock and provides it to the preemptive wakeup module 125 using the early warning bus 175. In the exemplary device 100, the system RTC 170 generates a 12-bit wide early warning countdown decrement based on a 32 kilohertz (kHz) clock in response to a count equal to approximately 4 milliseconds before the scheduled alarm time.

[0018] In response to receiving the early warning countdown from the system RTC 170 over the bus 175, the preemptive wakeup module 125 determines which resources are required to implement the event associated with the alarm and which resource has the longest wakeup time. As described further herein with respect to FIG. 3, the preemptive wakeup module 125 determines which resource takes the longest time to transition from sleep mode to awake mode and preemptively wakes up the resource that is needed some time before the scheduled event that corresponds to the longest wakeup time. This ensures that the required resource is fully woken up and accessible before the scheduled event, but not so far in advance that it significantly impacts the power consumption of the CPUSS 110 in the low power mode.

[0019] The preemptive wakeup module 125 then compares the longest wakeup time with the value of the early warning countdown on the bus 175. During the penultimate period of the low frequency clock and the early warning countdown on the bus 175, the system RTC 170 decrements the early warning countdown more quickly based on the higher frequency clock. In the exemplary device 100, the system RTC 170 decrements the early warning countdown on the bus 175 every microsecond based on the 1 MHz clock, 32 microseconds before the scheduled alarm time. In response to the value of the early warning countdown on the bus 175 being equal to the longest wakeup time, the preemptive wakeup module 125 triggers a clock request to the PRCM 150 for an appropriate clock signal, turning off the sleep mode indicator from the CPUSS 110 to the PRCM 150 and prompting the wakeup of the CPUSS 110.

[0020] In response to the internal counter value being equal to the stored alarm time, the system RTC 170 generates and provides a scheduled event signal 180 to the CPU 120. The CPU 120 then performs the action indicated by the scheduled event signal 180. The preemptive wake-up module 125 triggers the wake-up of the CPUSS 110 at the required wake-up time before the scheduled alarm time, so that the resources required to process the alarm-related event are fully transitioned from sleep mode to awake mode by the time the CPU 120 receives the scheduled event signal 180. Thus, the CPU 120 can immediately begin processing the scheduled event without delay while other components of the CPUSS 110 wake up from sleep mode.

[0021] FIG. 2 illustrates a timing diagram for components in the example device 100 shown in FIG. 1. Graph 210 shows a variable frequency countdown clock based on which the early warning countdown is decremented. In this example, the early warning countdown has a total duration of 4 milliseconds, or 128 low frequency clock periods for a 32 kHz low frequency clock. For simplicity, only the last 12 of the 128 low frequency clock periods are shown, with the last portion showing an increase in clock frequency to decrement the early warning countdown faster. Graph 220 shows the decrement value for the 12-bit early warning countdown bus 175 from the system RTC 170 to the preemptive wakeup module 125. Graph 230 shows the scheduled event signal 180 from the system RTC 170 to the CPU 120.

[0022] The early warning bus 175 runs from the system RTC 170 to the preemptive wakeup module 125 in the CPUSS 110, which decrements the early warning countdown in anticipation of a scheduled wakeup event. After decrementing based on the lower 32 kHz frequency for 127 clock cycles, 11 of which are shown in graph 220, the early warning countdown on the bus 175 decrements faster, 1 MHz for the exemplary device 100, based on the higher frequency clock. By using a low frequency clock for the first 11 bits of the 12-bit early warning bus 175 and a high frequency clock for only the last bit, the power used by the clocks in the device 100 is reduced compared to using a high frequency clock for all 12 bits of the early warning bus 175.

[0023] The preemptive wakeup module 125 in the CPUSS 110 compares the value of the early warning countdown 175 with the longest wakeup time for resources required to perform the event for which the alarm is scheduled, and in response to the value of the early warning countdown on the bus 175 being equal to the longest wakeup time, causes these resources to initiate a wakeup from sleep mode. This provides the required resources with enough time to fully transition from sleep mode to active mode before the scheduled event, while keeping them in sleep mode for as long as possible. After the 12-bit early warning countdown on the bus 175 has expired, the system RTC 170 generates and sends a scheduled event signal 180 to the CPU 120, which performs the intended operation.

[0024] 3 illustrates an example preemptive wakeup module 300, such as the preemptive wakeup module 125 in the example device 100 shown in FIG. 1. The preemptive wakeup module 300 includes a multiplexer 310, a comparator 330, and a wakeup initiation module 340. The multiplexer 310 receives latency values ​​315-325 from a register that contains known wakeup times for resources in a CPU SS associated with the preemptive wakeup module 300 and resources used by such CPU SS. For example, the latency value 315 may be a value of 1 microsecond corresponding to a wakeup time for a 10 GHz clock used by the associated CPU SS. The latency value 320 may be a value of 2 microseconds corresponding to a wakeup time for a 20 GHz clock used by the associated CPU SS. The latency value 325 may be a value of 3.5 microseconds, corresponding to the wake-up time for the SRAM associated with the CPUSS to transition from a retention state to an active state. Multiplexer 310 includes three inputs, although any number of inputs may be used according to the particular implementation.

[0025] The multiplexer 310 receives a control signal 305 indicating the particular input that the multiplexer 310 should output. The control signal 305 indicates which resource used by the CPUSS to perform the scheduled event has the longest wake-up time. For example, the CPU may use a 10 GHz clock and SRAM to perform the scheduled event. Since the SRAM has a longer wake-up time than the 10 GHz clock, 3.5 microseconds compared to 1 microsecond, the control signal 305 indicates that the multiplexer 310 should output a latency value 325. Although the exemplary preemptive wake-up module 300 includes a multiplexer, any suitable selector logic circuit may be used based on the particular implementation.

[0026] The comparator 330 compares the output of the multiplexer 310 with the value of a system RTC early warning countdown 375, such as the early warning countdown provided on bus 175 from the system RTC 170 shown in FIG. 1. The wakeup initiation module 340 receives the output of the comparator 330 and generates an appropriate clock request 345 to a power reset clock manager associated with the CPUSS to turn off a sleep mode indicator 350 from the CPUSS to the power reset clock manager. The power reset clock manager then provides an appropriate clock signal to transition the SRAM from retention mode to active mode. As a result of the preemptive wakeup module 300 and the system RTC early warning countdown 375, the resources required for the scheduled event are fully powered up and accessible for use by the CPU upon receiving the scheduled event signal, without wakeup latency. The preemptive wakeup module 300 ensures that the required resources are fully powered up and accessible prior to the scheduled event, but not so far in advance that it significantly impacts the power consumption of the CPUSS and reduces the effectiveness of the low power mode.

[0027] 4 illustrates an example device 400 configured for preemptive wakeup of multiple processing units from a low power mode. The example device 400 is similar to the example device 100 shown in FIG. 1, except that whereas the example device 100 includes only a single CPUSS 110, the example device 400 includes multiple CPUSSs 410A-N. The device 400 includes a power reset clock manager (PRCM) 450 and a system real-time clock (RTC) 470. A bus 430A enables the PRCM 450 and the CPUSS 410A to send and receive clock signals and clock requests, reset signals, and sleep mode indications. Similarly, a bus 430N enables the PRCM 450 and the CPUSS 410N to send and receive clock signals and clock requests, reset signals, and sleep mode indications. The PRCM 450 controls power to the SRAM 415A in the CPUSS 410A via an SRAM power interface 445A. The PRCM 450 controls power to the SRAM 415N in the CPUSS 410N via an SRAM power interface 445N.

[0028] The system RTC 470 includes channels 1 through M. The number of channels in the system RTC 470 need not equal the number of CPUSSs 410 included in the exemplary device 400, since each CPUSS 410 can own multiple channels at a time. This allows each CPUSS 410 to schedule multiple events and alarm times and have multiple scheduled events pending at a time. Regardless of the number of channels owned by a CPUSS 410, only a single early warning bus is required for a particular CPUSS 410, reducing the number of channels and communication buses required within the device 400 compared to a device that implements two channels for each scheduled event, one channel for the early wakeup event and one channel for the scheduled event itself. The early warning bus associated with a particular CPUSS 410 indicates the time delay for the next scheduled event.

[0029] Ownership of channels within the system RTC 470 may be subject to security rules and peripheral firewalls so that a CPUSS 410 cannot overwrite or interfere with channels owned by a different CPUSS 410. The system RTC 470 is coupled to each CPUSS 410A-N by a unique early warning bus 475A-N. Bus 460 carries a CPUSS reset event signal from the PRCM 450 to the system RTC 470 and a reset event acknowledge signal from the system RTC 470 to the PRCM 450. A reset event signal from the PRCM 450 may indicate a particular CPUSS 410 to be reset, and the system RTC 470 will reset only the channels owned by that particular CPUSS 410.

[0030] 5 illustrates, in flow chart form, an example process 500 for preemptive wake-up of a processing unit from a low power mode, such as the CPUSS 110 and electronic device 100 shown in FIG. 1. The process 500 is performed by a processing unit executing instructions stored in a non-transitory computer-readable medium, such as the CPUSS 110 executing instructions stored in the SRAM 115 from the electronic device 100. The flow chart begins with operation 505, during which the RTC 170 decrements an early warning countdown to a predetermined time associated with a scheduled task. In operation 510, the preemptive wake-up module 125 determines a set of resources required to perform the scheduled task. In operation 515, the preemptive wake-up module 125 determines a maximum latency value indicating the longest wake-up time.

[0031] At operation 520, the preemptive wakeup module 125 compares the maximum latency value to the early warning countdown value. At operation 525, the preemptive wakeup module 125 determines whether the early warning countdown value is equal to the maximum latency value. If the early warning countdown value is not equal to the maximum latency value, the system RTC 170 continues to decrement the early warning countdown, and the preemptive wakeup module 125 again compares the maximum latency value and the early warning countdown value until the two are equal. In response to the maximum latency value and the early warning countdown value being equal, the preemptive wakeup module 125 generates a clock request at operation 530 and disables the sleep mode indicator at operation 535.

[0032] As used herein, the term "couple" means either an indirect or direct wired or wireless connection. Thus, if a first device couples to a second device, the connection may be through a direct connection or through an indirect connection via other devices and connections. The phrase "based on" means "based at least in part on." Thus, if X is based on Y, X may be a function of Y and any number of other factors.

[0033] Modifications may be made to the exemplary embodiments described, and other embodiments are possible, within the scope of the invention.

Claims

1. 1. An electronic circuit comprising: A real-time clock (RTC) subsystem including an alarm register for storing a predetermined time for performing a task, providing an early warning countdown value based on the predetermined time; providing a scheduled event signal at said predetermined time; the RTC subsystem, a processing subsystem, a processor coupled to the RTC subsystem for receiving the scheduled event signal; a memory coupled to the processor, the memory and the processor configured to operate in cooperation to perform the tasks; a preemptive wakeup circuit coupled to the RTC subsystem to receive the early warning countdown value, latency values ​​indicative of respective wake-up times for the memory and clock generator, and a selector signal indicative of a maximum latency value among the latency values ​​indicative of a longest wake-up time, the preemptive wakeup circuit configured to generate a clock request signal and disable a sleep mode indicator based on the early warning countdown value; the processing subsystem including: a power controller coupled to the processing subsystem, the power controller configured to provide a clock signal and power up the memory based on the sleep mode indicator; 2. An electronic circuit comprising:

2. 2. The electronic circuit of claim 1, The electronic circuit, wherein the power controller is further configured to transition the memory into a retention mode and disable the clock signal in response to the sleep mode indicator and the clock request signal.

3. 2. The electronic circuit of claim 1, The electronic circuit, wherein the power controller is further configured to transition the memory to an active mode in response to the sleep mode indicator being disabled by the preemptive wakeup circuit.

4. 2. The electronic circuit of claim 1, The preemptive wakeup circuit comprises: a selector logic circuit configured to receive the latency value and the selector signal; a comparator coupled to the selector logic circuit and configured to output a signal indicating that the early warning countdown value is equal to the maximum latency value; a wake-up initiation circuit coupled to the comparator, the wake-up initiation circuit configured to generate a clock request signal and disable the sleep mode indicator; 2. An electronic circuit comprising:

5. 2. The electronic circuit of claim 1, the RTC subsystem is further configured to decrement the early warning countdown value based on a first clock frequency for a first portion of time and a second clock frequency for a second portion of time, the second clock frequency being greater than the first clock frequency.

6. 6. An electronic circuit according to claim 5, The early warning countdown value is 12 bits.

7. 6. An electronic circuit according to claim 5, The second portion of the time is shorter than the first portion of the time.

8. 2. The electronic circuit of claim 1, The RTC subsystem further comprises a real time clock for providing the scheduled event signal and the early warning countdown value.

9. 2. The electronic circuit of claim 1, The electronic circuitry is configured to cause the processor to write the predetermined time to the alarm register.

10. 2. The electronic circuit of claim 1, An electronic circuit, the RTC subsystem coupled to the power controller, the RTC subsystem further configured to clear the alarm register in response to a processing subsystem reset signal.

11. 2. The electronic circuit of claim 1, the alarm register is a first alarm register, the predetermined time is a first predetermined time, The electronic circuit further includes a second alarm register configured to store a second predetermined time for the RTC subsystem to perform a specific task.

12. 2. The electronic circuit of claim 1, the alarm register is a first alarm register of a plurality of alarm registers included in the RTC subsystem, each alarm register of the plurality of alarm registers configured to store a respective predetermined time for performing a unique task; An electronic circuit configured to cause the processor to write to a subset of the plurality of alarm registers.

13. 13. An electronic circuit according to claim 12, comprising: An electronic circuit, wherein the RTC subsystem is coupled to the power controller, the RTC subsystem further configured to clear a subset of the plurality of alarm registers in response to a processing subsystem reset signal.

14. 1. A method of preemptive wakeup for a processing system, comprising: decrementing the early warning countdown value to a predetermined time at which a task is scheduled; determining a set of resources including memory to be used to perform the scheduled task and a set of latency values ​​indicative of wake-up times, the set of latency values ​​including respective latency values ​​indicative of the wake-up times for respective resources in the set of resources; receiving a selector signal determining a maximum latency value from the set of latency values ​​indicating which resource of the set of resources has the longest wake-up time; comparing said maximum latency value to said early warning countdown value; generating a clock request and disabling a sleep mode indicator in response to the maximum latency value and the early warning countdown value being equal; waking up the memory by a power controller in response to the sleep mode indicator; A method comprising:

15. 15. The method of claim 14, the early warning countdown value is decremented based on a first clock frequency for a first portion of the early warning countdown value and a second clock frequency for a second portion of the early warning countdown value; A method, wherein the first clock frequency is lower than the second clock frequency and a first portion of the early warning countdown value is longer than a second portion of the early warning countdown value.

16. 15. The method of claim 14, The method further comprising transitioning, by the power controller, the set of resources from a sleep mode to an active mode in response to the clock request and disabling the sleep mode indicator.

17. A preemptive wakeup circuit comprising: a selector logic circuit having a first input for receiving latency values ​​indicative of respective wake-up times for components used by a processing unit to execute a task, and a second input for receiving a selector signal indicative of a maximum latency value among said latency values ​​indicative of which component among said components has the longest wake-up time; a comparator coupled to the selector logic, the comparator having a first input receiving an early warning countdown value based on the determined time to perform the task, and a second input receiving an output of the selector logic; a wake-up initiation subcircuit coupled to the comparator, the wake-up initiation subcircuit configured to generate a clock request and disable a sleep mode indicator based on the early warning countdown value; a preemptive wakeup circuit including:

18. 18. A preemptive wakeup circuit as claimed in claim 17, comprising: The preemptive wakeup circuit, wherein the selector logic circuit includes a multiplexer.

19. 18. A preemptive wakeup circuit as claimed in claim 17, comprising: The preemptive wakeup circuit, wherein the wakeup initiation subcircuit is further configured to generate the clock request and disable the sleep mode indicator in response to the comparator indicating that the early warning countdown value and an output of the selector logic circuit are equal.

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