Transfer process for realizing semiconductor devices

Abstract

A method for fabricating and transferring high-quality, manufacturable light-emitting devices, such as micro-sized light-emitting diodes (μLEDs), edge-emitting lasers, and vertical-cavity surface-emitting lasers (VCSELs), using epitaxial lateral overgrowth (ELO) and release methods. III-nitride semiconductor layers are grown on a host substrate using a growth-limiting mask, and the III-nitride semiconductor layers on the wings of the ELO are then fabricated into a light-emitting device. The device is released from the host substrate to a thickness corresponding to the growth-limiting mask and then transferred or lifted off from the host substrate. Post-processing of the device, such as attaching a distributed Bragg reflector (DBR) mirror, forming cladding layers, and / or adding a heat sink, is then performed.

Description

[Technical field]

[0001] (CROSS REFERENCE TO RELATED APPLICATIONS) This application claims the benefit under 35 USC Section 119(e) of the following co-pending and commonly assigned applications: U.S. Provisional Application No. 63 / 041,659, filed June 19, 2020 by Srinivas Gandrothula and Takeshi Kamikawa and entitled “TRANSFER PROCESS TO REALIZE SEMICONDUCTOR DEVICES” (Attorney Docket No. G&C30794.0777USP1(UC 2020-723-1));

[0002] This application is related to the following co-pending and commonly assigned applications:

[0003] U.S. Utility Patent Application No. 16 / 608,071, filed October 24, 2019 by Takeshi Kamikawa, Srinivas Gandrothula, Hongjian Li, and Daniel A. Cohen, entitled “METHOD OF REMOVING A SUBSTRATE” (Attorney Docket No. 30794.0653USWO(UC2017-621-2)), which was filed May 7, 2018 by Takeshi Kamikawa, Srinivas Gandrothula, Hongjian Li, and Daniel A. Cohen, entitled “METHOD OF REMOVING A SUBSTRATE” under 35 U.S.C. Section 365(c). This application claims the benefit of commonly assigned, co-pending PCT International Patent Application No. PCT / US18 / 31393 (Attorney Docket No. 30794.0653WOU1 (UC2017-621-2)), entitled "METHOD OF REMOVING A SUBSTRATE," which in turn claims the benefit of commonly assigned, co-pending U.S. Provisional Patent Application No. 62 / 502,205 (Attorney Docket No. 30794.0653USP1 (UC2017-621-1)), filed May 5, 2017, by Takeshi Kamikawa, Srinivas Gandrothula, Hongjian Li, and Daniel A. Cohen, entitled "METHOD OF REMOVING A SUBSTRATE," under 35 U.S.C. Section 119(e);

[0004] U.S. Utility Patent Application No. 16 / 642,298, filed February 20, 2020 by Takeshi Kamikawa, Srinivas Gandrothula, and Hongjian Li, entitled “METHOD OF REMOVING A SUBSTRATE WITH A CLEAVING TECHNIQUE” (Attorney Docket No. 30794.0659USWO (UC2018-086-2)), which was filed September 17, 2018 by Takeshi Kamikawa, Srinivas Gandrothula, and Hongjian Li, entitled “METHOD OF REMOVING A SUBSTRATE WITH A CLEAVING TECHNIQUE” under 35 U.S.C. Section 365(c). This application claims the benefit of co-pending and commonly assigned PCT International Patent Application No. PCT / US18 / 51375 (Attorney Docket No. 30794.0659WOU1 (UC2018-086-2)), entitled "METHOD OF REMOVING A SUBSTRATE WITH A CLEAVING TECHNIQUE," filed on September 15, 2017 by Takeshi Kamikawa, Srinivas Gandrothula, and Hongjian Li under 35 U.S.C. Section 119(e), which application is hereby incorporated by reference in its entirety. This application claims the benefit of co-pending and commonly assigned U.S. Provisional Patent Application No. 62 / 559,378 (Attorney Docket No. 30794.0659USP1 (UC2018-086-1)), entitled "METHOD OF USE IN COMPONENTS WITH THIS TECHNIQUE";

[0005] U.S. Utility Patent Application No. 16 / 978,493, filed September 4, 2020 by Takeshi Kamikawa, Srinivas Gandrothula, and Hongjian Li, entitled “METHOD OF FABRICATING NON-POLAR AND SEMI-POLAR DEVICES USING EPITAXIAL LATERAL OVERGROWTH” (Attorney Docket No. 30794.0680USWO(UC2018-427-2)), which was filed April 1, 2019 by Takeshi Kamikawa, Srinivas Gandrothula, and Hongjian Li, entitled “METHOD OF FABRICATING NONPOLAR AND SEMIPOLAR DEVICES USING EPITAXIAL LATERAL OVERGROWTH” under 35 U.S.C. Section 365(c). This application claims the benefit of co-pending and commonly assigned PCT International Patent Application No. PCT / US19 / 25187 (Attorney Docket No. 30794.0680WOU1 (UC2018-427-2)) entitled "METHOD OF FABRICATING NONPOLAR AND SEMIPOLAR DEVICES USING EPITAXIAL LATERAL OVERGROWTH," filed on March 30, 2018 by Takeshi Kamikawa, Srinivas Gandrothula, and Hongjian Li under 35 U.S.C. Section 119(e), which application is incorporated herein by reference in its entirety. This application claims the benefit of co-pending and commonly assigned U.S. Provisional Patent Application No. 62 / 650,487 (Attorney Docket No. G&C30794.0680USP1 (UC2018-427-1)), entitled "METHOD FOR USE IN AN IMPROVED PHARMACEUTICALLY ...

[0006] U.S. Utility Patent Application No. 17 / 048,383, filed on October 16, 2020 by Takeshi Kamikawa and Srinivas Gandrothula and entitled “METHOD FOR DIVIDING A BAR OF ONE OR MORE DEVICES” (Attorney Docket No. 30794.0681USWO (UC2018-605-2)), which was filed on May 17, 2019 by Takeshi Kamikawa and Srinivas Gandrothula under 35 U.S.C. Section 365(c) and entitled “METHOD FOR DIVIDING A BAR OF ONE OR MORE DEVICES.” This application claims the benefit of commonly assigned PCT International Application No. PCT / US19 / 32936 (Attorney Docket No. 30794.0681WOU1 (UC2018-605-2)), entitled "METHOD FOR DIVIDING A BAR OF ONE OR MORE DEVICES," which claims the benefit of commonly assigned U.S. Provisional Application No. 62 / 672,913 (Attorney Docket No. G&C30794.0681USP1 (UC2018-605-1)), filed on May 17, 2018, by Takeshi Kamikawa and Srinivas Gandrothula, entitled "METHOD FOR DIVIDING A BAR OF ONE OR MORE DEVICES," under 35 U.S.C. Section 119(e);

[0007] U.S. Utility Application No. 17 / 049,156, filed on October 20, 2020 by Srinivas Gandrothula and Takeshi Kamikawa and entitled “METHOD OF REMOVING SEMICONDUCTING LAYERS FROM A SEMICONDUCTING SUBSTRATE” (Attorney Docket No. 30794.0682USWO (UC 2018-614-2)), which application is hereby incorporated by reference in its entirety under 35 U.S.C. Section 365(c) by Srinivas Gandrothula and Takeshi Kamikawa and entitled “METHOD OF REMOVING SEMICONDUCTING LAYERS FROM A SEMICONDUCTING SUBSTRATE” (Attorney Docket No. 30794.0682USWO (UC 2018-614-2)), which application is hereby incorporated by reference in its entirety ... under 35 U.S.C. Section 365(c) by Srinivas Gandrothula and Takeshi Kamikawa and entitled “METHOD OF REMOVING SEMICONDUCTING LAYERS FROM A SEMICONDUCTING SUBSTRATE” (Attorney Docket No. 30794.0682USWO (UC 2018-614-2)), which application is hereby incorporated by reference in its entirety under 35 U.S.C. Section 365(c) by Srinivas G This application claims the benefit of co-pending and commonly assigned PCT International Patent Application No. PCT / US19 / 34686 (Attorney Docket No. 30794.0682WOU1 (UC 2018-614-2)) entitled "METHOD OF REMOVING SEMICONDUCTION LAYERS FROM A SEMICONDUCTION SUBSTRATE," filed on May 30, 2018 by Srinivas Gandrothula and Takeshi Kamikawa under 35 U.S.C. Section 119(e), entitled "METHOD OF REMOVING SEMICONDUCTION LAYERS FROM A SEMICONDUCTION SUBSTRATE," and is hereby incorporated by reference in its entirety. This application claims the benefit of co-pending and commonly assigned U.S. Provisional Application No. 62 / 677,833 (Attorney Docket No. G&C30794.0682USP1 (UC2018-614-1)), entitled "SUBSTRATE";

[0008] U.S. Utility Patent Application No. 17 / 285,827, filed April 15, 2021 by Takeshi Kamikawa and Srinivas Gandrothula and entitled “METHOD OF OBTAINING A SMOOTH SURFACE WITH EPITAXIAL LATERAL OVERGROWTH” (Attorney Docket No. 30794.0693USWO(UC 2019-166-2)), which application was filed October 31, 2019 by Takeshi Kamikawa and Srinivas Gandrothula under 35 U.S.C. Section 365(c) and entitled “METHOD OF OBTAINING A SMOOTH SURFACE WITH EPITAXIAL LATERAL OVERGROWTH” This application claims the benefit of co-pending and commonly assigned PCT International Patent Application No. PCT / US19 / 59086 (Attorney Docket No. 30794.0693WOU1 (UC 2019-166-2)), entitled "METHOD OF OBTAINING A SMOOTH SURFACE WITH EPITAXIAL LATERAL SURFACE FORMATION ... This application claims the benefit of co-pending and commonly assigned U.S. Provisional Application No. 62 / 753,225 (Attorney Docket No. G&C30794.0693USP1 (UC2019-166-1)), entitled "METHOD FOR USE IN AN IMPROVED PHARMACEUTICALLY IMPROVED PHARMACEUTICALLY IMPROVED OVERGROWTH";

[0009] PCT International Patent Application No. PCT / US20 / 13934, filed on January 16, 2020 by Takeshi Kamikawa, Srinivas Gandrothula, and Masahiro Araki, entitled “METHOD FOR REMOVAL OF DEVICES USING A TRENCH” (Attorney Docket No. 30794.0713WOU1 (UC2019-398-2)), which application was filed on January 16, 2019 by Takeshi Kamikawa, Srinivas Gandrothula, and Masahiro Araki, entitled “METHOD FOR REMOVAL OF DEVICES USING A TRENCH” under 35 U.S.C. Section 119(e). This application claims the benefit of co-pending and commonly assigned U.S. Provisional Application No. 62 / 793,253 (Attorney Docket No. G&C30794.0713USP1 (UC2019-398-1)), entitled "TRENCH";

[0010] PCT International Patent Application No. PCT / US20 / 20647, filed March 2, 2020 by Takeshi Kamikawa and Srinivas Gandrothula and entitled “METHOD FOR FLATTENING A SURFACE ON AN EPITAXIAL LATERAL GROWTH LAYER” (Attorney Docket No. 30794.0720WOU1 (UC2019-409-2)), which application was filed March 1, 2019 by Takeshi Kamikawa and Srinivas Gandrothula under 35 U.S.C. Section 119(e) and entitled “METHOD FOR FLATTENING A SURFACE ON AN EPITAXIAL LATERAL GROWTH LAYER” (Attorney Docket No. 30794.0720WOU1 (UC2019-409-2)), This application claims the benefit of co-pending and commonly assigned U.S. Provisional Application No. 62 / 812,453 (Attorney Docket No. G&C30794.0720USP1 (UC2019-409-1)), entitled "LAYER";

[0011] PCT International Patent Application No. PCT / US20 / 22430, filed September 17, 2020 by Takeshi Kamikawa, Srinivas Gandrothula, and Masahiro Araki, entitled “METHOD FOR REMOVING A BAR OF ONE OR MORE DEVICES USING SUPPORTING PLATES” (Attorney Docket No. 30794.0724WOU1 (UC 2019-416-2)), which was filed March 12, 2019 by Takeshi Kamikawa, Srinivas Gandrothula, and Masahiro Araki, entitled “METHOD FOR REMOVING A BAR OF ONE OR MORE DEVICES USING SUPPORTING PLATES” under 35 U.S.C. Section 119(e). This application claims the benefit of co-pending and commonly assigned U.S. Provisional Application No. 62 / 817,216 (Attorney Docket No. G&C 30794.0724USP1 (UC 2019-416-1)), entitled "METHOD FOR USE IN COMPONENTS WITH METHODS OF USE IN COMPONENTS OF THE PATENT PLATES";

[0012] PCT International Patent Application No. PCT / US21 / 27914, filed April 19, 2021 by Takeshi Kamikawa, Masahiro Araki, and Srinivas Gandrothula, and entitled “METHOD FOR REMOVING A DEVICE USING AN EPITAXIAL LATERAL OVERGROWTH TECHNIQUE” (Attorney Docket No. 30794.0762WOU1 (UC 2020-706-2)), which application was filed April 17, 2020 by Takeshi Kamikawa, Masahiro Araki, and Srinivas Gandrothula, and entitled “METHOD FOR REMOVING A DEVICE USING AN EPITAXIAL LATERAL OVERGROWTH TECHNIQUE” under 35 U.S.C. Section 119(e). This application claims the benefit of co-pending and commonly assigned U.S. Provisional Application No. 63 / 011,698 (Attorney Docket No. G&C30794.0762USP1 (UC 2020-706-1)), entitled "METHOD OF USE IN COMPONENTS WITH METHODS ...

[0013] All of those applications are incorporated herein by reference.

[0014] FIELD OF THEINVENTION

[0015] The present invention simplifies the method of fabricating semiconductor devices, primarily light emitting devices, by depositing or separating semiconductor layers from a host substrate. [Background technology]

[0016] Small size light emitting diodes (LEDs) (also known as micro LEDs or μLEDs) are inorganic LEDs at micron dimensions and are self-emitting, which means that μLEDs can achieve the highest contrast ratio and simplify display panel design. Recently, several studies have shown interest in employing μLEDs at sizes of 100-200 μm as backlight sources in liquid crystal displays (LCDs) to increase contrast ratio, reduce the complexity of the LCD architecture, and improve other display parameters such as viewing angle and aperture ratio. Because μLEDs are sized at a microscopic scale, each μLED represents a pixel in a monochrome display, or three red, green, and blue μLEDs form a pixel in a full-color display. In addition, μLEDs are made of well-developed inorganic semiconductor materials such as InGaN or AlGaInP, and offer advantages over existing display technologies such as LCDs and organic LEDs, including high peak brightness, excellent energy efficiency, chemical robustness, and long operating lifetime.

[0017] The current focus of the III-nitride materials system is on Ga x Al y In z N, where 0≦x≦1, 0≦y≦1, 0≦z≦1, and x+y+z=1. Most of the research attention has been focused on InGaN-based μLEDs, but there has also been some work on UV-AlGaN μLEDs for display applications.

[0018] One of the most significant advantages of the InGaN material system is emission wavelength tunability, since the bandgaps of GaN and InN are 3.4 eV and 0.7 eV, respectively, and alloys of InGaN can theoretically span the entire visible spectrum by varying the composition percentage of indium and gallium in the active region, also known as the quantum well (QW).

[0019] In addition, current InGaN materials, especially for display applications, are grown on sapphire (Al2O3) or silicon (Si) substrates using metal-organic chemical vapor deposition (MOCVD). Depending on the reactor dimensions, wafer diameters can be scaled from 2 inches to 6 inches for sapphire substrates or up to 18 inches for silicon substrates, and this scalability is ideal for mass production due to low material costs.

[0020] Epitaxial lateral overgrowth (ELO) can in principle be employed on any of the aforementioned substrates, therefore scalability is not an issue in applying the technique, and ELO is known for better crystalline quality compared to growing device layers directly on a foreign template.

[0021] Conventional LEDs (at least larger than 300 μm on a side) usually have a large upper light-emitting area device design to reduce the carrier concentration in the active region and avoid the effect of efficiency reduction. Due to this large light-emitting area, non-radiative centers such as crystal defects may not play a major role in device operation. However, when the light-emitting area is about 100 μm×100 μm to 10 μm×10 μm or even smaller, existing defects in the light-emitting layer may significantly degrade the performance.

[0022] In addition to the scalable flexibility when using foreign substrates such as sapphire or silicon, in conventional approaches, laser lift-off or other damage-inducing methods can be employed to remove the fabricated devices from the foreign substrate to other substrates or display panels, but no methods have been reported to utilize homogeneous substrates. Furthermore, when used with foreign or heterogeneous substrates to obtain high quality device layers, buffer or seed layers must be included to avoid laser lift-off damage, and the overall device will be thicker.

[0023] μLEDs have great potential in displays and other emerging applications, but there are several challenges that need to be addressed before commercial products for mass production can be realized. Three fundamental issues with InGaN μLEDs are size-dependent efficiency, color gamut (long wavelength emission), and mass transfer techniques.

[0024] Producing high quality μLEDs is problematic due to their size-limited efficiency (due to increased non-radiative recombination when the size of the element dimensions rivals crystalline defects in the semiconductor layers, or the presence of defects at a given element dimension). Mass migration of μLEDs is also a unique problem for display manufacturers of μLED displays, with each red, green, and blue element representing a pixel, and large numbers of pixels being required for display applications.

[0025] Despite the numerous existing methods for mass transfer, an ideal mass transfer method should have a fast transfer rate with high yield and selectivity for dead or defective pixels, which is particularly challenging for display builders.

[0026] Pick-and-place methods developed using elastomeric stamps are the standard approach for transferring μLEDs into solid-state lighting packaging. Although typical pick-and-place methods are suitable for the transfer of μLED displays, selectivity or avoidance of dead pixels, or local repair of dead pixels after transferring them onto the display panel, is necessary when millions of elements are involved.

[0027] In addition to advancing μLED transfer technology for display applications, there are also other emerging applications including biomedical and optogenetics due to the heterogeneous integration of inorganic semiconductors onto flexible and transparent substrates.

[0028] Edge-emitting lasers, commonly known as Fabry-Perot lasers, are focused on many high-energy applications such as automotive lighting, specialty lighting, outdoor and indoor lighting, and visible light communication (Li-Fi) applications. However, most of the development has been focused on fabricating them in a conventional manner, including on a host substrate in the final product.

[0029] There is also a strong interest in fabricating vertical cavity surface emitting lasers (VCSELs) that meet the goals of manufacturability, good quality, non-critical tolerances, best performance, and good yield. Distributed Bragg reflectors (DBRs) are key building blocks in the formation of semiconductor microcavities and VCSELs. Successes with epitaxial GaAs DBR mirrors have paved the way for the universal deployment of III-V VCSELs in communications and mobile applications.

[0030] However, similar development of GaN-based blue VCSELs has been hindered by the challenge of preparing DBRs that can be mass-produced. It has been recognized that a key component and obstacle in GaN VCSEL technology is the preparation of the DBR mirror, especially the DBR mirror on the substrate side. Furthermore, semiconductor epitaxial DBRs or conductive DBRs can be made electrically and thermally conductive, thus bringing significant benefits to VCSEL performance.

[0031] There are approaches to fabricating continuous VCSEL structures by employing semiconductor epitaxial DBRs on a host substrate, but this is laborious due to the requirement of a large number of quarter-wave layer pairs. For example, for epitaxial DBRs of lattice-matched AlInN / GaN or AlGaN / GaN DBRs, at least 30 or more quarter-wave layer pairs are required to achieve better reflectivity. Due to differences in lattice parameters between the component layers (leading to high tensile or compressive strain during growth of the DBR before reaching the required number of pairs for high reflectivity), the growth of AlGaN / GaN DBRs has also already encountered significant cracking, morphological degradation, or dislocation generation.

[0032] As a result, it would be ideal to stack or laminate the VCSEL gain medium with a separate vertical conductive DBR or epitaxial DBR. However, the use of methods such as chemical mechanical polishing (CMP), or laser lift-off (LLO, which was developed to separate GaN LEDs from sapphire substrates using backside illumination with an excimer laser), or photoelectric, or electroetching, are the only available methods for substrate removal so that the VCSEL gain medium, which is removed from the host substrate, can be stacked to the desired DBR.

[0033] However, these methods have their own limitations when implementing them on an industrial scale. For example, the LLO method does not work with GaN or Si substrates due to the opacity of the GaN or Si substrates to the excimer laser, which is a serious limitation for VCSEL devices grown on bulk GaN substrates.

[0034] Typically, substrate removal requires a follow-up polishing step after layer separation to smooth the surface and fine-tune the cavity thickness. Achieving precise control of cavity thickness through polishing with good uniformity across the wafer can be a challenging task.

[0035] The use of a photoelectron etching approach has the advantage of precisely controlling the thickness of the microresonator through a bandgap selective etching process, but the yield, controllability, and time to remove the substrate may prevent this approach from being adopted for mass production.

[0036] The work done by Kuramoto et al., APEX,11,112101 (2018) on developing an epitaxial DBR, and Hamaguchi et al., APEX,12,044004 (2019) on developing a curved mirror approach on the substrate side are some examples from this industry that circumvent some of the limitations of manufacturability methods.

[0037] For visible light emitters, III-nitride materials such as GaN are required to fabricate good quality VCSELs. Alternatively, there are approaches that utilize III-nitride templates on foreign substrates such as Si, sapphire, SiC, etc. However, especially for devices with stimulated emission and smaller dimensions of the emitting area, homogeneous epitaxy would be suggested rather than non-homogeneous or heteroepitaxy to tolerate micron-level defects.

[0038] There is also a need for a method to fabricate a good quality emitting aperture for a VCSEL device that emits light perpendicular to the substrate.

[0039] In U.S. Patent No. 9,407,067 B2 and U.S. Patent Application Publication No. 2019 / 0173263 A1 (Patent Document 1), and in the publication Phys. Status Solidi A 2016, 213, 1170-1176, Hamaguchi et al. describe fabricating a light-emitting element aperture on the ELO region. However, unwanted crystal quality between the mass generation and the resonance length of the cavity may affect the final characteristics of the device.

[0040] also used a curved mirror approach, but it still requires substrate thinning to reduce absorption losses in the cavity, which can be a difficult process to control on an industrial scale. In addition, removing or thinning the substrate by chemical or mechanical polishing is laborious and would affect the yield.

[0041] In Takeshi et al., OPEX, Vol. 27, Issue 17, pp. 24717-24723 (2019), and in PCT International Patent Application No. PCT / US18 / 31393, filed May 7, 2018, by Takeshi Kamikawa, Srinivas Gandrothula, Hongjian Li, and Daniel A. Cohen, cross-referenced above, entitled “METHOD OF REMOVING A SUBSTRATE”, and Gandrothula et al., APEX, Vol. 13, Number 4, (2020), a robust method for removing a substrate after fabricating light-emitting elements on the substrate was demonstrated. The method utilized the ELO wings as the light-emitting aperture and the smooth layer surface of the device layer on the growth limiting mask of the ELO wings as a bonding support surface for external carrier thermal or / and conductive DBRs such as AlN / GaN DBRs on Si, SiC, GaN, etc.

[0042] Nonetheless, there remains a need in the art for improved transfer processes for realizing semiconductor devices. The present invention fulfills that need. [Prior art documents] [Patent documents]

[0043] [Patent Document 1] U.S. Patent Application Publication No. 2019 / 0173263 (specification) Summary of the Invention [Means for solving the problem]

[0044] To overcome the limitations in the prior art described above, as well as other limitations that will become apparent upon perusal and understanding of this specification, the present invention discloses a method for fabricating a semiconductor layer on a host substrate, which can be a homogeneous or heterogeneous substrate or template that contains the material of the fabricated and separated semiconductor layer, and the fabrication and separation are performed on the wings of III-nitride ELO layers, thereby resulting in devices with good crystalline quality on these layers in terms of dislocation density and stacking faults.

[0045] The present invention provides a solution for mass transfer of small size LEDs such as μLEDs, local repair of μLEDs on display panels, and improved yield in edge-emitting laser devices, and also enables innovative designs such as double cladding laser devices, useful in stacking the resonant cavities of VCSEL devices with at least one perfectly conducting DBR mirror.

[0046] The present invention begins with placing or positioning a semiconductor device layer on a host substrate using ELO and etching, with or without minimal bonding to the host substrate. Once the semiconductor device layer is released from the host substrate, with or without minimal bonding to the host substrate, several unique devices can be realized, including μLEDs, edge-emitting lasers, and VCSELs.

[0047] The present invention can be realized using either a homogeneous host substrate similar to the material of the device layer for better crystal quality and improved efficiency, or a foreign substrate such as Si, SiC, sapphire, Ga2O3, III-nitride template, or ELO-containing III-nitride template substrate. Alternatively, this approach can be adopted for any semiconductor material system.

[0048] Specifically, the present invention implements the following steps: a III-nitride ELO layer is grown on a host substrate using an ELO method, using a growth-limiting mask. The III-nitride ELO layer is intended to be an area with reduced dislocation density compared to areas that are not III-nitride ELO layers. The light-emitting area of ​​a micro-LED, or the gain medium (ridge) of an edge-emitting laser, or the light-emitting aperture of a VCSEL, is at least partially restricted to the wings of the III-nitride ELO layer, so that a good crystal quality layer can be guaranteed. In the case of edge-emitting lasers, such as double-clad edge-emitting lasers, or at least one DBR mirror of a VCSEL, or a microcavity LED (where at least one DBR mirror is placed to minimize crosstalk), there is still a need for further post-processing. In the case of a VCSEL, preferably, the light-emitting aperture is made completely within the wings of the III-nitride ELO layer. In the case of μLEDs, in a front-end process, p-pads and n-pads may be finished on the wings of the III-nitride ELO layer, and then the devices are separated and detached, but not lifted off from the host substrate.

[0049] The detached elements remain on the host substrate with very minimal or no attachment, so lifting them off of the host substrate for post-processing or in preparation for packaging does not require harsh lift-off methods such as LLO or polishing. The elements can be removed from the substrate either by an elastomeric stamp, or by a vacuum chuck, or by bonding, or by attaching them to a separate carrier substrate.

[0050] The present invention can avoid damage at the backside of the III-nitride device layers even when removed from a foreign or heterogeneous substrate. This damage-free removal method can be highly beneficial when transferring the μLED from its foreign or homogeneous substrate to another substrate, such as a mechanically flexible or optically transparent substrate.

[0051] In the case of edge-emitting lasers, even if the laser elements remain on the host substrate (e.g., wafer), they are detached from the host substrate in the form of elements with minimal or no attachment, which reduces the stiffness of the host substrate. Generally, bonding or attaching the elements with the stiff host substrate to another carrier for better heat sinking or for further processing such as facet cleaving and facet coating will result in bending of the substrate, leading to some process breakage. However, in the present invention, since the elements are detached from the host substrate, the present invention can selectively pick some elements and attach them to a heat sink carrier, allocating more heat sink area, rather than crowding the elements all together. The wafer-scale bonding process also improves yield due to the flexibility of the detached elements on the host substrate.

[0052] In the case of special designs such as double clad lasers, epitaxial cladding layers or cladding layers prepared externally, for example using sputtering or chemical vapor deposition, can be attached to the back of the removed element either by surface activated bonding or through a bonding assist layer. In particular, the back of the III-nitride ELO layers have an interface with a roughness of about <2 nm, since the surfaces of these layers are replicas of the surfaces of the growth limiting masks used in the ELO method. This roughness can allow simple surface activation to bond an external cladding such as a dielectric or epitaxial multilayer or another carrier wafer containing a conductive DBR mirror. The present invention can ideally help to avoid intermediate layers when bonding a DBR, cladding layer, or external cladding to the back of the element, since the III-nitride ELO layers are sufficiently smooth for such a surface activated bonding process, and the surface activated bonding can include a method for exposing the plasma to the carrier or substrate surface.

[0053] The interface at the growth-limiting mask and the III-nitride ELO layer is smooth enough to fabricate or attach a DBR mirror without heavy chemical processing. The III-nitride ELO layer and the III-nitride device layer, which together constitute an island-like III-nitride semiconductor layer, are removed from the substrate, and a DBR mirror is attached to the back of the wing of the ELO III-nitride layer, which becomes the interface provided between the growth-limiting mask and the ELO III-nitride layer. When fabricated, the μLEDs on the wings of the III-nitride ELO layer can be transferred onto a different carrier for further processing, such as with a simple PDMS stamp, or a vacuum chuck, or glue attached to a carrier plate. The edge-emitting laser fabricated on the wings of the III-nitride ELO layer can be transferred onto a better thermal management system, or the gain medium of the edge-emitting laser can be stacked with a double cladding layer when fabricated.

[0054] The ELO methods used to form the III-nitride island semiconductor layers may include growth by metalorganic chemical vapor deposition (MOCVD), hydride vapor phase epitaxy (HVPE), etc., to precisely control the thickness of the VCSEL device, and therefore the cavity length. The III-nitride ELO layers and III-nitride device layers are sized such that one or more of the III-nitride island semiconductor layers form rods (known as semiconductor rods or device rods). By doing this, nearly identical devices can be fabricated next to each other in a self-assembled array, and thus scaling up by integration can be more easily achieved. Alternatively, the III-nitride ELO layers can be made to first coalesce so that they can later be separated into device rods or individual chips.

[0055] All elements of such a rod can be addressed separately or together with other elements by designing an appropriate fabrication process. For example, one can make a common cathode or anode for such rods for monolithic integration, or address individual elements for full color display applications. As a result, high yields can be obtained.

[0056] The present invention functions regardless of material system, with blue and green pixels typically being made from III-nitride material systems, while red pixels typically being made from the AlInGaP material system. The present invention aims to provide not only high quality light emitting layers, but also a simplified transfer or pixel repair system for current display applications.

[0057] The simplified fabrication process described in this invention provides a way to repair local pixels for μLED displays, realize edge-emitting Fabry-Perot lasers, realize edge-emitting laser devices with improved thermal properties and smaller footprint for improved yield, or realize complex double-cladding thin edge-emitting lasers by removing the host substrate, or stack vertical conductive DBR mirrors for VCSELs.

[0058] Furthermore, the present invention can use heterosubstrates to grow island-like III-nitride semiconductor layers that form rods. For example, GaN templates grown on heterosubstrates such as sapphire, Si, GaAs, SiC, etc. can be used in the present invention.

[0059] Furthermore, the ELO method can significantly reduce dislocation and stacking fault densities, which are important issues when using heterosubstrates.

[0060] The present invention combines ELO and substrate removal techniques to provide a method for realizing better thermally managed devices, devices with smaller footprints, at least half the size of conventional devices, since these devices can be realized on the wings of III-nitride ELO layers, and more unique devices that require substrate removal to employ cladding on surfaces perpendicular to the light emission, i.e., the top and bottom of edge-emitting devices.

[0061] Therefore, the present invention can simultaneously solve many types of problems that arise with the use of heterosubstrates: for example, in a laser device, the interface between the growth-limiting mask and the III-nitride ELO layer can be used as a facet for the cavity. Important aspects of the present invention include the following:

[0062] No damage is generated because laser lift-off is not used. When using laser lift-off, device layer thicknesses have some tight tolerances to avoid damage from the laser, but the process of the present invention is not limited by damage.

[0063] The damage-free separation process can be applied to any type of substrate, including homogeneous and heterogeneous substrates.

[0064] Improves the process for transferring devices since selected devices can be extracted from the host substrate.

[0065] · Vacuum or stamping processes allow for element selectivity.

[0066] · The present invention fabricates the light emitting area of ​​the device on the wings of the III-nitride ELO layer, thereby providing better crystal quality within the light emitting area, which improves performance.

[0067] The present invention can utilize foreign substrates such as Si, SiC, sapphire, template substrates, ELO-assisted semiconductor substrates, etc. to scale up manufacturability for industrial needs.

[0068] The present invention can be utilized to increase yields by fabricating devices with smaller footprints confined to the wings of III-nitride ELO layers.

[0069] Fabry-Perot or edge-emitting lasers can be better fabricated with the edge-emitting laser element removed from the host substrate, facilitating a thermal management scheme.

[0070] Inter-wafer bonding problems such as warping can be avoided because the present invention bonds separate or isolated devices from the host substrate to an external carrier, which is typically a better thermally conductive carrier. Also, instead of attaching separate devices together to an external carrier (which limits the available heat spreading on the carrier), more thermal space can be allocated to each device on the carrier by selective transfer.

[0071] Complex designs such as cladding stacks on both sides of the emitting surface or on surfaces perpendicular to the emission.

[0072] Edge-emitting lasers can be fabricated on wings of III-nitride ELO layers and the ridges can be placed in areas with minimal defect density to improve electrical properties and lifetime.

[0073] A double-clad edge-emitting laser can be fabricated, where epitaxial cladding layers can be grown along the laser element structure during and after the ELO process, and after transferring the detached wings (laser elements), additional layers of the element can be etched into the cladding layers. For example, AlN can be used as the epitaxial cladding layers.

[0074] The light emitting aperture of the device can be fabricated on the wings of the III-nitride ELO layer, which offers better crystal quality in terms of defects and stacking faults than light emitting apertures fabricated directly on the original substrate.

[0075] The resonant cavity length of the VCSEL can be controlled epitaxially, rather than using complex techniques of thinning or chemical methods on the native substrate.

[0076] At least one of the DBR mirrors of the VCSEL cavity may be placed on the wings of the III-nitride ELO layer, and the DBR mirror may be placed on the back surface of the III-nitride ELO layer after separating the III-nitride ELO layer from the substrate. The back surface of the III-nitride ELO layer is very smooth and therefore suitable for making a DBR mirror for a VCSEL device due to the limited light scattering when reflected.

[0077] In the present invention, the preparation of the surface for the DBR mirror for the resonant cavity VCSEL uses only a growth-limiting mask.

[0078] The present invention can be applied to create curved mirrors when long resonant cavities for VCSELs are desired.

[0079] The present invention includes a method to achieve stress relaxation of the III-nitride ELO layer by removing the III-nitride ELO layer from its host substrate and then placing one of the DBR mirrors, which results in a crack-free and long-life device.

[0080] The substrate can be recycled for the next batch of devices.

[0081] The method is independent of the crystal orientation of the original substrate.

[0082] Some possible designs using this method are illustrated in the detailed description of the invention below. The present invention, when combined with the cross-referenced invention relating to removing semiconductor devices from semiconductor substrates described above, has many advantages over conventional manufacturable device elements. The present specification also provides, for example, the following: (Item 1) 1. A method, comprising: growing one or more epitaxial lateral overgrowth (ELO) layers and a device layer on the substrate using a growth limiting mask; fabricating one or more devices on or above the ELO layer and device layer; releasing the ELO layer and device layer above the growth limiting mask from the substrate; transferring the released ELO layer and device layer to a carrier wafer; A method comprising: (Item 2) 2. The method of claim 1, wherein the step of detaching comprises a separation process that separates the ELO layer and device layer into the devices. (Item 3) Item 11. The method of item 1, wherein the transferring step comprises a solderless bonding process. (Item 4) 2. The method of claim 1, wherein the transferring step includes a bonding process using solder. (Item 5) 2. The method of claim 1, wherein the transferring step integrates the ELO layer and device layer onto the carrier wafer, the carrier wafer being larger than the substrate. (Item 6) 2. The method of claim 1, wherein the transferred ELO layer and device layer are integrated into a photonic integrated circuit. (Item 7) 2. The method of claim 1, wherein the producing step occurs after the transferring step. (Item 8) Item 14. The method of item 1, wherein the released ELO layer and device layer remain on the growth limiting mask. (Item 9) Item 9. The method of item 8, wherein the detached ELO layer and device layer remain on the growth limiting mask with assistance from an anchored hook layer. (Item 10) Item 10. The method of item 1, further comprising removing the ELO layer and device layer from the substrate. (Item 11) Item 11. The method of item 10, wherein the removing step is performed using pick and place, a vacuum chuck, surface activated bonding, or bonding through an intermediate layer. (Item 12) Item 11. The method of item 10, wherein the removing step is performed selectively. (Item 13) 2. The method of claim 1, wherein the substrate is a semiconductor substrate. (Item 14) Item 14. The method of item 13, wherein the semiconductor substrate is independent of crystal orientation. (Item 15) 2. The method of claim 1, wherein the carrier wafer has one or more cladding layers for the device, a distributed Bragg reflector (DBR) layer, or a heat sink. (Item 16) The carrier wafer may include one or more epitaxial distributed Bragg reflectors for the devices. The method according to item 1, having a dielectric braided (DBR) layer. (Item 17) Item 13. The method of item 1, wherein the growth-limiting mask comprises a multi-layer structure. (Item 18) A device fabricated by the method of any one of items 1-17. (Item 19) An element, the element comprising: one or more epitaxial lateral overgrowth (ELO) layers and a device layer grown on a substrate using a growth limiting mask; one or more devices are fabricated on or above the ELO layer and device layer; the ELO layer and device layer are released from the substrate over the growth limit mask; The released ELO layer and device layer are transferred to a carrier wafer. (Item 20) 20. The device of claim 19, wherein the device comprises a micro-sized light emitting diode (μLED), an edge-emitting laser, or a vertical-cavity surface-emitting laser (VCSEL). [Brief description of the drawings]

[0083] Reference is now made to the drawings in which like reference numbers represent corresponding parts throughout. [Figure 1] FIG. 1 is a schematic diagram of a substrate, a growth-limiting mask, a non-coalesced III-nitride epitaxial lateral overgrowth (ELO) layer, and a coalesced III-nitride ELO layer according to one embodiment of the present invention.

[0084] [Figure 2A] 2A, 2B, and 2C illustrate a III-nitride ELO layer and a III-nitride device layer together forming an island-like III-nitride semiconductor layer according to one embodiment of the present invention. [Figure 2B] 2A, 2B, and 2C illustrate a III-nitride ELO layer and a III-nitride device layer together forming an island-like III-nitride semiconductor layer according to one embodiment of the present invention. [Figure 2C]2A, 2B, and 2C illustrate a III-nitride ELO layer and a III-nitride device layer together forming an island-like III-nitride semiconductor layer according to one embodiment of the present invention.

[0085] [Diagram 3] FIG. 3 illustrates that the III-nitride ELO layer and III-nitride device layer are detached from the host substrate without any contact, with the open areas of the substrate being used as weak links to hold the detached devices, and the hook layer assisting the fastening process to keep the detached devices attached to the substrate.

[0086] [Figure 4] FIG. 4 illustrates front-end processed devices including micro-LEDs, edge-emitting lasers, and VCSELs, and the tool used to remove the detached III-nitride ELO and III-nitride device layers from the host substrate.

[0087] [Diagram 5] FIG. 5 includes a schematic diagram of possible devices fabricated on the wings of a III-nitride ELO layer.

[0088] [Figure 6] FIG. 6 illustrates a process for fabricating and releasing a μLED device fabricated from III-nitride ELO layers and III-nitride device layers.

[0089] [Figure 7] FIG. 7 illustrates a process for fabricating and releasing an edge-emitting laser device from III-nitride ELO layers and III-nitride device layers.

[0090] [Figure 8] FIG. 8 illustrates a process for fabricating and releasing the VCSEL device from the III-nitride ELO layers and the III-nitride device layers.

[0091] [Figure 9] FIG. 9 is a schematic diagram of the components of a double-clad edge-emitting laser in which the n-side cladding is externally deposited onto the interface of the wings of III-nitride ELO layers.

[0092] [Figure 10] FIG. 10 illustrates a process for fabricating and releasing an externally deposited clad edge-emitting laser from III-nitride ELO layers and III-nitride device layers.

[0093] [Figure 11A] 11A, 11B, 11C, and 11D are schematics of a release process for separating III-nitride ELO layers from a host substrate and images from an experimental demonstration of release of III-nitride ELO layers without contact with the host substrate. [Figure 11B] 11A, 11B, 11C, and 11D are schematics of a release process for separating III-nitride ELO layers from a host substrate and images from an experimental demonstration of release of III-nitride ELO layers without contact with the host substrate. [Figure 11C] 11A, 11B, 11C, and 11D are schematics of a release process for separating III-nitride ELO layers from a host substrate and images from an experimental demonstration of release of III-nitride ELO layers without contact with the host substrate. [Figure 11D] 11A, 11B, 11C, and 11D are schematics of a release process for separating III-nitride ELO layers from a host substrate and images from an experimental demonstration of release of III-nitride ELO layers without contact with the host substrate.

[0094] [Figure 12A] FIG. 12A illustrates the elastomeric stamp process for transferring the released III-nitride ELO layer and III-nitride device layer onto a target patterned carrier.

[0095] [Figure 12B]FIG. 12B illustrates a process for transferring the released III-nitride ELO layer and III-nitride device layers using a spin-on-glass (SoG) resist material.

[0096] [Figure 12C] 12C and 12D illustrate the transferred polar c-plane III-nitride ELO layer and its interfacial surface roughness. [Figure 12D] 12C and 12D illustrate the transferred polar c-plane III-nitride ELO layer and its interfacial surface roughness.

[0097] [Figure 12E] 12E and 12F illustrate the transferred semi-polar 20-21 planar III-nitride ELO layer and its interfacial surface roughness. [Figure 12F] 12E and 12F illustrate the transferred semi-polar 20-21 planar III-nitride ELO layer and its interfacial surface roughness.

[0098] [Figure 12G] 12G and 12H illustrate the transferred non-polar 10-10 planar III-nitride ELO layer and its interfacial surface roughness. [Figure 12H] 12G and 12H illustrate the transferred non-polar 10-10 planar III-nitride ELO layer and its interfacial surface roughness.

[0099] [Figure 12I] FIG. 12I illustrates a surface effect strategy for the interface of III-nitride ELO layers.

[0100] [Figure 13] FIG. 13 includes a schematic diagram of a release process for separating the III-nitride ELO layers and securing them to a host substrate using weak links in the open areas.

[0101] [Figure 14A]14A and 14B include schematics of the detachment process for separating III-nitride ELO layers and anchoring them to a host substrate using hook layers, as well as images from an experimental demonstration of detachment of III-nitride ELO layers without contact with the host substrate. [Figure 14B] 14A and 14B include schematics of the detachment process for separating III-nitride ELO layers and anchoring them to a host substrate using hook layers, as well as images from an experimental demonstration of detachment of III-nitride ELO layers without contact with the host substrate.

[0102] [Figure 15] FIG. 15 includes schematics of the release process for separating the III-nitride ELO layers and anchoring them to the host substrate using hook layers using two different approaches.

[0103] [Figure 16A] 16A and 16B include schematic diagrams of a process for isolating edge-emitting laser devices on the wings of a III-nitride ELO layer and attaching the devices to an outer cladding template carrier to achieve a double-clad laser. [Figure 16B] 16A and 16B include schematic diagrams of a process for isolating edge-emitting laser devices on the wings of a III-nitride ELO layer and attaching the devices to an outer cladding template carrier to achieve a double-clad laser.

[0104] [Figure 17A] 17A and 17B include schematics of a process for isolating the VCSEL devices on the wings of the III-nitride ELO layer and attaching the devices to an external DBR mirror template carrier. [Figure 17B] 17A and 17B include schematics of a process for isolating the VCSEL devices on the wings of the III-nitride ELO layer and attaching the devices to an external DBR mirror template carrier.

[0105] [Figure 17C] FIG. 17C illustrates a DBR mirror template on a SiC carrier, where the DBR is composed of AlN / GaN or Al(Ga)N / GaN layers.

[0106] [Figure 17D] FIG. 17D includes a schematic diagram for preparing DBR layers on a GaN substrate and transferring them onto a thermally conductive carrier using a PEC process.

[0107] [Figure 17E] FIG. 17E is a schematic diagram for depositing a porous GaN template at the interface of the removed VCSEL device as a second DBR layer.

[0108] [Figure 18] FIG. 18 is a schematic diagram for allocating more space for selectively harvested device layers from a host substrate.

[0109] [Figure 19A] FIG. 19A is a vacuum chuck design for picking up the detached III-nitride ELO layer and III-nitride device layers from the host substrate.

[0110] [Figure 19B] FIG. 19B is a process for harvesting the detached III-nitride ELO layer and III-nitride device layer from the host substrate using a vacuum chuck.

[0111] [Figure 19C] FIG. 19C is a schematic diagram for utilizing a vacuum chuck containing a III-nitride ELO layer and a III-nitride device layer for further post-processing on the interface.

[0112] [Figure 19D] FIG. 19D is a schematic diagram for utilizing a vacuum chuck to locally repair defective elements on a targeted application such as a display.

[0113] [Figure 20] FIG. 20 is a schematic diagram for harvesting selected elements using an elastomeric PDMS stamp.

[0114] [Figure 21] FIG. 21 includes a schematic diagram illustrating the benefit of a wafer-scale bonding process in which the devices to be bonded are in a relaxed state due to separation from the host substrate.

[0115] [Figure 22] FIG. 22 contains a schematic diagram for achieving larger scale wafers using the transfer process of the present invention.

[0116] [Figure 23] FIG. 23 is a flow chart and schematic diagram of a monolithic deposition process for μLEDs on a complementary metal-oxide-semiconductor (CMOS) integrated circuit (IC) wafer.

[0117] [Figure 24] FIG. 24 includes schematic diagrams of a substrate, growth limiting masks, non-coalesced III-nitride ELO layers, and coalesced III-nitride ELO layers used in a scenario for extracting multiple elements from a wing of a III-nitride ELO layer.

[0118] [Figure 25A] 25A, 25B, and 25C are a flow chart and schematic diagram illustrating a fabrication scenario for a VCSEL device using the present invention. [Figure 25B] 25A, 25B, and 25C are a flow chart and schematic diagram illustrating a fabrication scenario for a VCSEL device using the present invention. [Figure 25C] 25A, 25B, and 25C are a flow chart and schematic diagram illustrating a fabrication scenario for a VCSEL device using the present invention.

[0119] [Figure 26] FIG. 26 is a flow chart illustrating a method of fabricating a semiconductor device in accordance with the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0120] In the following description of the preferred embodiment, reference is made to specific embodiments in which the present invention may be practiced. It is to be understood that other embodiments may be utilized and structural changes may be made without departing from the scope of the present invention. (overview)

[0121] The present invention describes a method for fabricating semiconductor devices, such as light emitting devices including μLEDs, edge emitting lasers, and VCSELs, using ELO methods, where the III-nitride semiconductor layers remain on the host substrate without direct contact or having very delicate contact with the host substrate. Because of the reliance on ELO methods, the present invention is readily applicable to foreign substrates such as Si, SiC, sapphire, etc., templates of semiconductor layers, or substrates that include ELO engineered layers and templates.

[0122] The present invention discloses methods for fabricating and transferring μLEDs, including microcavity μLEDs, edge-emitting lasers, and VCSELs, targeting more tolerant designs and better thermal properties for mass production. The present invention can incorporate curved DBR mirrors on either the p-side or n-side of the device, or can incorporate buried DBR designs in addition to planar DBR designs. The present invention encompasses the following approaches:

[0123] 1. μLEDs or microcavity LEDs can be fabricated on wings of III-nitride ELO layers with good crystal quality, detached from the host substrate, and then selectively harvested or transferred onto a carrier such as a display back panel.

[0124] 2. The gain medium of an edge-emitting laser can be fabricated on the wings of the III-nitride ELO layers, the laser device can be separated from the host substrate, and the device can be harvested and mounted on a heat sink carrier or permanently attached to a heat sink.

[0125] 3. One of the cladding layers of a double-clad edge-emitting laser can be epitaxially grown, for example using AlN, and then the entire device structure including the waveguide, quantum wells, p-type and n-type layers can be fabricated. The gain medium can be fabricated on the wings of the III-nitride ELO layers, the device can be detached on the host substrate, the device can be attached to a carrier, and then the device can be polished from the back side at least until exposing the epitaxially grown cladding layers.

[0126] 4. A short cavity VCSEL with a planar DBR mirror can be fabricated, with the aperture location being made on the wings of the III-nitride ELO layer for better crystal quality.

[0127] 5. Long cavity VCSELs can be fabricated with curved DBR mirrors, which reduce diffraction losses by focusing the reflected light back into the aperture. Long cavities can be useful for better thermal management and increased lifetime, output power, and efficiency. Long cavity VCSELs can effectively dissipate heat laterally from the active layer, especially compared to GaN-based VCSELs, which sometimes use dielectric layer DBRs on both sides of the cavity, which do not dissipate heat as well.

[0128] 6. Short or long cavity embedded optical reflector DBR mirror designs can be used for better thermal performance. This design avoids unwanted crystalline quality due to coalescence.

[0129] In the following examples, the process of realizing a μLED and the transfer process are described.

[0130] 1 illustrates the method using schematic diagrams 100A and 100B, which begins with providing a III-nitride based substrate 101, such as a bulk GaN substrate 101.

[0131] In schematic diagram 100A, a growth-limiting mask 102 is formed on or above a III-nitride based substrate 101. Specifically, the growth-limiting mask 102 is placed in contact with the substrate 101 directly, or indirectly, through an intermediate layer grown, such as by MOCVD, that is made from a III-nitride based semiconductor layer or template that is deposited on the substrate 101.

[0132] The growth limiting mask 102 can be formed from an insulator film (e.g., a SiO2 film deposited on a base substrate 101 by, for example, plasma-enhanced chemical vapor deposition (CVD), sputtering, ion beam deposition (IBD), etc.), which is photolithographically patterned using a predetermined optical mask and then etched to include opening areas 103 and no-growth regions 104 (which may or may not be patterned). The present invention can use SiO2, SiN, SiON, tin, etc. as the growth limiting mask 102.

[0133] An epitaxial III-nitride layer 105, such as a GaN-based layer 105, is grown on the GaN substrate 101 and the growth-limiting mask 102 using the ELO method. The growth of the III-nitride ELO layer 105 occurs first in the open areas 103 on the III-nitride-based substrate 101 and then laterally from the open areas 103 over the growth-limiting mask 102. The growth of the III-nitride ELO layer 105 can be stopped or interrupted before the III-nitride ELO layer 105 in adjacent open areas 103 can coalesce on top of the growth-limiting mask 102, and this interrupted growth results in no-growth regions 104 between adjacent III-nitride ELO layers 105. Alternatively, the growth of III-nitride ELO layer 105 may continue and coalesce with neighboring III-nitride ELO layers 105, thereby forming coalesced regions 106 of increased defects in the areas where they meet, as shown in schematic diagram 100B.

[0134] In Figures 2A, 2B, and 2C, schematics 200a, 200b, 200c, 200d, and 200e illustrate how additional III-nitride device layers 107 are deposited on or above the III-nitride ELO layer 105, which may include an active region 107a, a p-type layer 107b, an electron blocking layer (EBL) 107c, and a cladding layer 107d, as well as other layers.

[0135] III-nitride ELO layer 105 includes one or more flat surface regions 108 and layer bend regions 109 at its edges adjacent non-growth regions 104. The width of flat surface region 108 is at least 5 μm, and most preferably 30 μm or greater.

[0136] The light emitting active region 107a of the element 110 is treated with a flat surface region 108, preferably between the aperture area 103 and the edge portion 109. By doing so, the rod of the element 110 will possess an array of twin or nearly identical light emitting apertures along the length of the rod on either side of the aperture area 103, as shown in schematic diagrams 200d and 200e.

[0137] There are many methods for removing the light emitting region from the substrate 101. For example, the present invention can utilize the ELO method to remove the light emitting device. In the present invention, the bond strength between the substrate 101 and the III-nitride ELO layer 105 is weakened by the growth limiting mask 102. In this case, the bond area between the substrate 101 and the III-nitride ELO layer 105 is the opening area 103, and the width of the opening area 103 is narrower than that of the III-nitride ELO layer 105. As a result, the bond area is reduced by the growth limiting mask 102, so that this method is preferred for removing the epitaxial layers 105, 107.

[0138] In one embodiment, the III-nitride ELO layers 105 are allowed to merge with each other, as shown in schematic diagram 100b in FIG. 1. After the III-nitride ELO layers 105 are merged, the subsequent III-nitride device layer 107 is deposited. Light-emitting element apertures are fabricated on the wing regions of the III-nitride ELO layers 105 to separate from the merged regions 106 and the aperture area 103. The III-nitride device layer 107 can then be split using, for example, dry etching or laser scribing, as shown in schematic diagrams 300a, 300b, and 300c in FIG. 3. As shown in schematic diagram 300a in FIG. 3, the separation distance S is the distance between adjacent III-nitride ELO layers 105 after etching a portion above the aperture area 103. Furthermore, the width of the separation region is defined as the separation distance S. The light-emitting apertures mentioned above are located outside the separation region. Preferably, the edge of the light emitting aperture is more than 3 μm from the edge of the isolation region.

[0139] 3, the III-nitride device layer 107 does not show any connection with the host substrate 101, but is still held on the host substrate 101 by van der Waals forces or some weak interference forces between the growth-limiting mask 102 and the III-nitride ELO layer 105. However, to fix the detached III-nitride ELO layer 105, two types of weak connection patterns, namely, auxiliary layer 301 or hook layer 302, can be provided to separate the III-nitride ELO layer 105 and the III-nitride device layer 107 from the host substrate 101, as shown in schematic diagrams 300b and 300c. Exemplary fabrication steps in the present invention are described in further detail below:

[0140] Step 1: A growth-limiting mask 102 with a plurality of stripe-shaped opening areas 103 is directly or indirectly formed on a substrate 101, where the substrate 101 is a Group III nitride-based semiconductor, or the substrate 101 is a heterosubstrate, or the substrate 101 is a prepared template.

[0141] Step 2: Using the growth limiting mask 102, grow multiple epitaxial layers 105, 107 on the substrate 101 such that the growth extends in a direction parallel to the stripe opening areas 103 of the growth limiting mask 102, and the III-nitride ELO layer 105 is non-coalesced in one embodiment. However, a coalesced III-nitride ELO layer 105 can be used in another embodiment.

[0142] Step 3: Fabricate elements 110 by conventional methods on the wing regions of the III-nitride ELO layer 105, primarily the planar surface regions 108, e.g., for VCSELs, optically reflective element structures (DBRs), p-electrodes, n-electrodes, pads, etc. are deposited in place, and similarly for μLEDs, p-electrodes, n-electrodes, pads, etc. are deposited.

[0143] Step 4: Form structures for separating element 110 units, the elements 110 are separated from each other and from the host substrate 101, and if necessary, weak links 301, 302 can be established to secure the separated III-nitride element layers 107.

[0144] In the separation process, the open region of III-nitride ELO layer 105 is referred to as region 1 201, as shown in Figure 2, and the wing region where the wings of neighboring III-nitride ELO layers 105 may or may not meet is referred to as region 2 202. Region 2 202 in the non-coalesced III-nitride ELO layer 105 and III-nitride device layer 107 includes at least bend portion 109.

[0145] Region 1 201 and region 2 202 are etched to expose at least the growth limiting mask 102, as necessary, and the III-nitride ELO layer 105 and III-nitride device layer 107 are either split into individual devices 110 or combined together as a group of devices 110. Weak van der Waals or unknown interaction forces between the growth limiting mask 102 and the III-nitride ELO layer 105 may help prevent the III-nitride device layer 107 from separating from the host substrate 101, even if the III-nitride ELO layer 105 has no contact with the host substrate 101 after etching regions 1 and 2 201, 202, as shown in schematic 300a in FIG. 3. It has been confirmed that the III-nitride ELO layer 105 still remains on the growth limiting mask 102 of the host substrate 101 due to processes such as solvent cleaning, UV ozone exposure, etc. Therefore, cleaning of the III-nitride ELO layer 105 and III-nitride device layer 107 after separation using RIE or other techniques can help remove residues and also prepare the surface for bonding processes or chemical treatments to recover from etch damage, which is a great advantage in reducing process time and cost.

[0146] Alternatively, as shown in schematic diagrams 300b and 300c in FIG. 3, an auxiliary layer 301 or hook layer 302 connecting with the host substrate 101 can fix the III-nitride ELO layer 105 and the III-nitride device layer 107 to the host substrate 101, and these layers 301, 302 can be easily removed ultrasonically or mechanically. The hook layer 302 can preferably be a dielectric layer, for example, SiO2, which can be placed between the devices 110 so that the newly placed dielectric layer is located on the exposed portion of the growth limit mask 102. The strength of the auxiliary layer 301 or hook layer 302 can be controlled by the thickness of the newly placed dielectric layer.

[0147] Many kinds of materials can be used as the hook layer 302, such as SiOx, SiNx, AlOx, SiONx, AlONx, TaOx, ZrOx, AlNx, TiOx, NbOx, etc. (x>0). The hook layer 302 is preferably a transparent layer for the light from the active layer 107a of the element 110, because there will be no need to remove the hook layer 302 after removing the III-nitride ELO layer 105 from the substrate 101. Alternatively, the hook layer 302 can be an insulating layer. If the hook layer 302 is not an insulating layer and the hook layer 302 connects the p-type layer and the n-type layer of the element 110, it will eventually result in a short circuit, in which case the hook layer 302 needs to be removed.

[0148] In addition, AlONx, AlNx, AlOx, SiOx, SiN, and SiON have the effect of passivating the surface of the element 110, especially the etched GaN. Since the hook layer 302 covers the sidewall of the element 110, the selection of these materials is preferable to reduce the leakage current flowing from the sidewall of the element 110. Furthermore, the narrower the size of the element 110, the higher the leakage current, therefore the passivation of the sidewall of the element 110 is very important, especially in the isolation region.

[0149] Furthermore, the strength of the bond between the III-nitride ELO layer 105 and the growth limiting mask 102 can be controlled by varying the thickness of the hook layer 302 .

[0150] Step 5: III-nitride ELO layer 105 and III-nitride device layer 107 are removed from substrate 101 as shown by schematics 400a, 400b, 400c, 400d, 400e, 400f, 400g in Fig. 4. As mentioned above, III-nitride ELO layer 105 and III-nitride device layer 107 are fixed to host substrate 101 as shown by schematics 400a, 400b, 400c, and can be peeled or removed using PDMS (polydimethylsiloxane) elastomer stamp 400d, or vacuum chuck 400e, or by bonding or attaching to a carrier as shown in 400f and 400g.

[0151] For example, front-end completed process elements 110 such as μLEDs 401 and edge-emitting lasers 402 can be mounted on a display back panel or heat sink plate using tools such as PDMS elastomer stamp 400d and vacuum chuck 400e. However, some elements 110 such as VCSELs 403, or dual cladding edge-emitting lasers (not shown), or microcavity μLEDs (not shown) may require further post-processing, such as deposition or polishing of DBR mirrors or external cladding layers, and in such scenarios, III-nitride layers 105, 107 can be bonded to an external carrier such as glass, Si, SiC, Cu, CuW, etc. using spin-on glass resist as shown by 400f, or bonded to an external carrier using metallization or DBR mirrors as shown by 400g.

[0152] If the bond strength is weak (such as with a thin hook layer 302 or without a hook layer 302 ), a commercial adhesive tape (not shown) can be used to remove element 110 .

[0153] Step 6: After lifting off or harvesting the III-nitride devices 110 from the host substrate 101, the devices 110 can be placed in desired locations on a pre-patterned back panel for display applications, e.g., in the case of micro-LEDs. For other types of devices 110, such as double-clad edge-emitting lasers or VCSELs or microcavity LEDs, the interface 111 between the growth-limiting mask 102 and the III-nitride ELO layer 105 is atomically smooth within the nanometer range, so that the interface 111 can be bonded to a conductive DBR or cladding layer by surface activated bonding. The following steps are performed for devices 110 that require further post-processing or post-treatment.

[0154] Step 7: Post-processing.

[0155] In the case of microcavity LED 401, a substrate containing a DBR mirror may be attached using surface activated bonding, as shown at 400g, onto the back surface of element 110, which forms the interface 111 between the III-nitride ELO layer 105 and the growth limiting mask 102.

[0156] For a dual-clad edge-emitting laser 402 requiring a second cladding layer, a carrier (e.g., AlN on Si or SiC) containing an externally deposited cladding layer is attached to the back surface of element 110 as is attached to the DBR surface by surface activated bonding, as shown at 400g.

[0157] Alternatively, the epitaxial cladding layer AlN and laser device 110 structure can be fabricated on the wings of the III-nitride ELO layer 105. Then, after depositing the III-nitride device layer 107, detached from the host substrate 101, onto an external carrier, either by a spin-on glass coating method as shown in 400f or by some other means, the back surface of the device 110 can be polished to expose at least the epitaxial cladding layer.

[0158] In the case of the VCSEL 403, a second optically reflective element (i.e., a DBR mirror) is attached to the rear surface of the device 110. An alternative exists to place the second DBR mirror on the interface 111 at the wing of the III-nitride ELO layer 105.

[0159] For example, an externally prepared DBR mirror substrate can be attached to the back surface of the III-nitride device 110 by surface activated bonding, or diffusion pressure bonding, or by some other means, so that the top and bottom DBR mirrors of the III-nitride device 110 on the wing regions of the III-nitride ELO layer 105 can be used as a resonant cavity for the VCSEL 403. Alternatively, the external DBR can be replaced with an epitaxial light reflecting layer (such as an AlN / GaN, AlInGaN / GaN, or AlN / SiC DBR) to improve the thermal performance of the VCSEL 403. In this case, the external DBR can be grown on a thermally conductive substrate such as Si, SiC, AlN, etc. by MOCVD, laser ablation, and sputtering. Since the DBR is bonded to the III-nitride ELO layer 105 after the growth of the active region 107a of the device layer 107, the VCSEL 403 can be fabricated with a thermally conductive DBR without worrying about any lattice mismatch or internal stress to the active region.

[0160] Additionally, a DBR mirror layer may be deposited directly on the interface 111 of the III-nitride ELO layer 105 .

[0161] Step 8 (optional): Fabricate the n-electrodes in separate designated areas (top and bottom electrode structures need to be deposited after the second DBR layer is in place).

[0162] Step 9 (optional): Separate the rod into elements 110 (can be performed after step 3).

[0163] Step 10 (optional): Mount each element 110 onto a heat sink plate such as SiC, AlN, etc.

[0164] Step 11 (optional): Split the heat sink plate to separate the elements 110.

[0165] These steps are explained in further detail below: Step 1: Create a growth restriction mask

[0166] In one embodiment, III-nitride based layers 105 are grown by ELO on a III-nitride substrate 101, such as an m-plane GaN substrate 101, that is patterned with a growth limiting mask 102 made of SiO2, and these III-nitride ELO layers 105 may or may not coalesce on top of the growth limiting mask 102.

[0167] The growth limiting mask 102 consists of stripes separated by open areas 103, the stripes between which have a width of 1 μm to 20 μm and a spacing of 30 μm to 150 μm. If a non-polar III-nitride substrate 101 is used, the open areas 103 may be <0001> When an axis-oriented, semi-polar (20-21) or (20-2-1) planar III-nitride substrate 101 is used, the aperture area 103 is oriented parallel to [-1014] or [10-14], respectively; other planes may be used as well, with the aperture area 103 oriented in other directions.

[0168] When using the III-nitride substrate 101, the present invention can obtain high quality III-nitride semiconductor layers 105, 107. As a result, the present invention can also easily obtain a device 110 with reduced defect density, such as reduced dislocations and stacking faults.

[0169] Additionally, these techniques can be used with heterosubstrates 101 such as sapphire, SiC, LiAlO2, Si, Ga2O3, etc., with or without buffer or template layers, as long as the substrate 101 allows for the growth of III-nitride ELO layers 105 through the growth-limiting mask 102. Step 2: Grow multiple epitaxial layers onto the substrate using growth-limiting masks

[0170] In step 2, III-nitride device layer 107 is grown by conventional methods on III-nitride ELO layer 105 in planar region 108. In one embodiment, MOCVD is used for epitaxial growth, resulting in islands of III-nitride semiconductor layers including III-nitride ELO layer 105 and III-nitride device layer 107. The islands of III-nitride semiconductor layers are separated from each other because MOCVD growth is stopped before III-nitride ELO layer 105 coalesces. In one embodiment, III-nitride ELO layer 105 is made to coalesce, after which etching is performed to remove unwanted regions 1 and / or 2 201, 202.

[0171] Trimethylgallium (TMGa), trimethylindium (TMIn), and triethylaluminum (TMAl) are used as III-element sources. Ammonia (NH3) is used as the raw gas to provide nitrogen. Hydrogen (H2) and nitrogen (N2) are used as carrier gases for the III-element sources. It is important to include hydrogen in the carrier gas to obtain a smooth surface epilayer.

[0172] Salt and bis(cyclopentadienyl)magnesium (Cp2Mg) are used as n-type and p-type dopants. Pressure settings are typically 50-760 Torr. III-nitride semiconductor layers are generally grown at temperatures ranging from 700-1,250°C.

[0173] For example, the growth parameters include: TMG is 12 sccm, NH3 is 8 slm, carrier gas is 3 slm, SiH4 is 1.0 sccm, and the V / III ratio is about 7,700. (ELO of Limited Area Epitaxy (LAE) III-Nitride Layers)

[0174] In the prior art, some pyramidal hillocks have been observed on the surface of m-plane III-nitride films following growth. See, for example, US Patent Application Publication No. 2017 / 0092810, incorporated herein by reference. Furthermore, wavy surfaces and recessed areas appear on the growth surface, which exacerbates the surface roughness. This is a very serious problem when VCSEL structures are fabricated on the surface. For that reason, it is better to grow epitaxial layers on non-polar and semi-polar substrates, which are well known to be difficult.

[0175] For example, according to some papers, a smooth surface can be obtained by controlling the off-angle (>1 degree) of the growth surface of the substrate and by using N2 carrier gas conditions. However, these are very limited conditions for mass production due to high production costs. Furthermore, GaN substrates have a large variation of off-angle with respect to their origin from their fabrication methods. For example, if the substrate has a large off-angle distribution in-plane, it will have different surface morphology at these points within the wafer. In this case, the yield is reduced by the large off-angle distribution in-plane. Therefore, it is necessary that the technique does not depend on the off-angle distribution in-plane. The present invention solves these problems as described below:

[0176] 1. The growth area is limited by the area of ​​the growth limiting mask 102 from the edge of the substrate 101.

[0177] 2. The substrate 101 is a non-polar or semi-polar III-nitride substrate 101 with an off-angle orientation ranging from -16 degrees to +30 degrees from the m-plane towards the c-plane. Alternatively, a heterosubstrate 101 can be used, on which III-nitride based semiconductor layers are deposited, with the layers having an off-angle orientation ranging from +16 degrees to -30 degrees from the m-plane towards the c-plane.

[0178] 3. The island-shaped III-nitride semiconductor layer consisting of the III-nitride ELO layer 105 and the III-nitride device layer 107 has a long side perpendicular to the a-axis of the III-nitride semiconductor crystal.

[0179] 4. During MOCVD growth, a hydrogen atmosphere can be used.

[0180] The present invention can be used with a hydrogen atmosphere during non-polar and semi-polar growth. Using this condition is preferred because hydrogen can prevent excessive growth at the edges of the open area 103 from occurring during the initial growth stages.

[0181] These results have been obtained under the following growth conditions:

[0182] In one embodiment, the growth pressure ranges from 60 to 760 Torr, but preferably the growth pressure ranges from 100 to 300 Torr to obtain a wide width for the island-like III-nitride semiconductor layer, the growth temperature ranges from 900 to 1,200 degrees Celsius, the V / III ratio ranges from 10 to 30,000, the TMG is 2 to 20 sccm, the NH3 ranges from 0.1 to 10 slm, and the carrier gas is only hydrogen gas or both hydrogen and nitrogen gas. To obtain a smooth surface, the growth conditions of each plane need to be optimized by conventional methods.

[0183] After about 2-8 hours of growth, the III-nitride ELO layer 105 has a thickness of about 8-50 μm and a rod width of about 20-150 μm. Step 3: Fabricate the element

[0184] In step 3, elements 110 are fabricated by conventional methods on the planar surface region 108. A variety of element 110 designs are possible, as illustrated by multiple aperture elements 500a, lasers 500b, edge-emitting lasers 500c, VCSELs 500d, and μLEDs 500e in FIG.

[0185] For μLED 500e, p-pad 601 and n-pad 602 can be fabricated along either the length or width of the wings of III-nitride ELO layer 105, as shown in steps A (epitaxy), B (device fabrication), C (device release), D (bonding / harvesting stamp), and E (removal and n-face preparation) in FIG. 6 .

[0186] For edge-emitting laser 500c, bump formation 701, n-pad 702, and p-pad 703 are defined on the wings of III-nitride ELO layer 105 as shown in steps A (epitaxy), B (laser device fabrication), C (laser device release), D (bonding / harvesting stamp), and E (removal and n-pad preparation) in FIG.

[0187] As shown in steps A (epitaxy), B (VCSEL device fabrication), C (VCSEL device release), D (bonding / harvesting stamp), and E (removal and n-pad preparation) in FIG. 8 for VCSEL 500d, an optical reflector was designed on the designated portion of the wing region of III-nitride ELO layer 105 by defining a current confinement region 801 on the p-GaN side. Later, a contact layer, a current spreading layer 802, e.g., ITO, is deposited on the region with the current confinement opening. An optical reflector DBR mirror 803 is a combination of dielectric layers with different refractive indexes that are placed over the current confinement opening such that the contact layer is between the p-GaN and the DBR. A p-pad 804 and an n-pad 805 are lithographically defined.

[0188] 9, which requires cladding layers 901, 902 (e.g., ITO and AlN) in close proximity to the gain medium 903 and the waveguide 904 to confine the laser mode to the gain medium 903, and may also require additional processing (e.g., bump processing) after removing the III-nitride device layers 107 from the host substrate 101. In such a scenario, a permanent bond or a slightly stronger bond is needed to firmly hold the removed III-nitride device layers 107.

[0189] In a conventional scenario where the processed device wafer is bonded to a carrier wafer, wafer bowing can limit yield, however, in the present invention, bowing may not be the primary cause of yield reduction since the devices 110 are already in a relaxed state since they have been detached from the host substrate 101. The double cladding 901, 902 can be realized in the present invention in several alternative ways.

[0190] 1. An epitaxial cladding layer 902, such as AlN, can be grown on the III-nitride ELO layer 105 before the other III-nitride device layers 107 are grown. In such a scenario, the detached III-nitride device layer 107 must be bonded to a slightly stronger carrier plate 905 to hold the lifted-off III-nitride device layer 107 while performing post-processing such as polishing. By polishing the lifted-off III-nitride device layer 107 on the interface 111 to expose at least the epitaxial cladding, and then bonding to a heat sink carrier plate 906, a thin dual cladding laser device 110, as shown in FIG. 9, can be achieved.

[0191] 2. Either vacuum chuck or PDMS elastomer stamp can be used to pick up the detached III-nitride device layer 107 from the host substrate 101, and then perform surface activated bonding onto the external cladding deposition carrier wafer, as shown in FIG. 10, which illustrates the process cycle of steps A (epitaxy), B (laser device fabrication), C (laser device release), D (bonding / picking stamp) and E (removal and n-pad preparation) for fabricating and releasing III-nitride ELO layer device 110, specifically, externally attached cladding edge-emitting laser. The surface roughness of the interface 111 at the growth limiting mask 102 is sufficiently smooth to facilitate surface activated bonding. Surface activated bonding is very useful to avoid thermal discontinuities and unwanted light scattering. Step 4: Forming a structure to separate element units

[0192] The aim of this step is to prepare the III-nitride device layer 107 for separation from the host substrate 101, which includes elements such as current confinement, current spreading, DBR, p-electrode, and n-electrode. By using a selective etching mask, the III-nitride device layer 107 is separated from the host substrate 101 by etching region 1 201 and region 1 202 to expose at least the growth limiting mask 102.

[0193] Separation or division can be performed by scribing with tools such as diamond-tipped or laser scribers, e.g., RIE (reactive ion etching) or ICP (inductively coupled plasma), but are not limited to these methods are also used to separate element units.

[0194] Alternatively, some methods illustrated in FIG. 3 , such as providing an auxiliary layer 301 or leaving a hook layer 302, can help prevent the detached III-nitride device layer 107 from floating away from the host substrate 101. As explained below, there are several ways to keep the detached III-nitride device layers 107 on the host substrate 101 before transferring them onto a separate carrier. 1. Without hook:

[0195] After the desired devices 110 are fabricated on the wings of the III-nitride ELO layer 105, regions 1 and 2 201, 202 are selectively etched to expose the underlying growth limiting mask 102. It has been found that the detached III-nitride device layer 107 remains on the host substrate 101 even if no protection is provided to secure the detached III-nitride device layer 107. It is hypothesized that the interaction between the growth limiting mask 102 and the III-nitride ELO layer 105 at high temperatures during MOCVD growth may form a weak bond that may prevent the III-nitride device layer 107 from flying away from the host substrate 101. Schematic diagrams of the detached III-nitride device layer 107 after exposing the underlying growth limiting mask 102 by etching the regions 1 and 2 201, 202 in patterns 1 and 2 are shown in schematic diagrams 1100a, 1100b in Fig. 11A, schematic diagrams 1100c, 1100d in Fig. 11B, schematic diagrams 1100e, 1100f in Fig. 11C, and the merged version of the ELO layer 105 is shown in images 1100g, 1100h, 1100i and schematic diagram 1100j in Fig. 11D. The present invention proposes that the detached III-nitride device layer 107 can be easily picked up from its host substrate 101 selectively by either a PDMS elastomer stamp or a vacuum chuck without hooks, and then placed on a target carrier. This is generally discussed in Figures 12A, 12B, 12C, 12D, 12E, 12F, 12G, 12H, and 12I, a schematic diagram 1200a of which is shown in Figure 12A, in which multi-color III-nitride elements 110 from multiple different source wafers 1201 can be selectively picked up by a PDMS elastomeric stamp 1202 and transferred onto a target substrate 1203, such as a patterned back panel.

[0196] Alternatively, this approach can also be used to selectively pick and transfer devices 110, such as VCSELs, edge-emitting lasers, etc., onto a different carrier wafer. 2.Hook type 1:

[0197] It is also possible to ensure that the detached III-nitride device layer 107 remains on the host substrate 101 by modifying the growth limiting mask 102. Region 1 201 connecting the III-nitride ELO layer 105 directly to the host substrate 101 can be modified such that after exposing the growth limiting mask 102 in region 1 202, the weak connection to the host substrate 101 is still intact, as shown in elements 1300a, 1300b, 1300c in FIG. 3.Hook type 2:

[0198] This type of hook is implemented after releasing the III-nitride device layer 107 as described in the "no hook" process. A thin layer of hook layer 302, preferably of the same material as the growth limiting mask 102, is placed over the III-nitride device layer 107 as shown in schematics 1400a, 1400b and images 1400c, 1400d, 1400e, 1400f, 1400g in Figures 14A and 14B. This hook layer 302 prevents the III-nitride device layer 107 from flowing away from the substrate 101. The strength of the hook layer 302 can be controlled by its thickness. 4. Hook Type 3 and Type 4:

[0199] Type 3 and Type 4 hooks are shown in schematic diagrams 1500a, 1500b, 1500c, 1500d in Figure 15, with extensions to Type 2 hooks. Alternatively, the hook layer 302 pattern can be modified in some manner to secure the III-nitride device layer 107. The hook layer 302 must be anchored to at least one side of the III-nitride device layer 107, as shown in schematic diagrams 1500a, 1500b for Type 3, or can be fully anchored to all sides of the III-nitride device layer 107, as shown in schematic diagrams 1500c, 1500d for Type 4. Step 5. The III-nitride device layers are removed from the substrate.

[0200] The auxiliary layer 301 and hook layer 302 are very delicate, so ultrasound or small impacts are sufficient to break the layers 301, 302. Alternatively, chemical treatments can be used to release the layers 301, 302. The III-nitride device layer 107, with or without the auxiliary layer 301 or hook layer 302, can be transferred from its host substrate 101 using one or more of the following methods. 1. Elastomeric stamp (PDMS stamp):

[0201] As shown in schematic 400d in Figure 4, the PDMS stamp is flexible to pick up the released III-nitride device layer 107 from its host substrate 101. As also shown by schematic 1200a in Figure 12A, the III-nitride device layer 107 can be selectively picked up for transfer onto a target substrate, such as a back panel. 2. Vacuum chuck:

[0202] The present invention proposes a new method for picking up detached III-nitride device layers 107 from their host substrate 101. Because the III-nitride device layers 107 have very weak or no connection with the host substrate 101, it is easy to remove these III-nitride device layers 107 using a vacuum-controlled chuck, as shown in schematic diagram 400e in Figure 4. In addition, local repairs can be performed by selectively picking up using the vacuum chuck. 3. Spin-on-glass (SoG) resist:

[0203] Since the detached III-nitride device layers 107 have been pre-processed, their surfaces are smooth. However, small variations in surface elevation within the detached III-nitride device layers 107 can be ignored when a spin-on-glass (SoG) material is used for planarization. It is also useful that a more robust process, such as polishing or resist reflow at high temperature, can be performed on the interface 111 between the growth limiting mask 102 and the III-nitride ELO layer 105 when a SoG material is used to bond the detached III-nitride device layers 107.

[0204] Demonstration of the harvesting of detached III-nitride device layer 107 using SoG is shown as schematics 1210a, 1210b, 1210c, 1210d in FIG. 12B , where schematic 1210a shows the incorporated III-nitride ELO layer 105, schematic 1210b shows the detached III-nitride device layer 107 after removal of regions 1 and 2 201, 202, schematic 1210c shows the SoG on sapphire substrate 1202 attached to the detached III-nitride device layer 107, and schematic 1210d shows the III-nitride device layer 107 attached to the SoG on sapphire substrate 1202.

[0205] In a first step, a merged version of III-nitride ELO layer 105 is grown on the patterned host substrate 101. In a second step, region 1 201 and region 1 202 are removed using a dry etch to expose at least the growth-limiting mask 102. This embodiment does not use an auxiliary layer 301 or a hook layer 302 to hold the detached III-nitride device layer 107 after etching.

[0206] Then, a separate carrier substrate, e.g., sapphire, is coated with SoG material, and the separate carrier substrate with SoG is placed over the detached III-nitride device layer 107 containing host substrate 101 and kept in a high temperature furnace at 300°C-450°C for oxidation. The detached III-nitride device layer 107 is successfully transferred onto the separate carrier substrate with SoG, exposing the III-nitride ELO layer 105 and the interface 111 with the growth limit mask 102. The surface roughness of the interface 111 was found to be less than 1 nm for a scan over 5 μm×5 μm using atomic force microscopy (AFM).

[0207] Additionally, an epitaxial DBR, such as an AlN / GaN DBR pair on SiC, or an epitaxial structure, or a carrier including a deposited cladding layer, such as AlN / SiC or Cu, can be attached to the interface 111 using surface activated bonding. Further details of such a process can be found in step 6. This process can use any material, such as a liquid or gel, which is cured after bonding, such as by heating or UV exposure. 4.Permanent bonding:

[0208] Elements 110 that may require polishing, or DBR mirrors, or outer cladding layers, can be attached directly to the detached III-nitride device layers 107. In this case, SoG materials can be used to attach carriers for the DBR mirrors or outer cladding layers to the III-nitride device layers 107 directly on the host substrate 101 or on a separate carrier. Depending on the type of element 110, a suitable process can be selected.

[0209] The edge-emitting lasers can be permanently bonded from the host substrate 101, through an intermediate layer, onto a heat sink carrier wafer.

[0210] In this step, a heat sink plate made of AlN is prepared. Au-Sn solder is placed on the heat sink plate, the heat sink plate is heated above the melting temperature of the solder, and the detached III-nitride devices 110 on the host substrate 101 are bonded to the heat sink plate using the Au-Sn solder. The devices 110 can be mounted on the heat sink plate in two ways: (1) an n-electrode can be prepared separately on the back surface at the interface 111 of the growth limiting mask 102 and the III-nitride ELO layer 105; or (2) a p-electrode is directly deposited, which results in a junction-down configuration. Step 6-11: Post-processing of the device after separation from the host substrate

[0211] Some devices 110, such as microcavity LEDs, double-clad edge-emitting lasers, or VCSELs, need to utilize the surface of the interface 111 or the n-type layer of the III-nitride device layers 107. Generally, some researchers utilize the back surface of the host substrate 101 by thinning it to a level where there is negligible absorption of the incident light. However, it is preferable to eliminate the unwanted absorption and introduce controllable doping to the n-side of the device 110, which is only possible when the III-nitride device layers 107 are epitaxially controlled. In the present invention, only epitaxially grown III-nitride device layers 107 are used, so there are several advantages.

[0212] 1. Epitaxial doping control is possible for the cavity layer.

[0213] 2. A homogeneous substrate 101 can be used.

[0214] 3. When III-nitride device layers 107 are grown on a foreign substrate 101, either laser lift-off or chemical lift-off must be used to selectively harvest the III-nitride device layers 107, which would induce damage into the cavity layers and limit the design space. However, the inventive approach to removing the III-nitride device layers 107 would not induce damage into the cavity layers or limit the design space.

[0215] 4. Epitaxial layers grown on the wings of III-nitride ELO layer 105 are generally of better quality than epitaxial layers grown directly on the host substrate 101.

[0216] 5. The III-nitride device layer 107 on the n-side of the device 110 has an interface 111 with the growth limiting mask 102, which is crystal orientation independent. For example, when a chemical lift-off such as photoelectrochemical etching (PEC) is used to remove the III-nitride device layer 107 from the substrate 101, the surface roughness of the interface 111 is crystal orientation dependent. In the case of a III-nitride device layer 107 made of c-polar GaN, the interface 111 is N-polar, and it is roughened by a PEC etch with KOH. However, in the present invention, the surface of the interface 111 depends only on the surface of the growth limiting mask 102.

[0217] 6. Even if the surface of interface 111 is not utilized, dry etching, or chemical etching, or polishing can be used on interface 111 to obtain a desired value for surface roughness instead of polishing the entire host substrate 101 from the back side.

[0218] 7. The surface roughness of the interface 111 between the growth-limiting mask 102 and the III-nitride ELO layer 105 is at the nanometer level, e.g., <2 nm, which can even be manipulated by the material and thickness of the growth-limiting mask 102. The surface is smooth enough to employ surface-activated bonding with a DBR or cladding layer.

[0219] 8. Double clad lasers require a cladding layer, e.g., AlN. The higher the aluminum composition or thickness, the more chance there is for cracking, thereby affecting the epitaxial quality of the device 110. Therefore, an epitaxial cladding layer, prepared separately as a template, can be attached directly to the detached edge-emitting laser device 110 after the device 110 is harvested from the host substrate 101.

[0220] Alternatively, the cladding layer may be epitaxially grown directly on the III-nitride ELO layer 105 since the III-nitride ELO layer 105 must be relaxed in a non-coalesced form and more strain-relaxed compared to the host substrate 101, thereby allowing for a larger composition of aluminum or a thicker aluminum layer without cracking.

[0221] The surface roughness of the interface 111 between the growth limiting mask 102 and the III-nitride ELO layer 105 is in the nanometer range (<2 nm), and the surface of the interface 111 is independent of the crystal orientation of the host substrate 101 . The interfaces 111 for various crystal orientations are shown in images 1220a and 1220b and schematic diagram 1220c in Fig. 12C, images 1230a, 1230b, 1230c, and 1230d in Fig. 12D, schematic diagram 1240a in Fig. 12E, images 1250a, 1250b, 1250c, and 1250d in Fig. 12F, images 1260a, 1260b, 1260c, and 1260d in Fig. 12G, images 1270a, 1270b, and 1270c in Fig. 12H, and schematic diagrams 1280a, 1280b, and 1280c in Fig. 12I. Only the surface of the growth limiting mask 102 is replicated on the III-nitride ELO layer 105. The surface morphology of interface 111 can be controlled by the properties of growth-limiting mask 102 and the growth parameters of III-nitride ELO layer 105 .

[0222] 12C, 12D, 12F, 12G, and 12H include images of the surface of interface 111. Specifically, images 1230a, 1230b, 1230c, 1230d, 1250a, 1250b, 1250c, 1250d, 1260a, 1260b, 1260c, 1260d, 1270a, 1270b, 1270c represent experimental results for three different crystal orientations, namely polar c-plane (1000), semi-polar (20-21), and non-polar (10-10), and a thinner growth-limiting mask 102, a thicker growth-limiting mask 102, and a multi-layered growth-limiting mask 102, respectively.

[0223] Images 1220a, 1220b and schematic diagram 1220c in Figure 12C illustrate results obtained by implementing the removal method described in the present invention, in which III-nitride ELO layer 105 and III-nitride device layer 107 are grown from a polar c-plane substrate 101, III-nitride ELO layer 105 and III-nitride device layer 107 are etched to expose growth limiting mask 102, a carrier is attached to III-nitride device layer 107, and III-nitride ELO layer 105 and III-nitride device layer 107 are removed from substrate 101.

[0224] Images 1230a, 1230b, 1230c, 1230d in FIG. 12D show the transferred III-nitride ELO layer 105 consisting of c-plane III-nitride. The growth limiting mask 102 was 1 μm thick SiO2 in this case. Image 1230a in FIG. 12D is the back surface of III-nitride ELO layer 105.

[0225] The surface shown in image 1230a is an N-polar surface, which in principle would become rough when exposed to chemicals such as potassium hydroxide (KOH). For example, when a PEC etching method is used to remove a Ga-polar semiconductor layer, the surface exposed to the chemicals cannot be used to fabricate a DBR mirror. In this method, the as-grown III-nitride ELO layer 105 on the growth limiting mask 102 is used to fabricate a DBR mirror.

[0226] A magnified image of the surface of interface 111 as viewed through a laser microscope is shown in image 1230b, and an image taken using a secondary electron microscope (SEM) is shown in image 1230c. Atomic Force Microscopy (AFM) performed on the surface of interface 111 resulted in image 1230d. The surface roughness was found to be sub-nanometer to 1 or 2 nanometers, which is best for placing the second DBR mirror and completing the resonant cavity of the VCSEL element 110.

[0227] Schematic diagram 1240a in FIG. 12E, images 1250a, 1250b, 1250c, 1250d in FIG. 12F, images 1260a, 1260b, 1260c, 1260d in FIG. 12G, and images 1270a, 1270b, 1270c in FIG. 12H show the results of as-grown III-nitride ELO layers 105 removed from semi-polar 20-21 and non-polar 10-10 substrates 101.

[0228] Images 1250a, 1250b, 1250c, 1250d in Figure 12F are images of III-nitride ELO layer 105 transferred from semi-polar 20-21 planar substrate 101. The growth limiting mask 102 was, in this case, 0.2 μm thick SiO2.

[0229] Image 1250a is the back surface of III-nitride ELO layer 105, more specifically the 20-21 surface.

[0230] A magnified image of the surface of interface 111 as viewed through a laser microscope is shown in image 1250b, and an SEM image is shown in image 1250c. An AFM image performed on one of the back surfaces, specifically the wing region of III-nitride ELO layer 105, is shown in image 1250d. The surface roughness is found to range from sub-nanometer to several nanometers, which is best for placing the second DBR mirror and completing the resonant cavity of VCSEL device 110.

[0231] Similarly, images 1260a, 1260b, 1260c, 1260d in FIG. 12G represent the transferred III-nitride ELO layer 105 consisting of non-polar 10-10 planes. The growth-limiting mask 102 was 1 μm thick SiO2 in this case. Image 1260a is the back surface of III-nitride ELO layer 105, which is the 10-10 surface. In this method, the as-grown III-nitride ELO layer 105 on the growth-limiting mask 102 is used to fabricate the DBR mirror.

[0232] A magnified image of the surface of interface 111 as viewed through a laser microscope is shown in image 1260b, and an SEM image is shown in image 1260c. An AFM image taken on one of the back surfaces, specifically the wing region of III-nitride ELO layer 105, is shown in image 1260d. The surface roughness is found to be sub-nanometer to a few nanometers, which is best for placing the second DBR mirror and completing the resonant cavity of VCSEL device 110.

[0233] Images 1270a, 1270b, 1270c in FIG. 12H represent the transferred III-nitride ELO layer 105 in the non-polar 10-10 plane. The growth limiting mask is in this case a multilayer of 50 nm SiN and 1 μm thick SiO2, with the SiN facing the interface of the ELO surface. Image 1270a is the back surface of III-nitride ELO layer 105. The surface shown in the image is the back surface of the 10-10 surface. In this method, the as-grown III-nitride ELO layer 105 on the growth limiting mask is used to fabricate the DBR mirror.

[0234] A magnified image of the surface of interface 111 as viewed through a laser microscope is shown in image 1270b. An AFM image performed on the surface, particularly the wing region of III-nitride ELO layer 105, is shown in image 1270c. The AFM results in images 1260d and 1270c show the surface roughness of the wings of III-nitride ELO layer 105 when they are on SiO2 and SiN, respectively. On the SiN surface, III-nitride ELO layer 105 has a finer grain structure compared to III-nitride ELO layer 105 on SiO2 surface. The surface roughness is found to be sub-nanometer to several nanometers, which is best for placing the second DBR mirror and completing the resonant cavity of VCSEL device 110.

[0235] As explained above, the growth-limiting mask 102 may affect the back surface. However, controlling the interface 111 when no chemicals are involved is a much simpler method to achieve than chemical or mechanical polishing or PEC etching. Advantageously, the yield at the interface 111 can be improved by using a thicker growth-limiting mask 102 and / or multiple growth-limiting masks 102.

[0236] Alternatively, placing a metal layer on top of the growth limit mask 102 that can withstand the temperatures used to form the III-nitride ELO layer 105 can provide a mirror-like finish to the interface 111 of the removed III-nitride ELO layer 105. The interface 111 at the wing of the removed III-nitride ELO layer 105 can later be used to place a second DBR mirror for the resonant cavity of the VCSEL 110.

[0237] The present invention helps to obtain better crystal quality and smoother surfaces for the DBR mirrors of the resonant cavity of the VCSEL device 110. Furthermore, this approach is independent of crystal orientation, whereas other techniques are either finicky, chemically sensitive, or less tolerant of crystal orientation for mass production.

[0238] The essence of the present invention is to use ELO technique not only to obtain better crystal quality for the device layer 107 and a smooth interface for the DBR mirror of the resonant cavity, but also to control the cavity thickness and recycle the expensive host substrate 101, e.g., III-nitride substrate 101. A second DBR mirror layer, without an intermediate layer, preferably epitaxially grown, conductive and with better thermal performance, can also be attached to the interface 111 by surface activated bonding.

[0239] Case 1: As shown by the rough surface 1280a of the interface 111 in FIG. 12I, a thinner growth-limiting mask 102, for example, 10 nm to 50 nm thick, may deteriorate at higher MOCVD growth temperatures while performing epitaxial lateral overgrowth. In this case, interdiffusion between the III-nitride ELO layer 105 and the substrate 101 or underlying layers below the growth-limiting mask 102 may occur through the growth-limiting mask 102, thus producing non-controllable open areas (pits or small voids) in the growth-limiting mask 102. These non-controllable open areas may be refilled with the predetermined opening areas 103 during the growth of the III-nitride ELO layer 105, resulting in a connecting path between the substrate 101 and the III-nitride ELO layer 105. The epitaxial layers diffused into these non-controllable open areas may result in a rough interface 111. In this case, the yield of having a smooth surface at interface 111 in the wings of removed III-nitride ELO layer 105 may be reduced.

[0240] Case 2: As shown by the smooth surface 1280b of the interface 111 in FIG. 12I, a thicker growth confinement mask 102, for example, 100 nm to 1,000 nm, or more typically 1,000 nm, can limit the degraded regions, such as damaged regions, within the growth confinement mask 102 at higher MOCVD growth temperatures while performing epitaxial lateral overgrowth. Thus, the uncontrollable open areas can be eliminated by increasing the height of the growth confinement mask 102, which translates into a better interface between the III-nitride ELO layer 105 and the growth confinement mask 102.

[0241] Case 3: Alternatively, instead of a thicker growth-limiting mask 102, a combination of multiple growth-limiting masks 102 would also work as case 2, as shown by the smooth surface 1280c at the interface 111 in FIG. 12I. One growth-limiting mask 102, e.g., SiO2, can be used for easy lift-off, and another growth-limiting mask 102, e.g., SiN, can be used for stability at higher temperatures, resulting in a combined growth-limiting mask 102. A combined thickness of 100 nm to 1,000 nm or more, typically 1,000 nm, is preferred. By choosing a thermally stable growth-limiting mask 102 at the interface 111 of the III-nitride ELO layer 105, a better surface can be obtained for the interface 111 on the removed element 110. (a) Depositing the cladding layer

[0242] A low index cladding layer, e.g., AlN, may be deposited on the interface 111 of the growth-limiting mask 102 and the III-nitride ELO layer 105 after the detached III-nitride ELO layer 105 and III-nitride device layer 107 are harvested from the host substrate 101. The schematic 1600a in Fig. 16A shows a detached III-nitride laser device 110 fabricated on a host substrate 101 including the III-nitride device layer 107 deposited on or above the n-type III-nitride ELO layer 105, which includes an active region 107a, a p-type layer 107b, an electron blocking layer (EBL) 107c, and a cladding layer 107d, as well as other layers. The n-contact 1601 and the p-contact 1602. Etched regions 1 and 2 201, 202 are also shown.

[0243] FIG. 16B includes a schematic diagram 1600b of the harvesting process for the element 110 and a schematic diagram 1600c of reattaching the element 110 onto a heat sink carrier substrate 1603. A conventional laser structure can be used in which the cladding layer 107d is epitaxially integrated into the element layer 107, and then a plate that can be used as a heat sink carrier 1603 is attached. Harvesting the element 110 and reattaching it onto the heat sink carrier 1603 adds the advantage of allocating a larger size to the element 110. For example, as shown in FIG. 16B, when reattaching the element 110 onto the carrier plate 1603, a larger space y can be allocated to the element 110, even when the lateral dimension of the element 110 is smaller, which helps improve thermal stability by spreading heat over a larger area and thereby removing heat efficiently.

[0244] Alternatively, instead of picking the elements 110 and placing them on the desired locations, the heat sink carrier 1603 may be attached directly onto a selected number of the picked elements 110 using SoG or permanent bonding methods. (b) Attaching the DBR mirror for the VCSEL element

[0245] The released III-nitride ELO layer 105 or pre-processed VCSEL device 110, represented by schematic diagrams 1700a, 1700b in FIG. 17A, requires a second DBR mirror 1701 to close the resonant cavity 1702 within the VCSEL device 110.

[0246] The present invention allows some freedom for the desired VCSEL design. For better thermal performance, a proposal has been made to use a short-cavity VCSEL, i.e., about 7λ cavity length (λ is the desired optical output wavelength), or a long-wavelength cavity (about 23λ cavity length or more). Since the cavity is epitaxially controlled, the cavity length can be precisely engineered or even polished before the n-type combined III-nitride ELO layer 105 is epitaxially integrated with other III-nitride device layers 107 of the VCSEL design. A typical VCSEL device 110 is fabricated in a front-end process with all the desired elements, such as a current blocking layer 1703, a current spreader 1704, a DBR mirror 1701, a p-pad 1705, and an n-pad 1706. The VCSEL device 110 is then released from the host substrate 101 by removing Region 1 201 and / or Region 1 202.

[0247] As shown in schematic diagrams 1700c, 1700d in FIG. 17B, a detached hooked or unhooked VCSEL element 110 is then picked from the processed VCSEL wafer, as shown in 1700c, using one of the tools described above, and a final DBR mirror 1707 is deposited on the interface 111 of the III-nitride ELO layer 105 and the growth limiting mask 102 to achieve the VCSEL 110, as shown in 1700d.

[0248] Specifically, FIG. 17B includes a schematic diagram 1700c of a harvesting process for the VCSEL device 110 from a processed VCSEL wafer, and a schematic diagram 1700d of adding a second type of DBR mirror 1707 to the device 110 using a DBR carrier substrate 1708.

[0249] In choosing the second type of DBR mirror, there may be several options. 1. Epitaxial DBR:

[0250] This is shown as 1700e in Figure 17C. An epitaxial DBR pair 1707, such as AlN / GaN, AlInN / GaN, Al(Ga)N / GaN, or AlInGaN / AlInGaN, is prepared on a carrier substrate 1708, such as Si, SiC, sapphire, or GaN, and attached to the interface 111 of the detached III-nitride ELO layer 105 of the VCSEL 110, either using surface activated bonding or through some intermediate layer. Preferably, surface activated bonding works because the surface roughness of the interface 111 is in the nanometer range. The preparation of epitaxial DBR vs. 1707 included the following:

[0251] (a) An AlN / GaN quarter-wave thick layer 1707 can be epitaxially grown on a SiC, Si, or sapphire carrier substrate 1708, which is then attached to the interface 111 of the detached III-nitride ELO layer 105 of the VCSEL 110 by surface activated bonding. Surface activated bonding is preferred because it avoids unwanted light scattering and thermal discontinuities are minimized.

[0252] (b) As shown in schematic diagrams 1700f, 1700g, 1700h in FIG. 17D, a GaN or sapphire substrate 1709 is provided and a sacrificial layer 1710 is grown thereon, the sacrificial layer 1710 comprising an alloy of In, Ga, and N. Then, n pairs of AlN / GaN epitaxial DBR mirror layers 1707 are grown on the sacrificial layer 1710. Afterwards, the DBR mirror 1707 comprising n pairs of AlN / GaN layers is attached to a thermally conductive substrate 1708 by removing the sacrificial layer 1710, such as by PEC etching or electrochemical etching. Then, the newly established template substrate 1708 comprising the DBR mirror layer 1707 is attached to the interface 111 of the detached III-nitride ELO layer 105 of the VCSEL device 110. 2. Nanoporous template:

[0253] This is shown in the schematic diagrams 1700c, 1700a, 1700i of Fig. 17E. A highly doped GaN layer 1711 is grown on a foreign substrate 1712 such as SiC, Si, or sapphire, porosity is introduced into the highly doped GaN layer 1711, which effectively reduces the refractive index, and then the layer 1711 is attached by a carrier 1712 to the interface 111 of the separated III-nitride ELO layer 105 and the III-nitride device layer 107 of the VCSEL device 110. For better uniformity of the porosity on the layer 1711, some trenches 1713 are recommended for the layer 1711 so that uniform porosity can be achieved over the entire layer 1711.

[0254] Alternatively, a dielectric DBR layer, such as a pair of SiO2 / Nb2O5 layers, can be deposited. Typically, ten pairs can be deposited on the interface 111 of the decoupled III-nitride ELO layer 105 to realize the VCSEL device 110. Preferably, a thermally conductive DBR layer is epitaxially grown on a thermally conductive carrier and then the surface is bonded to the interface 111 without any intermediate layer.

[0255] For GaN VCSELs, it is well known that it is difficult to grow epitaxial DBR and active layers successively on a substrate by MOCVD. The difference in lattice mismatch and thermal expansion coefficients prevent growing high crystalline quality layers. The laser characteristics obtained through conventional processes are not very good. Therefore, the yield of this type of GaN VCSEL is extremely low.

[0256] In the present invention, the device 110 including the active layer, the epitaxial DBR with the substrate 101, and the heat sink can be prepared independently. These elements can then be bonded together using a surface activation process or the like. By doing so, the present invention can avoid the above problems and obtain a high-yield mass production process.

[0257] Generally, surface activated bonding and other bonding methods are used for wafer-based bonding because they need to bond large areas. In this case, the elements 110 are very small, so the bond failure caused by the twisting or bending of the wafer can be prevented, which increases the yield. (The element is mounted on a heat sink plate)

[0258] After step 5, the separated / isolated elements 110 can be lifted off and placed at the desired location using the approach described above, i.e., (1) PDMS stamp, (2) vacuum chuck, (3) carrier plate structure including SoG material used for surface bonding, and (4) permanent bonding, instead of crowding the elements 110 together.

[0259] For example, as shown in schematic diagrams 1800a, 1800b, 1800c, 1800d in Figure 18, device source wafers 1800a, 1800c including devices 110 are attached to selectively patterned heat sink plates 1800b, 1800d, where schematic diagram 1800a is a fully featured device 110 source wafer and schematic diagram 1800c is a device 110 source wafer with some devices 110 removed. The devices 110 initially have a lateral dimension x that is smaller than the wings of the III-nitride ELO layer 105 and therefore can be distributed over a larger space on the heat sink plate shown in schematic diagrams 1800b, 1800d with thickness h, which helps to spread heat more efficiently.

[0260] Moreover, another advantage is that since the devices 110 on the host substrate 101 are released from the host substrate 101, they possess less stress than devices fabricated directly on the host substrate. Therefore, in the present invention, after releasing the III-nitride ELO layer 105 and the III-nitride device layer 107, the DBR template, or cladding template, or heat sink can be attached in wafer scale. Wafer bow tolerance can be tolerated in the way the present invention translates the device 110 out of its host substrate 101, and thus the yield can be improved in industrial practice. Use of a Vacuum Chuck to Harvest III-Nitride ELO Device Layers and Localized Repair Methods

[0261] The present invention provides a solution to the problem of mass transfer of smaller light-emitting apertures (alternatively called emissive inorganic pixels) when the targeted size falls below 50 μm. The VCSELs or μLEDs 110 fabricated on the wings of the III-nitride ELO layer 105 can be removed as described above. In particular, these elements 110 preferably have a larger wing area of ​​the III-nitride ELO layer 105 and a smaller open area resulting from the etching area 1 201, i.e. the ratio between the wing area and the open area should be greater than 1, more preferably 5-10, in particular the open area should be about 1-5 μm. Thus, the elements 110 can be more easily removed from the substrate 101 and transferred in an easy manner to an external carrier or processed in further steps.

[0262] As shown in schematic diagrams 1900a and 1900b in FIG. 19A and schematic diagrams 1910a, 1910b, 1910c, 1910d, 1910e in FIG. 19B, the vacuum chuck 1901 is a combination of at least two plates 1902, 1903, where the bottom plate 1903 has a vacuum hole with a dimension d1 1904 slightly smaller than the element 110 to be lifted off from the host substrate 101, and the top plate 1902 has a larger vacuum hole 1905 that can be controlled either electrically or magnetically to physically extract the detached element 110 out of the host substrate 101.

[0263] Vacuum chuck 1901 is placed over the detached device 110 on the host substrate 101 and the device 110 is extracted out of the host substrate 101 by turning on the vacuum and opening vacuum holes 1905 .

[0264] As shown in schematic diagrams 1910a and 1910b in FIG. 19B, the element 110 contained by the vacuum chuck 1901 is either placed on a processed carrier plate or directly attached onto a display rear panel, or a DBR template, or a cladding template, or a heat sink.

[0265] In FIG. 19C, schematic view 1920a is a side view of vacuum check 1901, schematic view 1920b is a top view of vacuum chuck 1901, schematic view 1920c is a top view of enlarged portion 1921 of vacuum chuck 1901, and schematic view 1920d is a plan view of enlarged portion 1921 of vacuum chuck 1901.

[0266] As shown in schematic diagrams 1930a, 1930b, 1930c, 1930d, 1930e in Fig. 19D, a unique application of the present invention when using a vacuum chuck 1901 is realized when a defective element 110 requires replacement due to breakage. As shown in schematic diagram 1930a, a selective hole containing mask 1931 is attached to the bottom plate 1903 as shown in schematic diagram 1930b, the defective element 110 is harvested from the host substrate 101 as shown in schematic diagram 1930c, and then a non-defective element 110 is reattached to the defective location on the display panel as shown in schematic diagram 1930d, resulting in a local pixel repair as shown in schematic diagram 1930e. (Definition of terms) (III-nitride substrate)

[0267] The III-nitride based substrate 101 may comprise any type of III-nitride based substrate, so long as the III-nitride based substrate 101 allows for the growth of the III-nitride semiconductor layers 105, 107 through the growth-limiting mask 102, and may comprise any GaN substrate 101 sliced ​​from a bulk GaN and AlN crystal substrate 101, for example, on the {0001}, {11-22}, {1-100}, {20-21}, {20-2-1}, {10-11}, {10-1-1} plane, etc., or other plane. (Hetero Substrate)

[0268] Furthermore, the present invention can also use a heterosubstrate 101. For example, a GaN template or other III-nitride based semiconductor layer can be grown on a heterosubstrate 101 such as sapphire, Si, GaAs, SiC, Ga2O3, etc., prior to deposition of a growth limiting mask 102. The GaN template or other III-nitride based semiconductor layer is typically grown on the heterosubstrate 101 to a thickness of about 2-6 μm, and then the growth limiting mask 102 is placed on the GaN template or other III-nitride based semiconductor layer. (Growth restriction mask)

[0269] The growth limiting mask 102 comprises a dielectric layer such as SiO2, SiN, SiON, Al2O3, AlN, AlON, MgF, ZrO2, TiN, or a refractory or noble metal such as W, Mo, Ta, Nb, Rh, Ir, Ru, Os, Pt, etc. The growth limiting mask 102 can be a layered structure selected from the above materials. It can also be a multi-stacking layer structure selected from the above materials.

[0270] In one embodiment, the thickness of the growth limiting mask 102 is about 0.05-3 μm. The width of the mask 102 is preferably greater than 20 μm, and more preferably the width is greater than 40 μm. The growth limiting mask 102 is deposited by, but not limited to, sputtering, e-beam evaporation, plasma enhanced chemical vapor deposition (PECVD), ion beam deposition (IBD), and the like.

[0271] On an m-plane freestanding GaN substrate 101, a growth limiting mask 102 comprises a plurality of open areas 103, which are periodically arranged in a first direction parallel to the 11-20 direction of the substrate 101 and a second direction parallel to the 0001 direction of the substrate 101, with intervals extending in the second direction. The length of the open areas 103 is, for example, 200-35,000 μm, the width is, for example, 2-180 μm, and the intervals between the open areas 103 are, for example, 20-180 μm. The width of the open areas 103 is typically constant in the second direction, but may be varied in the second direction as necessary.

[0272] On the c-plane freestanding GaN substrate 101 , the open areas 103 are arranged in a first direction parallel to the 11-20 direction of the substrate 101 and in a second direction parallel to the 1-100 direction of the substrate 101 .

[0273] On a semi-polar (20-21) or (20-2-1) GaN substrate 101, the open areas 103 are oriented parallel to [-1014] and [10-14], respectively.

[0274] Alternatively, a heterosubstrate 101 can be used. When a c-plane GaN template is grown on a c-plane sapphire substrate 101, the open area 103 is in the same orientation as a free-standing c-plane GaN substrate, and when an m-plane GaN template is grown on a m-plane sapphire substrate 101, the open area 103 is in the same orientation as a free-standing m-plane GaN substrate. By doing this, the m-plane cleavage plane can be used to split the rod of the device 110 with the c-plane GaN template, and the c-plane cleavage plane can be used to split the rod of the device 110 with the m-plane GaN template, which is much preferred. (III-nitride semiconductor layer)

[0275] III-nitride ELO layer 105 and III-nitride semiconductor device layer 107 can include In, Al, and / or B as well as other impurities such as Mg, Si, Zn, O, C, H, and the like.

[0276] The III-nitride device layer 107 generally comprises more than two layers, including at least one of an n-type layer, an undoped layer, and a p-type layer. The III-nitride device layer 107 specifically comprises a GaN layer, an AlGaN layer, an AlGaInN layer, an InGaN layer, etc. When the device has multiple III-nitride device layers 107, the distance between adjacent island-like III-nitride device layers 107 is generally 30 μm or less, preferably 10 μm or less, but is not limited to these figures. (Advantages of epitaxial lateral overgrowth)

[0277] The crystallinity of the III-nitride ELO layer 105 from the stripe openings 103 of the growth-limiting mask 102 that is grown on the growth-limiting mask 102 is very high. As a result, the III-nitride device layer 107 also has high crystallinity quality.

[0278] Furthermore, two advantages may be obtained using III-nitride based substrate 101. One advantage is that high quality III-nitride device layers 107, such as with very low defect densities, may be obtained on the wings of III-nitride ELO layer 105, as compared to the use of a sapphire substrate.

[0279] The advantage of using heterosubstrates 101 such as sapphire (m-plane, c-plane), LiAlO2, SiC, Si, etc. for the growth of epilayers 105, 107 is that these substrates are low-cost substrates, which is an important advantage for mass production.

[0280] In terms of the quality of the device 110, the use of a free-standing III-nitride based substrate 101 is more preferable due to the reasons mentioned above. On the other hand, the use of a hetero-substrate 101 makes it cheaper and more scalable.

[0281] Also, because the growth-limiting mask 102 and the III-nitride ELO layer 105 are not chemically bonded, the stress in the III-nitride ELO layer 105 can be relieved by sliding induced at the interface between the growth-limiting mask 102 and the III-nitride ELO layer 105. (flat surface area)

[0282] The flat surface regions 108 are between the layer bend regions 109. Furthermore, the flat surface regions 108 are within the stripe regions of the growth limiting mask 102.

[0283] Fabrication of the semiconductor device 110 is primarily performed on the planar surface region 108. The width of the planar surface region 108 is preferably at least 5 μm, more preferably 10 μm or more. The planar surface region 108 has a high uniformity of thickness for each of the semiconductor layers 105, 107. (layer bending area)

[0284] 2B illustrates the layer bending region 109. If the layer bending region 109, including the active layer 107a, remains in the device 110, some of the light emitted from the active layer 107a will be reabsorbed. As a result, it is preferable to remove at least a portion of the active layer 107a in the layer bending region 109 by etching.

[0285] If the layer bending region 109 including the active layer 107a remains in the VCSEL device 110, the laser mode may be influenced by the layer bending region 109 due to the low refractive index (e.g., InGaN layer). As a result, it is preferable to remove at least a portion of the active layer 107a in the layer bending region 109 by etching.

[0286] The light emitting region formed by active layer 107a is the current injection region. In the case of a VCSEL 110, the light emitting region is a resonant cavity opening structure that is either vertically above the p-side of the device 110 or vertically below the n-side of the device (or vice versa).

[0287] For VCSEL device 110, the edge of the light emitting region should be at least 1 μm or more, and more preferably 5 μm, from the edge of layer bending region 109.

[0288] From another perspective, the epitaxial layer in the flat surface region 108 excluding the opening area 103 has a lower defect density than the epitaxial layer in the opening area 103. Therefore, it is more preferable that the opening structure be formed in the flat surface region 108 (including on the wing regions of the III-nitride ELO layer 105). (Semiconductor element)

[0289] The semiconductor element 110 may be, for example, but is not limited to, a Schottky diode, a light emitting diode, a semiconductor laser, a photodiode, a transistor, etc. The present invention is particularly useful for a VCSEL element 110. The present invention is particularly useful for a semiconductor laser element 110 that requires a smooth region for cavity formation. (Heat sink plate)

[0290] As mentioned above, the removed element 110 may be transferred to a heat sink plate, which may be AlN, SiC, Si, Cu, CuW, etc. Solder may be used to attach the element 110 onto the heat sink, which may be Au-Sn, Su-Ag-Cu, Ag paste, etc., that is disposed on the heat sink plate. The n-electrode or p-electrode is then bonded to the solder. The element 110 may also be flip-chip bonded to the heat sink plate.

[0291] When the element 110 is bonded to a heat sink plate, the size of the heat sink plate does not matter and can be designed as desired. (DBR mirror)

[0292] The light reflecting layer described in this invention is also called DBR mirror, which can be composed of dielectric or epitaxial layers. The dielectric DBR mirror is composed of, for example, a semiconductor multilayer film or a dielectric multilayer film. Examples of dielectric materials include, but are not limited to, Si, Mg, Al, Hf, Nb, Zr, Sc, Ta, Ga, Zn, Y, B, Ti, etc., or nitrides of these elements, such as SiN, AlN, AlGaN, GaN, BN, etc., or oxides of these elements, such as SiOx, TiOx, NbOx, ZrOx, TaOx, ZnOx, AlOx, HfOx, SiNx, AlNx, etc. The light reflecting layer can be obtained by alternately stacking one or more dielectric materials with different refractive indices. Materials with different refractive indices, different thicknesses, and various numbers of material layers can be selected to obtain the desired light reflectance. The thickness of each film of the dielectric layer can be adjusted depending on the material and the oscillation wavelength of the light emitted from the resonant cavity.

[0293] Preferably, the thicknesses of these layers are odd multiples of a quarter of the oscillation wavelength. The reflectivities of the two optically reflective elements (one on the top and one on the bottom) are different. These two optically reflective elements, including the active layer, the n-GaN layer, and a portion of the p-GaN layer, are collectively referred to as the resonant cavity. In general, the reflectivity of the light-emitting side of the optically reflective layer of the device is less than the other side. One of the DBR mirrors can be dielectric and the other can be an epitaxial DBR.

[0294] The epitaxial DBR mirror may comprise an AlN / GaN DBR mirror layer epitaxially integrated on a substrate. Additionally, the epitaxial DBR mirror may comprise (Ga)N / GaN or AlInN / GaN. The substrate may comprise SiC, Si, GaN, or sapphire. (Current Confinement Region)

[0295] The resonant cavity can be created using a current confinement region by shaping it thin enough to confine the current flowing through the VCSEL device 110 to within the diameter of the aperture of the resonant cavity. This can be achieved by making the layer around the aperture where the current injection occurs more conductive than the neighboring regions. For example, using reactive ion etching, or plasma etching, or a dielectric mask, the neighboring regions of the aperture can be made resistive. Alternative Embodiments

[0296] The following describes alternative embodiments of the present invention. (First embodiment)

[0297] A III-nitride based semiconductor device 110 and a method for manufacturing the device 110 are described according to a first embodiment.

[0298] In a first embodiment, as shown by elements 100a and 100b in FIG. 1, a base or host substrate 101 is first provided, and a growth limiting mask 102 having a plurality of striped opening areas 103 is formed on the substrate 101.

[0299] In this embodiment, the III-nitride ELO layers 105 do not coalesce and form island-like III-nitride semiconductor layers, as shown in schematic diagram 100a in FIG. 1, or the III-nitride ELO layers 105 are allowed to coalesce and / or contact neighboring III-nitride ELO layers 105 to form a base layer, as shown in schematic diagram 100b in FIG. 1. Then, device layers 107, such as multi-quantum well structures, waveguides, electron blocking layers, p-GaN, etc., are grown on the above III-nitride ELO layers 105. Devices 110, such as μLEDs, microcavity LEDs, edge-emitting lasers, and VCSELs, are fabricated on the wing regions of the III-nitride ELO layers 105. For example, at least one of the DBR mirrors of the VCSEL element 110 is fabricated in a front-end processing step; similarly, for the edge-emitting laser, the front-end processes (such as fabricating the bumps, p-pads and n-pads, and their release layers, etc.) are all defined.

[0300] III-nitride ELO layer 105 and III-nitride device layer 107 are then separated into individual elements 110 or groups of elements 110 by etching region 1 201 and region 1 202 to expose the underlying growth limiting mask 102, as shown in Figures 2A and 3. At this stage, III-nitride ELO layer 105 and III-nitride device layer 107 have no connections to host substrate 101. The only forces that may be holding III-nitride ELO layer 105 and III-nitride device layer 107 on host substrate 101 are weak interaction forces (van der Waals forces) at interface 111 between growth limiting mask 102 and III-nitride ELO layer 105.

[0301] The III-nitride ELO layer 105 and III-nitride device layer 107 are then transferred onto a carrier using tools such as a PDMS elastomer stamp, a vacuum chuck, SoG material bonding, bonding through an interlayer, surface activated bonding, etc. After lifting off the III-nitride ELO layer 105 and III-nitride device layer 107 from the host substrate 101, further processing may be required or the devices 110 may be directly transferred for the targeted application.

[0302] Several devices 110, such as double cladding lasers or hybrid DBR mirror VCSELs, are feasible using the present invention. Experimental observations of the rear surface of the III-nitride ELO layer 105 at the interface 111 between the growth limiting mask 102 and the III-nitride ELO layer 105 show surface roughness in the nanometer range (<2 nm), regardless of crystal orientation. Thus, surface activated bonding of an epitaxial DBR (AlN / GaN) onto a SiC substrate can be used to realize a hybrid DBR VCSEL device 110, or deposition of an external low index cladding layer such as AlN can be used to realize a double clad laser device 110. The advantage of not introducing an additional intermediate layer between the interface 111 and the DBR or cladding layer is to improve thermal performance and avoid unwanted light scattering.

[0303] The present invention is advantageous for obtaining a smooth interface 111 for fabricating the DBR mirror of the VCSEL device 110. Common approaches such as thinning the substrate or removing semiconductor layers by PEC etching are laborious and crystal orientation dependent. However, the present approach is robust and crystal plane independent. Moreover, the substrate 101 used to produce the device layer 107 can be recycled several times for similar fabrication. The present approach provides not only a smooth interface 111 for the DBR mirror, but also a good crystal quality device 110, since the present invention proposes to fabricate the resonant cavity completely on the wing region of the III-nitride ELO layer 105. Preferably, this does not include the opening area 103 of the growth limiting mask 102 where the III-nitride ELO layer 105 is grown on the substrate 101. Second embodiment

[0304] The second embodiment uses a hook process to remove the III-nitride ELO layer 105, which comprises an auxiliary layer 301 or hook layer 302 as shown in FIG. 3, which temporarily holds the III-nitride ELO layer 105 and releases them onto a temporary carrier substrate, a permanent bonding substrate, a CMOS panel, a TFT back panel, etc. Using the ELO method, larger wings can be obtained for the III-nitride ELO layer 105, and some elements 110, such as VCSELs, LEDs, power electronic elements, etc., can be fabricated on these wings. By doing so, these elements 110 have reduced defects compared to elements fabricated from conventional substrates.

[0305] In the first part of the hook process, using either separate or combined III-nitride ELO layers 105 as shown at 100a and 100b in FIG. 1, respectively, the element 110 is fabricated on the III-nitride ELO layer 105. The III-nitride ELO layer 105 is masked with a SiO2 layer deposited by, for example, chemical vapor deposition, atomic layer deposition, or sputtering. The mask can be patterned in such a way as to extract the useful tips on the wings of the III-nitride ELO layer 105 by placing one of two different types of hook designs.

[0306] For example, in a type 1 hook pattern, region 1 202 is etched through the growth limiting mask 102, and the remaining help layer 301 acts as a hook and holds the element 110, as shown in schematic diagram 300b in FIG.

[0307] In another example, in a type 2 hook pattern, a dielectric layer is deposited as hook layer 302, as shown in schematic diagram 300c in Figure 3, which also allows for other types of hook patterns, for example, type 3 and type 4 hook patterns, as shown in schematic diagrams 1500a, 1500b, 1500c, 1500d in Figure 15. This process may be performed after front-end processes are performed on separate or combined III-nitride ELO layer 105 and III-nitride device layer 107.

[0308] For example, for small size LED device 110, device 110 fabricated on the wings of III-nitride ELO layer 105 includes p-electrodes and n-electrodes on the top side of III-nitride device layer 107. The mask used to etch III-nitride ELO layer 105 and III-nitride device layer 107 on host substrate 101 can also act as a passivation layer to protect against electrical leakage or improve efficiency for small size LED device 110.

[0309] Using a mask (typically SiO2), the desired chip dimensions are etched to expose at least the growth-limiting mask 102. Then, in a type-2 hook pattern, the hook layer 302 is placed to contact the exposed growth-limiting mask 102. Alternatively, the hook layer 302 can contact the host substrate 101 at the open ELO window. The process of etching the III-nitride ELO layer 105 and III-nitride device layer 107 to expose the underlying growth-limiting mask 102 can also be done in two steps, e.g., for thicker III-nitride semiconductor layers 105, 107, e.g., >10 μm, a hard mask is first used to etch slightly above the growth-limiting mask 102 so that the underlying growth-limiting mask 102 is not exposed, and then in a second step, a soft layer such as photoresist is used to expose at least the underlying growth-limiting mask 102. This configuration leads to one of the hook designs, labeled as pattern 1 in type-2 hook. An alternative method may expose the underlying growth-limiting mask without the two etching steps.

[0310] In type 2 hooks, after exposing the underlying growth-limiting mask 102, the etched layers 105, 107 do not retain support from the host substrate 101 as shown in FIG. 3, but they are sandwiched between the growth-limiting mask 102 and the etched open ELO window of the mask. At this stage, the elements 110 remain on the host substrate 101. Experimentally, it has been observed that all of the elements 110 remain on the growth-limiting mask 102 after exposing the growth-limiting mask 102, as shown in the optical microscope image 1100g in FIG. 11D. The III-nitride semiconductor layers 105, 107 at this point are sandwiched between the growth-limiting mask 102 and the mask used to expose the growth-limiting mask 102. This is a unique configuration that is only achievable using the approach of the present invention. Although the initial growth-limiting mask 102 for the ELO process was prepared at a low temperature of about 300° C. during the formation of the III-nitride ELO layer 105 and the III-nitride device layer 107 in the MOCVD reaction chamber, the growth-limiting mask 102 was exposed to a temperature higher than about 1,200° C., which is believed to have promoted a weaker bond, e.g., van der Waals forces, between the growth-limiting mask 102 and the back surface of the III-nitride ELO layer 105.

[0311] Alternatively, further fixation processes may be possible by placing a thin layer known as a chip fixation layer (preferably a dielectric SiO2) with a thickness of 10 nm to 300 nm on top of the etched mask, as shown in both Figures 3 and 15. Several hook designs, known as Type 2, Type 3, and Type 4, may be possible by selectively opening the chip fixation layer and etch mask combination. Schematic diagrams 1400a, 1400b in Figure 14A and images 1400c, 1400d, 1400e, 1400f, 1400g in Figure 14B illustrate an experimentally demonstrated Type 2 hook design, where the chip fixation layer protects the chip with stripes that extend across the width of the chip.

[0312] Now a carrier wafer, which can be temporary or permanent, can be attached to the chip. Using ultrasonic, mechanical, or thermal treatment, the only supporting hook layer can be destroyed and the chip can be transferred onto the carrier wafer.

[0313] This unique process is not only useful in solving the current microLED mass transfer problem, but also helps realize the unique designs of VCSELs and double-clad edge-emitting Fabry-Perot lasers. (VCSEL: n-side curved mirror on epitaxial layer without substrate)

[0314] After placing the chip fixing layer, the device 110 is transferred onto a temporary wafer using crystal bonding, or electronic solder, or temporary attachment layer, as shown by schematic diagrams 1210a, 1210b, 1210c, 1210d in FIG. 12B. After transfer onto the temporary carrier wafer, the back side of the device 110 is patterned in a concave manner by reflowing resist, and a curved mirror will be fabricated on the epitaxial layers before the device 110 is transferred back onto a permanently bonded wafer for packaging, and light will be extracted from the p-side of the device 110. Using this process to remove the substrate 101, light emission from the p-side of the device 110 is possible for the VCSEL device 110, while with other processes such as PEC etching or electrochemical etching, an n-side curved mirror on the removed epitaxial layers may not be possible. (Double-clad Fabry-Perot (FP) laser)

[0315] Different from dividing the III-nitride ELO layer 105 and the III-nitride device layer 107 into small size LED or VCSEL device 110, the FP laser device 110 can be designed on the wing region of the III-nitride layer 105 by placing a ridge structure and a confinement layer on the III-nitride device layer 107 on the wing region. For example, an ITO layer is placed as one cladding layer from the outside before removing the laser device 110 by any of the hooking techniques discussed above, and after removing, another cladding layer such as aluminum nitride (AlN) is placed from the outside. This process is more controllable to achieve the double clad FP laser device 110 because the thickness of the wing region of the III-nitride ELO layer 105 can be epitaxially controlled for very precise design of the long wavelength laser device 110, and the precisely designed epitaxial layers 105, 107 for the laser device 110 are removed from the growth limit mask 102. The two cladding layers are applied externally using, for example, sputtering, e-beam, electron cyclotron resonance (ECR), chemical vapor deposition (CVD), etc. Alternatively, if the back surface of the wing region of III-nitride ELO layer 105 is not necessarily flat, the thickness of the n-GaN layer in III-nitride device layer 107 can be etched back to a desired value after transferring FP laser device 110 onto a carrier substrate before applying the second cladding layer, even if it exceeds the desired dimension. In this configuration, a junction-down or sandwich cooling technique can be provided on final device 110 for better thermal management. (Third embodiment)

[0316] As shown in schematic diagrams 2000a, 2000b, 2000c, 2000d in FIG. 20, this embodiment describes a method of removing detached elements 110 from their host substrate 101 using a PDMS stamp 2001. Since the detached III-nitride ELO layer 105 has no connection with the host substrate 101, or even if there is a very weak connection or hook layer 302 created in the open area resulting from etching of region 1 201, this connection can be easily broken by the movement of the PDMS stamp 2001. The PDMS stamp 2001 can be designed to pick up the detached III-nitride ELO layer 105 and III-nitride element layer 107 together, or even to pick up some of them selectively. Adhesive and stamping method:

[0317] 1. A rigid carrier 2002, such as glass or Si, is attached to a PDMS stamp 2001 to collect several released elements 110.

[0318] 2. In addition to the flat PDMS stamp 2001, a PDMS tooth structure 2003 may also be used. The PDMS tooth structure 2003 may be used to selectively pick up the detached elements 110 off the host substrate 101. For example, it is possible to spin coat uncured PDMS material onto glass and then bring the tooth structure 2003 into contact with the uncured PDMS 2004 such that a small amount of uncured PDMS 2004 will be transferred onto the PDMS tooth structure 2003. The PDMS tooth structure 2003 with the uncured PDMS 2004 may then be brought into contact with the detached elements 110 and the uncured PDMS 2004 may be allowed to harden. After hardening, the selected elements 110 may be removed from the host substrate 101. (Fourth embodiment)

[0319] The fourth embodiment is about picking up the detached III-nitride ELO layer 105 and III-nitride device layer 107 out of the host substrate 101 using a vacuum chuck 1901, which is designed to include at least two plates 1902, 1903 as shown in Figure 19A. Plate 1903 contains finite size holes, which are smaller than the size of the removed device 110, and plate 1902 has larger size vacuum holes 1905 to control the retention process. The vacuum holes 1905 can be controlled by mechanical, electromagnetic, or hydraulic methods.

[0320] 19D, the vacuum chuck 1901 may be used to harvest only selected elements 110 by closing unnecessary vacuum holes 1904 on the plate 1903. The vacuum chuck 1901 with the removed elements 110 may also be used for post-processing. Fifth embodiment

[0321] The fifth embodiment is about harvesting the detached III-nitride ELO layer 105 and III-nitride device layer 107 from the host substrate 101 using low temperature oxidation of the SoG material. The SoG material is placed on a glass or Si substrate, the surfaces are placed in physical contact at room temperature, and then annealed with applied pressure at 425° C. The detached III-nitride ELO layer 105 and III-nitride device layer 107 oxidize, form a bond with the SoG material, and self-detach from the host substrate 101. Alternatively, ultrasound or small impacts can detach the III-nitride ELO layer 105 and III-nitride device layer 107 from the host substrate 101.

[0322] The present invention may be practiced without applied pressure, or room temperature surface activated bonding, or low temperature oxygen plasma assisted wafer bonding, etc. III-nitride ELO layer 105 and III-nitride device layer 107 may be prepared to aid in room temperature surface activated bonding or low temperature oxygen plasma assisted wafer bonding after release from host substrate 101.

[0323] The present invention may use surface activated bonding in at least two places, one to separate the detached III-nitride ELO layer 105 and III-nitride device layer 107 from the host substrate 101, and another to reattach the interface 111 of the III-nitride ELO layer 105 and growth limiting mask 102 for post-treating a surface such as an outer cladding layer for a dual cladding laser device 110, or a DBR mirror for a VCSEL device 110, or a heat sink plate for better thermal performance, or for integrating the III-nitride ELO layer 105 and III-nitride device layer 107 onto a Si-photonics substrate such as a silicon nitride (SiN) waveguide, including a CMOS compatible substrate. Sixth embodiment

[0324] The sixth embodiment is about using the interface 111 of the removed III-nitride ELO layer 105 and the III-nitride device layer 107. The interface 111 at the growth limiting mask 102 and the III-nitride ELO layer 105 has been experimentally observed to be extremely smooth. AFM scans reveal a surface roughness of about <2 nm, in some cases on the sub-nanometer scale. In post-processing of the device 110, such as a VCSEL, an externally clad-deposited dual cladding laser, or an edge-emitting laser, an external carrier, including either a DBR mirror layer, a cladding layer, or a heat sink, must be attached to the removed III-nitride ELO layer 105 at the interface 111. Since the surface of the interface 111 is smooth, the above-mentioned post-processing elements can be attached at room temperature, either by surface activated bonding or by a plasma-associated bonding mechanism. The smooth surface helps to avoid intermediate layers for successful attachment, thus obtaining a better performing device 110. Seventh embodiment

[0325] In the seventh embodiment, AlGaN layers are used in the III-nitride ELO layer 105 and / or the III-nitride device layer 107 and the resulting island-like III-nitride semiconductor layer. The AlGaN layer can be grown on various off-angle substrates 101 as the III-nitride ELO layer 105. The AlGaN layer can have a very smooth surface using the present invention. Using the present invention, the AlGaN layer can be removed from various off-angle substrates 101 as the III-nitride ELO layer 105 and the III-nitride device layer 107 and the island-like III-nitride semiconductor layer.

[0326] In this case, an active laser element 110 emitting UV light (UV-A or UV-B or UV-C) can be grown on the AlGaN ELO layer 105. After removal, the AlGaN ELO layer 105 and III-nitride element layer 107 provide the UV-element 110 with a quasi-AlGaN substrate. In this way, a high quality UV-LED or laser element 110 can be obtained without absorption by the substrate 101. Eighth embodiment

[0327] In an eighth embodiment, the III-nitride ELO layer 105 is grown on various off-angle substrates 101. The off-angle orientations range from 0 to +15 degrees and 0 to -28 degrees from the m-plane toward the c-plane. The present invention allows the rods of the element 110 to be removed from various off-angle substrates 101 without destroying the rods. When various crystal plane substrates 101 are used, the removed regions of the rods in the aperture area 103 may include step-like cleavage surfaces, making the aperture area 103 unsuitable for fabricating DBR mirrors for the VCSEL element 110 when the rods are mechanically removed. However, independent of the crystal orientation, the surfaces of the wing regions of the III-nitride ELO layer 105 are sufficiently smooth for fabricating such delicate DBR mirrors for the VCSEL element 110. For example, when the semipolar bar of element 110 is removed from its host substrate 101 with semipolar planes 20-2-1 or 20-21, the open area resulting from etching region 1 201 may include cleaved nonpolar planes 10-10, etc., which are at angles 75 or 15 degrees from the semipolar planes of the host substrate 101, which appear as a staircase pattern in the open area, as shown in Figures 12B, 12C, 12D, and 12E. However, the wing regions of the III-nitride ELO layer 105 of the bar include a smoother surface than the open area. Therefore, the present proposal to fabricate the DBR mirror for the VCSEL element 110 on the wing regions of the III-nitride ELO layer 105 is the best solution independent of crystal planes. This is a great advantage of the present technique, since various off-angle oriented semiconductor planar elements 110 can be realized without changing the fabrication process. Ninth embodiment

[0328] In a ninth embodiment, III-nitride ELO layer 105 is grown on a c-plane substrate 101 with two different miscut orientations. III-nitride ELO layer 105 and III-nitride device layer 107 are then removed from substrate 101 after processing into the desired device 110 using the invention described herein. (Tenth embodiment)

[0329] In the tenth embodiment, a sapphire substrate 101 is used together with a buffer layer. The resulting structure is almost the same as the first embodiment, but using a sapphire substrate 101 and a buffer layer. In this embodiment, the buffer layer may also include an additional n-GaN or undoped GaN layer. The buffer layer is grown at a low temperature of about 500-700°C. The n-GaN or undoped GaN layer is grown at a higher temperature of about 900-1,200°C. The total thickness is about 1-3 μm. A growth limiting mask 102 is then placed on the buffer layer and the n-GaN or undoped GaN layer.

[0330] On the other hand, it may not be necessary to use a buffer layer. For example, the growth-limiting mask 102 can be placed directly on the heterosubstrate 101. Then, the III-nitride ELO layer 105 and / or the III-nitride device layer 107 can be grown. In this case, the III-nitride ELO layer 105 easily separates from the substrate 101 due to the heterointerface containing many defects.

[0331] By employing the present invention, a smooth interface 111 of III-nitride ELO layer 105 can be obtained, for example, for a resonant cavity, even when using a heterosubstrate 101, because the wing regions of III-nitride ELO layer 105 and the interface 111 between growth limiting mask 102 and III-nitride ELO layer 105 are used as mirrors for a resonant cavity in device 110.

[0332] The use of heterosubstrates 101 also has a large impact on mass production. For example, the heterosubstrates 101 used can be low-cost and large-size substrates 101 such as sapphire, GaAs and Si, compared to free-standing GaN substrates 101. This results in low-cost devices 110. Furthermore, sapphire and GaAs substrates are known to be low-thermal conductivity materials, and therefore devices 110 using these substrates 101 have thermal issues. However, using the present invention, the devices 110 are removed from the heterosubstrate 101, so these thermal issues can be avoided.

[0333] Furthermore, when the ELO growth method is used to remove the rods of the element 110, this method can significantly reduce the dislocation and stacking fault densities, which are a significant problem when using heterosubstrates 101.

[0334] Thus, the present invention is able to solve many of the problems resulting from the use of heterosubstrates 101 . (Eleventh embodiment)

[0335] There is a great demand to extend the operating wavelength range to much shorter wavelengths, such as 400 nm or lower, for spectroscopy, including displays, augmented reality (AR) / virtual reality (VR) displays, quantum-related technologies, general metrology, and biosensing. Many demonstrations have utilized photonic integrated circuits (PICs) based on silicon nitride (SiN), lithium niobate (LiNbO3), tantalum pentoxide (Ta2O5), aluminum nitride (AlN), aluminum oxide (Al2O3), or other suitable materials with large band gap energy to address the short wavelength range. However, in all these demonstrations, the lasers have either been externally coupled or fabricated in processes that are not scaled to the high volume and low cost required for wide deployment.

[0336] To address new and emerging markets, a wafer-scale process is needed that provides on-chip sources and amplifiers in a common passive platform that operates down to 400 nm wavelengths, and that preferably can be easily transferred to state-of-the-art fabrication facilities. In addition, the approach described in this invention, which does not require intermediate layers, allows utilization of the full transparency range of passive waveguide materials without being limited by the bandgaps of those intermediate layers.

[0337] The present invention can be used to heterogeneously integrate electrically pumped GaN lasers and detectors coupled to SiN or TiO2 waveguides with very high element uniformity using wafer-scale processes. The present technology has the promise of revolutionizing many fields including displays, stereoscopic light projection, AR / VR displays, position, navigation and timing (PNT), quantum sensing, and computing by enabling wafer-scale manufacturing of photonic integrated chips with on-chip sources using mass production high quality CMOS facilities, as shown in schematics 2100a, 2100b, 2100c, and 2100d in FIG. 21, where schematic 2100a represents a semiconductor layer wafer consisting of detached elements 110, schematic 2100b represents a carrier wafer, schematic 2100c represents elements 110 attached to carrier wafer 2100b, and schematic 2100d represents an application where laser element 2101, modulator 2102, and multiplexer 2103 are combined on carrier wafer 2100b. (Twelfth embodiment)

[0338] The twelfth embodiment has the advantage of improved yield using the process of the present invention. The present invention first separates the III-nitride ELO layer 105 and the III-nitride device layer 107 on the host substrate 101, but the separated / detached III-nitride ELO layer 105 and the III-nitride device layer 107 remain on the growth limit mask 102 of the host substrate 101 by relying on weak interaction forces and / or weak links 301, 302. By doing so, the device 110 is already in a relaxed state, and therefore wafer bending or cracking of the device layer 107 due to stress, etc. may not be an issue when transferring the device 110 at the wafer scale. See, for example, schematic diagrams 2100a, 2100b, 2100c, 2100d in FIG. 21. Thirteenth embodiment

[0339] As shown by schematic diagrams 2200a, 2200b, 2200c, 2200d, 2200e in Fig. 22, the thirteenth embodiment is about making large-scale substrates using epitaxial layer transfer process. Enlarged III-nitride substrates with better epitaxial quality can be obtained by modifying some processes of the present invention. As shown in schematic diagram 2200a, the coalesced III-nitride ELO layer 105 on the host substrate 101 can be separated into small groups from the host substrate 101 by etching regions 1 and 2 201, 202 as shown in schematic diagram 2200b, and then tiled onto larger carrier substrates 2201 such as Si, sapphire, etc. as shown in schematic diagram 2200c. Once tiled onto the larger carrier substrate 2201, device 110 epitaxy can be performed by loading the tiled epitaxy layers including carrier 2201 into an MOCVD reactor.

[0340] This method is particularly useful when special orientations are required, such as semi-polar or non-polar III-nitride substrates 101. Semi-polar or non-polar crystal orientation substrates are a by-product of the conventional c-plane fabrication process. HVPE processed c-plane substrate boules are sliced ​​into various crystal orientations to produce semi-polar substrates. The cracking problem between the III-nitride layer and the HVPE carrier substrate prevents the fabrication of thicker boules, thus limiting the achievable dimensions for semi-polar and non-polar substrates.

[0341] However, using the present invention, one can use smaller available special orientation substrates 101 to generate base III-nitride ELO layers 105, then separate them from their host substrates 101 and tile them onto larger carrier wafers 2201 using either surface activated bonding or some intermediate layer that can withstand MOCVD temperatures when the III-nitride device layers 107 are grown. Using the process of consolidation illustrated in FIG. 22, larger size III-nitride wafers can be realized.

[0342] The same process can be applied in device 110 processing. For example, first, the high-quality III-nitride ELO layer 105 and the n-type III-nitride device layer 107 can be separated from the host substrate 101 as shown in schematic diagram 2200d, and transferred onto the carrier substrate 2201 as shown in schematic diagram 2200e, and then the carrier substrate 2201 can be reintroduced into the MOCVD reactor to grow any remaining III-nitride device layers 107, such as active layers and p-type layers. After completing the growth of the III-nitride device layers 107 on the carrier wafer 2201, the desired device 110 can be fabricated. (Fourteenth embodiment)

[0343] The fourteenth embodiment is about realizing small pixel elements per inch 110 for AR / VR display applications, as shown in schematic diagrams 2300a, 2300b, 2300c, 2300d, 2300e, 2300f in FIG. 23. The III-nitride device layer 107 in schematic diagram 2300a of step A is separated on the growth restriction mask 102 with the p-pad metal layer 2301 as a selective etchant mask, as shown in schematic diagram 2300b of step B and schematic diagram 2300c of step C. Then, the III-nitride device layer 107 and the substrate 101 are flipped, and a CMOS integrated control (IC) wafer 2302 is attached or bonded to the selective pitch of the separated III-nitride device layer 107 on the host substrate 101, as shown in schematic diagram 2300d of step D, and the host substrate 101 is removed, as shown in schematic diagram 2300e of step E. An n-contact layer 2303 and an electrical pad 2304 are processed on the n-type layer, which is the interface 111 of the III-nitride ELO layer 105. To avoid blocking the emitted light, a transparent conductive layer 2305 can be placed on the interface 111 of the III-nitride ELO layer 105 to displace the reflective n-metal contact 2303 onto the CMOS IC wafer, as shown in the schematic diagram 2300f of step F. Furthermore, a passivation layer 2306 can be deposited on the III-nitride device layer 107. Fifteenth embodiment

[0344] As shown in schematic diagrams 2400a, 2400b in Fig. 24, the fifteenth embodiment describes a method of obtaining multiple light emitting devices 110 from a wing of a single III-nitride ELO layer 105. When the required light emitting device 110 dimensions are in the range of 1 μm to 50 μm (along one side for non-circular or diametric dimensions), etching regions for releasing the devices 110, such as region 1 201 and region 1 202, are separated such that multiple devices 110 can be extracted from a single wing of the III-nitride ELO layer 105, as shown in schematic diagrams 2400a, 2400b in Fig. 24. This extraction method reduces the number of bent regions 109 in uncoalesced III-nitride ELO layers 105, as shown in schematic diagram 2400a, and reduces the number of coalesced III-nitride ELO layers 105 on substrate 101, as shown in schematic diagram 2400b, which therefore increases the useful element 110 extraction area from a single wafer, leading to increased yield. Sixteenth embodiment

[0345] As shown in schematic diagrams 2500a, 2500b, 2500c, 2500d, 2500e, 2500f, 2500g, 2500h in Figures 25A, 25B, and 25C, the sixteenth embodiment describes a method of realizing a VCSEL device 110. After growing the III-nitride device layer 107 in schematic diagram 2500a of step A and releasing the device 110 in schematic diagram 2500b of step B, the device 110 remains on the growth limiting mask 102 with or without supporting hooks as illustrated in schematic diagram 2500c of step C, and the device 110 has been dispersed from the substrate 101 onto a larger pre-processed carrier substrate using pick-and-place or vacuum methods or the like such that the interface 111 faces down against a pre-patterned patch of epitaxial DBR. This dispersion of elements 110 from the growth substrate 101 can be performed several times in order to place the elements over a larger carrier substrate, as illustrated in schematic diagram 2500d of step D. After placement on the carrier substrate, surface activated bonding is performed between the dispersed elements 110 and the epitaxial DBR layer of the carrier, as illustrated in schematic diagram 2500e of step E. Surface activated bonding can be performed at more accelerated conditions since no material damage results from the processing performed primarily with the epitaxial semiconductor layers 105, 107.

[0346] Front-end processes such as current aperture definition, p-contact layer deposition, dielectric DBR placement, etc. are performed on a large carrier substrate, as illustrated in schematic diagram 2500f of step F, which improves yield and reduces manufacturing costs. The carrier containing the epitaxial DBR can be used as one of the electrical contacts. A second electrical contact can be placed on the top surface of device 110. However, if device 110 is smaller or some technological complexity is involved, a release layer can be deposited on the carrier wafer to separate the two electrical contacts, as illustrated in schematic diagrams 2500g and 2500h of step G. (Process Flow Chart)

[0347] FIG. 26 is a flow chart illustrating a method of fabricating a semiconductor device in accordance with the present invention.

[0348] Block 2601 represents providing a host substrate 101. In one embodiment, the substrate 101 is a semiconductor substrate independent of crystal orientation, such as a III-nitride based substrate 101, e.g., a GaN based substrate, or a heterosubstrate 101, such as a sapphire substrate. This step may also include the optional step of depositing a template layer on or above the substrate 101, which may comprise a buffer layer, such as a GaN underlayer, and / or one or more intermediate layers.

[0349] Block 2602 represents depositing a growth limiting mask 102 on or above the substrate 101, i.e., on the substrate 101 itself or on a template layer. The growth limiting mask 102 is patterned to include a plurality of stripe-like opening areas 103. The growth limiting mask 102 may comprise a multi-layer structure.

[0350] Block 2603 represents forming one or more III-nitride layers 105 on or above the growth-limiting mask 102 using epitaxial lateral overgrowth (ELO). This step may or may not include stopping the growth of the III-nitride ELO layers 105 before adjacent ones of the III-nitride ELO layers 105 coalesce with one another.

[0351] Block 2604 represents growing one or more III-nitride device layers 107 on or above the III-nitride ELO layer 105, thereby fabricating one or more element 110 rods on the substrate 101. Additional element 110 fabrication can occur before and / or after the elements 110 are removed from the substrate 101.

[0352] For the μLED device 110, this step may include defining a p-pad and an n-pad and metallizing both pads, the p-pad metallization having a vertical pad configuration.

[0353] For a Fabry-Perot or dual clad laser device 110, this step may include defining raised structures on the wings of the III-nitride ELO layer 105, defining p-pads and n-pads, and metallizing both pads, the p-pad metallization comprising a vertical pad configuration.

[0354] For the VCSEL device 110, this step may include defining a current confinement aperture, defining a p-pad and an n-pad, and metallizing both pads, the p-pad metallization comprising a vertical pad configuration.

[0355] Block 2605 represents releasing the III-nitride ELO layer 105 and the III-nitride device layer 107 into separate devices 110. This step may include a separation process that divides the ELO layer 105 and the device layer 107 into the devices 110. This step may also include etching the III-nitride ELO layer 105 and the III-nitride device layer 107 to release them into separate devices 110, which may include placing a release mask on the III-nitride ELO layer 105 to define the etch.

[0356] Block 2606 represents an optional step of providing an auxiliary layer 301 or hook layer 302 to secure the III-nitride ELO layer 105 and the III-nitride device layer 107 onto the substrate 101; optionally, the auxiliary layer 301 or hook layer 302 may not be present.

[0357] For a Fabry-Perot or dual clad laser element 110, this step may include accessing the pads on a release mask, selectively bonding the element 110 to a carrier for faceting and coating, element 110 singulation, and attachment of the carrier on which at least one of the pads is formed to a heat sink.

[0358] For the VCSEL device 110, this step may include surface activated bonding to a carrier substrate containing an epitaxial DBR (taking advantage of the surface smoothness at the interface 111 between the III-nitride ELO layer 105 and the growth limit mask 102), accessing pads on the release mask, device 110 singulation, and attachment to a heat sink or carrier on which at least one of the electrical pads is formed.

[0359] Block 2607 represents transferring the III-nitride ELO layer 105 and the III-nitride device layer 107 using a pick and place or a vacuum chuck.

[0360] For the μLED elements 110, this step may include mounting the elements 110 on an intermediate substrate, local repair on the display panel, and / or dispersing the elements 110 on the display panel, followed by defining the electrical paths.

[0361] Block 2608 represents the step of surface activated bonding onto a larger substrate.

[0362] Block 2609 represents performing a regrowth of the III-nitride device layer 107 on the larger III-nitride ELO layer 105 .

[0363] Block 2610 represents the resulting product of this method, i.e., one or more III-nitride based semiconductor devices 110, such as μLEDs, Fabry-Perot or dual clad lasers, or VCSELs, fabricated according to this method, and the substrate 101 that has been removed from the device 110 and is available for recycling and reuse. (Advantages and Benefits)

[0364] The present invention is particularly useful when bonding an ELO layer or element to another carrier or substrate without the use of solder.

[0365] Generally, the surface activated bonding method requires flatness and smoothness with a large area when bonding the wafers. When bonding each wafer, force and heat are applied to the wafer. It is difficult to apply force and heat in a uniform manner, especially when each wafer is made of different materials. Some parts of the wafers can be bonded to each other, but the rest cannot be bonded. Therefore, the yield is not high. In the present invention, the ELO layer and the element are small in size, and bonding with small size can avoid these problems. The length of the transferred ELO layer is preferably 40 mm or less, more preferably 20 mm. The width of the transferred ELO layer is also preferably 200 μm or less, more preferably 100 μm.

[0366] The following describes a process flow for obtaining the above advantages. Case 1:

[0367] 1. Grow an ELO layer onto a substrate using a growth limiting mask.

[0368] 2. The device layers are grown on the ELO layer.

[0369] 3. The devices are fabricated on the device layer.

[0370] 4. The elements are separated on the growth limiting mask.

[0371] 5. Transfer the device to a carrier wafer, with or without a DBR or cladding layer, without solder.

[0372] 6. Divide the carrier wafer into chips. Case 2:

[0373] 1. Grow an ELO layer onto a substrate using a growth limiting mask.

[0374] 2. The device layers are grown on the ELO layer.

[0375] 3. The ELO layer is cleaved over the growth limiting mask.

[0376] 4. Transfer the device to a carrier wafer, with or without a DBR or cladding layer, without the use of solder.

[0377] 5. Devices are fabricated on a device layer on a carrier wafer.

[0378] 6. Divide the carrier wafer into chips.

[0379] Case 2 has the advantage that the ELO layer does not have electrodes or element structures such as raised stripes when bonding, so a strong and high temperature process can be applied when bonding, which can improve the bonding yield. The present invention provides several other advantages and benefits as well.

[0380] The expensive III-nitride based substrate 110 can be reused after the substrate 101 is removed from the device layer 106.

[0381] High crystalline quality layers 105, 106, 109 can be obtained using a substrate 101 of the same or similar material with very low defect density.

[0382] Using the same or similar materials for both the substrate 101 and the layers 105, 107 can reduce distortion in the layers 105, 107.

[0383] Using materials with the same or similar thermal expansion for both the substrate 101 and the layers 105, 107 can reduce bending of the substrate 101 during epitaxial growth.

[0384] The layer 105 grown by ELO has good crystalline quality.

[0385] When the III-nitride ELO layers 105 do not coalesce with each other, the internal strain is relieved, which helps to avoid any occurrence of cracks. For the device layers 107 that are AlGaN layers, it is very useful, especially for high Al-content layers.

[0386] The resonant cavity of the VCSEL element is fabricated on the ELO wing region.

[0387] The ELO wing regions are low defect areas, which improve the device properties.

[0388] There is no need for a laborious substrate thinning process to fabricate the second DBR mirror of the cavity. Thinning is required for conventional fabrication to avoid significant absorption of the emission wavelength of the device.

[0389] Alternative processes such as photochemical etching processes for removing semiconductor layers are crystal plane dependent and extremely slow. However, the method described herein does not have crystal plane dependency. Any plane of the crystal can be grown at the growth limiting mask by controlling the growth parameters and the growth limiting mask to obtain a smooth interface.

[0390] On the other hand, the removal method of the present invention is inexpensive, robust and can be used for population transfer.

[0391] After removing the III-nitride ELO layers 105, they can simply be surface bonded to externally prepared DBR mirrors by surface activation or diffusion bonding, since the interfaces of the removed layers are sufficiently smooth to support such bonding techniques.

[0392] Long cavity curved mirror structures can be fabricated without complex steps, using only epitaxially grown layers, which allows recycling of the substrate.

[0393] The island-shaped III-nitride semiconductor layer is formed separately such that the tensile or compressive stress is reduced.

[0394] Furthermore, the growth limiting mask 102 and the III-nitride ELO layer 105 are not chemically bonded, and therefore stress in the III-nitride ELO layer 105 and the additional device layer 107 can be relieved by sliding induced at the interface between the growth limiting mask 102 and the III-nitride ELO layer 105.

[0395] High quality semiconductor crystal layers 105, 107 can be grown by suppressing the curvature of the substrate 101, and furthermore, even when the layers 105, 107 are very thick, the occurrence of cracks etc. can be suppressed, so that large area semiconductor devices can be easily realized.

[0396] The fabrication method can be easily adapted to large wafer sizes (>2 inches). (Conclusion)

[0397] The description of the preferred embodiments of the present invention now concludes. The foregoing description of one or more embodiments of the present invention has been presented for the purpose of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise form disclosed. Many modifications and variations are possible in light of the above teachings. It is intended that the scope of the present invention be limited not by the detailed description for carrying out the invention, but rather by the claims appended hereto.

Claims

1. 1. A method, comprising: growing one or more epitaxial lateral overgrowth (ELO) layers and a device layer on the substrate using a growth limiting mask; forming a structure for isolating a plurality of element units composed of the ELO layer and the element layer on the growth limiting mask from each other and from the substrate, wherein connections are established for fixing the separated plurality of element units to the substrate; After breaking the connections, transferring the separated plurality of element units from the substrate to a carrier wafer. A method comprising:

2. The method of claim 1 , wherein the forming step includes a separation process that divides the ELO layer and device layer into the plurality of device units.

3. The method of claim 1 , wherein the transferring step comprises a solderless bonding process.

4. The method of claim 1 , wherein the transferring step comprises a bonding process using solder.

5. The method of claim 1 , wherein the transferring step integrates the separated multiple element units onto the carrier wafer, the carrier wafer being larger than the substrate.

6. The method of claim 5 , wherein the isolated multiple element units are integrated into a photonic integrated circuit.

7. The method of claim 1 , wherein one or more devices are fabricated using the ELO layer and device layer before and / or after the transferring step.

8. The method of claim 1 , wherein the separated element units remain on the growth limiting mask.

9. The method of claim 8 , wherein the connection comprises a fixed hook layer or a backing layer.

10. The method of claim 1 , further comprising removing the separated plurality of element units from the substrate.

11. The method of claim 10 , wherein the removing step is performed using pick and place, a vacuum chuck, surface activated bonding, or bonding through an intermediate layer.

12. The method according to claim 10 , wherein the removing step selectively extracts the separated plurality of element units from the substrate.

13. The method of claim 1 , wherein the substrate is a semiconductor substrate.

14. The method of claim 13 , wherein the semiconductor substrate is independent of the crystal orientation of the substrate.

15. The method of claim 1 , wherein the carrier wafer has one or more cladding layers, distributed Bragg reflector (DBR) layers, or heat sinks for the separated multiple element units.

16. The method of claim 1 , wherein the carrier wafer has one or more epitaxial distributed Bragg reflector (DBR) layers for the isolated plurality of element units.

17. The method of claim 1 , wherein the growth-limiting mask comprises a multi-layer structure.

18. 10. The method of claim 1, wherein each of the separated element units comprises a micro-sized light emitting diode (μLED), an edge-emitting laser, or a vertical-cavity surface-emitting laser (VCSEL).

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