Semiconductor Device

Abstract

To provide a technology that can reduce variations in characteristic values such as current and capacitance of memory cells.SOLUTION: A semiconductor device includes a first data line, a second data line, and a memory cell connected to the first data line and the second data line. The memory cell includes a plurality of switches, a first data holding circuit, a second data holding circuit, a third data holding circuit, a fourth data holding circuit, and an input line. The characteristic value of the memory cell can be changed by controlling the switch connected to the first data line among the plurality of switches based on the value held by the third data holding circuit and controlling the switch connected to the second data line among the plurality of switches based on the value held by the fourth data holding circuit.SELECTED DRAWING: Figure 4

Description

[Technical field]

[0001] The present disclosure relates to a semiconductor device and is applicable to, for example, a semiconductor device that is required to execute a large number of product-sum operations. [Background technology]

[0002] With the development of machine learning through deep learning, artificial intelligence (AI) is being applied in various fields. This method requires a large number of multiplication and accumulation operations, so an AI accelerator is used to accelerate the processing of multiplication and accumulation operations.

[0003] Processing in Memory (PIM) may be used in AI accelerators. For example, Japanese Patent Application Laid-Open No. 2020-129582 (Patent Document 1) discloses a semiconductor device having a memory cell that is connected to a data line, stores ternary data, and performs a multiply-and-accumulate operation between the stored data, input data, and data on the data line. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] JP 2020-129582 A Summary of the Invention [Problem to be solved by the invention]

[0005] In the configuration of Patent Document 1, when the number of memory cells connected to the data lines increases, a stable sum operation may not be possible due to variations in characteristic values ​​such as the current and capacitance of the memory cells.

[0006] Other objects and novel features of the present disclosure will become apparent from the description of the present specification and the accompanying drawings. [Means for solving the problem]

[0007] A representative embodiment of the present disclosure can be briefly outlined as follows. That is, the semiconductor device includes a first data line, a second data line, and a memory cell connected to the first data line and the second data line. The memory cell includes a plurality of switches, a first data retention circuit, a second data retention circuit, a third data retention circuit, a fourth data retention circuit, and an input line. A switch of the plurality of switches connected to the first data line is controlled based on a value held by the third data retention circuit, and a switch of the plurality of switches connected to the second data line is controlled based on a value held by the fourth data retention circuit, thereby changing a characteristic value of the memory cell. Effect of the Invention

[0008] According to the semiconductor device, it is possible to reduce the variation in the characteristic values ​​of the memory cells. [Brief description of the drawings]

[0009] [Figure 1] FIG. 1 is a block diagram showing an example of the configuration of an inference device according to an embodiment. [Diagram 2] FIG. 2 is a block diagram showing an example of the configuration of the product-sum calculation device shown in FIG. [Diagram 3] FIG. 3 is a diagram showing one column of memory cells and related parts in the memory array shown in FIG. [Figure 4] FIG. 4 is a diagram showing an example of the configuration of the product operation memory cell shown in FIG. [Diagram 5] FIG. 5 is a circuit diagram showing details of an example of the configuration of the product operation memory cell shown in FIG. [Figure 6] FIG. 6 is a plan view showing the layout of the product operation memory cell shown in FIG. [Figure 7] FIG. 7 is a diagram showing an example of the configuration of the inference reference cell shown in FIG. [Figure 8] FIG. 8 is a diagram showing a configuration example of the adjustment reference cell shown in FIG. [Figure 9] FIG. 9 is a diagram showing an example of the configuration of the fine adjustment cell shown in FIG. [Figure 10] FIG. 10 is a diagram for explaining A / D conversion. [Figure 11] FIG. 11 is a diagram for explaining A / D conversion when an error occurs. [Figure 12] Fig. 12(a) is a diagram for explaining a current comparison between a product operation memory cell and an adjustment reference cell, and Fig. 12(b) is a diagram for explaining a current comparison between a product operation memory cell and an adjustment reference cell. [Figure 13] FIG. 13 is a diagram showing a current path of the product operation memory cell (ME[0]). [Figure 14] FIG. 14 is a diagram showing a current path of the adjustment reference cell. [Figure 15] FIG. 15 is a diagram showing the current paths of the fine-tuning cell. [Figure 16] FIG. 16 is a diagram showing the configuration of a product operation memory cell in the first modified example. [Figure 17] FIG. 17 is a diagram showing the configuration of a product operation memory cell in the second modified example. [Figure 18] FIG. 18 is a diagram showing the configuration of a product operation memory cell in the third modified example. [Figure 19] FIG. 19 is a diagram showing the configuration of an adjustment reference cell in the fourth modified example. [Figure 20] FIG. 20 is a diagram showing a configuration of a memory cell array in the fifth modified example. [Figure 21] FIG. 21 is a diagram showing voltages on the data lines and the common power supply line in the embodiment. [Figure 22] FIG. 22 is a diagram showing voltages on the data lines and the common power supply line in the fifth modified example. [Diagram 23] FIG. 23 is a diagram showing the configuration of a product operation memory cell in the sixth modified example. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] Hereinafter, the embodiments and modifications will be described with reference to the drawings. In the following description, the same components are designated by the same reference numerals, and repeated description may be omitted.

[0011] <Configuration of inference device> FIG. 1 is a block diagram showing an example of the configuration of an inference device according to an embodiment.

[0012] The inference device in the embodiment includes an AI accelerator 130, a central processing unit (CPU) 200, an imaging device (IMAGING DEVICE) 300, and a display device (DISPLAY DEVICE) 400. The imaging device 300 is a camera, scanner, or the like, and acquires image data and provides it to the central processing unit 200. The central processing unit 200 processes the provided image data and provides it to the AI ​​accelerator 130. The AI ​​accelerator 130 performs inference based on the provided image data and provides the inference result to the central processing unit 200. The central processing unit 200 processes the provided inference result and provides it to the display device 400. The display device 400 displays the provided inference result.

[0013] The AI ​​accelerator 130 includes an integrated block 110 configured by assembling a number of product-sum calculation devices 100 and its control circuit (CNTR) 120. The product-sum calculation devices 100 are configured using a PIM architecture. The AI ​​accelerator 130 is a semiconductor device formed on a single semiconductor substrate, such as a microcontroller incorporating the product-sum calculation devices 100.

[0014] <Configuration of the multiply-and-accumulate unit> Fig. 2 is a block diagram showing an example of the configuration of the product-sum calculation device shown in Fig. 1. In addition to the product-sum calculation process, the product-sum calculation device 100 in the embodiment has an adjustment function for reducing the variation in characteristic values ​​of memory cells with a product-sum calculation function (hereinafter, referred to as "product calculation memory cells") that perform the product-sum calculation process.

[0015] The product-sum calculation device 100 includes a memory cell array 101, a current source (CS) 102, a common power line switch (CVSW) 103 as a constant current source (CCS), and a sense amplifier 104. The product-sum calculation device 100 further includes an inference control circuit (I_CNTR) 105, a adjustment control circuit (T_CNTR) 106, an input buffer (IB) 107, and a memory controller (M_CNTR) 108.

[0016] The memory cell array 101 is composed of a plurality of multiplication memory cells (ME) 10. The multiplication memory cells 10 are connected to a data line (PBL) 13a and a data line (NBL) 13b. The sum of the number of multiplication memory cells 10 connected to the data lines 13a and 13b is determined by a sense amplifier 104 as a comparison circuit based on input data supplied from an input buffer 107, thereby performing a multiplication and accumulation operation.

[0017] The multiplication memory cell 10 performs a multiplication operation between a ternary logical value stored in the multiplication memory cell 10 and a logical value of input data, and operates to draw current from the data lines 13a and 13b according to the result of the multiplication operation. The multiplication memory cell 10 of the embodiment is an example using a current sense.

[0018] In each of the data lines 13a and 13b, currents according to the product operation results of the multiple product operation memory cells 10 are superimposed, and the current and voltage are determined in each of the data lines 13a and 13b. That is, a sum operation is performed by the data lines 13a and 13b to obtain the sum of the products obtained in the multiple product operation memory cells 10. The result of the sum operation, which is the product sum operation, is output via the data lines 13a and 13b.

[0019] The inference control circuit 105 controls the inference reference cell and the like to perform AD conversion, as described later. The adjustment control circuit 106 is used to optimize a current path, as described later, of the multiplication memory cell 10 and reduce variations. Details will be described later.

[0020] <Configuration of memory cell columns in memory array> FIG. 3 is a diagram showing one column of memory cells and related parts in the memory array shown in FIG.

[0021] A memory cell column in the memory cell array 101 includes a plurality of product operation memory cells 10, a plurality of inference reference cells (IREF) 20, a tuning reference cell (TREF) 30, and a fine tuning cell (FT) 40. Each cell is connected to a data line 13a and a data line 13b. A current source (CS) 102, a common power switch (CVSW) 103, and a sense amplifier (SA) 104 are also connected to the data line 13a and the data line 13b. Each cell will be described below.

[0022] <Configuration of Multiplication Memory Cell (ME)> FIG. 4 is a diagram showing an example of the configuration of the product operation memory cell shown in FIG.

[0023] The product operation memory cell 10 includes two weight memory cells (MC) 11a, 11b and eight switches 12a-12d, 12i-12l for performing product-sum operations. The product operation memory cell 10 further includes four path switching memory cells (MC) 11c-11f and eight switches 12e-12h, 12m-12p for switching current paths.

[0024] The switches 12e and 12f are connected to the data line 13a and the memory cell 11c, and when, for example, a logical value "1" is stored in the memory cell 11c, the switch 12e is in an on state and the switch 12f is in an off state. The switches 12c and 12d are connected between the node n1 and the switches 12e and 12f, respectively. The switches 12c and 12d are connected to an input line (IL) 15, and when the input data (ID) provided to the input line 15 is at a high level indicating, for example, a logical value "1", the switches 12c and 12d are in an on state.

[0025] The switches 12a and 12b are connected to the node n1 and the memory cell 11a, and when, for example, a logical value "1" is stored in the memory cell 11a, the switches 12a and 12b are turned on. The switches 12g and 12h are connected between the switches 12a and 12b and the common power line 14, and are also connected to the memory cell 11e. When, for example, a logical value "1" is stored in the memory cell 11e, the switch 12g is turned on and the switch 12h is turned off.

[0026] The switches 12m and 12n are connected to the data line 13b and the memory cell 11d, and when, for example, a logical value "1" is stored in the memory cell 11d, the switch 12m is in an on state and the switch 12n is in an off state. The switches 12k and 12l are connected between the node n2 and the switches 12m and 12n, respectively. The switches 12k and 12l are connected to the input line 15, and when the input data provided to the input line 15 is, for example, a logical value "1", the switches 12k and 12l are in an on state.

[0027] The switches 12i and 12j are connected to the node n2 and the memory cell 11b, and when, for example, a logical value "1" is stored in the memory cell 11b, the switches 12i and 12j are turned on. The switches 12o and 12p are connected between the switches 12i and 12j and the common power supply line (CVSS) 14, and are also connected to the memory cell 11f. When, for example, a logical value "1" is stored in the memory cell 11f, the switch 12o is turned on and the switch 12p is turned off.

[0028] (Multiply and add) The memory cell 11a provides an in-phase value (T) to the switches 12a and 12b, and the memory cell 11b provides an in-phase value (T) to the switches 12i and 12j. As a result, when the input data (ID) provided to the input line 15 becomes a high level indicating a logical value "1", the multiplication operation of the multiplication operation memory cell 10 is controlled by the data held in the memory cells 11a and 11b.

[0029] The product-sum operation is performed using the following three values ​​(a) to (c): Therefore, it is prohibited for both the values ​​of memory cells 11a and 11b to be the logical value "1." (a) Data line 13a is connected to the common power supply line 14 (logical value "+1") (b) Data line 13b is connected to the common power supply line 14 (logical value "-1") (c) The connection between the data line 13a side and the common power supply line 14 and the connection between the data line 13b side and the common power supply line 14 are both cut off (logical value "0")

[0030] The sum operation is performed by a current passing through the switch of the multiplication operation memory cell 10 on the data line 13a and the data line 13b.

[0031] When both memory cells 11a and 11b store a logical value of "0", the product operation memory cell 10 stores a logical value of "0". When memory cell 11a stores a logical value of "1" and memory cell 11b stores a logical value of "0", the product operation memory cell 10 stores a logical value of "+1". When memory cell 11a stores a logical value of "0" and memory cell 11b stores a logical value of "1", the product operation memory cell 10 stores a logical value of "-1". Here, the following description will be given assuming that the logical value "1" is stored in memory cells 11c, 11d, 11e, and 11f.

[0032] As a result, when a logical value of "0" is stored in the multiplication memory cell 10, the switches 12a, 12b, 12i, and 12j are turned off. Therefore, even if the input data (ID) is, for example, a logical value of "1", no current flows from the data lines 13a and 13b to the common power supply line 14.

[0033] On the other hand, when the logical value "+1" is stored in the multiplication memory cell 10, the switches 12a and 12b are turned on, and the switches 12i and 12j are turned off. At this time, if the input data (ID) is a logical value "1", a current flows from the data line 13a to the common power supply line 14 via the switches 12e, 12c, 12a, and 12g in the on state, and the voltage of the data line 13a drops. At this time, the voltage of the data line 13b does not drop. On the other hand, if the input data (ID) is a logical value "0", the switches 12c, 12d, 12k, and 12l in the on state are turned off. Therefore, no current flows from the data lines 13a and 13b to the common power supply line 14, and the voltage of the data lines 13a and 13b does not drop.

[0034] Furthermore, when the logical value "-1" is stored in the multiplication memory cell 10, the switches 12i and 12j are turned on, and the switches 12a and 12b are turned off. At this time, if the input data (ID) is a logical value "1", a current flows from the data line 13b to the common power supply line 14 via the switches 12m, 12k, 12i, and 12o in the on state, the voltage of the data line 13b drops, and the voltage of the data line 13a does not drop. On the other hand, if the input data is a logical value "0", the switches 12c, 12d, 12k, and 12l in the on state are turned off. Therefore, no current flows from the data lines 13a and 13b to the common power supply line 14, and the voltage of the data lines 13a and 13b does not drop.

[0035] That is, it can be considered that memory cell 11a is used to store a logical value "+1" in product operation memory cell 10, and memory cell 11b is used to store a logical value "-1" in product operation memory cell 10.

[0036] As a result, a multiplication operation is performed between the ternary values ​​stored in the multiplication operation memory cell 10 and the value of the input data (ID). That is, six states, 0x0, 0x(+1), 0x(-1), 1x0, 1x(+1), and 1x(-1), are formed according to the logical value of the input data (ID) and the logical value of the multiplication operation memory cell 10. In this case, a multiplication operation is performed between the logical value of the input data (ID) and the logical value stored in the multiplication operation memory cell 10. When the result of the multiplication operation is a logical value "1", a current flows between the data line 13a and the common power supply line 14, and the voltage of the data line 13a decreases. On the other hand, when the result of the multiplication operation is a logical value "-1", a current flows between the data line 13b and the common power supply line 14, and the voltage of the data line 13b decreases.

[0037] (Current path switching) Some of the switches 12a to 12h are connected in series (cascade connection), thereby forming a current path that connects the data line 13a to the common power supply line 14. Multiple current paths can be formed. Depending on the on / off state of the switches 12a to 12h, one of the multiple current paths is selected and the current path is switched. Some of the switches 12i to 12p are connected in series (cascade connection), thereby forming a current path that connects the data line 13b to the common power supply line 14. Multiple current paths can be formed. Depending on the on / off state of the switches 12i to 12p, one of the multiple current paths is selected and the current path is switched.

[0038] Since the memory cell 11c provides complementary values ​​(T / B) to the switches 12e and 12f, one of the switches 12e and 12f is turned on and the other is turned off. Since the memory cell 11d provides complementary values ​​(T / B) to the switches 12m and 12n, one of the switches 12m and 12n is turned on and the other is turned off. Since the memory cell 11e provides complementary values ​​(T / B) to the switches 12g and 12h, one of the switches 12g and 12h is turned on and the other is turned off. Since the memory cell 11f provides complementary values ​​(T / B) to the switches 12o and 12p, one of the switches 12o and 12p is turned on and the other is turned off. As a result, one of the four current paths is selected for each of the data line 13a and the data line 13b.

[0039] <Detailed configuration of multiplication memory cell (ME)> FIG. 5 is a circuit diagram showing the configuration of the product operation memory cell shown in FIG.

[0040] The memory cells 11a to 11f serving as data retention circuits in the product operation memory cell 10 are composed of static random access memory (SRAM) memory cells. The SRAM memory cells are composed of, for example, six transistors. The data retained in the memory cells 11a to 11f is controlled by three pairs of data lines (BT[2:0], BB[2:0]) 16a to 16f and two word lines (WL[1:0]) 17a and 17b for normal SRAM operation. This allows one of the six SRAM memory cells to be specified from the outside and a value to be written or read. The switches 12a to 12p in the product operation memory cell 10 are composed of NMOS transistors.

[0041] The configuration of memory cells 11a to 11f will be described using memory cell 11c as an example. Memory cell 11c is composed of a plurality of P-channel field effect transistors (referred to as PMOS transistors) and a plurality of N-channel field effect transistors (referred to as NMOS transistors). In the drawings of this disclosure, PMOS transistors are distinguished from NMOS transistors by marking their gate electrodes with a circle. When no distinction is made between channel types, field effect transistors are hereinafter referred to as MOS transistors.

[0042] The memory cell 11c includes a first inverter circuit IV1 composed of a PMOS transistor P1 and an NMOS transistor N1, and a second inverter circuit IV2 composed of a PMOS transistor P2 and an NMOS transistor N2. The first inverter circuit IV1 and the second inverter circuit IV2 are connected between a power supply line to which a power supply voltage (Vd) is supplied and a ground line to which a ground potential (Vs) is supplied. The input of the first inverter circuit IV1 is connected to the output of the second inverter circuit IV2, and the input of the second inverter circuit IV2 is connected to the output of the first inverter circuit IV1. That is, the first inverter circuit IV1 and the second inverter circuit IV2 are cross-connected to form a latch circuit. The transfer NMOS transistors N3 and N4 are connected between the inputs of the second inverter circuit IV2 and the first inverter circuit IV1 and a pair of complementary data lines (BT[0], BB[0]) 16a and 16b. The gate electrodes of the transfer NMOS transistors N3 and N4 are connected to the word line (WL[0]) 17a.

[0043] The pair of complementary data lines 16a, 16b and the word line 17a are used when writing data to the memory cell 11c. That is, when writing data to the memory cell 11c, complementary voltages (high level and low level) according to the logical value of the data to be written are supplied to the complementary data lines 16a, 16b, and a high level is supplied to the word line 17a. As a result, the complementary voltages on the pair of complementary data lines 16a, 16b are supplied to a latch circuit constituted by a first inverter circuit IV1 and a second inverter circuit IV2 via the transfer NMOS transistors N3, N4. As a result, a logical value "0" or "1" is written to the memory cell 11c. The logical value held in the memory cell 11c is output from nodes n3, n4. The nodes n3, n4 are connected to the gates of the NMOS transistors constituting the switches 12e, 12f.

[0044] The memory cell 11a has the same configuration as the memory cell 11c, but the transfer NMOS transistors N3 and N4 are connected to a pair of complementary data lines (BT[1], BB[1]) 16c and 16d, which are different from the pair of complementary data lines 16a and 16b. The logical value held in the memory cell 11a is output only from the node n3. This makes it possible to write a logical value different from that of the memory cell 11c to the memory cell 11a. The node n3 is connected to the gates of the NMOS transistors constituting the switches 12a and 12b.

[0045] The memory cell 11e has the same configuration as the memory cell 11c. However, the transfer NMOS transistors N3 and N4 of the memory cell 11e are connected to a pair of complementary data lines (BT[2], BB[2]) 16e and 16f, which are different from the pair of complementary data lines 16a and 16b and the pair of complementary data lines 16c and 16d. This makes it possible to write a logical value different from that of the memory cell 11c to the memory cell 11a. The logical value held in the memory cell 11e is output from nodes n3 and n4. The nodes n3 and n4 are connected to the gates of the NMOS transistors constituting the switches 12g and 12h.

[0046] The memory cell 11d has the same configuration as the memory cell 11c, but the gate electrodes of the transfer NMOS transistors N3 and N4 are connected to a word line (WL[1]) 17b that is different from the word line 17a. This makes it possible to write a logical value different from that of the memory cell 11c to the memory cell 11d by setting the word line 17b to a high level at a timing different from that of the word line 17a. The logical value held in the memory cell 11d is output from nodes n3 and n4. The nodes n3 and n4 are connected to the gates of the NMOS transistors that constitute the switches 12g and 12h.

[0047] The memory cell 11b has the same configuration as the memory cell 11a, but the gate electrodes of the transfer NMOS transistors N3 and N4 are connected to a word line 17b different from the word line 17a. This makes it possible to write a logical value different from that of the memory cell 11a to the memory cell 11d by setting the word line 17b to a high level at a timing different from that of the word line 17a. That is, the memory cell 11a used to store the logical value "+1" in the product operation memory cell 10 is controlled by the word line 17a, and the memory cell 11b used to store the logical value "-1" in the product operation memory cell 10 is controlled by the word line 17b. The logical value held in the memory cell 11b is output from the node n3. The node n3 is connected to the gates of the NMOS transistors constituting the switches 12i and 12j.

[0048] Memory cell 11f has the same configuration as memory cell 11e, but the gate electrodes of transfer NMOS transistors N3 and N4 are connected to word line 17b, which is different from word line 17a. This makes it possible to write a logical value different from that of memory cell 11e to memory cell 11f by setting word line 17b to high level at a timing different from that of word line 17a. The logical value held in memory cell 11f is output from nodes n3 and n4. Nodes n3 and n4 are connected to the gates of NMOS transistors constituting switches 12o and 12p.

[0049] <Layout of multiplication memory cell (ME)> FIG. 6 is a plan view showing an example of the layout of the product operation memory cell shown in FIG.

[0050] The word lines (WL[1:0]) and input lines (IL[0]) are arranged to extend along the X direction. The data line pairs (BT[2:0], BB[2:0]), the common ground line (CVSS), the data line (PBL), and the data line (NBL) are arranged to extend along the Y direction, which is perpendicular to the X direction.

[0051] Switches 12o and 12p are arranged to the left of memory cell 11f, and a common ground line (CVSS) is arranged to the left of switches 12o and 12p. Memory cell 11e is arranged to the right of memory cell 11f, and switches 12g and 12h are arranged to the right of memory cell 11e.

[0052] Switches 12a and 12b are arranged to the left of memory cells 11a and 11b, switches 12i and 12j are arranged to the left of switches 12a and 12b, and switches 12k and 12l are arranged to the right of memory cells 11a and 11b.

[0053] A data line (NBL) is arranged to the left of memory cell 11d, and switches 12m and 12n are arranged to the left of the data line (NBL). A memory cell 11c is arranged to the right of memory cell 11d. A data line (PBL) is arranged to the right of memory cell 11c, switches 12e and 12f are arranged to the right of the data line (PBL), and switches 12c and 12d are arranged to the right of switches 12e and 12f.

[0054] The memory cells 11f and 11e for path switching and the memory cells 11d and 11c are arranged in pairs in the X direction, and the memory cells 11a and 11b for weighting are arranged in pairs in the Y direction. The complementary data lines (BT, BB) can be shared between adjacent memory cells.

[0055] The memory cells 11a and 11b for weighting and the memory cells 11f and 11e and the memory cells 11d and 11c for path switching are of different layouts. The former are so-called horizontal SRAM cells, and the latter are vertical SRAM cells.

[0056] In FIG. 6, the area surrounded by a solid line indicates wiring PO forming the gate electrode of a MOS transistor, and the area surrounded by a dashed line indicates a semiconductor region OD forming the source region or drain region of the MOS transistor. The area surrounded by a dashed line indicates metal wiring formed by the first metal wiring layer (conductive layer) M1. The area surrounded by a solid line and marked with an x ​​indicates a contact region CO. The contact region CO electrically connects, for example, two layers overlapping the contact region CO. The gate electrode portions are marked with the symbols of the PMOS transistor and NMOS transistor described in FIG. 5. The gate electrode portions marked with the symbols constitute the gate electrodes of the MOS transistors indicated by the symbols.

[0057] A memory cell 11e, which is a vertical SRAM cell, will be described. The gate electrodes of the PMOS transistors P1, P2 and the NMOS transistors N3, N4 constituting the memory cell 11e are arranged parallel to the X direction. The gate electrodes of the PMOS transistors P1 and P2 are extended to form the gate electrodes of the NMOS transistors N1 and NMOS transistors N2, respectively. That is, the gate electrodes of the PMOS transistors P1 and NMOS transistors N1 are integrally formed. The gate electrodes of the PMOS transistors P2 and NMOS transistors N2 are integrally formed. The gate electrodes of the PMOS transistors P1 and P2 are aligned in the Y direction. The gate electrodes of the NMOS transistors N1 to N4 are aligned in the Y direction. The adjacent memory cell 11f is arranged point-symmetrically with the memory cell 11e. The memory cells 11c and 11d are configured similarly to the memory cells 11e and 11f.

[0058] The memory cell 11a, which is a horizontal SRAM cell, will be described. The gate electrodes of the PMOS transistors P1, P2 and the NMOS transistors N3, N4 constituting the memory cell 11a are arranged parallel to the X direction. The gate electrodes of the PMOS transistors P1 and P2 are extended to form the gate electrodes of the NMOS transistors N1 and NMOS transistors N2, respectively. That is, the gate electrodes of the PMOS transistors P1 and NMOS transistors N1 are integrally formed. The gate electrodes of the PMOS transistors P2 and NMOS transistors N2 are integrally formed. The gate electrodes of the PMOS transistors P1 and P2 are aligned in the Y direction. The gate electrodes of the NMOS transistors N1 and N3 are aligned in the Y direction. The gate electrodes of the NMOS transistors N2 and N4 are aligned in the Y direction. The adjacent memory cell 11b is aligned symmetrically (mirror-inverted) with the memory cell 11a.

[0059] Since the memory cells 11a to 11f are composed of six SRAM cells, it is important to reduce the area overhead. The weight memory cells 11a and 11b are composed of horizontal cells in which the T nodes of the two cells appear on the same side, since only the T node is used for control. The path switching memory cells 11c to 11f are composed of vertical cells in which the T node and B node appear on the same side, since both the T node and the B node are used. This configuration can improve wiring efficiency and reduce the cell area. By configuring the memory cells using two types of SRAM layouts (vertical SRAM cells and horizontal SRAM cells) in combination, area efficiency can be improved.

[0060] <Writing a logical value to the multiplication memory cell (ME) and performing a multiplication operation> Returning to FIG. 5, writing a logical value to the product operation memory cell will be described.

[0061] When writing a logical value "+1" to the multiplication memory cell 10, a high level is supplied to the complementary data line 16c, a low level is supplied to the complementary data line 16d, and the word line 17a is set to a high level. This selects the memory cell 11a, turns on the transfer NMOS transistors N3 and N4 in the memory cell 11a, and supplies a low level to the input of the first inverter circuit IV1. As a result, the latch circuit in the memory cell 11a latches a state that makes the node n3 a high level state.

[0062] Next, a high level is supplied to the complementary data line 16d, a low level is supplied to the complementary data line 16c, and the word line 17b is set to a high level. This selects the memory cell 11b, turns on the transfer NMOS transistors N3 and N4 in the memory cell 11b, and supplies a high level to the input of the first inverter circuit IV1. As a result, the latch circuit in the memory cell 11b latches a state that makes the node n3 a low level state.

[0063] As a result, the switches 12a and 12b are turned on, and the switches 12i and 12j are turned off. If a logical value of "1" is written to the memory cells 11c and 11e, and if the input data (ID) supplied to the input line 15 is, for example, at a high level in this state, the switches 12c, 12d, 12e, and 12g are turned on. As a result, the switches 12e, 12c, 12a, and 12g form a current path that allows a current to flow from the data line 13a to the common power supply line 14.

[0064] Although the case where a logical value "+1" is written to the AND operation memory cell 10 has been described, the same applies to the case where a logical value "-1" and a logical value "0" are written. Here, it is assumed that a logical value "1" is written to the memory cells 11d and 11f. When a logical value "-1" is written to the AND operation memory cell 10, if the input data (ID) is at a high level, a current path connecting the data line 13b and the common power supply line 14 is formed by the switches 12m, 12k, 12i, and 12o. On the other hand, when a logical value "0" is written to the AND operation memory cell 10, even if the input data (ID) is at a high level, no current path is formed connecting the data lines 13a and 13b and the common power supply line 14.

[0065] <Sum operation> As shown in FIG. 2, a large number of multiplication memory cells (ME) 10 are connected to the data lines 13a and 13b. As a result, a current corresponding to the sum of the number of current paths formed in each multiplication memory cell 10 flows through the data lines 13a and 13b. That is, a current corresponding to the sum of the products on the logical value "+1" side flows through the data line 13a, and a current corresponding to the sum of the products on the logical value "-1" side flows through the data line 13b. As a result, the result of the multiplication and sum calculation on the logical value "+1" side is output to the data line 13a, and the result of the multiplication and sum calculation on the logical value "-1" side is output to the data line 13b. Therefore, the difference between the current in the data line 13a and the current in the data line 13b is analog-to-digital converted (A / D converted) to obtain the expected result of the multiplication and sum calculation. Of course, the currents flowing through the data lines 13a and 13b may be A / D converted to obtain the difference between the obtained digital signals.

[0066] The multiplication operation memory cell 10 stores three logical values, "+1", "0", and "-1", used in the sum-of-products operation. Therefore, it is possible to prevent data used in learning and inference from being compressed too much, and it is possible to improve the accuracy of learning and inference. Furthermore, it is possible to perform a large number of sum-of-products operations by changing the input data (ID) without changing the logical value stored in the multiplication operation memory cell 10. Therefore, it is possible to reduce the number of data transfer processes. Furthermore, since the sum operation is realized by each of the multiplication operation memory cells 10 drawing current from the data line 13a and the data line 13b, it is possible to perform multiple sum operations in one operation. This makes it possible to further reduce the number of data transfer processes and reduce power consumption.

[0067] <Current source (CS)> Returning to FIG. 3, the current source (CS) will be described.

[0068] A current source (CS) 102 constituted by PMOS transistors P3 to P6 is connected to one set of data lines 13a and 13b. The source-drain paths of the PMOS transistors P3 and P6 are connected between the data line 13a and a power supply of voltage (Vd), forming a bias circuit for biasing the data line 13a. The source-drain paths of the PMOS transistors P4 and P5 are connected between the data line 13b and a power supply of voltage (Vd), forming a bias circuit for biasing the data line 13b. A current is supplied to the data lines 13a and 13b via the current source 102.

[0069] <Common power switch (CVSW)> A ground potential (Vs) is supplied to the common power supply line (CVSS) 14 via a common power supply switch (CVSW) 103 shown in Fig. 3. The common power supply switch 103 is composed of an NMOS transistor N5, and a product-sum operation enable signal (MACE) is supplied to the gate of the NMOS transistor N5. A constant current source (CCS) may be connected instead of the ground potential (Vs).

[0070] <Sense amplifier (SA)> The data lines 13a and 13b are connected to a latch-type sense amplifier (SA) 104 via a pair of transfer switches. The pair of transfer switches is composed of NMOS transistors N7 and N8 controlled by a comparison enable signal (CE) and PMOS transistors P7 and P8 controlled by its inverted signal ( / CE).

[0071] The sense amplifier (SA) 104 is composed of an inverter circuit IV3 and an inverter circuit IV4 cross-connected thereto. The PMOS transistors P7, P8 and the NMOS transistors N7, N8 are turned on by a comparison enable signal (CE) and its inverted signal ( / CE). This amplifies and latches the potential difference between the data line 13a and the data line 13b, which is supplied via a pair of transfer switches. In other words, the sense amplifier 104 is a comparison circuit that compares the value of the current of the data line 13a with the value of the current of the data line 13b.

[0072] The output of the sense amplifier 104, which has a logical value of “1” or “0”, is supplied to an inference control circuit 105.

[0073] <Inference reference cell (IREF)> FIG. 7 is a diagram showing an example of the configuration of the inference reference cell shown in FIG.

[0074] The inference reference cell 20 has a structure similar to that of the multiplication memory cell 10. The difference is that the signal line (PL) 21a and the signal line (NL) 21b to which the selection signals (PS, NS) are supplied instead of the outputs of the memory cells 11a and 11b are connected to the switches 12a, 12b, 12i, and 12j. Also, the difference is that the signal line (RL) 25 to which the control signal (CD) is supplied instead of the input line (IL) 15 is connected. By making the inference reference cell 20 have a structure similar to that of the multiplication memory cell 10, the inference reference cell 20 has a driving force equivalent to that of the multiplication memory cell 10 with respect to the data line 13a and the data line 13b. The inference reference cell 20 also has an adjustment function for switching the current path.

[0075] <Reference cell for adjustment (TREF)> FIG. 8 is a diagram showing a configuration example of the adjustment reference cell shown in FIG.

[0076] The adjustment reference cell 30 has a structure similar to that of the product operation memory cell 10. It differs in that selection switches 31a and 31b are arranged between the data line 13a and the switches 12e and 12f. It also differs in that selection switches 32a and 32b are arranged between the data line 13b and the switches 12m and 12n. It also differs in that the switches 12e, 12f, 12m, and 12n are connected to a common node n6. It also differs in that a signal line (TL) 35 to which a control signal (TCD) is supplied is connected instead of the input line (IL) 15.

[0077] When the selection signal (TPE) supplied to the signal line 33a is at a high level and the selection signal (TPEB) supplied to the signal line 33b is at a low level, the switches 31a and 31b connect the switches 12e, 12f, 12m, and 12n to the data line 13a. When the selection signal (TNE) supplied to the signal line 34a is at a high level and the selection signal (TNEB) supplied to the signal line 34b is at a low level, the switches 32a and 32b connect the switches 12e, 12f, 12m, and 12n to the data line 13b.

[0078] By making the adjustment reference cell 30 have a structure similar to that of the product operation memory cell 10, the adjustment reference cell 30 is made to have a driving force equivalent to that of the product operation memory cell 10 with respect to the data lines 13a and 13b.

[0079] The adjustment reference cell 30 has a function of switching current paths using multiple memory cells, similar to the product operation memory cell 10. Furthermore, since the adjustment reference cell 30 is not used for product-sum operations, all six memory cells can be used for path switching. By providing selection switches 31a, 31b, 32a, and 32b connected to the data lines 13a and 13b, eight current paths can be selected. A circuit configuration that allows path switching can achieve a current value close to that of the product operation memory cell.

[0080] <Fine-tuning cell (FT)> Fig. 9 is a diagram showing an example of the configuration of the fine-tuning cell shown in Fig. 3. The fine-tuning cell 40 is used to determine the magnitude of a current.

[0081] The fine-tuning cell 40 includes NMOS transistors N14 to N17 and NMOS transistors N18_1 to N18_n. The source-drain paths of the NMOS transistors N14 to N17 are connected in series between the data line 13a and the data line 13b. The source-drain paths of the NMOS transistors N18_1 to N18_n are connected in series between a node connecting the NMOS transistors N15 and NMOS transistors N16 and the common power supply line 14. A signal line (FL) 41 to which a control signal (FTL) is supplied is connected to the gate electrodes of the NMOS transistors N14 and N17. A signal line (FPL) 42a to which a selection signal (FTPS) is supplied is connected to the gate of the NMOS transistor N15. A signal line (FNL) 42b to which a selection signal (FTNS) is supplied is connected to the gate of the NMOS transistor N16, and a power supply line 43 to which a power supply voltage (Vd) (or a pulsed control signal) is supplied is connected to the gates of the NMOS transistors N18_1 to N18_n.

[0082] Since it has NMOS transistors N18_1 to N18_n connected in series in multiple stages, it is possible to pass a minute amount of current to the data line 13a and data line 13b selected by the signal lines 42a and 42b. By providing a plurality of fine-tuning cells (FT) 40 with different numbers of series stages (the number of NMOS transistors N18_1 to N18_n), it is possible to select a plurality of minute current values. For example, the minute current value is 1%, 2%, 5%, etc. of the current of the product operation memory cell 10. Incidentally, by providing a fine-tuning cell 40 with a current of about 50% of the current of the product operation memory cell 10, it can also be used to judge the magnitude of the current between the product operation memory cell 10 and the inference reference cell 20, which will be described later.

[0083] Using an example, the operation of A / D conversion in the memory cell array 101 will be described with reference to Figures 7 and 10. Figure 10 is a diagram for explaining the A / D conversion. The A / D conversion is controlled by the inference control circuit 105, and is performed in eight steps.

[0084] ​The inference reference cell 20 is controlled by eight control signals (CD[7:0]) output from the inference control circuit 105. In the example shown in FIG. 10, one reference cell 20 is connected to a signal line through which the control signal (CD[0]) is supplied. Two reference cells 20 are connected to a signal line through which the control signal (CD[1]) is supplied. Four reference cells 20 are connected to a signal line through which the control signal (CD[2]) is supplied. Eight reference cells 20 are connected to a signal line through which the control signal (CD[3]) is supplied. Sixteen reference cells 20 are connected to a signal line through which the control signal (CD[4]) is supplied. Thirty-two reference cells 20 are connected to a signal line through which the control signal (CD[5]) is supplied. Sixty-four reference cells 20 are connected to a signal line through which the control signal (CD[6]) is supplied. That is, the control signals (CD[6:0]) are weighted. In order to detect a difference of 1 or less, a reference cell 20 (hereinafter referred to as a 0.5 cell) with half the driving force of a single cell is connected to a signal line through which a control signal (CD[7]) is supplied.

[0085] As an example, a case will be described in which the sum-of-products value on the "+1" side is "32" and the sum-of-products value on the "-1" side is "21" by the sum-of-products operation. That is, the current on the data line 13a indicates the sum-of-products value "32" (#PBL=32), and the current on the data line 13b indicates the sum-of-products value "21" (#NBL=21). In this case, the difference between the sum-of-products is "11". Output data (MQ[0]) corresponding to this difference is output from the AD conversion control logic unit (ADC) 105a of the inference control circuit 105.

[0086] In the first step (1st), the sense amplifier 104 as a comparison circuit compares the currents of the data lines 13a and 13b. Since "32">"21", the control logic unit 105a outputs the logical value "0" indicating the sign "+" as the output data (MQ[0]). Also, since the current of the data line 13a is larger, the control logic unit 105a sets the selection signal (NS) to a high level and the selection signal (PS) to a low level. Furthermore, the control logic unit 105a sets the data line 13a in a state in which 0.5 cells can be connected, and sets the data line 13b in a state in which a specified number of inference reference cells 20 can be connected. The specified number here is "64". Here, by setting the selection signal (NS) supplied to the signal line 21b of the specified inference reference cell 20 to a high level, the switches 12k and 12l are turned on, and the common power supply line (CVSS) can be connected to the data line 13b via the switch of the specified inference reference cell 20. Also, by setting the selection signal (PS) supplied to the signal line 21a of the 0.5 cell to a high level, the switches 12a and 12b are turned on, and the common power supply line (CVSS) can be connected to the data line 13a via the switch of the 0.5 cell. After this, by setting the signal line (RL) 25 to a high level, the switches 12c, 12d, 12k, and 12l are turned on, and the common power supply line (CVSS) is connected to the data line via the switch. This state is called the cell being connected to the data line.

[0087] In the second step (2nd), the control logic unit 105a turns on the switches 12c and 12d in the 0.5 cell via the signal line (RL) 25, and the 0.5 cell is connected to the data line 13a. The control logic unit 105a also turns on the switches 12k and 12l in the 64 inference reference cells 20 via the signal line (RL) 25, and connects the 64 inference reference cells to the data line 13b. As a result, the value in the data line 13a becomes "32+α", and the value in the data line 13b becomes 21+64=85. Here, α is a current value added by the 0.5 cell and is a value smaller than 1. The sense amplifier 104 compares this "32+α" with "85". As a result of the comparison, the value of the data line 13b becomes larger, and the control logic unit 105a outputs the logical value "0" as the output data (MQ[0]).

[0088] In the third step (3rd), the control logic unit 105a specifies "32", half of "64", as the specified number, and turns on the switches 12k and 12l by the control signal (CD) supplied to the signal line 25. As a result, the value of the data line 13a remains the same as before, "32+α", but the value of the data line 13b becomes 21+32=53. Because a comparison by the sense amplifier 104 determines that the value of the data line 13b is larger, the control logic unit 105a outputs the logical value "0" as the output data (MQ[0]).

[0089] In the fourth step (4th), the control logic unit 105a specifies "16" as the number of inference reference cells 20. As a result, the value of the data line 13a is the same as before, "32+α", but the value of the data line 13b becomes 21+16=37. Since the value of the data line 13b is determined to be larger by comparison by the sense amplifier 104, the control logic unit 105a outputs the logical value "0" as the output data (MQ[0]).

[0090] In the fifth step (5th), the control logic unit 105a also specifies the number of reference cells 20 for inference and outputs a control signal (CD) to the signal line 25, as in the fourth step (4th). However, in the fifth step (5th), half the number of reference cells 20 for inference is specified, that is, "8". This causes the sense amplifier 104 to compare the value "32+α" on the data line 13a with the value 21+8=29 on the data line 13b. In the fifth step (5th), the value on the data line 13a becomes greater than the value on the data line 13b, so the control logic unit 105a outputs a logical value "1" as output data (MQ[0]).

[0091] In the fifth step (5th), "8" was added to the value on the data line 13b, but the value on the data line 13a became larger than the value on the data line 13b. In the sixth step (6th), the control logic unit 105a specifies "8+4=12" as the number of inference reference cells 20. As a result, the value on the data line 13a is the same as before, "32+α", but the value on the data line 13b becomes 21+12=33. As a result of comparison by the sense amplifier 104, it is determined that the value on the data line 13b is larger, the control logic unit 105a outputs the logical value "0" as the output data (MQ[0]).

[0092] In the seventh step (7th), the control logic unit 105a specifies "8+2=10" as the number of inference reference cells 20. As a result, the value of the data line 13a is the same as before, "32+α", but the value of the data line 13b becomes 21+10=31. Since the sense amplifier 104 determines that the value of the data line 13a is greater than the value of the data line 13b by comparison, the control logic unit 105a outputs the logical value "1" as the output data (MQ[0]).

[0093] In the seventh step (7th), "8+2" was added to the value on the data line 13b, but the value on the data line 13a became larger than the value on the data line 13b. In the eighth step (8th), the control logic unit 105a specifies "8+2+1=11" as the number of inference reference cells 20. As a result, the value on the data line 13a is the same as before, "32+α", but the value on the data line 13b becomes 21+11=32. Since the sense amplifier 104 determines by comparison that the value on the data line 13a is larger than the value on the data line 13b, the control logic unit 105a outputs the logical value "1" as the output data (MQ[0]).

[0094] As described above, the current values ​​of the data lines 13a and 13b are compared while changing the number of reference cells 20 to be specified for inference. When the value of the data line 13a is greater than the value of the data line 13b as a result of the comparison, the control logic unit 105a outputs a logical value of "1" as output data (MQ[0]). When the value of the data line 13b is greater than the value of the data line 13a, the control logic unit 105a outputs a logical value of "0" as output data (MQ[0]).

[0095] This converts the result of the multiply-and-accumulate operation into a serial 8-bit signal. The first bit is a sign bit, and the bits are output sequentially from the most significant bit to the least significant bit. In the example shown in Figure 10, the output (Output), which is the result of the AD conversion, is 0b0000_1011=11 (=32-21).

[0096] In this way, the dichotomy method is used to search for the difference in current between data line 13a and data line 13b, and the result is converted into a serial digital signal and output. When the data length of the output data (MQ[0]) shown in Figure 10 reaches the data length desired by the user, the process can be terminated. This makes it possible to reduce the power and time required for unnecessary A / D conversion.

[0097] Since the method involves adding the current of the reference cell to the current of the data line with the smaller current and comparing them using a dichotomy method, if there are many product operation memory cells connected to the data lines, the current variations of the product operation memory cells are superimposed and a larger level of error occurs. This will be explained using Figure 11. Figure 11 is a diagram for explaining A / D conversion when an error occurs.

[0098] 10, a case will be described in which the product-sum value on the "+1" side is "32" and the product-sum value on the "-1" side is "21" by the product-sum operation. Due to the variation in memory cell current, the value of data line 13a decreases by β as indicated by the right-facing arrow "→", and the value of data line 13b increases by γ as indicated by the left-facing arrow "←". In other words, the value of data line 13a becomes "32-β" and the value of data line 13b becomes "21+γ".

[0099] 11, the effect of the variation in memory cell current does not appear until the fourth step (4th). The first to fourth steps are the same as those shown in FIG.

[0100] In the fifth step (5th), the control logic unit 105a specifies "8" as the number of inference reference cells 20. As a result, the value of the data line 13b becomes 21+γ+8=29+γ. The value of the data line 13a is "32+α-β". Here, for example, if 0<α<1, β=4, and γ=3, the value of the data line 13a "32+α-β" becomes "28+α", and the value of the data line 13b "29+γ" becomes "32". Since 0<α<1, the value of the data line 13b is determined to be larger by the comparison of the sense amplifier 104, and the control logic unit 105a outputs the logical value "0" as the output data (MQ[0]).

[0101] In the sixth step (6th), the number of the reference cells 20 for inference is also specified as half, i.e., "4". As a result, the value of the data line 13b becomes 21+γ+4=25+γ. The value of the data line 13a is "32+α-β". Since β=4 and γ=3, the value of the data line 13a, "32+α-β", becomes "28+α", and the value of the data line 13b, "25+γ", becomes "28". Since 0<α<1, the value of the data line 13a becomes larger than the value of the data line 13b by comparison by the sense amplifier 104, and the control logic unit 105a outputs the logical value "1" as the output data (MQ[0]).

[0102] In the seventh step (7th), the control logic unit 105a specifies "4+2=6" as the number of inference reference cells 20. As a result, the value of the data line 13a is "32+α-β" as before, but the value of the data line 13b is 21+γ+6=27+γ. Since β=4 and γ=3, the value of the data line 13a, "32+α-β", becomes "28+α", and the value of the data line 13b, "27+γ", becomes "30". Since 0<α<1, the value of the data line 13b is determined to be larger by the comparison of the sense amplifier 104, and the control logic unit 105a outputs the logical value "0" as the output data (MQ[0]).

[0103] In the eighth step (8th), the control logic unit 105a specifies "4+1=5" as the number of inference reference cells 20. As a result, the value of the data line 13a is "32+α-β" as before, but the value of the data line 13b is 21+γ+5=26+γ. Since β=4 and γ=3, the value of the data line 13a, "32+α-β", becomes "28+α", and the value of the data line 13b, "26+γ", becomes "29". Since 0<α<1, the value of the data line 13b is determined to be larger by the comparison of the sense amplifier 104, and the control logic unit 105a outputs the logical value "0" as the output data (MQ[0]).

[0104] In the example shown in FIG. 11, the output (Output) that is the result of AD conversion is 0b0000_0100=4, which is different from the normal value "32-21=11" and an error occurs.

[0105] <Adjustment operation> The current adjustment of the product operation memory cell 10 and the inference reference cell 20 using the adjustment reference cell 30 and the fine adjustment cell 40 will be described with reference to FIGS. 12(a), 12(b) and 13 to 15. FIG.

[0106] FIG. 12(a) is a diagram for explaining a current comparison of a product operation memory cell and an adjustment reference cell. FIG. 12(b) is a diagram for explaining a current comparison of a product operation memory cell, an adjustment reference cell, and a fine adjustment cell. FIG. 12(a) and FIG. 12(b) show an example in which there are (N+1) product operation memory cells (ME[N:0]) 10 and (M+1) inference reference cells (IREF[M:0]) 20. Here, N and M are natural numbers. FIG. 13 is a diagram showing a current path of a product operation memory cell (ME[0]). FIG. 14 is a diagram showing a current path of an adjustment reference cell. FIG. 15 is a diagram showing a current path of a fine adjustment cell.

[0107] (Step 0) A logic value of "0" is written into all the product operation memory cells 10 and the memory cells 11c to 11f for path selection of the inference reference cell 20 to perform initialization.

[0108] (Step 1) One multiplication memory cell 10 or one inference reference cell 20 is selected, and the data line 13a or data line 13b connected by the weight memory cells 11a and 11b is selected. As an example, as shown in FIG. 12(a), the multiplication memory cell (ME[0]) is selected. As shown in FIG. 13, the logical value "1" is written in the weight memory cell 11a and the logical value "0" is written in the memory cell 11b, and the data line 13a is connected. Since the logical value "0" is written in the memory cells 11c to 11f, a current path is formed as shown by the thick solid line in FIG. 13.

[0109] (Step 2) A comparison operation is performed by connecting the adjustment reference cell 30 to a data line side different from the data line to which the product operation memory cell 10 as the adjustment target cell or the inference reference cell 20 is connected. At this time, the fine adjustment cell 40 is not connected to either of the data lines 13a and 13b by a control signal (FTL). The magnitude of the current value of the data line 13a and the current value of the data line 13b are judged by a sense amplifier 104 connected to the data lines 13a and 13b, and the output of the sense amplifier 104 is stored in a register.

[0110] In step 1, since the data line 13a of the product operation memory cell 10 is selected, the data line 13b is selected in the adjustment reference cell 30. That is, the selection signals (TNE) and (TPEB) are set to high level, and the selection signals (TNEB) and (TPE) are set to low level, and the data line 13b is connected. As shown in Fig. 14, for example, a logical value "0" is written in the memory cell 11a, and a logical value "1" is written in the memory cell 11b. Since a logical value "0" is written in the memory cells 11c to 11f, a current path is formed as shown by the thick solid line in Fig. 14.

[0111] (Step 3) The comparison operation is performed again with the fine-tuning cell 40 connected to the data line side with the smaller current flowing based on the first comparison result in step 2. If the current values ​​of the adjustment reference cell 30 and the product operation memory cell 10 are very close, the comparison result will change due to the current addition of the fine-tuning cell 40, and this is detected to determine that the adjustment reference cell 30 and the product operation memory cell 10 match.

[0112] 12(b), the current flowing through the data line 13b is small, and the data line 13b is selected in the fine-tuning cell 40. That is, the control signal (FTL) and the selection signal (FTNS) are set to a high level, the data line 13b is connected, and a current path is formed as shown by the thick solid line in FIG.

[0113] (Step 4) If the currents of the product operation memory cell 10 and the adjustment reference cell 30 match, the process proceeds to the next cell, and adjustments are made from step 1 onwards. If they do not match, the logical values ​​written in the path selection memory cells 11c to 11f are changed to switch the path in the relevant cell, and the operations from step 2 onwards are repeated. A current path of the product operation memory cell 10 whose current matches that of the adjustment reference cell 30 is searched for. If the current does not match that of the adjustment reference cell 30 even after searching all current paths of the product operation memory cell 10 or the inference reference cell 20 selected in step 1, the logical values ​​of the memory cells 11a to 11f of the adjustment reference cell 30 are changed to switch the current path in the adjustment reference cell, and path selections of all product operation memory cells 10 and inference reference cells 20 from step 0 onwards are redone.

[0114] In this manner, the currents of all the product operation memory cells (ME[N:0]) and the inference reference cells (IREF[M:0]) are adjusted based on the current path of one adjustment reference cell.

[0115] According to the embodiment, one or more of the following advantages can be obtained.

[0116] (1) The characteristic values ​​of the product operation memory cell and the inference reference cell can be changed by switching the path.

[0117] (2) The characteristic values ​​of the product operation memory cell and the inference reference cell can be maintained by the memory cell as a data holding circuit.

[0118] (3) Since the variation in the product operation memory cell current can be reduced, it is possible to prevent malfunctions during inference.

[0119] (4) By making periodic adjustments, it is possible to prevent malfunctions caused by deterioration of transistors over time.

[0120] (5) The operating conditions can be adjusted to suit the operating environment, such as temperature, which can improve reliability.

[0121] <Modification> Below, some representative modified examples of the embodiment are exemplified. In the following description of the modified examples, the same reference numerals as those in the above-mentioned embodiment may be used for parts having the same configuration and function as those described in the above-mentioned embodiment. The description of such parts may be appropriately cited within the scope of technical inconsistency. Furthermore, a part of the above-mentioned embodiment and all or a part of the multiple modified examples may be appropriately applied in a composite manner within the scope of technical inconsistency.

[0122] (First Modification) 16 is a circuit diagram showing a configuration of a multiplication memory cell 10 in the first modified example. The multiplication memory cell 10 in the first modified example is an example of a cell that is compatible with capacitance sensing in order to perform AD conversion using capacitance (sum operation is performed with voltage (capacitance)).

[0123] The multiplication memory cell 10 in the first modification includes four memory cells (MC) 11a, 11b, 11e, and 11f, switches 12a and 12i corresponding to the memory cells 11a and 11b, and switches 12c and 12k controlled based on input data (ID) supplied to an input line (IL). The multiplication memory cell 10 further includes switches 12g and 12o corresponding to the memory cells 11e and 11f, a main capacitance element 18a, and adjustment capacitance elements 18b and 18c corresponding to the memory cells 11e and 11f. The capacitance value of the main capacitance element 18a is Ca, the capacitance value of the capacitance element 18b is Cb, and the capacitance value of the capacitance element 18c is Cc. Cb,Cc< <Caである。

[0124] As described in FIG. 4, memory cell 11a is used to store a logical value "+1" in product operation memory cell 10, and memory cell 11b is used to store a logical value "-1" in product operation memory cell 10. The switch 12a is supplied with the output of memory cell 11a. The switch 12i is supplied with the output of memory cell 11b. The switch 12g is supplied with the output of memory cell 11e. The switch 12o is supplied with the output of memory cell 11f. The switch 12c is supplied with input data (ID). The switch 12k is supplied with input data (ID).

[0125] A node n5, which is a connection point between the switch 12a and the switch 12f, is connected to one electrode of the main capacitance element 18a. The node n5 is connected to one electrode of the capacitance element 18b via the switch 12g, and the node n5 is connected to one electrode of the capacitance element 18c via the switch 12o. A common power supply line (CVSS) is connected to the other electrodes of the main capacitance element 18a, the capacitance element 18b, and the capacitance element 18c. The node n5 is connected to the data line 13a via the switches 12a and 12c, and is connected to the data line 13b via the switches 12i and 12k. A precharge circuit (not shown) to which a power supply voltage (Vd) is supplied is connected to the common power supply line 14. A precharge circuit (not shown) to which a power supply voltage (Vd) is supplied is also connected to the data line 13a and the data line 13b.

[0126] When the input data (ID) is at a low level, the switches 12c and 12k are in an off state, and one electrode of the main capacitance element 18a is electrically isolated from the data line 13a and the data line (NBL) 13b.

[0127] Next, when the input data (ID) becomes high level, the switches 12c and 12k are turned on so as to electrically connect the data lines 13a and 13b to one electrode of the main capacitance element 18a. When the logical value "1" is stored in the memory cell 11a and the switch 12a is turned on, the main capacitance element 18a is connected to the data line 13a. This causes charge dispersion between the parasitic capacitance 19a of the data line 13a and the main capacitance element 18a, and the voltage of the data line 13a is determined. When the logical value "1" is stored in the memory cell 11b and the switch 12i is turned on, the main capacitance element 18a is connected to the data line 13b. This causes the voltage of the data line 13b to be determined by charge dispersion between the main capacitance element 18a and the parasitic capacitance 19b of the data line 13b.

[0128] Next, cases where the result of the multiplication operation in the multiplication operation memory cell 10 is "0", "+1" and "-1" will be described.

[0129] The result of the multiplication operation is "0" when the input data (ID) is "0" or when the stored data in both memory cells 11a and 11b is "0". At this time, the switches 12c and 12k are turned off or the switches 12a and 12i are turned off. This disconnects the main capacitance element 18a from the data lines 13a and 13b.

[0130] On the other hand, the result of the multiplication operation becomes "+1" when the input data (ID) is "1", the stored data in memory cell 11a is "1", and the stored data in memory cell 11b is "0". At this time, switches 12c and 12k are turned on, switch 12a is turned on, and switch 12i is turned off. As a result, main capacitance element 18a is connected to data line 13a and disconnected from data line 13b.

[0131] Moreover, the result of the multiplication operation becomes "-1" when the input data (ID) is "1", the stored data in memory cell 11a is "0", and the stored data in memory cell 11b is "1". At this time, switches 12c and 12k are turned on, switch 12a is turned off, and switch 12i is turned on. As a result, main capacitance element 18a is disconnected from data line 13a and connected to data line 13b.

[0132] A plurality of multiplication memory cells 10 are connected to the data lines 13a and 13b. Therefore, the difference between the number of main capacitance elements 18a charged to the power supply voltage (Vd) connected to the data line 13a and the number of main capacitance elements 18a charged to the power supply voltage (Vd) connected to the data line 13b is the sum-of-products result. In this case, since no current flows, the determination is made with high impedance (Hi-Z). During inference, the sum-of-products operation is performed using the capacitance of the multiplication memory cell 10 that is conductive with the parasitic capacitance 19a of the data line 13a and the parasitic capacitance 19b of the data line 13b. Specifically, the voltage difference between the data lines 13a and 13b is the sum-of-products result.

[0133] In order to adjust the variation in capacitance of the main capacitance element 18a connected to the data line 13a and the data line 13b, adjustment capacitance elements 18b and 18c are connected to the main capacitance element 18a, and an appropriate composite capacitance is configured by path switching. With this configuration, it is possible to switch between four types of capacitance for the data line 13a and the data line 13b. The details will be described below.

[0134] When the memory cell 11e stores a logical value of "0" and the memory cell 11f stores a logical value of "0", the switches 12g and 12o are turned off, so that only one electrode of the main capacitance element 18a is connected to the node n5.

[0135] When the memory cell 11e stores a logical value of "1" and the memory cell 11f stores a logical value of "0," the switch 12g is turned on and the switch 12o is turned off, thereby connecting one electrode of the main capacitance element 18a and one electrode of the capacitance element 18b to the node n5.

[0136] When the memory cell 11e stores a logical value of "0" and the memory cell 11f stores a logical value of "1," the switch 12g is turned off and the switch 12o is turned on, thereby connecting one electrode of the main capacitance element 18a and one electrode of the capacitance element 18c to the node n5.

[0137] When the memory cell 11e stores a logical value of "1" and the memory cell 11f stores a logical value of "1", the switch 12g is turned on and the switch 12o is turned on, thereby connecting one electrode of the main capacitance element 18a, one electrode of the capacitance element 18b, and one electrode of the capacitance element 18c to the node n5.

[0138] In this modification, capacitance determination is used, but the characteristic value can be changed as in the embodiment, and the value can be maintained by the memory cell. Also, by using the adjustment function, it is possible to prevent malfunction during inference by adjusting the characteristics of multiple product operation memory cells connected to the same data line to a reference value.

[0139] (Second Modification) FIG. 17 is a diagram showing the configuration of a product operation memory cell in the second modified example.

[0140] In the embodiment, one weight memory cell 11a is arranged on the data line 13a side, and one weight memory cell 11b is arranged on the data line 13b side. On the other hand, in the second modified example, multiple weight memory cells are arranged on each of the data line 13a side and the data line 13b side.

[0141] Four weighting memory cells 11a0-11a3 are arranged on the data line 13a side, and their outputs are supplied to four AND circuits AN0-AN3. Column selection signal lines WS0-WS3 are supplied to the AND circuits AN0-AN3, respectively. The AND circuits AN0-AN3 perform logical AND, and the outputs are output to the OR circuit OR1. The OR circuit OR1 performs logical OR, and the output is output to the AND circuit AN4. The input data (ID) is supplied to the AND circuit AN4 via the input line 15. The AND circuit AN4 performs logical AND, and the output is supplied to the switches 12a and 12b.

[0142] Four weighting memory cells 11b0-11b3 are arranged on the data line 13b side, and their outputs are supplied to four AND circuits AN5-AN8. Column selection signal lines WS0-WS3 are supplied to the AND circuits AN5-AN8, respectively. The AND circuits AN5-AN8 perform logical product, and the outputs are output to an OR circuit OR2. The OR circuit OR2 performs logical sum, and the output is output to an AND circuit AN9. Input data (ID) is supplied to the AND circuit AN9 via an input line 15. The AND circuit AN9 performs logical product, and the outputs are supplied to the switches 12i and 12j.

[0143] For example, when the column selection signal line WS0 is set to a high level to select the memory cells 11a0 and 11b0, a multiplication operation is performed between the logical values ​​stored in the memory cells 11a0 and 11b0 and the logical value of the input data (ID). Then, a sum operation is performed between the result of the multiplication operation and the current value in the data line 13a and the current value in the data line 13b. At this time, the column selection signal lines WS1 to WS3 are set to a low level to prevent the memory cells 11a1 to 11a3 and 11b1 to 11b3 from being selected.

[0144] Since multiple weight memory cells are arranged and columns can be selected, the bit width of the weight memory cells can be adjusted, which can greatly reduce the area.

[0145] (Third Modification) FIG. 18 is a diagram showing the configuration of a product operation memory cell in the third modified example.

[0146] In the multiplication memory cell 10 in the third modification, instead of the weight memory cells 11a and 11b in the multiplication memory cell 10 in the embodiment, multiple weight wirings PW and NW from an SRAM macro arranged outside the memory array 101 are used. One of the multiple weight wirings PW on the data line 13a side is connected to the gates of the NMOS transistors constituting the switches 12a and 12b. One of the multiple weight wirings NW on the data line 13b side is connected to the gates of the NMOS transistors constituting the switches 12i and 12j. The weight wirings PW and NW are provided in a number corresponding to the multiplication memory cells 10 included in the memory array 101, and calculation is performed by simultaneously inputting weight data to the multiple multiplication memory cells 10. For example, 32 weight wirings PW and NW are provided.

[0147] It may be more advantageous in terms of area to hold the weight data in an SRAM macro outside the product operation memory cell and supply it directly from there, rather than having a memory cell for weights inside the product operation memory cell as in the embodiment.

[0148] (Fourth Modification) FIG. 19 is a diagram showing the configuration of an adjustment reference cell in the fourth modified example.

[0149] The adjustment reference cell 30 in the embodiment has switches 31a and 31b for selecting the data line 13a side and switches 32a and 32b for selecting the data line 13b side in the cell. Therefore, it does not have exactly the same configuration as the multiplication memory cell 10, and a certain deviation in the current value occurs.

[0150] The adjustment reference cell 30 in the fourth modification is configured by connecting two P-side adjustment reference cells 30a and N-side adjustment reference cells 30b, which have exactly the same configuration as the product operation memory cell 10, to the data lines 13a and 13b, respectively. This makes it possible to bring the current value of the adjustment reference cell 30 even closer to that of the product operation memory cell 10, enabling more precise product-sum operation than in the embodiment. It is possible to prevent malfunctions during inference. Note that the P-side adjustment reference cell 30a and the N-side adjustment reference cell 30b are adjusted to each other before starting adjustment of the product operation memory cell 10.

[0151] (Fifth Modification) Fig. 20 is a diagram showing the configuration of a memory cell array in the fifth modified example. Fig. 21 is a diagram showing voltages on data lines and common power supply lines in an embodiment. Fig. 22 is a diagram showing voltages on data lines and common power supply lines in the fifth modified example. The horizontal axis of the graphs in Figs. 21 and 22 is time (TIME) and the vertical axis is voltage (VOLTAGE).

[0152] The common power switch 103 in the embodiment is composed of one switch. The common power switch 103 in the fifth modified example is composed of multiple switches 103a and 103b connected in parallel. The multiple switches 103a and 103b are composed of NMOS transistors with different driving powers. The switches 103a and 103b are connected to the common power line 14 via switches SWa and SWb.

[0153] During adjustment, only one cell, such as a product operation memory cell and an inference reference cell, is always conductive, and the data line 13a or data line 13b is discharged. During actual inference, the number of conductive cells differs for each operation, and the potential of the common power supply line (CVSS) differs. As shown in FIG. 21, the difference between the potential of the common power supply line (CVSS) when there are few conductive cells during inference (IS) and the potential of the common power supply line (CVSS) during adjustment (TU) is small. The difference between the potential of the common power supply line (CVSS) when there are many conductive cells during inference (IM) and the potential of the common power supply line (CVSS) during adjustment (TU) is large. For this reason, even if the currents are made uniform during adjustment, the current value may deviate depending on how the body bias is applied during inference.

[0154] For example, during inference, switch SWa is turned on and switch SWb is turned off, and switch 103a is used. During adjustment, switch SWa is turned off and switch SWb is turned on, and switch 103b is used. The gate width of the NMOS transistor constituting switch 103b is set smaller than the gate width of the NMOS transistor constituting switch 103a.

[0155] Since the accuracy is likely to decrease when the number of conductive cells is large, switch 103b is used to reduce the difference between the potential of the common power supply line (CVSS) when the number of conductive cells at inference is large (IM) and the potential of the common power supply line (CVSS) at adjustment (TU) as shown in Fig. 22. Note that although the difference between the potential of the common power supply line (CVSS) when the number of conductive cells at inference is small (IS) and the potential of the common power supply line (CVSS) at adjustment (TU) becomes large, the effect on accuracy when the number of conductive cells is small is small.

[0156] During adjustment, common power switches of different sizes are used to reproduce the situation during inference when there are a large number of conductive cells, which makes it possible to prevent malfunctions during inference.

[0157] (Sixth Modification) Fig. 23 is a diagram showing the configuration of a product operation memory cell in the sixth modified example. The horizontal axis of the graph in Fig. 23 is time (TIME), and the vertical axis is voltage (VOLTAGE).

[0158] SRAM memory has two operating modes: normal operation mode (NO_M) and resume standby (RS) mode (RS_M). Normal operation mode is the operating mode when reading and writing data. RS mode is an operating mode that reduces power consumption by reducing the power supply voltage to a level that does not cause data loss while retaining written data. The power supply voltage is reduced by setting the potential of the ground wiring of the memory array to a potential higher than the ground potential (0V) (a potential between the power supply potential and the ground potential).

[0159] In the embodiment, the sources of the NMOS transistors N1 and N2 of the SRAM memory constituting the memory cells 11a to 11f are supplied with a ground potential (Vs), and the inference operation is performed in the normal mode. In this modification, the inference operation (MAC) is performed in the RS mode.

[0160] In this modification, a current source CSm is connected to node n5 to which the sources of NMOS transistors N1 and N2 of the SRAM memory constituting memory cells 11a to 11f are connected. In the RS mode, the driving force of the current source CSm is reduced to make the potential of node n5 higher than the ground potential (Vs) to change the source bias. This makes it possible to reduce the subthreshold leakage current of the MOS transistors in the off state constituting memory cells 11a to 11f.

[0161] Of the gates of the NMOS transistors connected to nodes n3 and n4 that hold the complementary data (T, B) of the memory cells 11a to 11f, the high level (H) side is not affected, and the low level (L) side is kept in a cutoff state, so there is no effect on inference, and leakage power can be reduced. This will be explained below.

[0162] For example, in the memory cell 11e, the node n3 that holds the complementary data (T) is on the high level side, and the node n4 that holds the complementary data (B) is on the low level side. Even when the normal operation mode is switched to the RS mode, the node n3 maintains a high level (H) potential, and the potential of the gate of the NMOS transistor that constitutes the switch 12g is maintained, so that the cell current (I C ) is not affected. When the node n4 is in the RS mode, the low level (L) potential rises, but the NMOS transistor constituting the switch 12h remains cut off, so the leakage current (I L ) is not affected by inferences.

[0163] The disclosure made by the present inventors has been specifically described above based on the embodiments, but it goes without saying that the present disclosure is not limited to the above-described embodiments and can be modified in various ways without departing from the gist of the disclosure. [Explanation of symbols]

[0164] 10. Multiplication operation memory cell (memory cell) 11a...Memory cell (first data retention circuit) 11b memory cell (second data retention circuit) 11e, 11c...Memory cell (third data retention circuit) 11f, 11d...Memory cell (fourth data retention circuit) 12a~12p···switch 13a Data line (PBL, first data line) 13b Data line (NBL, second data line) 15 Input line (IL) 104 Sense amplifier (comparison circuit) 130 AI accelerator (semiconductor device)

Claims

1. A first data line; A second data line; a memory cell connected to the first data line and the second data line; a determination circuit connected to the first data line and the second data line; Equipped with The memory cell includes: a plurality of switches connected to the first data line and the second data line; a first data retention circuit; a second data retention circuit; a third data retention circuit; a fourth data retention circuit; An input line, Equipped with a switch among the plurality of switches connected to the first data line is controlled based on the value held by the first data holding circuit and the input data supplied to the input line, and a switch among the plurality of switches connected to the second data line is controlled based on the value held by the second data holding circuit and the input data supplied to the input line, thereby performing a multiplication operation; A semiconductor device in which a characteristic value of the memory cell can be changed by controlling one of the plurality of switches connected to the first data line based on a value held by the third data retention circuit, and controlling one of the plurality of switches connected to the second data line based on a value held by the fourth data retention circuit.

2. 2. The semiconductor device according to claim 1, a plurality of the memory cells are connected to the first data line and the second data line; input data is supplied in parallel to the input lines of each of the plurality of memory cells; In the plurality of memory cells, a result of a multiplication operation of the input data and the data stored in the first data holding circuit and the second data holding circuit is output to the first data line and the second data line; A semiconductor device in which an add operation is performed on data output from a plurality of the memory cells.

3. 3. The semiconductor device according to claim 2, a reference cell connected to the first data line and the second data line and capable of supplying a reference value of the characteristic value; a path that outputs a characteristic value close to the reference value is selected from among the paths selected by the third data holding circuit and the fourth data holding circuit.

4. 4. The semiconductor device according to claim 3, A semiconductor device comprising: a plurality of current sources commonly connected to a plurality of the memory cells; and capable of selecting one of the plurality of current sources when selecting the path based on a current value.

5. 3. The semiconductor device according to claim 2, A semiconductor device, wherein the first data retention circuit, the second data retention circuit, the third data retention circuit and the fourth data retention circuit are composed of SRAM, the SRAM is operable in a first operating state and a second operating state in which power is reduced more than in the first operating state, and a product-sum operation is performed in the second operating state.

6. 2. The semiconductor device according to claim 1, a semiconductor device, wherein the first data retention circuit and the second data retention circuit are constituted by SRAM formed in a first layout, and the third data retention circuit and the fourth data retention circuit are constituted by SRAM formed in a second layout.

7. A first data line; A second data line; A common power line; a memory cell storing ternary data, and performing a multiply-and-accumulate operation between the stored data, input data, and data on the first data line and the second data line; Equipped with The memory cell includes: a first data holding circuit and a first switch for establishing or interrupting a path between the first data line and the common power supply line; a second data holding circuit and a second switch for establishing or interrupting a path between the second data line and the common power supply line; a third data holding circuit and a third switch for switching a path between the first data line and the common power supply line; a fourth data holding circuit and a fourth switch for switching a path between the second data line and the common power supply line; A semiconductor device comprising:

8. 8. The semiconductor device according to claim 7, the first switch is controlled based on data held in the first data holding circuit; the second switch is controlled based on data held in the second data holding circuit; the third switch is controlled based on data held in the third data holding circuit; the fourth switch is controlled based on data held in the fourth data holding circuit.

9. The semiconductor device according to claim 8, further comprising: a reference cell connected to the first data line and the second data line and providing a reference to the first data line and the second data line; a determination circuit connected to the first data line and the second data line; Equipped with The data to be stored in the third data holding circuit and the fourth data holding circuit are determined based on a result of the determination by the determination circuit.

10. 10. The semiconductor device of claim 9, The semiconductor device further comprises a second reference cell connected to the first data line and the second data line, the second reference cell providing a reference smaller than the reference to the first data line and the second data line.

11. A first data line; A second data line; A common power line; a plurality of memory cells each having a first input, a second input, and a third input, the plurality of memory cells connecting the first data line or the second data line to a common power supply line via a plurality of switches controlled by the first to third inputs; a determination circuit connected to the first data line and the second data line; Equipped with The memory cell includes: a first switch connected between the first data line and the common power supply line and controlled by the first input; a second switch connected between the second data line and the common power supply line and controlled by the second input; a third switch connected between the first data line and the common power supply line and controlled by the third input; a fourth switch connected between the second data line and the common power supply line and controlled by the third input; a fifth switch connected between the first data line and the common power supply line, and a first data holding circuit controlling the fifth switch; a sixth switch connected between the second data line and the common power supply line; and a second data holding circuit that controls the sixth switch.

12. 12. The semiconductor device of claim 11, Further, a reference cell is connected to the first data line and the second data line, and configured to supply a current or a voltage equivalent to that of the memory cell to the first data line and the second data line, The data to be stored in the first data holding circuit and the second data holding circuit are determined based on a result of the determination by the determination circuit.

13. 13. The semiconductor device of claim 12, The semiconductor device further includes a second reference cell connected to the first data line and the second data line and configured to supply a current or voltage to the first data line and the second data line that is smaller than that of the memory cell.

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