Back-to-back power field effect transistors with associated current sensors

Abstract

The exemplary device includes a first power field effect transistor (FET) (204) having a first source (306) and a second power FET (206) having a second source (308). The first and second power FETs (204, 206) share a common drain (402). The first and second sources (306, 308) are disposed on a first side of a substrate (406), and the common drain (402) is disposed on a second side of the substrate (406) opposite the first side. The exemplary device includes a current sense FET disposed between a first portion and a second portion of the first source (306). The current sense FET senses a current passing through the first and second power FETs (204, 206).

Description

[Technical field]

[0001] This application relates generally to power transistors, and more particularly to back-to-back power field effect transistors with associated current sensors. [Background technology]

[0002] Power transistors are used as switches in power electronics. In many existing applications (e.g., USB ports), the power switch is accomplished using a separate (e.g., stand-alone) transistor that is activated or controlled by a separate external controller. In many situations, the current passing through the power transistor is monitored by detecting the voltage drop across a resistor placed in series with the power transistor. Summary of the Invention

[0003] An example device includes a first power field effect transistor (FET) having a first source and a second power FET having a second source. The first and second power FETs share a common drain. The first source and the second source are disposed on a first side of a substrate, and the common drain is disposed on a second side of the substrate opposite the first side. The example device includes a current sense FET disposed between a first portion of the first source of the first power FET and a second portion of the first source of the first power FET. The current sense FET senses a current passing through the first and second power FETs.

[0004] An exemplary apparatus includes a power transistor assembly including back-to-back power field effect transistors (FETs) and including a current sense FET integrated within the power FETs, and the apparatus includes a controller for controlling operation of the power FETs, the power FETs being integrated with the controller in a single package.

[0005] An exemplary device includes a first power field effect transistor (FET) having a first source coupled to a first doped region. The exemplary device includes a second power FET having a second source coupled to a second doped region. The first doped region is disposed proximate to a second doped region on a common substrate associated with a common drain for the first and second power FETs. The substrate has a non-uniform current density distribution when a current is passing between the first and second power FETs. The exemplary device includes a current sense FET having a third source coupled to a third doped region. The third doped region is disposed at a first location on the common substrate. The current sense FET measures a current passing between the first power FET and the second power FET at the first location.

[0006] An example electronic device includes a Universal Serial Bus (USB) connector. The example electronic device includes an internal circuitry connector that communicatively couples the USB connector to internal circuitry of the electronic device. The example electronic device includes a first power field effect transistor (FET) having a first source. The example electronic device includes a second power FET having a second source. The first source and the second source are disposed on a first side of a substrate, and a common drain is disposed on a second side of the substrate opposite the first side. The first and second power FETs are electrically coupled between the USB connector and the internal circuitry connector to pass current from the internal circuitry to an external device when the first and second power FETs are turned on. The example electronic device includes a current sense FET integrated within the first and second power FETs. [Brief description of the drawings]

[0007] [Figure 1] 1 illustrates an example electronic device constructed in accordance with the teachings described herein.

[0008] [Diagram 2] 2 illustrates an example implementation of an example USB interface of the example electronic device of FIG. 1;

[0009] [Diagram 3] 3 is a top view of the example power transistor assembly of FIG. 2 integrated with the example controller of FIG. 2 in a single package.

[0010] [Figure 4] FIG. 4 is a cross-sectional view of the example power transistor assembly of FIG. 3 taken along line 4-4.

[0011] [Diagram 5] 4 is a diagram of an example current density distribution across the XY plane within the doped region of the example power transistor assembly of FIG. 3.

[0012] [Figure 6] FIG. 6 is a cross-sectional view of the example power transistor assembly of FIG. 3 taken along line 6-6.

[0013] [Figure 7] 4 is a graph illustrating the rate of change of the ratio of resistance of the first current sense FET to the main power FET of FIGS. 2 and 3 as the temperature varies from 25° C. to 125° C.;

[0014] [Figure 8] 4 is a graph illustrating the rate of change of the ratio of resistance of the second current sense FET to the main power FET of FIGS. 2 and 3 as the temperature varies from 25° C. to 125° C.; DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0015] The drawings are not drawn to scale. Instead, the thickness of layers or regions may be exaggerated in the drawings. Generally, the same reference numbers are used throughout the drawings and the accompanying description to refer to the same or similar parts. As used herein, a statement that any part (e.g., a layer, film, region, area, or plate) is on another part in some manner (e.g., disposed on, located on, or formed on, etc.) indicates that the referenced part is in contact with the other part or that the referenced part is on the other part with one or more intermediate parts therebetween. A statement that any part is in contact with another part means that there is no intermediate part between the two parts. Although the drawings show each layer and region with clear lines and boundaries, some or all of these lines and / or boundaries may be idealized. In reality, the boundaries and / or lines may not be observable, may be blended, and / or may be irregular.

[0016] As used herein, the term "above" is used in reference to the bulk region of a base semiconductor substrate (e.g., a semiconductor wafer) upon which components of an integrated circuit are formed. In particular, as used herein, a first component of an integrated circuit is "above" a second component when the first component is further from the bulk region of the semiconductor substrate. Similarly, as used herein, a first component is "below" another component when the first component is closer to the bulk region of the semiconductor substrate. As noted above, one component may be above or below another component that is between them or that is directly adjacent to one another.

[0017] In many electronic devices, power transistors are controlled to switch on or off by a controller implemented externally to the power transistor (in a separate integrated circuit (IC)). However, the connection (e.g., wire bonds and / or clip bonds) between the external controller and one or more associated power transistors creates additional resistance that can degrade the overall performance of the associated system. Also, one of the factors that defines the performance and / or capabilities of a metal-oxide-semiconductor field-effect transistor (MOSFET) is the total resistance between the drain and source when the transistor is powered on (also called the on-resistance (Ron)). Generally, as the on-resistance decreases, the performance of the associated transistor increases. The examples described herein implement an ultra-low on-resistance (e.g., less than 2.5 mΩ) power transistor integrated with a controller in a single package to reduce the resistance across the connection between the controller and the transistor. This is achieved by implementing the power transistor using two field-effect transistors (FETs) in a back-to-back arrangement and integrating it with the controller in a wafer-level chip-scale package (WCSP). As used herein, a back-to-back FET refers to two FETs arranged in a particular circuit topology in which the two FETs have separate sources but share a common drain. Some example back-to-back FETs described herein also have a particular physical structure in which two FETs are formed in close proximity to each other on a single semiconductor (e.g., silicon) substrate. In such an example, the common drain corresponds to the semiconductor substrate and / or underlying backside metal formed on opposite sides of the substrate with separate sources isolated from each other via a trench extending into the semiconductor substrate between the source metals. The back-to-back arrangement prevents current from flowing through the system in either direction when the FETs are turned off. The integration of power FETs with a corresponding controller in a single package also provides a much smaller footprint than circuit elements with similar functionality implemented in other electronic devices.

[0018] Although implementing back-to-back power FETs in a WCSP may reduce resistance, such implementation leads to current crowding where the distribution of current density across the FET is non-uniform. The non-uniform current density distribution makes it difficult to accurately sense the current, as is often done for power transistors implemented in many electronic devices. For example, in many existing electronic devices, the current passing through a power transistor is measured based on the voltage drop across a resistor placed in series with the power transistor. However, sensing the current through an external resistor cannot accurately determine the non-uniform current distribution within the associated transistor. Examples described herein overcome this challenge by integrating one or more current sense FETs with a main FET used to implement the back-to-back power FETs. More specifically, in some examples, the one or more current sense FETs are significantly smaller than the main power FET such that the current sense FETs can be placed in different locations associated with different current densities within the main power FET. In this way, although the current density distribution is non-uniform, the average current across the main power FET can be more accurately measured, this average current being based on the perpendicular path of the current through the main power FET, rather than an external current through a resistor in series with the main power FET. Also, in some instances, the location where the current is expected to be highest may be measured by a specific current sense FET in order to monitor peak current values ​​(e.g., when there is an excess current beyond the intended or expected current) to more accurately identify potential overcurrent situations. Also, a current sense FET integrated into the structure of the main power FET provides a faster response time than is possible using other current sensing methods based on external current sensors.

[0019] FIG. 1 illustrates an example electronic device 100 configured in accordance with the teachings described herein. For example, the example electronic device 100 of FIG. 1 includes an example power supply 102, an example central processing unit 104, and an example universal serial bus (USB) interface 106. The electronic device 100 can be any type of electronic device, such as a laptop computer, a tablet computer, a desktop computer, a smartphone, a personal digital assistant (PDA), etc. The power supply 102 may be associated with a DC power source (e.g., a battery) or an AC power source. In this example, the USB interface 106 implements a power transistor configured in accordance with the teachings described herein. Details regarding the implementation of the USB interface 106 are provided in connection with FIG. 2. Although the power transistor is described in the context of the example USB interface 106 of FIG. 1, the examples described herein may be implemented in any suitable application for turning power on and off. As such, the inclusion of a USB interface 106 is merely an example, and the teachings described herein may additionally or alternatively be implemented for other power applications in electronic devices that may or may not include a USB interface.

[0020] As shown in the illustrated example of FIG. 2, the USB interface 106 includes a power transistor assembly 202 that includes two back-to-back power FETs 204, 206 that act as main power FETs (labeled M1 and M2 in the illustrated example) for switching on and off the delivery of power to an external device connected via a USB connector 208. In some examples, the USB connector 208 corresponds to a USB Type-C (USB-C) connector. The power delivered to the external device via the USB connector 208 is obtained from the power source 102 of FIG. 1 via an internal integrated circuit (IC) connector 210. In some examples, the main power FETs 204, 206 of the power transistor assembly 202 are integrated with an example controller 212 in a single package. The example controller 212 controls when the main power FETs 204, 206 are turned on and off. Additionally, in some examples, the controller 212 may variably adjust (e.g., decrease) the gate-source voltage (Vgs) for at least one of the main power FETs 204, 206 to limit (e.g., maintain the current below a certain threshold) the current passing through the power transistor assembly 202 when appropriate. In the illustrated example of Figure 2, the second main power FET 206 is shown as a FET with an adjustable Vgs.

[0021] In some examples, whether the controller 212 turns on, off, or otherwise regulates the current passing through the main power FETs 204, 206 is based on the output of one or more current sense FETs 214, 216 (two are shown in the illustrated example labeled SF1 and SF2). In some examples, the current sense FETs 214, 216 are integrated at different locations within the main power FETs 204, 206 of the power transistor assembly 202, as shown and described below in connection with FIG. 3. Consistent with the description herein, a current sense FET can be described as being located within the main power FETs 204, 206 when the current sense FET is at least partially surrounded by a portion of at least one of the main power FETs 204, 206. In one implementation, for example, the current sense FETs 214, 216 may be disposed within the periphery of the main power FETs 204, 206. In another implementation, for example, the current sense FETs 214, 216 may be disposed between at least a portion of the first main power FET 204 and at least a portion of the second main power FET 206. In some examples, the current sense FETs 214, 216 have a similar structure as the main power FETs 204, 206 and share the same drain as the main power FETs 204, 206.

[0022] The example controller 212 of Figure 2 may be implemented by hardware, software, firmware, and / or any combination of hardware, software, and / or firmware. Thus, for example, the example controller 212 may be implemented by one or more analog or digital circuits, logic circuits, programmable processors, programmable controllers, digital signal processors (DSPs), application specific integrated circuits (ASICs), programmable logic devices (PLDs), and / or field programmable logic devices (FPLDs). Also, the example USB interface 106 of Figure 1 may include one or more elements, processes, and / or devices in addition to or instead of those illustrated in Figure 2, and / or may include two or more of any or all of the illustrated elements, processes, and devices. As used herein, the term "communicating," including variations thereof, encompasses direct communication and / or indirect communication through one or more intermediary components, and additionally includes selective communication at periodic intervals, scheduled intervals, aperiodic intervals, and / or one-time events that do not require direct physical (e.g., wired) communication and / or constant communication.

[0023] 3 is a top view of the example power transistor assembly 202 of FIG. 2 integrated with the example controller 212 of FIG. 2 in a single package 300. In some examples, the controller 212 and the power transistor assembly 202 are integrated into a single die. In other examples, the controller 212 and the power transistor assembly 202 may be fabricated on two separate dies that are then integrated into the single package 300. Whether the controller 212 is included on the same die as the power transistor assembly 202, the controller 212 is communicatively coupled to each of the main power FETs 204, 206 and each of the current sense FETs 214, 216 as illustrated in FIG. 3. Although the controller 212 and the power transistor assembly 202 are shown integrated into a single package 300 in FIG. 3, in some examples, the controller 212 may be implemented in a first package while the power transistor assembly 202 may be implemented in a second separate package.

[0024] With reference to the example power transistor assembly 202 shown in FIG. 3, the main power FETs 204, 206 include a number of source connections 302 corresponding to bumps formed on a top surface of an underlying conductive layer 304 that defines a source for each of the main power FETs 204, 206. More specifically, in this example, the main power FETs 204, 206 each include twenty source connections 302 arranged in two rows of ten connections extending between opposite ends of the main power FETs 204, 206. In other examples, the main power FETs 204, 206 may be implemented with a different number of rows and / or a different number of connections per row. For example, in some examples, each power FET 204, 206 may be configured with only a single row of any suitable number (e.g., 5, 8, 10, 11, etc.) of source connections 302. In other examples, each power FET 204, 206 may be configured with any suitable number of three or more rows of source connections 302. Although there are multiple source connections 302, all of the source connections 302 associated with the first main power FET 204 correspond to the same first source 306 and are electrically coupled through the underlying conductive layer 304. Similarly, all of the source connections 302 associated with the second main power FET 206 correspond to the same second source 308 and are electrically coupled through the associated underlying conductive layer 304. In some examples, at least one of the circles associated with each source 306, 308, designated as source connections 302 in FIG. 3, may be isolated from the corresponding source 306, 308 and may act as a gate for the corresponding source.

[0025] Although the first and second main power FETs 204, 206 have separate sources, they are configured in a back-to-back arrangement with a common drain 402, as shown in the cross-sectional view of Figure 4. More specifically, the illustrated first and second main power FETs 204, 206 are vertical FETs, with the sources 306 adjacent to each other on a first side of a substrate 406 and vertically offset from or above a common drain 402 located on the opposite side of the substrate 406. That is, as shown in the illustrated example of Figure 4, the drains 402 for both main power FETs 204, 206 correspond to a backside metal (BSM) 404 located on the bottom (back) side of the substrate 406. The BSM may include any suitable metal, such as silver. The substrate 406 may include any suitable semiconductor, such as silicon and / or n-type or p-type silicon. In the illustrated example, first and second doped regions 408, 410 corresponding to the location of channels for the corresponding power FETs 204, 206 are formed on the substrate 406 opposite the BSM 404. In some examples, the doped regions 408, 410 correspond to portions of the substrate 406 that have been doped or diffused with any suitable dopant to form either an n-type or p-type semiconductor. A conductive layer 304 is formed on the doped regions 408, 410, on which the source connection 302 is formed. The conductive layer 304 may include any suitable metal, such as aluminum. The source connection 302 may include any suitable metal in any suitable shape, such as a solder ball.

[0026] 3 and 4, a first source 306 of the first main power FET 204 extends between a first lateral side 310 of the example power transistor assembly 202 and a central axis or plane 312 of the example power transistor assembly 202. A second source 308 of the second main power FET 206 is located on the opposite side of the central plane 312 and extends between a second lateral side 314 of the example power transistor assembly 202 and the central plane 312. As shown in the illustrated examples, the first and second sources 306, 308 and corresponding first and second doped regions 408, 410 are separated by a trench 412. In some examples, the trench 412 may extend into the substrate 406 below the doped regions 408, 410. In some examples, the trench 412 may be filled with any suitable dielectric material to insulate and / or isolate the separate sources 306, 308 corresponding to the two main power FETs 204, 206.

[0027] With sources 306, 308 for the main power FETs 204, 206 on the top side of the power transistor assembly 202 and a drain 402 on the back side of the assembly, the FETs 204, 206 are vertical FETs, with current traveling vertically through doped regions 408, 410. However, the current path is not consistent throughout the power transistor assembly 202 and changes depending on the distance from the mid-plane 312 where the current exits (or enters) the first source 306 and travels to (or from) the second source 308. Various example current paths are represented by the arrows shown in FIG. 4. In this example, the current is represented as originating in the first FET 204 and traveling to the second FET 206. In other situations, the direction of the current can be reversed. In any event, at the outer end of the power transistor assembly 202 (e.g., toward the lateral sides 310, 314), current may follow a substantially vertical path downward from the first source 306 through the substrate 406 and then travel laterally across the drain 402 before traveling substantially vertically upward through the substrate 406 to reach the second source 308 represented by the first current path. As used in this context, vertical is defined as being orthogonal to the plane of the substrate 406 on which the primary power FETs 204, 206 are formed. Thus, as used herein, a "substantially vertical" current path refers to a current path that is within some threshold of 90 degrees (e.g., 5 degrees, 10 degrees) from the plane of the substrate 406. Current entering the substrate 406 closer to the mid-plane 312 (e.g., near the midpoint between the mid-plane 312 and the first lateral side 310) may extend a substantial depth into the substrate 406 without reaching the BSM 404 (e.g., the drain 402) before proceeding laterally and then follow a second current path 416 back to the second source 308. Current entering the substrate 406 adjacent the mid-plane 312 between the FETs 204, 206 may follow a third current path 418, where the current primarily proceeds laterally across the substrate 406 below the trench 412 to reach other sources. As shown in the illustrated example, some current paths do not extend into the BSM 404.In some examples, the BSM 404 may be omitted with the substrate 406 acting as the drain 402 for the main power FETs 204,206.

[0028] The non-uniform current path between the sources of the two main power FETs 204, 206 results in a non-uniform current density distribution across the power transistor assembly 202. FIG. 5 is a diagram illustrating an example current density distribution in the XY plane within the doped regions 408, 410 of the example power transistor assembly 202 of FIGS. 2-4. As depicted in the diagram of FIG. 5, the current is highest at the inner ends of the main power FETs 204, 206 close to the central plane 312 and decreases away from the central plane 312 toward the lateral sides 310, 314. The relatively high current near the central plane 312 is due to the relatively low resistance of the short current path (e.g., path 418 in FIG. 4) between the inner ends of the doped regions 408, 410 of the two main power FETs 204, 206 close to the central plane 312. In contrast, the lower current at distances farther from the mid-plane 312 is due to the greater resistance of the longer current paths (e.g., paths 414, 416 in FIG. 4) associated with the outer ends of the FETs 204, 206. In addition to the current density distribution varying across the XY plane as shown in FIG. 5, the current density distribution may also vary in the Z direction (e.g., at different depths within the substrate 406).

[0029] In many situations, it is desirable to measure the current passing through a power transistor. This is often done with a current sense FET. The challenge with this approach for the example power transistor assembly 202 in the illustrated example is that the measured current depends on where the current sense FET is located. The closer the current sense FET is located to the mid-plane 312, the higher the sensed current will be. Conversely, the further the current sense FET is located from the mid-plane 312, the lower the sensed current will be.

[0030] For accurate measurements, the substrate resistance is matched to the resistance of the current sense FET. In some examples, this is accomplished by constructing the current sense FETs 214, 216 with a similar structure (and using the same materials) as the main power FETs 204, 206, such that the current is located at a location where the current is approximately the average of the total current distribution. As used herein, approximately the average can be understood to be within a certain threshold (e.g., 10%) of the average. In some examples, the current is approximately the average of the total current distribution in the central third region 316 of each FET 204, 206 as shown in FIG. 3. That is, in some examples, the current sense FET (e.g., the first current sense FET 214) is located at a distance from the mid-plane 312 that is approximately one-third to two-thirds of the total distance between the mid-plane 312 and the corresponding lateral side 310, 314. In some examples, when the main power FETs 204, 206 include two rows of source connections 302 (as shown in FIG. 3), the current sense FET 214 is located a distance from the mid-plane 312 between the two rows of source connections 302. In other words, in some examples, the current sense FET 214 is surrounded by one of the main power FETs 204, 206 and located a distance from the other power FET.

[0031] The first current sense FET 214 may be located at any suitable location along the length of the central third region 316 since the current distribution is substantially uniform along the length of the main power FETs 204, 206. In some examples, the manufacturing process for making the first current sense FET 214 may be simplified if it is located at one end of the main power FETs 204, 206. Thus, in the illustrated example of FIG. 3, the first current sense FET 214 is located in the third region 316 associated with the first main power FET 204 at one end of the power FET. In some examples, the current in the central third region 316 of the substrate 406 of the first main power FET 204 is approximately the same as the current in the central third region 316 of the substrate 406 of the second main power FET 206. Thus, in some examples, the first current sense FET 214 may alternatively be located in the third region 316 of the second main power FET 206. In some examples, different current sense FETs may be disposed in the middle third region 316 of both main power FETs 204, 206. In some examples, multiple current sense FETs may be disposed in the middle third region 316 of one of the main power FETs 204, 206. In some such examples, different current sense FETs may be disposed at different locations along the longitudinal length of the corresponding main power FET. In some examples, multiple current sense FETs may be disposed at different locations on a single main power FET that are different distances from the mid-plane 312. In some such examples, the different current sense FETs may all be disposed within the middle third region 316 of the main power FET. In other such examples, one or more current sense FETs may be disposed outside of the middle third region 316.

[0032] In some examples, when only one current sense FET (e.g., current sense FET 214 in FIG. 3) is used across both main power FETs 204, 206, the current sense FET 214 is located over the main power FET 204 that remains in the linear region during operation and does not reach saturation. As described above in connection with FIG. 2, the controller 212 may variably adjust (e.g., decrease) the Vg of the second main power FET 206 to limit the current passing through the power transistor assembly 202. As the Vg of the second main power FET 206 decreases, the drain-source voltage (VdS) increases and may reach saturation. In contrast, the first main power FET 204 is either fully on or fully off, so that the first main power FET 204 operates in the linear region. In such examples, as shown in FIG. 3, the first current sense FET 214 is located over the first main power FET 204 because the first main power FET 204 does not enter saturation.

[0033] The structure of the first current sense FET 214 is substantially similar to that of the first main power FET 204, except for its size, as shown in the cross-sectional view of the example power transistor assembly 202 shown in FIG. 6 taken along line 6-6 in FIG. 3. As shown in the illustrated example of FIG. 6, the relatively small first current sense FET 214 is formed within the structure of the much larger first main power FET 204, with the source connection 602 on the same conductive layer 304 on the same doped region 408 on the substrate 406. Also, the current sense FET 214 shares the same drain 402 that is common between both the first and second main power FETs 204, 206. The first current sense FET 214 is electrically isolated from the first main power FET 204 based on a trench 604 etched through the conductive layer 304 and the doped region 408. In some examples, the trench 604 is filled with a dielectric material. As shown in the illustrated example of FIG. 6, the first current sense FET 214 is disposed between the first portion 606 and the second portion 608 of the first source 306 of the first main power FET 204 .

[0034] The first current sense FET 214, located as shown in FIG. 3 in the central third region 316 of the first main power FET 204, allows for accurate determination of the average current in the power transistor assembly 202 relative to the total current distribution during normal operation. An important factor affecting the accuracy of the current sense FET is the temperature at which the current sense FET and the associated main power FET are operating, since the characteristics of the FETs change with temperature. FIG. 7 is a graph illustrating the rate of change of the ratio of the resistance of the first current sense FET 214 to the resistance of the main power FETs 204, 206 at 25° C. and 125° C. In contrast, FIG. 8 is a graph illustrating the rate of change of the ratio of the resistance of the second current sense FET 216 to the resistance of the main power FETs 204, 206 at 25° C. and 125° C. 7 and 8, the rate of change of ratio with temperature change from 25° C. to 125° C. for the first current sense FET 214 is approximately half the rate of change of ratio for the second current sense FET 216. Less ratio change corresponds to more accurate measurements. Thus, the location of the first current sense FET 214 in the central third region 316 of the first main power FET 204 provides greater accuracy in measuring current compared to the second current sense FET 216 located closer to the mid-plane 312.

[0035] While the location of the first current sense FET 214 provides an accurate current measurement under normal operating conditions, the first current sense FET 214 cannot accurately detect an overcurrent condition. As described above in connection with FIG. 5, the current is highest at the inner ends of the main power FETs 204, 206 proximate the mid-plane 312 as defined by the trench 412, and is highest at corresponding locations in the substrate 406 below the trench 412. If a large current crowds near the mid-plane 312 during an overcurrent condition, the power transistor assembly 202 may overheat, especially the area proximate the mid-plane 312. If the temperature of the power transistor assembly 202 increases, the resistance match between the first current sense FET 214 and the corresponding main power FET 204 may be disturbed. As a result, the current measurement by the first current sense FET 214 during such conditions may not be accurate or reliable. Also, when detecting an overcurrent condition, it is desirable to detect the highest current present. However, the first current sense FET 214 is positioned to detect the average current rather than the highest current, thereby further weakening the FET's ability to pass current and reliably detect an overcurrent condition. Therefore, in some examples, the second current sense FET 216 is positioned within the power transistor assembly 202 at or near the mid-plane 312, as shown in Figure 3, where the current is highest. More specifically, in some examples, the second current sense FET 216 is located a distance from the mid-plane 312 that is within 10% of the total distance between the mid-plane 312 and one of the lateral sides 310, 314.

[0036] Although the current is substantially consistent along the longitudinal length of the power transistor assembly 202, the current may be slightly higher near the center of the assembly away from the ends. This is especially true in overcurrent conditions because as temperature increases, the characteristics of the FETs change and the highest temperature is likely to be near the center of the power transistor assembly 202 where the current is also highest. Thus, in this example, the second current sense FET 216 is located toward the center of the power transistor assembly 202. More specifically, in some examples, the second current sense FET 216 is located within the central two-thirds of the longitudinal power transistor assembly 202.

[0037] The structure of the second current sense FET 216 is substantially similar to the structure of the first current sense FET 214 shown in FIG. 6, except that the second current sense FET 216 is located closer to the mid-plane 312 and the trench 412. In the illustrated example of FIG. 3, the second current sense FET 216 is located on the same side of the mid-plane 312 as the first current sense FET 214 (e.g., surrounded by the first main power FET 204). In other examples, the second current sense FET 216 may be located on the opposite side of the mid-plane 312 to be located within the second main power FET 206. In other examples, separate current sense FETs may be located on either side of the mid-plane 312. As shown in the illustrated example, the second current sense FET 216 is not located directly in-line with the mid-plane 312 because the current sense FET is formed within an associated main power FET and is spaced from the mid-plane 312 by the trench 412. In this example, however, the second current sense FET 216 is directly adjacent to the trench 412 .

[0038] In some examples, the power transistor assembly 202 includes both a first current sense FET 214 (located in the central third region 316 where the current is averaged) for accurately monitoring the current under normal operating conditions, and a second current sense FET 216 (located at or near the central plane 312 where the current is highest) for reliably detecting overcurrent conditions. In other examples, only one of the first or second current sense FETs 214, 216 may be included in the power transistor assembly 202. In other examples, additional current sense FETs may be included in the power transistor assembly 202 to provide redundancy and / or additional measurement points that may be averaged and / or combined in any suitable manner. While the general areas of the current sense FETs 214, 216 have been described above, the exact locations for a particular power transistor assembly design may be determined by performing a finite element analysis of that particular design.

[0039] As used herein, the term "and / or" (when used in the form of A, B, and / or C, etc.) refers to any combination or subset of A, B, and C, such as (a) A alone, (b) B alone, (c) C alone, (d) A with B, (e) A with C, (f) B with C, and (g) A with B and C. Also, as used herein, the phrase "at least one of A or B" (or "at least one of A and B") refers to implementations that include any of (a) at least one A, (b) at least one B, and (c) at least one A and at least one B.

[0040] Thus, exemplary methods, apparatus, and articles of manufacture have been described that enable implementation of a power switching component (e.g., a USB interface) comprising a power transistor assembly and an associated controller in a smaller form factor than is available in other electronic devices. The small form factor is achieved by integrating two back-to-back power FETs with their associated controllers into a single package. The examples described herein also enable accurate measurement of the average current passing through a main power FET, despite the fact that the current density distribution of the FETs is non-uniform based on their construction and mode of operation. Accurate current measurement is achieved by implementing one or more current sense FETs at a location within the main power FET where the current is expected to be average during normal operating conditions. In some examples, accurate detection of an overcurrent condition is achieved by implementing one or more current sense FETs at a location within the main power FET where the current is expected to be highest. Not only do current sense FETs in the positions described herein provide more accurate monitoring of the current conditions in the main power FET than other current sensing techniques, but the current sense FETs can provide faster response times than other known approaches enabling an associated controller to respond more quickly when appropriate, thereby improving system operation.

[0041] Modifications may be made to the exemplary embodiments described, and other embodiments are possible, within the scope of the invention.

Claims

1. An apparatus comprising:

1. A transistor assembly comprising: two back-to-back field effect transistors (FETs) having respective doped regions and respective two rows of source connections and a shared drain; a first current sense FET having a doped region and a source at least partially surrounded by a doped region of one of the two back-to-back FETs, the first current sense FET being disposed in an intermediate region between the two rows of source connections of one of the two back-to-back FETs; a second current sense FET having a source and a doped region at least partially surrounded by a doped region of one of the two back-to-back FETs, the second current sense FET being positioned a first distance from an interface of the two back-to-back FETs, the first distance being within ten percent of a second distance extending between the interface and an outer lateral side of one of the two back-to-back FETs; a trench at least partially surrounding and separating a doped region and a source of the current sense FET from a doped region and a source of one of the two back-to-back FETs; the transistor assembly comprising: a controller configured to control operation of the back-to-back FETs; Including, The apparatus, wherein the two back-to-back FETs and the controller are integrated into a single package.

2. 2. The apparatus of claim 1, a first portion of the doped regions and source of a first of the two back-to-back FETs is closer to the doped regions and source of a second of the two back-to-back FETs than the doped regions and source of the current sense FET, and a second portion of the doped regions and source of the first back-to-back FET is farther from the doped regions and source of the second back-to-back FET than the doped regions and source of the current sense FET.

3. 3. The apparatus of claim 2, the first portion extends at least one-third of the distance between an inner end of the first back-to-back FET proximate to the second back-to-back FET and an outer lateral side of the first back-to-back FET away from the second back-to-back FET; the second portion extends at least one-third of the distance between an inner end of the first back-to-back FET and an outer lateral end of the first back-to-back FET.

4. An apparatus comprising: a substrate having a first side and a second side opposite the first side; a first field effect transistor (FET) having a first doped region on a first side of the substrate and a first source on the first doped region; a second FET having a second doped region on the first side of the substrate, a second source on the second doped region and a drain on the second side of the substrate, the drain being shared with the first FET; a first current sensing FET disposed in a laterally intermediate region of the first FET, the first current sensing FET having a third doped region on a first side of the substrate and a third source on the third doped region, the third doped region being at least partially surrounded by the first doped region and the third source being at least partially surrounded by the first source; a second current sense FET disposed in a vertically intermediate region of the first FET, the second current sense FET having a fourth doped region on a first side of the substrate and a fourth source on the fourth doped region, the fourth doped region and the fourth source being at least partially surrounded by the first doped region and the first source; a first trench at least partially surrounding and separating the third doped region and the third source from the first doped region and the first source; 13. An apparatus comprising:

5. 5. The apparatus of claim 4, The first current sensing FET and the first and second FETs share the drain.

6. 5. The apparatus of claim 4, the second current sense FET is disposed a first distance from an interface between the first FET and the second FET, the first distance being within 10 percent of a second distance extending between the interface and an outer lateral side of the first FET.

7. 7. The apparatus of claim 6, a second trench separating the first doped region and the first source from the second doped region and the second source, the second trench extending in a vertical direction along a midplane between the first FET and the second FET; the first doped region and the first source extend to a first side away from the mid-plane, and the second doped region and the second source extend to a second side opposite the first side away from the mid-plane.

8. 8. The apparatus of claim 7, a first source including a row of first source connections aligned along the longitudinal direction between first and second ends of the first source, the source connections protruding from an underlying conductive surface.

9. 9. The apparatus of claim 8, the first current sense FET is closer to a first end of the first source than any of the source connections.

10. 9. The apparatus of claim 8, A device, wherein a first one of the source connections is closer to a first end of the first source than the third source.

11. 9. The apparatus of claim 8, the first source further includes a row of second source connections aligned along the longitudinal direction, the row of second source connections being farther from the mid-plane than the row of first source connections; the first current sense FET is further from the mid-plane than the first row of source connections and closer to the mid-plane than the second row of source connections.

12. 7. The apparatus of claim 6, a controller configured to control operation of the first and second FETs based on an output of the first current sensing FET; a package integrating therein the first and second FETs and the first current sense FET; The apparatus further comprises:

13. 13. The apparatus of claim 12, The apparatus, wherein the controller is further configured to variably adjust a gate-source voltage of the second FET.

14. 7. The apparatus of claim 6, 11. An apparatus, wherein the third source is a first distance away from a plane extending between the first and second sources, and the fourth source is a second distance away from the plane that is greater than the first distance.

15. 7. The apparatus of claim 6, the first and second sources extend longitudinally side by side between first and second ends and extend laterally spaced apart from one another toward respective first and second side sides; the first source includes an inner third region adjacent to the second source, an outer third region adjacent to the first lateral side, and an intermediate third region between the inner third region and the outer third region;

16. 7. The apparatus of claim 6, the first and second sources extend longitudinally side by side between first and second ends and extend laterally spaced apart from one another toward respective first and second side sides; the first source includes an inner third region adjacent to the second source, an outer third region adjacent to the first lateral side, and an intermediate third region between the inner third region and the outer third region; the source of the first current sense FET being at least partially surrounded by the inner third region.

17. 7. The apparatus of claim 6, The apparatus, wherein the substrate is disposed relative to the first and second doped regions such that the substrate has a non-uniform current density distribution as current passes between the first and second FETs.

18. 18. The apparatus of claim 17, 11. An apparatus, comprising: a substrate providing a first current path for current between a first portion of the first and second doped regions extending laterally through the substrate at a first depth; a second current path for current between a second portion of the first and second doped regions extending laterally through the substrate at a second depth greater than the first depth; and a third current path for current between a third portion of the first and second doped regions extending laterally through the substrate at a third depth greater than the second depth.

19. 20. The apparatus of claim 18, the second and third current paths extend substantially vertically into the substrate, away from the corresponding second and third portions of the first doped region, before extending laterally through the substrate at the corresponding second and third depths.

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