Surface-emitting semiconductor light-emitting device

Abstract

To provide a plane emission type semiconductor light-emitting device with improved light output.SOLUTION: A plane emission type semiconductor light-emitting device includes a first semiconductor layer, a light-emitting layer provided on the first semiconductor layer, a second semiconductor layer provided on the light-emitting layer, an uneven structure provided on the second semiconductor layer, a first metal layer covering the uneven structure, and a second metal layer provided between the uneven structure and the first metal layer. The second metal layer is provided on at least one of a bottom surface of the concave part, an upper surface of the convex part, and a side surface of the convex part in the uneven structure. The reflectance of the light emitted from the light-emitting layer on the second metal layer is lower than that of the light on the first metal layer.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The embodiment relates to a surface-emitting semiconductor light-emitting device. [Background technology]

[0002] A surface-emitting semiconductor light-emitting device is required to have a high optical output. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2020-68330 A Summary of the Invention [Problem to be solved by the invention]

[0004] The embodiments provide a surface-emitting semiconductor light-emitting device with improved light output. [Means for solving the problem]

[0005] A surface-emitting semiconductor light-emitting device according to an embodiment includes a first semiconductor layer, a light-emitting layer provided on the first semiconductor layer, a second semiconductor layer provided on the light-emitting layer, a concave-convex structure provided on the second semiconductor layer, a first metal layer covering the concave-convex structure, and a second metal layer provided between the concave-convex structure and the first metal layer. The second metal layer is provided on any one of bottom surfaces of concaves, top surfaces of convexities, and side surfaces of the convexities in the concave-convex structure, and the reflectance of the second metal layer for light emitted from the light-emitting layer is lower than the reflectance of the first metal layer for the light. [Brief description of the drawings]

[0006] [Figure 1] 1 is a schematic cross-sectional view showing a surface-emitting semiconductor light-emitting device according to an embodiment. [Diagram 2] 1 is a perspective view showing a schematic view of a surface-emitting semiconductor light-emitting device according to an embodiment; [Diagram 3] 2 is a schematic cross-sectional view showing a structure of a photonic crystal of a surface-emitting semiconductor light-emitting device according to an embodiment. FIG. [Figure 4] 1A to 1C are schematic cross-sectional views showing a method for manufacturing a photonic crystal according to an embodiment. [Diagram 5] 5A to 5C are schematic cross-sectional views showing a method for manufacturing a photonic crystal according to a first modified example of the embodiment. [Figure 6] 5A to 5C are schematic cross-sectional views showing a method for manufacturing a photonic crystal according to a second modified example of the embodiment. [Figure 7] 10A to 10C are schematic cross-sectional views showing a method for manufacturing a photonic crystal according to a third modified example of the embodiment. [Figure 8] FIG. 11 is a schematic cross-sectional view showing a photonic crystal according to a modified example of the embodiment. [Figure 9] FIG. 11 is a schematic cross-sectional view showing a surface-emitting semiconductor light-emitting device according to a modified example of the embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0007] Hereinafter, the embodiments will be described with reference to the drawings. The same parts in the drawings are given the same numbers, and detailed descriptions thereof will be omitted as appropriate, and different parts will be described. Note that the drawings are schematic or conceptual, and the relationship between the thickness and width of each part, the size ratio between parts, etc. are not necessarily the same as the actual ones. Even when the same parts are shown, the dimensions and ratios of each part may be different depending on the drawing.

[0008] Furthermore, the arrangement and configuration of each part will be explained using the X-axis, Y-axis, and Z-axis shown in each figure. The X-axis, Y-axis, and Z-axis are mutually perpendicular and represent the X-direction, Y-direction, and Z-direction, respectively. In addition, the Z-direction may be described as upward and the opposite direction as downward.

[0009] 1 is a schematic cross-sectional view showing a surface-emitting semiconductor light-emitting device 1 according to an embodiment. The surface-emitting semiconductor light-emitting device 1 is, for example, a surface-emitting QCL (Quantum Cascade Laser).

[0010] The surface-emitting semiconductor light-emitting device 1 includes a semiconductor substrate 10, a first semiconductor layer 20, a light-emitting layer 30, a second semiconductor layer 40, a third semiconductor layer 50, a front electrode 60, an insulating film 70, and a back electrode 80.

[0011] The semiconductor substrate 10 is, for example, an n-type InP substrate, or may be an n-type GaAs substrate.

[0012] The first semiconductor layer 20 is provided on the semiconductor substrate 10. The first semiconductor layer 20 is, for example, an n-type InP layer. A buffer layer may be provided between the semiconductor substrate 10 and the first semiconductor layer 20.

[0013] The light emitting layer 30 is provided on the first semiconductor layer 20. The light emitting layer 30 has, for example, a quantum well structure that causes intersubband transition of carriers. The light emitting layer 30 includes, for example, an n-type III-V compound semiconductor doped with silicon, and emits light due to the subband transition of electrons.

[0014] The light emitting layer 30 has a quantum well structure in which quantum well layers 33 and barrier layers 35 are alternately stacked in a direction perpendicular to the upper surface of the first semiconductor layer 20, for example, in the Z direction. The quantum well layers 33 are made of, for example, a first compound semiconductor (InGaAs), and the barrier layers 35 are made of, for example, a second compound semiconductor (AlInAs).

[0015] The light emitting layer 30 includes, for example, a light emitting multiple quantum well region made of a first compound semiconductor and a second compound semiconductor, and an injection multiple quantum well region made of the first compound semiconductor and the second compound semiconductor. Furthermore, the light emitting layer 30 has a structure in which pairs of the light emitting multiple quantum well region and the injection multiple quantum well region are stacked in multiple stages.

[0016] The second semiconductor layer 40 is provided on the light emitting layer 30. The second semiconductor layer 40 is, for example, an n-type InP layer.

[0017] The third semiconductor layer 50 is provided on the second semiconductor layer 40. The third semiconductor layer 50 is, for example, an n-type InGaAs layer. A photonic crystal (PC) is provided on the third semiconductor layer 50. The photonic crystal (hereinafter, PC50f) includes a concave-convex structure having a certain periodicity. The PC50f guides the light emitted from the light emitting layer 30 in a direction toward the semiconductor substrate 10.

[0018] As a photonic crystal, PC50f has the function of selecting a wavelength and controlling the emission angle of the laser light. Light of a desired wavelength according to the design of PC50f resonates in the light emitting layer 30 and lasing occurs. The laser light is emitted in a direction approximately perpendicular to the boundary between the light emitting layer 30 and the first semiconductor layer 20. Here, "approximately perpendicular" means that the angle with respect to the boundary between the light emitting layer 30 and the first semiconductor layer 20 is 81° or more and 99° or less.

[0019] The PC 50f has, for example, a plurality of recesses arranged periodically as a two-dimensional diffraction grating. The recesses of the PC 50f have, for example, a right-angled triangular shape in the top view of the third semiconductor layer 50. Note that the shape and arrangement of the recesses or protrusions are not limited to the example shown here.

[0020] The front surface electrode 60 is provided on the third semiconductor layer 50. The front surface electrode 60 covers the PC 50f. The front surface electrode 60 reflects light emitted from the light emitting layer 30.

[0021] The surface-emitting semiconductor light-emitting device 1 has a mesa structure including a first semiconductor layer 20, a light-emitting layer 30, a second semiconductor layer 40, and a third semiconductor layer 50. An insulating film 70 covers the side surface of the mesa structure. The insulating film 70 is, for example, a silicon oxide film. The insulating film 70 also covers the surface of the semiconductor substrate 10 via a part of the first semiconductor layer 20.

[0022] The back electrode 80 is provided on the back surface 10B of the semiconductor substrate 10. The back electrode 80 includes, for example, a titanium (Ti) layer 81 and a gold (Au) layer 83. The Ti layer 81 is provided between the semiconductor substrate 10 and the Au layer 83.

[0023] In the surface-emitting semiconductor light-emitting device 1, carriers (electrons) are injected into the light-emitting layer 30 by passing a current between the front electrode 60 and the back electrode 80. The light-emitting layer 30 is a quantum well layer QCL light is generated by stimulated emission of light generated by energy relaxation of carriers in 33 and light guided by PC 50f. The QCL light is emitted to the outside from the rear surface 10B of the semiconductor substrate 10. The wavelength of the QCL light is, for example, 4.5 micrometers (μm).

[0024] 2(a) and (b) are perspective views that typically show a surface-emitting semiconductor light-emitting device 1 according to an embodiment. Surface-emitting semiconductor light FIG. 2(b) is a schematic diagram showing the back side of the device 1. Surface-emitting semiconductor light FIG. 2 is a schematic diagram showing the front side of the device 1.

[0025] 2(a), QCL light is emitted from the back surface 10B of the semiconductor substrate 10. The back electrode 80 is provided so as to surround the region from which the QCL light is emitted.

[0026] 2(b), a mesa-shaped light emitting region LER is provided on the front surface side of the semiconductor substrate 10. The insulating film 70 is formed so as to cover the side surface of the light emitting region LER and the front surface side of the semiconductor substrate 10.

[0027] The light emitting region LER includes a first semiconductor layer 20, a light emitting layer 30, a second semiconductor layer 40, and a third semiconductor layer 50. The surface electrode 60 is provided on the upper surface of the light emitting region LER so as to cover the PC 50f. The upper surface of the light emitting region LER has a square shape with each side having a length of 500 μm, for example.

[0028] 3(a) to 3(c) are schematic cross-sectional views illustrating the structure of a PC 50f of the surface-emitting semiconductor light emitting device 1 according to the embodiment. The PC 50f has any of the structures shown in FIGS.

[0029] The PC 50f is provided on the upper surface of the third semiconductor layer 50 opposite to the second semiconductor layer 40. The PC 50f includes a protrusion 50a and a recess 50b. A plurality of protrusions 50a are provided, and the recesses 50b are provided between adjacent protrusions 50a. The plurality of protrusions 50a are arranged in a direction along the upper surface of the second semiconductor layer 40, for example, in the X direction. The protrusions 50a are arranged in the X direction with a constant period. The protrusions 50a are also arranged in the Y direction (not shown) with a constant period. The periodic width of the protrusions 50a in each of the X direction and the Y direction is, for example, shorter than the wavelength of the QCL light.

[0030] The surface electrode 60 includes a first metal layer 63 and a second metal layer 65, and covers the PC 50f. The first metal layer 63 is, for example, an Au layer. The second metal layer 65 is, for example, a Ti layer. The second metal layer 65 may be, for example, a nickel (Ni) layer or a chromium (Cr) layer.

[0031] The second metal layer 65 is provided between the third semiconductor layer 50 and the first metal layer 63. The adhesion strength of the second metal layer 65 to the third semiconductor layer 50 is higher than the adhesion strength of the first metal layer 63 to the third semiconductor layer 50. In other words, the adhesion strength of the second metal layer 65 to the uneven structure including the protrusions 50a and the recesses 50b is higher than that of the first metal layer 63. 3 The adhesion strength to the uneven structure is higher than that of the

[0032] The adhesion strength to the concave-convex structure decreases as the thickness of the second metal layer 65 decreases. For example, when the thickness of the Ti layer is 25 nanometers (nm) or less, the adhesion strength of the second metal layer 65 to the concave-convex structure becomes insufficient.

[0033] On the other hand, the reflectance of the first metal layer 63 for the QCL light emitted from the light emitting layer 30 is higher than the reflectance of the second metal layer 65 for the QCL light. 1 This is higher than the absorption rate of the QCL light in the metal layer 63.

[0034] For example, when the thickness of the Ti layer (second metal layer 65) is 50 nm, the reflectance of an electrode in which a Ti layer and an Au layer (first metal layer 63) are stacked to QCL light is 40% lower than the reflectance of an electrode made of only an Au layer without a Ti layer to QCL light.

[0035] In the example shown in FIG. 3(a), the second metal layer 65 is provided on the upper surface of the protrusion 50a, but not on the side surface of the protrusion 50a or the bottom surface of the recess 50b. The thickness of the second metal layer 65 is, for example, 50 nm. The first metal layer 63 contacts the side surface of the protrusion 50a and the bottom surface of the recess 50b. For example, the reflectance of the surface electrode 60 shown in FIG. 3(a) is about 20% higher than when the thickness of the second metal layer 65 is 50 nm and the second metal layer 65 is provided so as to cover the entire surface of the uneven structure.

[0036] In the example shown in FIG. 3(b), the second metal layer 65 is provided on the bottom surface of the recess 50b, but is not provided on the upper surface and side surface of the protrusion 50a. The thickness of the second metal layer 65 is, for example, 50 nm. The first metal layer 63 contacts the upper surface and side surface of the protrusion 50a. In this example, the reflectance of the surface electrode 60 can be increased by about 20% compared to the case where the second metal layer 65 is provided so as to cover the entire surface of the uneven structure.

[0037] In the example shown in FIG. 3(c), the second metal layer 65 is provided on the side surface of the protrusion 50a, but not on the upper surface of the protrusion 50a or the bottom surface of the recess 50b. The thickness of the second metal layer 65 is, for example, 50 nm. The first metal layer 63 contacts the upper surface of the protrusion 50a and the bottom surface of the recess 50b. In this example, the reflectance of the surface electrode 60 can be increased compared to the case where the second metal layer 65 is provided so as to cover the entire surface of the uneven structure.

[0038] 3(a) and (c), the effective refractive index difference between the convex portion 50a and the concave portion 50b of the PC 50f can be increased by partially providing the second metal layer 65. This can improve the function of the PC 50f.

[0039] 4(a) and (b) are schematic cross-sectional views showing a manufacturing method of the PC 50f according to the embodiment.

[0040] 4(a), a plurality of second metal layers 65 are formed on the third semiconductor layer 50. The second metal layers 65 are arranged with a certain periodicity in the X direction and the Y direction along the upper surface of the third semiconductor layer 50, for example.

[0041] As shown in Fig. 4(b), the third semiconductor layer is selectively removed using the second metal layer 65 as an etching mask to form the protrusions 50a and the recesses 50b. Next, the first metal layer 63 is formed so as to cover the second metal layer 65 and the inner surfaces of the recesses 50b. This allows the PC 50f and the surface electrode 60 shown in Fig. 3(a) to be formed.

[0042] 5(a) to (c) are schematic cross-sectional views showing a manufacturing method of a PC 50f according to a first modified example of the embodiment.

[0043] 5(a), after forming an etching mask 53 on the third semiconductor layer 50, the third semiconductor layer 50 is selectively removed to form the protrusions 50a and the recesses 50b. The etching mask 53 is, for example, a photoresist.

[0044] As shown in FIG. 5(b), a second metal layer 65 is formed on the third semiconductor layer 50. The second metal layer 65 is formed by using a highly directional deposition method such as vacuum deposition. As a result, the second metal layer 65 is formed on the etching mask 53 and on the bottom surface of the recess 50b. In this process, deposition of the second metal layer 65 on the side surface of the protrusion 50a is suppressed.

[0045] 5(c), the second metal layer 65 formed on the etching mask 53 is removed together with the etching mask 53. This leaves the second metal layer 65 on the bottom surfaces of the recesses 50b, and exposes the upper and side surfaces of the protrusions 50a.

[0046] Next, the first metal layer 63 is formed so as to cover the bottom surfaces of the protrusions 50a and the recesses 50b, thereby forming the PC 50f and the surface electrode 60 shown in FIG.

[0047] 6(a) and (b) are schematic cross-sectional views showing a manufacturing method of a PC 50f according to a second modified example of the embodiment.

[0048] 6(a), a second metal layer 65 is formed so as to cover the protrusions 50a and the recesses 50b. The second metal layer 65 is formed so as to leave a space inside the recesses 50b.

[0049] The protrusions 50a and the recesses 50b are formed by selectively removing the third semiconductor layer 50 using, for example, an etching mask 53 (see FIG. 5(a)). The second metal layer 65 is formed after removing the etching mask 53. The second metal layer 65 is formed by, for example, a deposition method with good step coverage, such as sputtering.

[0050] As shown in FIG. 6(b), the second metal layer 65 is removed, leaving the portion formed on the side surface of the protrusion 50a. The second metal layer 65 is removed, for example, by anisotropic RIE (Reactive Ion Etching). Next, the first metal layer 63 is formed so as to cover the bottom surfaces of the protrusion 50a and the recess 50b. This allows the PC 50f and the surface electrode 60 shown in FIG. 3(c) to be formed.

[0051] 7(a) to (d) are schematic cross-sectional views showing a manufacturing method of a PC 50f according to a third modified example of the embodiment.

[0052] As shown in FIG. 7(a), an insulating film 55 is formed so as to cover the protrusions 50a and the recesses 50b. The insulating film 55 is formed so as to leave a space inside the recesses 50b. The insulating film 55 is, for example, a silicon oxide film. Next, a sacrificial film 57 is formed on the insulating film 55. The sacrificial film 57 is formed so as to fill the recesses 50b. The sacrificial film 57 is, for example, a silicon nitride film.

[0053] As shown in FIG. 7(b), the insulating film 55 and the sacrificial film 57 are removed, leaving the portions embedded inside the recesses 50b, to expose the upper surfaces of the protrusions 50a.

[0054] Next, after removing the sacrificial film 57, a second metal layer 65 is formed as shown in FIG. 7(c). The second metal layer 65 is formed by using a highly directional deposition method such as vacuum deposition. The second metal layer 65 is formed on the upper surface of the protrusion 50a and the bottom surface of the recess 50b. The portion of the second metal layer 65 formed on the bottom surface of the recess 50b is formed on the insulating film 55.

[0055] As shown in FIG. 7(d), the portion of the second metal layer 65 formed on the bottom surface of the recess 50b is removed together with the insulating film 55. The insulating film 55 is removed by, for example, wet etching. Next, the first metal layer 63 is formed so as to cover the bottom surfaces of the protrusion 50a and the recess 50b. This allows the PC 50f and the surface electrode 60 shown in FIG. 3(a) to be formed.

[0056] 8(a) to (c) are schematic cross-sectional views showing a PC 50f according to a modified example of the embodiment.

[0057] 8(a), the third semiconductor layer 50 is etched so that the second semiconductor layer 40 is exposed at the bottom of the recess 50b of the PC 50f. The second metal layer 65 is provided on the upper surface of the protrusion 50a of the PC 50f. The first metal layer 63 is provided so as to cover the protrusion 50a and the recess 50b, and is in contact with the second semiconductor layer 40 exposed at the bottom of the recess 50b.

[0058] In the example shown in FIG. 8(b), the second metal layer 65 is provided on the upper surface of the protrusion 50a of the PC 50f. Furthermore, a third metal layer 67 is provided on the side surface of the protrusion 50a and on the bottom surface of the recess 50b. The third metal layer 67 is provided between the first metal layer 63 and the third semiconductor layer 50. The layer thickness of the third metal layer 67 is thinner than the layer thickness of the second metal layer 65. The third metal layer 67 includes, for example, the same material as the second metal layer 65.

[0059] In this example, too, the reflectance of the front electrode 60 can be increased by making the thickness of the third metal layer 67 thinner than that of the second metal layer 65. In the PC 50f according to the embodiment, the provision of the second metal layer 65 ensures a predetermined adhesion strength between the PC 50f and the front electrode 60, but it is impossible to avoid a partial decrease in adhesion strength due to the first metal layer 63 being in direct contact with the third semiconductor layer 50. In this example, the provision of the third metal layer 67 between the first metal layer 63 and the third semiconductor layer 50 makes it possible to alleviate a partial decrease in adhesion strength on the side surface of the protrusion 50a and the bottom surface of the recess 50b.

[0060] In the example shown in FIG. 8(c), the third semiconductor layer 50 is not provided, and the PC 50f is provided on the upper surface of the second semiconductor layer 40 opposite to the light emitting layer 30.

[0061] The third metal layer 67 shown in Fig. 8(b) may be applied to the examples shown in Fig. 8(a) and (c). Although Fig. 8(a) to (c) show an example in which the second metal layer 65 is provided on the upper surface of the protrusion 50a of the PC 50f, the embodiment is not limited thereto. That is, the characteristic configurations of Fig. 8(a) to (c) can also be applied to the case in which the second metal layer 65 is provided on the bottom surface of the recess 50b or on the side surface of the protrusion 50a.

[0062] 9(a) and (b) are schematic cross-sectional views showing surface-emitting semiconductor light-emitting devices 2 and 3 according to modified examples of the embodiment.

[0063] 9(a), the surface electrode 60 is provided so as to cover the side surface of the light emitting region LER of the mesa structure via the insulating film 70. This allows the light emitted from the side surface of the light emitting region LER toward the outside to be returned to the inside of the light emitting region LER, thereby increasing the intensity of the QCL light.

[0064] 9(b), the surface electrode 60 is also provided to cover the side surface of the light emitting region LER of the mesa structure via the insulating film 70. In this example, the portion of the surface electrode 60 provided on the side surface of the light emitting region LER does not include the second metal layer 65, and the first metal layer 63 is in direct contact with the insulating film 70. This improves the reflectance of the portion of the surface electrode 60 provided on the side surface of the light emitting region LER, and can further increase the intensity of the QCL light.

[0065] Although some embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included in the scope and spirit of the invention, and are included in the scope of the invention and its equivalents described in the claims. [Explanation of symbols]

[0066] REFERENCE SIGNS LIST 1, 2, 3... surface-emitting semiconductor light-emitting device, 10... semiconductor substrate, 10B... rear surface, 20... first semiconductor layer, 30... light-emitting layer, 33... quantum well layer, 35... barrier layer, 40... second semiconductor layer, 50... third semiconductor layer, 50a... convex portion, 50b... concave portion, 53... etching mask, 55, 70... insulating film, 57... sacrificial film, 60... front surface electrode, 63... first metal layer, 65... second metal layer, 67... third metal layer, 80... rear surface electrode, 81... Ti layer, 83... Au layer, LER... light-emitting region, 50f... PC

Claims

1. a first semiconductor layer having a mesa structure; a light emitting layer provided on a narrow portion of the mesa structure of the first semiconductor layer; A second semiconductor layer provided on the light emitting layer; a projection-recess structure provided on the second semiconductor layer; a first metal layer covering the relief structure; a second metal layer provided between the concave-convex structure and the first metal layer, the second metal layer being provided on any one of bottom surfaces of concaves, top surfaces of convex portions, and side surfaces of the convex portions in the concave-convex structure, the second metal layer having a lower reflectance for light emitted from the light-emitting layer than a reflectance of the first metal layer for the light; an insulating film provided on a side surface of the narrow width portion, a side surface of the light emitting layer, and a side surface of the second semiconductor layer; Equipped with The uneven structure constitutes a photonic crystal structure.

2. 2. The surface-emitting semiconductor light-emitting device according to claim 1, wherein the adhesion strength of the second metal layer to the uneven structure is higher than the adhesion strength of the first metal layer to the uneven structure.

3. 3 . The surface-emitting semiconductor light-emitting device according to claim 1 , wherein the first metal layer is in contact with a bottom surface of the recess, an upper surface of the protrusion, and a side surface of the protrusion other than the one surface.

4. 3. The surface-emitting semiconductor light-emitting device of claim 1 or 2, further comprising a third metal layer provided on any one of the bottom surface of the recess, the top surface of the protrusion, and the side surface of the protrusion, located between the uneven structure and the first metal layer, and having a layer thickness thinner than that of the second metal layer.

5. 5. The surface-emitting semiconductor light-emitting device according to claim 4, wherein the third metal layer is made of the same metal material as the second metal layer.

6. Further comprising a third semiconductor layer provided on the second semiconductor layer; 6. The surface-emitting semiconductor light-emitting device according to claim 1, wherein the uneven structure is provided on the third semiconductor layer.

7. The surface-emitting semiconductor light-emitting device according to any one of claims 1 to 6, wherein the uneven structure has a plurality of the convex portions, and the plurality of the convex portions are arranged with a certain periodicity in a direction along the upper surface of the second semiconductor layer.

8. 8. The surface-emitting semiconductor light-emitting device according to claim 7, wherein a period of the plurality of protrusions is shorter than a wavelength of the light emitted from the light-emitting layer.

9. the light emitting layer includes a first layer including a first compound semiconductor and a second layer including a second compound semiconductor different from the first compound semiconductor, the first layer and the second layer being alternately stacked in a direction from the first semiconductor layer toward the second semiconductor layer, when operating as a quantum cascade laser, the laser includes a light-emitting multiple quantum well region made of the first compound semiconductor and the second compound semiconductor, and an injection multiple quantum well region made of the first compound semiconductor and the second compound semiconductor; 9. The surface-emitting semiconductor light-emitting device according to claim 1, wherein the pair of the light-emitting multiple quantum well region and the injection multiple quantum well region is laminated in a plurality of stages.

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